Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
1f934641 TG |
21 | * |
22 | * Historical information which is worth to be preserved: | |
23 | * | |
24 | * - SiS APIC rmw bug: | |
25 | * | |
26 | * We used to have a workaround for a bug in SiS chips which | |
27 | * required to rewrite the index register for a read-modify-write | |
28 | * operation as the chip lost the index information which was | |
29 | * setup for the read already. We cache the data now, so that | |
30 | * workaround has been removed. | |
1da177e4 LT |
31 | */ |
32 | ||
33 | #include <linux/mm.h> | |
1da177e4 LT |
34 | #include <linux/interrupt.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/sched.h> | |
d4057bdb | 38 | #include <linux/pci.h> |
1da177e4 LT |
39 | #include <linux/mc146818rtc.h> |
40 | #include <linux/compiler.h> | |
41 | #include <linux/acpi.h> | |
186f4360 | 42 | #include <linux/export.h> |
f3c6ea1b | 43 | #include <linux/syscore_ops.h> |
7dfb7103 | 44 | #include <linux/freezer.h> |
f26d6a2b | 45 | #include <linux/kthread.h> |
54168ed7 | 46 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 47 | #include <linux/slab.h> |
d4057bdb | 48 | #include <linux/bootmem.h> |
54d5d424 | 49 | |
f7a0c786 | 50 | #include <asm/irqdomain.h> |
1da177e4 LT |
51 | #include <asm/io.h> |
52 | #include <asm/smp.h> | |
6d652ea1 | 53 | #include <asm/cpu.h> |
1da177e4 | 54 | #include <asm/desc.h> |
d4057bdb YL |
55 | #include <asm/proto.h> |
56 | #include <asm/acpi.h> | |
57 | #include <asm/dma.h> | |
1da177e4 | 58 | #include <asm/timer.h> |
306e440d | 59 | #include <asm/i8259.h> |
a4dbc34d | 60 | #include <asm/setup.h> |
8a8f422d | 61 | #include <asm/irq_remapping.h> |
2c1b284e | 62 | #include <asm/hw_irq.h> |
1da177e4 | 63 | |
7b6aa335 | 64 | #include <asm/apic.h> |
1da177e4 | 65 | |
f44d1692 JL |
66 | #define for_each_ioapic(idx) \ |
67 | for ((idx) = 0; (idx) < nr_ioapics; (idx)++) | |
68 | #define for_each_ioapic_reverse(idx) \ | |
69 | for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--) | |
70 | #define for_each_pin(idx, pin) \ | |
71 | for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++) | |
72 | #define for_each_ioapic_pin(idx, pin) \ | |
73 | for_each_ioapic((idx)) \ | |
74 | for_each_pin((idx), (pin)) | |
2977fb3f | 75 | #define for_each_irq_pin(entry, head) \ |
a178b87b | 76 | list_for_each_entry(entry, &head, list) |
32f71aff | 77 | |
dade7716 | 78 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
d7f3d478 | 79 | static DEFINE_MUTEX(ioapic_mutex); |
44767bfa | 80 | static unsigned int ioapic_dynirq_base; |
b81975ea | 81 | static int ioapic_initialized; |
efa2559f | 82 | |
4467715a JL |
83 | struct irq_pin_list { |
84 | struct list_head list; | |
85 | int apic, pin; | |
86 | }; | |
87 | ||
49c7e600 | 88 | struct mp_chip_data { |
4467715a | 89 | struct list_head irq_2_pin; |
49c7e600 JL |
90 | struct IO_APIC_route_entry entry; |
91 | int trigger; | |
92 | int polarity; | |
96ed44b2 | 93 | u32 count; |
49c7e600 JL |
94 | bool isa_irq; |
95 | }; | |
96 | ||
154d9e50 JL |
97 | struct mp_ioapic_gsi { |
98 | u32 gsi_base; | |
99 | u32 gsi_end; | |
100 | }; | |
101 | ||
b69c6c3b SS |
102 | static struct ioapic { |
103 | /* | |
104 | * # of IRQ routing registers | |
105 | */ | |
106 | int nr_registers; | |
57a6f740 SS |
107 | /* |
108 | * Saved state during suspend/resume, or while enabling intr-remap. | |
109 | */ | |
110 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
111 | /* I/O APIC config */ |
112 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
113 | /* IO APIC gsi routing info */ |
114 | struct mp_ioapic_gsi gsi_config; | |
d7f3d478 JL |
115 | struct ioapic_domain_cfg irqdomain_cfg; |
116 | struct irq_domain *irqdomain; | |
15516a3b | 117 | struct resource *iomem_res; |
b69c6c3b | 118 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 119 | |
6f50d45f | 120 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 121 | |
6f50d45f | 122 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 123 | { |
6f50d45f | 124 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
125 | } |
126 | ||
6f50d45f | 127 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 128 | { |
6f50d45f | 129 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
130 | } |
131 | ||
154d9e50 | 132 | static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 133 | { |
6f50d45f | 134 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 135 | } |
9f640ccb | 136 | |
18e48551 JL |
137 | static inline int mp_ioapic_pin_count(int ioapic) |
138 | { | |
139 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
140 | ||
141 | return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; | |
142 | } | |
143 | ||
154d9e50 | 144 | static inline u32 mp_pin_to_gsi(int ioapic, int pin) |
18e48551 JL |
145 | { |
146 | return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; | |
147 | } | |
148 | ||
d32932d0 JL |
149 | static inline bool mp_is_legacy_irq(int irq) |
150 | { | |
151 | return irq >= 0 && irq < nr_legacy_irqs(); | |
152 | } | |
153 | ||
95d76acc JL |
154 | /* |
155 | * Initialize all legacy IRQs and all pins on the first IOAPIC | |
156 | * if we have legacy interrupt controller. Kernel boot option "pirq=" | |
157 | * may rely on non-legacy pins on the first IOAPIC. | |
158 | */ | |
18e48551 JL |
159 | static inline int mp_init_irq_at_boot(int ioapic, int irq) |
160 | { | |
95d76acc JL |
161 | if (!nr_legacy_irqs()) |
162 | return 0; | |
163 | ||
d32932d0 | 164 | return ioapic == 0 || mp_is_legacy_irq(irq); |
18e48551 JL |
165 | } |
166 | ||
d7f3d478 JL |
167 | static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic) |
168 | { | |
169 | return ioapics[ioapic].irqdomain; | |
170 | } | |
171 | ||
c040aaeb | 172 | int nr_ioapics; |
2a4ab640 | 173 | |
a4384df3 EB |
174 | /* The one past the highest gsi number used */ |
175 | u32 gsi_top; | |
5777372a | 176 | |
584f734d | 177 | /* MP IRQ source entries */ |
c2c21745 | 178 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
179 | |
180 | /* # of MP IRQ source entries */ | |
181 | int mp_irq_entries; | |
182 | ||
bb8187d3 | 183 | #ifdef CONFIG_EISA |
8732fc4b AS |
184 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
185 | #endif | |
186 | ||
187 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
188 | ||
efa2559f YL |
189 | int skip_ioapic_setup; |
190 | ||
7167d08e HK |
191 | /** |
192 | * disable_ioapic_support() - disables ioapic support at runtime | |
193 | */ | |
194 | void disable_ioapic_support(void) | |
65a4e574 IM |
195 | { |
196 | #ifdef CONFIG_PCI | |
197 | noioapicquirk = 1; | |
198 | noioapicreroute = -1; | |
199 | #endif | |
200 | skip_ioapic_setup = 1; | |
201 | } | |
202 | ||
54168ed7 | 203 | static int __init parse_noapic(char *str) |
efa2559f YL |
204 | { |
205 | /* disable IO-APIC */ | |
7167d08e | 206 | disable_ioapic_support(); |
efa2559f YL |
207 | return 0; |
208 | } | |
209 | early_param("noapic", parse_noapic); | |
66759a01 | 210 | |
2d8009ba FT |
211 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
212 | void mp_save_irq(struct mpc_intsrc *m) | |
213 | { | |
214 | int i; | |
215 | ||
216 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
217 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
218 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
219 | m->srcbusirq, m->dstapic, m->dstirq); | |
220 | ||
221 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 222 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
223 | return; |
224 | } | |
225 | ||
0e3fa13f | 226 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
227 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
228 | panic("Max # of irq sources exceeded!!\n"); | |
229 | } | |
230 | ||
7e899419 YL |
231 | static void alloc_ioapic_saved_registers(int idx) |
232 | { | |
233 | size_t size; | |
234 | ||
235 | if (ioapics[idx].saved_registers) | |
236 | return; | |
237 | ||
238 | size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers; | |
239 | ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL); | |
240 | if (!ioapics[idx].saved_registers) | |
241 | pr_err("IOAPIC %d: suspend/resume impossible!\n", idx); | |
242 | } | |
243 | ||
15516a3b JL |
244 | static void free_ioapic_saved_registers(int idx) |
245 | { | |
246 | kfree(ioapics[idx].saved_registers); | |
247 | ioapics[idx].saved_registers = NULL; | |
248 | } | |
249 | ||
11d686e9 | 250 | int __init arch_early_ioapic_init(void) |
8f09cd20 | 251 | { |
13315320 | 252 | int i; |
d6c88a50 | 253 | |
95d76acc | 254 | if (!nr_legacy_irqs()) |
1f91233c | 255 | io_apic_irqs = ~0UL; |
1f91233c | 256 | |
7e899419 YL |
257 | for_each_ioapic(i) |
258 | alloc_ioapic_saved_registers(i); | |
4c79185c | 259 | |
13a0c3c2 | 260 | return 0; |
0b8f1efa | 261 | } |
8f09cd20 | 262 | |
130fe05d LT |
263 | struct io_apic { |
264 | unsigned int index; | |
265 | unsigned int unused[3]; | |
266 | unsigned int data; | |
0280f7c4 SS |
267 | unsigned int unused2[11]; |
268 | unsigned int eoi; | |
130fe05d LT |
269 | }; |
270 | ||
271 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
272 | { | |
273 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 274 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
275 | } |
276 | ||
ad66e1ef | 277 | static inline void io_apic_eoi(unsigned int apic, unsigned int vector) |
0280f7c4 SS |
278 | { |
279 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
280 | writel(vector, &io_apic->eoi); | |
281 | } | |
282 | ||
4a8e2a31 | 283 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
284 | { |
285 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
286 | writel(reg, &io_apic->index); | |
287 | return readl(&io_apic->data); | |
288 | } | |
289 | ||
9a93d473 JL |
290 | static void io_apic_write(unsigned int apic, unsigned int reg, |
291 | unsigned int value) | |
130fe05d LT |
292 | { |
293 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 294 | |
130fe05d LT |
295 | writel(reg, &io_apic->index); |
296 | writel(value, &io_apic->data); | |
297 | } | |
298 | ||
cf4c6a2f AK |
299 | union entry_union { |
300 | struct { u32 w1, w2; }; | |
301 | struct IO_APIC_route_entry entry; | |
302 | }; | |
303 | ||
e57253a8 SS |
304 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
305 | { | |
306 | union entry_union eu; | |
307 | ||
308 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
309 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 310 | |
e57253a8 SS |
311 | return eu.entry; |
312 | } | |
313 | ||
cf4c6a2f AK |
314 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
315 | { | |
316 | union entry_union eu; | |
317 | unsigned long flags; | |
136d249e | 318 | |
dade7716 | 319 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 320 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 321 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 322 | |
cf4c6a2f AK |
323 | return eu.entry; |
324 | } | |
325 | ||
f9dadfa7 LT |
326 | /* |
327 | * When we write a new IO APIC routing entry, we need to write the high | |
328 | * word first! If the mask bit in the low word is clear, we will enable | |
329 | * the interrupt, and we need to make sure the entry is fully populated | |
330 | * before that happens. | |
331 | */ | |
136d249e | 332 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 333 | { |
50a8d4d2 F |
334 | union entry_union eu = {{0, 0}}; |
335 | ||
cf4c6a2f | 336 | eu.entry = e; |
f9dadfa7 LT |
337 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
338 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
339 | } |
340 | ||
1a8ce7ff | 341 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
342 | { |
343 | unsigned long flags; | |
136d249e | 344 | |
dade7716 | 345 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 346 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 347 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
348 | } |
349 | ||
350 | /* | |
351 | * When we mask an IO APIC routing entry, we need to write the low | |
352 | * word first, in order to set the mask bit before we change the | |
353 | * high bits! | |
354 | */ | |
355 | static void ioapic_mask_entry(int apic, int pin) | |
356 | { | |
357 | unsigned long flags; | |
335efdf5 | 358 | union entry_union eu = { .entry.mask = IOAPIC_MASKED }; |
f9dadfa7 | 359 | |
dade7716 | 360 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
361 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
362 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 363 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
364 | } |
365 | ||
1da177e4 LT |
366 | /* |
367 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
368 | * shared ISA-space IRQs, so we have to support them. We are super | |
369 | * fast in the common case, and fast for shared ISA-space IRQs. | |
370 | */ | |
4467715a JL |
371 | static int __add_pin_to_irq_node(struct mp_chip_data *data, |
372 | int node, int apic, int pin) | |
1da177e4 | 373 | { |
a178b87b | 374 | struct irq_pin_list *entry; |
0f978f45 | 375 | |
2977fb3f | 376 | /* don't allow duplicates */ |
4467715a | 377 | for_each_irq_pin(entry, data->irq_2_pin) |
0f978f45 | 378 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 379 | return 0; |
0f978f45 | 380 | |
4467715a | 381 | entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node); |
a7428cd2 | 382 | if (!entry) { |
c767a54b JP |
383 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
384 | node, apic, pin); | |
f3d1915a | 385 | return -ENOMEM; |
a7428cd2 | 386 | } |
1da177e4 LT |
387 | entry->apic = apic; |
388 | entry->pin = pin; | |
4467715a | 389 | list_add_tail(&entry->list, &data->irq_2_pin); |
875e68ec | 390 | |
f3d1915a CG |
391 | return 0; |
392 | } | |
393 | ||
4467715a | 394 | static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) |
df334bea | 395 | { |
a178b87b | 396 | struct irq_pin_list *tmp, *entry; |
df334bea | 397 | |
4467715a | 398 | list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) |
df334bea | 399 | if (entry->apic == apic && entry->pin == pin) { |
a178b87b | 400 | list_del(&entry->list); |
df334bea JL |
401 | kfree(entry); |
402 | return; | |
df334bea JL |
403 | } |
404 | } | |
405 | ||
4467715a JL |
406 | static void add_pin_to_irq_node(struct mp_chip_data *data, |
407 | int node, int apic, int pin) | |
f3d1915a | 408 | { |
4467715a | 409 | if (__add_pin_to_irq_node(data, node, apic, pin)) |
f3d1915a | 410 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
411 | } |
412 | ||
413 | /* | |
414 | * Reroute an IRQ to a different pin. | |
415 | */ | |
4467715a | 416 | static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node, |
4eea6fff JF |
417 | int oldapic, int oldpin, |
418 | int newapic, int newpin) | |
1da177e4 | 419 | { |
535b6429 | 420 | struct irq_pin_list *entry; |
1da177e4 | 421 | |
4467715a | 422 | for_each_irq_pin(entry, data->irq_2_pin) { |
1da177e4 LT |
423 | if (entry->apic == oldapic && entry->pin == oldpin) { |
424 | entry->apic = newapic; | |
425 | entry->pin = newpin; | |
0f978f45 | 426 | /* every one is different, right? */ |
4eea6fff | 427 | return; |
0f978f45 | 428 | } |
1da177e4 | 429 | } |
0f978f45 | 430 | |
4eea6fff | 431 | /* old apic/pin didn't exist, so just add new ones */ |
4467715a | 432 | add_pin_to_irq_node(data, node, newapic, newpin); |
1da177e4 LT |
433 | } |
434 | ||
4467715a | 435 | static void io_apic_modify_irq(struct mp_chip_data *data, |
2f210deb JF |
436 | int mask_and, int mask_or, |
437 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 438 | { |
0be275e3 | 439 | union entry_union eu; |
87783be4 | 440 | struct irq_pin_list *entry; |
047c8fdb | 441 | |
0be275e3 JL |
442 | eu.entry = data->entry; |
443 | eu.w1 &= mask_and; | |
444 | eu.w1 |= mask_or; | |
445 | data->entry = eu.entry; | |
446 | ||
447 | for_each_irq_pin(entry, data->irq_2_pin) { | |
448 | io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1); | |
449 | if (final) | |
450 | final(entry); | |
451 | } | |
c29d9db3 SS |
452 | } |
453 | ||
7f3e632f | 454 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 455 | { |
87783be4 CG |
456 | /* |
457 | * Synchronize the IO-APIC and the CPU by doing | |
458 | * a dummy read from the IO-APIC | |
459 | */ | |
460 | struct io_apic __iomem *io_apic; | |
136d249e | 461 | |
87783be4 | 462 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 463 | readl(&io_apic->data); |
1da177e4 LT |
464 | } |
465 | ||
4467715a | 466 | static void mask_ioapic_irq(struct irq_data *irq_data) |
87783be4 | 467 | { |
4467715a | 468 | struct mp_chip_data *data = irq_data->chip_data; |
dd5f15e5 TG |
469 | unsigned long flags; |
470 | ||
471 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 472 | io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 473 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 474 | } |
1da177e4 | 475 | |
4467715a | 476 | static void __unmask_ioapic(struct mp_chip_data *data) |
dd5f15e5 | 477 | { |
4467715a | 478 | io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL); |
1da177e4 LT |
479 | } |
480 | ||
4467715a | 481 | static void unmask_ioapic_irq(struct irq_data *irq_data) |
1da177e4 | 482 | { |
4467715a | 483 | struct mp_chip_data *data = irq_data->chip_data; |
1da177e4 LT |
484 | unsigned long flags; |
485 | ||
dade7716 | 486 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
4467715a | 487 | __unmask_ioapic(data); |
dade7716 | 488 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
489 | } |
490 | ||
c0205701 SS |
491 | /* |
492 | * IO-APIC versions below 0x20 don't support EOI register. | |
493 | * For the record, here is the information about various versions: | |
494 | * 0Xh 82489DX | |
495 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
496 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
497 | * 30h-FFh Reserved | |
498 | * | |
499 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
500 | * version as 0x2. This is an error with documentation and these ICH chips | |
501 | * use io-apic's of version 0x20. | |
502 | * | |
503 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
504 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
505 | * mode to edge and then back to level, with RTE being masked during this. | |
506 | */ | |
ad66e1ef | 507 | static void __eoi_ioapic_pin(int apic, int pin, int vector) |
c0205701 SS |
508 | { |
509 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
da165322 | 510 | io_apic_eoi(apic, vector); |
c0205701 SS |
511 | } else { |
512 | struct IO_APIC_route_entry entry, entry1; | |
513 | ||
514 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
515 | ||
516 | /* | |
517 | * Mask the entry and change the trigger mode to edge. | |
518 | */ | |
335efdf5 | 519 | entry1.mask = IOAPIC_MASKED; |
c0205701 SS |
520 | entry1.trigger = IOAPIC_EDGE; |
521 | ||
522 | __ioapic_write_entry(apic, pin, entry1); | |
523 | ||
524 | /* | |
525 | * Restore the previous level triggered entry. | |
526 | */ | |
527 | __ioapic_write_entry(apic, pin, entry); | |
528 | } | |
529 | } | |
530 | ||
4faefda9 | 531 | static void eoi_ioapic_pin(int vector, struct mp_chip_data *data) |
d32932d0 JL |
532 | { |
533 | unsigned long flags; | |
534 | struct irq_pin_list *entry; | |
535 | ||
536 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 537 | for_each_irq_pin(entry, data->irq_2_pin) |
ad66e1ef | 538 | __eoi_ioapic_pin(entry->apic, entry->pin, vector); |
c0205701 SS |
539 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
540 | } | |
541 | ||
1da177e4 LT |
542 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
543 | { | |
544 | struct IO_APIC_route_entry entry; | |
36062448 | 545 | |
1da177e4 | 546 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 547 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
548 | if (entry.delivery_mode == dest_SMI) |
549 | return; | |
1e75b31d | 550 | |
1da177e4 | 551 | /* |
1e75b31d SS |
552 | * Make sure the entry is masked and re-read the contents to check |
553 | * if it is a level triggered pin and if the remote-IRR is set. | |
554 | */ | |
335efdf5 TG |
555 | if (entry.mask == IOAPIC_UNMASKED) { |
556 | entry.mask = IOAPIC_MASKED; | |
1e75b31d SS |
557 | ioapic_write_entry(apic, pin, entry); |
558 | entry = ioapic_read_entry(apic, pin); | |
559 | } | |
560 | ||
561 | if (entry.irr) { | |
c0205701 SS |
562 | unsigned long flags; |
563 | ||
1e75b31d SS |
564 | /* |
565 | * Make sure the trigger mode is set to level. Explicit EOI | |
566 | * doesn't clear the remote-IRR if the trigger mode is not | |
567 | * set to level. | |
568 | */ | |
335efdf5 | 569 | if (entry.trigger == IOAPIC_EDGE) { |
1e75b31d SS |
570 | entry.trigger = IOAPIC_LEVEL; |
571 | ioapic_write_entry(apic, pin, entry); | |
572 | } | |
c0205701 | 573 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
ad66e1ef | 574 | __eoi_ioapic_pin(apic, pin, entry.vector); |
c0205701 | 575 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1e75b31d SS |
576 | } |
577 | ||
578 | /* | |
579 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
580 | * bit. | |
1da177e4 | 581 | */ |
f9dadfa7 | 582 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
583 | entry = ioapic_read_entry(apic, pin); |
584 | if (entry.irr) | |
c767a54b | 585 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 586 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
587 | } |
588 | ||
54168ed7 | 589 | static void clear_IO_APIC (void) |
1da177e4 LT |
590 | { |
591 | int apic, pin; | |
592 | ||
f44d1692 JL |
593 | for_each_ioapic_pin(apic, pin) |
594 | clear_IO_APIC_pin(apic, pin); | |
1da177e4 LT |
595 | } |
596 | ||
54168ed7 | 597 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
598 | /* |
599 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
600 | * specific CPU-side IRQs. | |
601 | */ | |
602 | ||
603 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
604 | static int pirq_entries[MAX_PIRQS] = { |
605 | [0 ... MAX_PIRQS - 1] = -1 | |
606 | }; | |
1da177e4 | 607 | |
1da177e4 LT |
608 | static int __init ioapic_pirq_setup(char *str) |
609 | { | |
610 | int i, max; | |
611 | int ints[MAX_PIRQS+1]; | |
612 | ||
613 | get_options(str, ARRAY_SIZE(ints), ints); | |
614 | ||
1da177e4 LT |
615 | apic_printk(APIC_VERBOSE, KERN_INFO |
616 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
617 | max = MAX_PIRQS; | |
618 | if (ints[0] < MAX_PIRQS) | |
619 | max = ints[0]; | |
620 | ||
621 | for (i = 0; i < max; i++) { | |
622 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
623 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
624 | /* | |
625 | * PIRQs are mapped upside down, usually. | |
626 | */ | |
627 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
628 | } | |
629 | return 1; | |
630 | } | |
631 | ||
632 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
633 | #endif /* CONFIG_X86_32 */ |
634 | ||
54168ed7 | 635 | /* |
05c3dc2c | 636 | * Saves all the IO-APIC RTE's |
54168ed7 | 637 | */ |
31dce14a | 638 | int save_ioapic_entries(void) |
54168ed7 | 639 | { |
54168ed7 | 640 | int apic, pin; |
31dce14a | 641 | int err = 0; |
54168ed7 | 642 | |
f44d1692 | 643 | for_each_ioapic(apic) { |
57a6f740 | 644 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
645 | err = -ENOMEM; |
646 | continue; | |
647 | } | |
54168ed7 | 648 | |
f44d1692 | 649 | for_each_pin(apic, pin) |
57a6f740 | 650 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 651 | ioapic_read_entry(apic, pin); |
b24696bc | 652 | } |
5ffa4eb2 | 653 | |
31dce14a | 654 | return err; |
54168ed7 IM |
655 | } |
656 | ||
b24696bc FY |
657 | /* |
658 | * Mask all IO APIC entries. | |
659 | */ | |
31dce14a | 660 | void mask_ioapic_entries(void) |
05c3dc2c SS |
661 | { |
662 | int apic, pin; | |
663 | ||
f44d1692 | 664 | for_each_ioapic(apic) { |
2f344d2e | 665 | if (!ioapics[apic].saved_registers) |
31dce14a | 666 | continue; |
b24696bc | 667 | |
f44d1692 | 668 | for_each_pin(apic, pin) { |
05c3dc2c SS |
669 | struct IO_APIC_route_entry entry; |
670 | ||
57a6f740 | 671 | entry = ioapics[apic].saved_registers[pin]; |
335efdf5 TG |
672 | if (entry.mask == IOAPIC_UNMASKED) { |
673 | entry.mask = IOAPIC_MASKED; | |
05c3dc2c SS |
674 | ioapic_write_entry(apic, pin, entry); |
675 | } | |
676 | } | |
677 | } | |
678 | } | |
679 | ||
b24696bc | 680 | /* |
57a6f740 | 681 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 682 | */ |
31dce14a | 683 | int restore_ioapic_entries(void) |
54168ed7 IM |
684 | { |
685 | int apic, pin; | |
686 | ||
f44d1692 | 687 | for_each_ioapic(apic) { |
2f344d2e | 688 | if (!ioapics[apic].saved_registers) |
31dce14a | 689 | continue; |
b24696bc | 690 | |
f44d1692 | 691 | for_each_pin(apic, pin) |
54168ed7 | 692 | ioapic_write_entry(apic, pin, |
57a6f740 | 693 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 694 | } |
b24696bc | 695 | return 0; |
54168ed7 IM |
696 | } |
697 | ||
1da177e4 LT |
698 | /* |
699 | * Find the IRQ entry number of a certain pin. | |
700 | */ | |
6f50d45f | 701 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
702 | { |
703 | int i; | |
704 | ||
705 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 706 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 707 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
708 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
709 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
710 | return i; |
711 | ||
712 | return -1; | |
713 | } | |
714 | ||
715 | /* | |
716 | * Find the pin to which IRQ[irq] (ISA) is connected | |
717 | */ | |
fcfd636a | 718 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
719 | { |
720 | int i; | |
721 | ||
722 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 723 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 724 | |
d27e2b8e | 725 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
726 | (mp_irqs[i].irqtype == type) && |
727 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 728 | |
c2c21745 | 729 | return mp_irqs[i].dstirq; |
1da177e4 LT |
730 | } |
731 | return -1; | |
732 | } | |
733 | ||
fcfd636a EB |
734 | static int __init find_isa_irq_apic(int irq, int type) |
735 | { | |
736 | int i; | |
737 | ||
738 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 739 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 740 | |
73b2961b | 741 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
742 | (mp_irqs[i].irqtype == type) && |
743 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
744 | break; |
745 | } | |
6f50d45f | 746 | |
fcfd636a | 747 | if (i < mp_irq_entries) { |
6f50d45f YL |
748 | int ioapic_idx; |
749 | ||
f44d1692 | 750 | for_each_ioapic(ioapic_idx) |
6f50d45f YL |
751 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
752 | return ioapic_idx; | |
fcfd636a EB |
753 | } |
754 | ||
755 | return -1; | |
756 | } | |
757 | ||
bb8187d3 | 758 | #ifdef CONFIG_EISA |
1da177e4 LT |
759 | /* |
760 | * EISA Edge/Level control register, ELCR | |
761 | */ | |
762 | static int EISA_ELCR(unsigned int irq) | |
763 | { | |
95d76acc | 764 | if (irq < nr_legacy_irqs()) { |
1da177e4 LT |
765 | unsigned int port = 0x4d0 + (irq >> 3); |
766 | return (inb(port) >> (irq & 7)) & 1; | |
767 | } | |
768 | apic_printk(APIC_VERBOSE, KERN_INFO | |
769 | "Broken MPtable reports ISA irq %d\n", irq); | |
770 | return 0; | |
771 | } | |
54168ed7 | 772 | |
c0a282c2 | 773 | #endif |
1da177e4 | 774 | |
335efdf5 | 775 | /* ISA interrupts are always active high edge triggered, |
6728801d AS |
776 | * when listed as conforming in the MP table. */ |
777 | ||
335efdf5 TG |
778 | #define default_ISA_trigger(idx) (IOAPIC_EDGE) |
779 | #define default_ISA_polarity(idx) (IOAPIC_POL_HIGH) | |
6728801d | 780 | |
1da177e4 LT |
781 | /* EISA interrupts are always polarity zero and can be edge or level |
782 | * trigger depending on the ELCR value. If an interrupt is listed as | |
783 | * EISA conforming in the MP table, that means its trigger type must | |
784 | * be read in from the ELCR */ | |
785 | ||
c2c21745 | 786 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 787 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 788 | |
335efdf5 | 789 | /* PCI interrupts are always active low level triggered, |
1da177e4 LT |
790 | * when listed as conforming in the MP table. */ |
791 | ||
335efdf5 TG |
792 | #define default_PCI_trigger(idx) (IOAPIC_LEVEL) |
793 | #define default_PCI_polarity(idx) (IOAPIC_POL_LOW) | |
1da177e4 | 794 | |
b77cf6a8 | 795 | static int irq_polarity(int idx) |
1da177e4 | 796 | { |
c2c21745 | 797 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
798 | |
799 | /* | |
800 | * Determine IRQ line polarity (high active or low active): | |
801 | */ | |
ab76085e TG |
802 | switch (mp_irqs[idx].irqflag & 0x03) { |
803 | case 0: | |
804 | /* conforms to spec, ie. bus-type dependent polarity */ | |
805 | if (test_bit(bus, mp_bus_not_pci)) | |
806 | return default_ISA_polarity(idx); | |
807 | else | |
808 | return default_PCI_polarity(idx); | |
809 | case 1: | |
810 | return IOAPIC_POL_HIGH; | |
811 | case 2: | |
812 | pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n"); | |
813 | case 3: | |
814 | default: /* Pointless default required due to do gcc stupidity */ | |
815 | return IOAPIC_POL_LOW; | |
1da177e4 | 816 | } |
1da177e4 LT |
817 | } |
818 | ||
ab76085e TG |
819 | #ifdef CONFIG_EISA |
820 | static int eisa_irq_trigger(int idx, int bus, int trigger) | |
821 | { | |
822 | switch (mp_bus_id_to_type[bus]) { | |
823 | case MP_BUS_PCI: | |
824 | case MP_BUS_ISA: | |
825 | return trigger; | |
826 | case MP_BUS_EISA: | |
827 | return default_EISA_trigger(idx); | |
828 | } | |
829 | pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus); | |
830 | return IOAPIC_LEVEL; | |
831 | } | |
832 | #else | |
833 | static inline int eisa_irq_trigger(int idx, int bus, int trigger) | |
834 | { | |
835 | return trigger; | |
836 | } | |
837 | #endif | |
838 | ||
b77cf6a8 | 839 | static int irq_trigger(int idx) |
1da177e4 | 840 | { |
c2c21745 | 841 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
842 | int trigger; |
843 | ||
844 | /* | |
845 | * Determine IRQ trigger mode (edge or level sensitive): | |
846 | */ | |
ab76085e TG |
847 | switch ((mp_irqs[idx].irqflag >> 2) & 0x03) { |
848 | case 0: | |
849 | /* conforms to spec, ie. bus-type dependent trigger mode */ | |
850 | if (test_bit(bus, mp_bus_not_pci)) | |
851 | trigger = default_ISA_trigger(idx); | |
852 | else | |
853 | trigger = default_PCI_trigger(idx); | |
854 | /* Take EISA into account */ | |
855 | return eisa_irq_trigger(idx, bus, trigger); | |
856 | case 1: | |
857 | return IOAPIC_EDGE; | |
858 | case 2: | |
859 | pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n"); | |
860 | case 3: | |
861 | default: /* Pointless default required due to do gcc stupidity */ | |
862 | return IOAPIC_LEVEL; | |
1da177e4 | 863 | } |
1da177e4 LT |
864 | } |
865 | ||
c4d05a2c JL |
866 | void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node, |
867 | int trigger, int polarity) | |
868 | { | |
869 | init_irq_alloc_info(info, NULL); | |
870 | info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
871 | info->ioapic_node = node; | |
872 | info->ioapic_trigger = trigger; | |
873 | info->ioapic_polarity = polarity; | |
874 | info->ioapic_valid = 1; | |
875 | } | |
876 | ||
96ed44b2 JL |
877 | #ifndef CONFIG_ACPI |
878 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity); | |
879 | #endif | |
880 | ||
881 | static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst, | |
882 | struct irq_alloc_info *src, | |
883 | u32 gsi, int ioapic_idx, int pin) | |
884 | { | |
885 | int trigger, polarity; | |
886 | ||
887 | copy_irq_alloc_info(dst, src); | |
888 | dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
889 | dst->ioapic_id = mpc_ioapic_id(ioapic_idx); | |
890 | dst->ioapic_pin = pin; | |
891 | dst->ioapic_valid = 1; | |
892 | if (src && src->ioapic_valid) { | |
893 | dst->ioapic_node = src->ioapic_node; | |
894 | dst->ioapic_trigger = src->ioapic_trigger; | |
895 | dst->ioapic_polarity = src->ioapic_polarity; | |
896 | } else { | |
897 | dst->ioapic_node = NUMA_NO_NODE; | |
898 | if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) { | |
899 | dst->ioapic_trigger = trigger; | |
900 | dst->ioapic_polarity = polarity; | |
901 | } else { | |
902 | /* | |
335efdf5 | 903 | * PCI interrupts are always active low level |
96ed44b2 JL |
904 | * triggered. |
905 | */ | |
335efdf5 TG |
906 | dst->ioapic_trigger = IOAPIC_LEVEL; |
907 | dst->ioapic_polarity = IOAPIC_POL_LOW; | |
96ed44b2 JL |
908 | } |
909 | } | |
910 | } | |
911 | ||
912 | static int ioapic_alloc_attr_node(struct irq_alloc_info *info) | |
913 | { | |
914 | return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE; | |
915 | } | |
916 | ||
49c7e600 JL |
917 | static void mp_register_handler(unsigned int irq, unsigned long trigger) |
918 | { | |
919 | irq_flow_handler_t hdl; | |
920 | bool fasteoi; | |
921 | ||
922 | if (trigger) { | |
923 | irq_set_status_flags(irq, IRQ_LEVEL); | |
924 | fasteoi = true; | |
925 | } else { | |
926 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
927 | fasteoi = false; | |
928 | } | |
929 | ||
930 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; | |
931 | __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge"); | |
932 | } | |
933 | ||
96ed44b2 JL |
934 | static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info) |
935 | { | |
936 | struct mp_chip_data *data = irq_get_chip_data(irq); | |
937 | ||
938 | /* | |
939 | * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger | |
940 | * and polarity attirbutes. So allow the first user to reprogram the | |
941 | * pin with real trigger and polarity attributes. | |
942 | */ | |
943 | if (irq < nr_legacy_irqs() && data->count == 1) { | |
944 | if (info->ioapic_trigger != data->trigger) | |
646c4b75 | 945 | mp_register_handler(irq, info->ioapic_trigger); |
96ed44b2 JL |
946 | data->entry.trigger = data->trigger = info->ioapic_trigger; |
947 | data->entry.polarity = data->polarity = info->ioapic_polarity; | |
948 | } | |
949 | ||
950 | return data->trigger == info->ioapic_trigger && | |
951 | data->polarity == info->ioapic_polarity; | |
952 | } | |
953 | ||
d32932d0 | 954 | static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi, |
c4d05a2c | 955 | struct irq_alloc_info *info) |
6b9fb708 | 956 | { |
d32932d0 | 957 | bool legacy = false; |
d7f3d478 | 958 | int irq = -1; |
d7f3d478 JL |
959 | int type = ioapics[ioapic].irqdomain_cfg.type; |
960 | ||
961 | switch (type) { | |
962 | case IOAPIC_DOMAIN_LEGACY: | |
963 | /* | |
d32932d0 JL |
964 | * Dynamically allocate IRQ number for non-ISA IRQs in the first |
965 | * 16 GSIs on some weird platforms. | |
d7f3d478 | 966 | */ |
d32932d0 | 967 | if (!ioapic_initialized || gsi >= nr_legacy_irqs()) |
d7f3d478 | 968 | irq = gsi; |
d32932d0 | 969 | legacy = mp_is_legacy_irq(irq); |
d7f3d478 JL |
970 | break; |
971 | case IOAPIC_DOMAIN_STRICT: | |
d32932d0 | 972 | irq = gsi; |
d7f3d478 JL |
973 | break; |
974 | case IOAPIC_DOMAIN_DYNAMIC: | |
d7f3d478 JL |
975 | break; |
976 | default: | |
977 | WARN(1, "ioapic: unknown irqdomain type %d\n", type); | |
d32932d0 JL |
978 | return -1; |
979 | } | |
980 | ||
981 | return __irq_domain_alloc_irqs(domain, irq, 1, | |
982 | ioapic_alloc_attr_node(info), | |
06ee6d57 | 983 | info, legacy, NULL); |
d32932d0 JL |
984 | } |
985 | ||
986 | /* | |
987 | * Need special handling for ISA IRQs because there may be multiple IOAPIC pins | |
988 | * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping | |
989 | * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are | |
990 | * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H). | |
991 | * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and | |
992 | * some BIOSes may use MP Interrupt Source records to override IRQ numbers for | |
993 | * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be | |
994 | * multiple pins sharing the same legacy IRQ number when ACPI is disabled. | |
995 | */ | |
996 | static int alloc_isa_irq_from_domain(struct irq_domain *domain, | |
997 | int irq, int ioapic, int pin, | |
998 | struct irq_alloc_info *info) | |
999 | { | |
1000 | struct mp_chip_data *data; | |
1001 | struct irq_data *irq_data = irq_get_irq_data(irq); | |
1002 | int node = ioapic_alloc_attr_node(info); | |
1003 | ||
1004 | /* | |
1005 | * Legacy ISA IRQ has already been allocated, just add pin to | |
1006 | * the pin list assoicated with this IRQ and program the IOAPIC | |
1007 | * entry. The IOAPIC entry | |
1008 | */ | |
1009 | if (irq_data && irq_data->parent_data) { | |
d32932d0 JL |
1010 | if (!mp_check_pin_attr(irq, info)) |
1011 | return -EBUSY; | |
4467715a JL |
1012 | if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic, |
1013 | info->ioapic_pin)) | |
d32932d0 JL |
1014 | return -ENOMEM; |
1015 | } else { | |
06ee6d57 TG |
1016 | irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, |
1017 | NULL); | |
d32932d0 JL |
1018 | if (irq >= 0) { |
1019 | irq_data = irq_domain_get_irq_data(domain, irq); | |
1020 | data = irq_data->chip_data; | |
1021 | data->isa_irq = true; | |
1022 | } | |
d7f3d478 JL |
1023 | } |
1024 | ||
d32932d0 | 1025 | return irq; |
d7f3d478 JL |
1026 | } |
1027 | ||
1028 | static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, | |
c4d05a2c | 1029 | unsigned int flags, struct irq_alloc_info *info) |
d7f3d478 JL |
1030 | { |
1031 | int irq; | |
d32932d0 JL |
1032 | bool legacy = false; |
1033 | struct irq_alloc_info tmp; | |
1034 | struct mp_chip_data *data; | |
d7f3d478 JL |
1035 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); |
1036 | ||
b81975ea | 1037 | if (!domain) |
d32932d0 | 1038 | return -ENOSYS; |
16ee7b3d | 1039 | |
16ee7b3d JL |
1040 | if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) { |
1041 | irq = mp_irqs[idx].srcbusirq; | |
d32932d0 JL |
1042 | legacy = mp_is_legacy_irq(irq); |
1043 | } | |
16ee7b3d | 1044 | |
d32932d0 JL |
1045 | mutex_lock(&ioapic_mutex); |
1046 | if (!(flags & IOAPIC_MAP_ALLOC)) { | |
1047 | if (!legacy) { | |
1048 | irq = irq_find_mapping(domain, pin); | |
16ee7b3d | 1049 | if (irq == 0) |
d32932d0 | 1050 | irq = -ENOENT; |
16ee7b3d JL |
1051 | } |
1052 | } else { | |
d32932d0 JL |
1053 | ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin); |
1054 | if (legacy) | |
1055 | irq = alloc_isa_irq_from_domain(domain, irq, | |
1056 | ioapic, pin, &tmp); | |
1057 | else if ((irq = irq_find_mapping(domain, pin)) == 0) | |
1058 | irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp); | |
1059 | else if (!mp_check_pin_attr(irq, &tmp)) | |
1060 | irq = -EBUSY; | |
1061 | if (irq >= 0) { | |
1062 | data = irq_get_chip_data(irq); | |
1063 | data->count++; | |
1064 | } | |
15a3c7cc | 1065 | } |
d7f3d478 JL |
1066 | mutex_unlock(&ioapic_mutex); |
1067 | ||
d32932d0 | 1068 | return irq; |
6b9fb708 JL |
1069 | } |
1070 | ||
d7f3d478 | 1071 | static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) |
1da177e4 | 1072 | { |
d7f3d478 | 1073 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
1da177e4 LT |
1074 | |
1075 | /* | |
1076 | * Debugging check, we are in big trouble if this message pops up! | |
1077 | */ | |
c2c21745 | 1078 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 1079 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 1080 | |
54168ed7 | 1081 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1082 | /* |
1083 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1084 | */ | |
1085 | if ((pin >= 16) && (pin <= 23)) { | |
1086 | if (pirq_entries[pin-16] != -1) { | |
1087 | if (!pirq_entries[pin-16]) { | |
1088 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1089 | "disabling PIRQ%d\n", pin-16); | |
1090 | } else { | |
d7f3d478 | 1091 | int irq = pirq_entries[pin-16]; |
1da177e4 LT |
1092 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
1093 | "using PIRQ%d -> IRQ %d\n", | |
1094 | pin-16, irq); | |
6b9fb708 | 1095 | return irq; |
1da177e4 LT |
1096 | } |
1097 | } | |
1098 | } | |
54168ed7 IM |
1099 | #endif |
1100 | ||
c4d05a2c | 1101 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL); |
d7f3d478 | 1102 | } |
6b9fb708 | 1103 | |
154d9e50 | 1104 | int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info) |
d7f3d478 JL |
1105 | { |
1106 | int ioapic, pin, idx; | |
1107 | ||
1108 | ioapic = mp_find_ioapic(gsi); | |
1109 | if (ioapic < 0) | |
358e96de | 1110 | return -ENODEV; |
d7f3d478 JL |
1111 | |
1112 | pin = mp_find_ioapic_pin(ioapic, gsi); | |
1113 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1114 | if ((flags & IOAPIC_MAP_CHECK) && idx < 0) | |
358e96de | 1115 | return -ENODEV; |
d7f3d478 | 1116 | |
c4d05a2c | 1117 | return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info); |
1da177e4 LT |
1118 | } |
1119 | ||
df334bea JL |
1120 | void mp_unmap_irq(int irq) |
1121 | { | |
d32932d0 JL |
1122 | struct irq_data *irq_data = irq_get_irq_data(irq); |
1123 | struct mp_chip_data *data; | |
df334bea | 1124 | |
d32932d0 | 1125 | if (!irq_data || !irq_data->domain) |
df334bea JL |
1126 | return; |
1127 | ||
d32932d0 JL |
1128 | data = irq_data->chip_data; |
1129 | if (!data || data->isa_irq) | |
1130 | return; | |
df334bea JL |
1131 | |
1132 | mutex_lock(&ioapic_mutex); | |
d32932d0 JL |
1133 | if (--data->count == 0) |
1134 | irq_domain_free_irqs(irq, 1); | |
df334bea JL |
1135 | mutex_unlock(&ioapic_mutex); |
1136 | } | |
1137 | ||
e20c06fd YL |
1138 | /* |
1139 | * Find a specific PCI IRQ entry. | |
1140 | * Not an __init, possibly needed by modules | |
1141 | */ | |
25d0d35e | 1142 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) |
e20c06fd | 1143 | { |
d7f3d478 | 1144 | int irq, i, best_ioapic = -1, best_idx = -1; |
e20c06fd YL |
1145 | |
1146 | apic_printk(APIC_DEBUG, | |
1147 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1148 | bus, slot, pin); | |
1149 | if (test_bit(bus, mp_bus_not_pci)) { | |
1150 | apic_printk(APIC_VERBOSE, | |
1151 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1152 | return -1; | |
1153 | } | |
79598505 | 1154 | |
e20c06fd YL |
1155 | for (i = 0; i < mp_irq_entries; i++) { |
1156 | int lbus = mp_irqs[i].srcbus; | |
79598505 JL |
1157 | int ioapic_idx, found = 0; |
1158 | ||
1159 | if (bus != lbus || mp_irqs[i].irqtype != mp_INT || | |
1160 | slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f)) | |
1161 | continue; | |
e20c06fd | 1162 | |
f44d1692 | 1163 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1164 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
79598505 JL |
1165 | mp_irqs[i].dstapic == MP_APIC_ALL) { |
1166 | found = 1; | |
e20c06fd | 1167 | break; |
e20c06fd | 1168 | } |
79598505 JL |
1169 | if (!found) |
1170 | continue; | |
1171 | ||
1172 | /* Skip ISA IRQs */ | |
d7f3d478 JL |
1173 | irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0); |
1174 | if (irq > 0 && !IO_APIC_IRQ(irq)) | |
79598505 JL |
1175 | continue; |
1176 | ||
1177 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
d7f3d478 JL |
1178 | best_idx = i; |
1179 | best_ioapic = ioapic_idx; | |
1180 | goto out; | |
79598505 | 1181 | } |
d7f3d478 | 1182 | |
79598505 JL |
1183 | /* |
1184 | * Use the first all-but-pin matching entry as a | |
1185 | * best-guess fuzzy result for broken mptables. | |
1186 | */ | |
d7f3d478 JL |
1187 | if (best_idx < 0) { |
1188 | best_idx = i; | |
1189 | best_ioapic = ioapic_idx; | |
e20c06fd YL |
1190 | } |
1191 | } | |
d7f3d478 JL |
1192 | if (best_idx < 0) |
1193 | return -1; | |
1194 | ||
1195 | out: | |
25d0d35e JL |
1196 | return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, |
1197 | IOAPIC_MAP_ALLOC); | |
e20c06fd YL |
1198 | } |
1199 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1200 | ||
d32932d0 | 1201 | static struct irq_chip ioapic_chip, ioapic_ir_chip; |
1da177e4 | 1202 | |
ed972ccf TG |
1203 | static void __init setup_IO_APIC_irqs(void) |
1204 | { | |
16ee7b3d JL |
1205 | unsigned int ioapic, pin; |
1206 | int idx; | |
ed972ccf TG |
1207 | |
1208 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1209 | ||
16ee7b3d JL |
1210 | for_each_ioapic_pin(ioapic, pin) { |
1211 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
1212 | if (idx < 0) | |
1213 | apic_printk(APIC_VERBOSE, | |
1214 | KERN_DEBUG " apic %d pin %d not connected\n", | |
1215 | mpc_ioapic_id(ioapic), pin); | |
1216 | else | |
1217 | pin_2_irq(idx, ioapic, pin, | |
1218 | ioapic ? 0 : IOAPIC_MAP_ALLOC); | |
1219 | } | |
ed972ccf TG |
1220 | } |
1221 | ||
17405453 YY |
1222 | void ioapic_zap_locks(void) |
1223 | { | |
1224 | raw_spin_lock_init(&ioapic_lock); | |
1225 | } | |
1226 | ||
a44174ee JL |
1227 | static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1228 | { | |
1229 | int i; | |
1230 | char buf[256]; | |
1231 | struct IO_APIC_route_entry entry; | |
1232 | struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry; | |
1233 | ||
1234 | printk(KERN_DEBUG "IOAPIC %d:\n", apic); | |
1235 | for (i = 0; i <= nr_entries; i++) { | |
1236 | entry = ioapic_read_entry(apic, i); | |
1237 | snprintf(buf, sizeof(buf), | |
1238 | " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", | |
335efdf5 TG |
1239 | i, |
1240 | entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ", | |
1241 | entry.trigger == IOAPIC_LEVEL ? "level" : "edge ", | |
1242 | entry.polarity == IOAPIC_POL_LOW ? "low " : "high", | |
a44174ee JL |
1243 | entry.vector, entry.irr, entry.delivery_status); |
1244 | if (ir_entry->format) | |
1245 | printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n", | |
adfaf183 | 1246 | buf, (ir_entry->index2 << 15) | ir_entry->index, |
a44174ee JL |
1247 | ir_entry->zero); |
1248 | else | |
1249 | printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", | |
335efdf5 TG |
1250 | buf, |
1251 | entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ? | |
1252 | "logical " : "physical", | |
a44174ee JL |
1253 | entry.dest, entry.delivery_mode); |
1254 | } | |
1255 | } | |
1256 | ||
74afab7a | 1257 | static void __init print_IO_APIC(int ioapic_idx) |
afcc8a40 | 1258 | { |
1da177e4 LT |
1259 | union IO_APIC_reg_00 reg_00; |
1260 | union IO_APIC_reg_01 reg_01; | |
1261 | union IO_APIC_reg_02 reg_02; | |
1262 | union IO_APIC_reg_03 reg_03; | |
1263 | unsigned long flags; | |
1da177e4 | 1264 | |
dade7716 | 1265 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1266 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1267 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1268 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1269 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1270 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1271 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1272 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1273 | |
6f50d45f | 1274 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1275 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1276 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1277 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1278 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1279 | |
54168ed7 | 1280 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1281 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1282 | reg_01.bits.entries); | |
1da177e4 LT |
1283 | |
1284 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1285 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1286 | reg_01.bits.version); | |
1da177e4 LT |
1287 | |
1288 | /* | |
1289 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1290 | * but the value of reg_02 is read as the previous read register | |
1291 | * value, so ignore it if reg_02 == reg_01. | |
1292 | */ | |
1293 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1294 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1295 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1296 | } |
1297 | ||
1298 | /* | |
1299 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1300 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1301 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1302 | */ | |
1303 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1304 | reg_03.raw != reg_01.raw) { | |
1305 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1306 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1307 | } |
1308 | ||
1309 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
a44174ee | 1310 | io_apic_print_entries(ioapic_idx, reg_01.bits.entries); |
cda417dd YL |
1311 | } |
1312 | ||
74afab7a | 1313 | void __init print_IO_APICs(void) |
cda417dd | 1314 | { |
6f50d45f | 1315 | int ioapic_idx; |
cda417dd YL |
1316 | unsigned int irq; |
1317 | ||
1318 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
f44d1692 | 1319 | for_each_ioapic(ioapic_idx) |
cda417dd | 1320 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1321 | mpc_ioapic_id(ioapic_idx), |
1322 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1323 | |
1324 | /* | |
1325 | * We are a bit conservative about what we expect. We have to | |
1326 | * know about every hardware change ASAP. | |
1327 | */ | |
1328 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1329 | ||
f44d1692 | 1330 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1331 | print_IO_APIC(ioapic_idx); |
42f0efc5 | 1332 | |
1da177e4 | 1333 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1334 | for_each_active_irq(irq) { |
0b8f1efa | 1335 | struct irq_pin_list *entry; |
4467715a JL |
1336 | struct irq_chip *chip; |
1337 | struct mp_chip_data *data; | |
0b8f1efa | 1338 | |
6fd36ba0 | 1339 | chip = irq_get_chip(irq); |
d32932d0 | 1340 | if (chip != &ioapic_chip && chip != &ioapic_ir_chip) |
6fd36ba0 | 1341 | continue; |
4467715a JL |
1342 | data = irq_get_chip_data(irq); |
1343 | if (!data) | |
05e40760 | 1344 | continue; |
4467715a | 1345 | if (list_empty(&data->irq_2_pin)) |
1da177e4 | 1346 | continue; |
4467715a | 1347 | |
8f09cd20 | 1348 | printk(KERN_DEBUG "IRQ%d ", irq); |
4467715a | 1349 | for_each_irq_pin(entry, data->irq_2_pin) |
c767a54b JP |
1350 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1351 | pr_cont("\n"); | |
1da177e4 LT |
1352 | } |
1353 | ||
1354 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1355 | } |
1356 | ||
efa2559f YL |
1357 | /* Where if anywhere is the i8259 connect in external int mode */ |
1358 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1359 | ||
54168ed7 | 1360 | void __init enable_IO_APIC(void) |
1da177e4 | 1361 | { |
fcfd636a | 1362 | int i8259_apic, i8259_pin; |
f44d1692 | 1363 | int apic, pin; |
bc07844a | 1364 | |
a46f5c89 TG |
1365 | if (skip_ioapic_setup) |
1366 | nr_ioapics = 0; | |
1367 | ||
1368 | if (!nr_legacy_irqs() || !nr_ioapics) | |
bc07844a TG |
1369 | return; |
1370 | ||
f44d1692 | 1371 | for_each_ioapic_pin(apic, pin) { |
fcfd636a | 1372 | /* See if any of the pins is in ExtINT mode */ |
f44d1692 | 1373 | struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1374 | |
f44d1692 JL |
1375 | /* If the interrupt line is enabled and in ExtInt mode |
1376 | * I have found the pin where the i8259 is connected. | |
1377 | */ | |
1378 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1379 | ioapic_i8259.apic = apic; | |
1380 | ioapic_i8259.pin = pin; | |
1381 | goto found_i8259; | |
fcfd636a EB |
1382 | } |
1383 | } | |
1384 | found_i8259: | |
1385 | /* Look to see what if the MP table has reported the ExtINT */ | |
1386 | /* If we could not find the appropriate pin by looking at the ioapic | |
1387 | * the i8259 probably is not connected the ioapic but give the | |
1388 | * mptable a chance anyway. | |
1389 | */ | |
1390 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1391 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1392 | /* Trust the MP table if nothing is setup in the hardware */ | |
1393 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1394 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1395 | ioapic_i8259.pin = i8259_pin; | |
1396 | ioapic_i8259.apic = i8259_apic; | |
1397 | } | |
1398 | /* Complain if the MP table and the hardware disagree */ | |
1399 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1400 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1401 | { | |
1402 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1403 | } |
1404 | ||
1405 | /* | |
1406 | * Do not trust the IO-APIC being empty at bootup | |
1407 | */ | |
1408 | clear_IO_APIC(); | |
1409 | } | |
1410 | ||
1c4248ca | 1411 | void native_disable_io_apic(void) |
1da177e4 | 1412 | { |
650927ef | 1413 | /* |
0b968d23 | 1414 | * If the i8259 is routed through an IOAPIC |
650927ef | 1415 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1416 | * so legacy interrupts can be delivered. |
650927ef | 1417 | */ |
1c4248ca | 1418 | if (ioapic_i8259.pin != -1) { |
650927ef | 1419 | struct IO_APIC_route_entry entry; |
650927ef EB |
1420 | |
1421 | memset(&entry, 0, sizeof(entry)); | |
335efdf5 TG |
1422 | entry.mask = IOAPIC_UNMASKED; |
1423 | entry.trigger = IOAPIC_EDGE; | |
1424 | entry.polarity = IOAPIC_POL_HIGH; | |
1425 | entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL; | |
1426 | entry.delivery_mode = dest_ExtINT; | |
1427 | entry.dest = read_apic_id(); | |
650927ef EB |
1428 | |
1429 | /* | |
1430 | * Add it to the IO-APIC irq-routing table: | |
1431 | */ | |
cf4c6a2f | 1432 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1433 | } |
54168ed7 | 1434 | |
93984fbd | 1435 | if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config()) |
1c4248ca | 1436 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1c4248ca JR |
1437 | } |
1438 | ||
1439 | /* | |
1440 | * Not an __init, needed by the reboot code | |
1441 | */ | |
1442 | void disable_IO_APIC(void) | |
1443 | { | |
7c6d9f97 | 1444 | /* |
1c4248ca | 1445 | * Clear the IO-APIC before rebooting: |
7c6d9f97 | 1446 | */ |
1c4248ca JR |
1447 | clear_IO_APIC(); |
1448 | ||
95d76acc | 1449 | if (!nr_legacy_irqs()) |
1c4248ca JR |
1450 | return; |
1451 | ||
1452 | x86_io_apic_ops.disable(); | |
1da177e4 LT |
1453 | } |
1454 | ||
54168ed7 | 1455 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1456 | /* |
1457 | * function to set the IO-APIC physical IDs based on the | |
1458 | * values stored in the MPC table. | |
1459 | * | |
1460 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1461 | */ | |
a38c5380 | 1462 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1463 | { |
1464 | union IO_APIC_reg_00 reg_00; | |
1465 | physid_mask_t phys_id_present_map; | |
6f50d45f | 1466 | int ioapic_idx; |
1da177e4 LT |
1467 | int i; |
1468 | unsigned char old_id; | |
1469 | unsigned long flags; | |
1470 | ||
1471 | /* | |
1472 | * This is broken; anything with a real cpu count has to | |
1473 | * circumvent this idiocy regardless. | |
1474 | */ | |
7abc0753 | 1475 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1476 | |
1477 | /* | |
1478 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1479 | */ | |
f44d1692 | 1480 | for_each_ioapic(ioapic_idx) { |
1da177e4 | 1481 | /* Read the register 0 value */ |
dade7716 | 1482 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1483 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1484 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1485 | |
6f50d45f | 1486 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 1487 | |
6f50d45f | 1488 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 1489 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 1490 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1491 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1492 | reg_00.bits.ID); | |
6f50d45f | 1493 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
1494 | } |
1495 | ||
1da177e4 LT |
1496 | /* |
1497 | * Sanity check, is the ID really free? Every APIC in a | |
1498 | * system must have a unique ID or we get lots of nice | |
1499 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1500 | */ | |
7abc0753 | 1501 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 1502 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 1503 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 1504 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1505 | for (i = 0; i < get_physical_broadcast(); i++) |
1506 | if (!physid_isset(i, phys_id_present_map)) | |
1507 | break; | |
1508 | if (i >= get_physical_broadcast()) | |
1509 | panic("Max APIC ID exceeded!\n"); | |
1510 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1511 | i); | |
1512 | physid_set(i, phys_id_present_map); | |
6f50d45f | 1513 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
1514 | } else { |
1515 | physid_mask_t tmp; | |
6f50d45f | 1516 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 1517 | &tmp); |
1da177e4 LT |
1518 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1519 | "phys_id_present_map\n", | |
6f50d45f | 1520 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1521 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1522 | } | |
1523 | ||
1da177e4 LT |
1524 | /* |
1525 | * We need to adjust the IRQ routing table | |
1526 | * if the ID changed. | |
1527 | */ | |
6f50d45f | 1528 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 1529 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
1530 | if (mp_irqs[i].dstapic == old_id) |
1531 | mp_irqs[i].dstapic | |
6f50d45f | 1532 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
1533 | |
1534 | /* | |
60d79fd9 YL |
1535 | * Update the ID register according to the right value |
1536 | * from the MPC table if they are different. | |
36062448 | 1537 | */ |
6f50d45f | 1538 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
1539 | continue; |
1540 | ||
1da177e4 LT |
1541 | apic_printk(APIC_VERBOSE, KERN_INFO |
1542 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 1543 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 1544 | |
6f50d45f | 1545 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 1546 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1547 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 1548 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1549 | |
1550 | /* | |
1551 | * Sanity check | |
1552 | */ | |
dade7716 | 1553 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1554 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1555 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 1556 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 1557 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
1558 | else |
1559 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1560 | } | |
1561 | } | |
a38c5380 SAS |
1562 | |
1563 | void __init setup_ioapic_ids_from_mpc(void) | |
1564 | { | |
1565 | ||
1566 | if (acpi_ioapic) | |
1567 | return; | |
1568 | /* | |
1569 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1570 | * no meaning without the serial APIC bus. | |
1571 | */ | |
1572 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
cff9ab2b | 1573 | || APIC_XAPIC(boot_cpu_apic_version)) |
a38c5380 SAS |
1574 | return; |
1575 | setup_ioapic_ids_from_mpc_nocheck(); | |
1576 | } | |
54168ed7 | 1577 | #endif |
1da177e4 | 1578 | |
7ce0bcfd | 1579 | int no_timer_check __initdata; |
8542b200 ZA |
1580 | |
1581 | static int __init notimercheck(char *s) | |
1582 | { | |
1583 | no_timer_check = 1; | |
1584 | return 1; | |
1585 | } | |
1586 | __setup("no_timer_check", notimercheck); | |
1587 | ||
1da177e4 LT |
1588 | /* |
1589 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1590 | * about the timer IRQ. We do the following to work around the situation: | |
1591 | * | |
1592 | * - timer IRQ defaults to IO-APIC IRQ | |
1593 | * - if this function detects that timer IRQs are defunct, then we fall | |
1594 | * back to ISA timer IRQs | |
1595 | */ | |
f0a7a5c9 | 1596 | static int __init timer_irq_works(void) |
1da177e4 LT |
1597 | { |
1598 | unsigned long t1 = jiffies; | |
4aae0702 | 1599 | unsigned long flags; |
1da177e4 | 1600 | |
8542b200 ZA |
1601 | if (no_timer_check) |
1602 | return 1; | |
1603 | ||
4aae0702 | 1604 | local_save_flags(flags); |
1da177e4 LT |
1605 | local_irq_enable(); |
1606 | /* Let ten ticks pass... */ | |
1607 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1608 | local_irq_restore(flags); |
1da177e4 LT |
1609 | |
1610 | /* | |
1611 | * Expect a few ticks at least, to be sure some possible | |
1612 | * glue logic does not lock up after one or two first | |
1613 | * ticks in a non-ExtINT mode. Also the local APIC | |
1614 | * might have cached one ExtINT interrupt. Finally, at | |
1615 | * least one tick may be lost due to delays. | |
1616 | */ | |
54168ed7 IM |
1617 | |
1618 | /* jiffies wrap? */ | |
1d16b53e | 1619 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 1620 | return 1; |
1da177e4 LT |
1621 | return 0; |
1622 | } | |
1623 | ||
1624 | /* | |
1625 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1626 | * number of pending IRQ events unhandled. These cases are very rare, | |
1627 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1628 | * better to do it this way as thus we do not have to be aware of | |
1629 | * 'pending' interrupts in the IRQ path, except at this point. | |
1630 | */ | |
1631 | /* | |
1632 | * Edge triggered needs to resend any interrupt | |
1633 | * that was delayed but this is now handled in the device | |
1634 | * independent code. | |
1635 | */ | |
1636 | ||
1637 | /* | |
1638 | * Starting up a edge-triggered IO-APIC interrupt is | |
1639 | * nasty - we need to make sure that we get the edge. | |
1640 | * If it is already asserted for some reason, we need | |
1641 | * return 1 to indicate that is was pending. | |
1642 | * | |
1643 | * This is not complete - we should be able to fake | |
1644 | * an edge even if it isn't on the 8259A... | |
1645 | */ | |
61a38ce3 | 1646 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 1647 | { |
61a38ce3 | 1648 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
1649 | unsigned long flags; |
1650 | ||
dade7716 | 1651 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
95d76acc | 1652 | if (irq < nr_legacy_irqs()) { |
4305df94 | 1653 | legacy_pic->mask(irq); |
b81bb373 | 1654 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
1655 | was_pending = 1; |
1656 | } | |
4467715a | 1657 | __unmask_ioapic(data->chip_data); |
dade7716 | 1658 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
1659 | |
1660 | return was_pending; | |
1661 | } | |
1662 | ||
3eb2cce8 | 1663 | atomic_t irq_mis_count; |
3eb2cce8 | 1664 | |
047c8fdb | 1665 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
4467715a | 1666 | static bool io_apic_level_ack_pending(struct mp_chip_data *data) |
d1ecad6e MN |
1667 | { |
1668 | struct irq_pin_list *entry; | |
1669 | unsigned long flags; | |
1670 | ||
1671 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 1672 | for_each_irq_pin(entry, data->irq_2_pin) { |
d1ecad6e MN |
1673 | unsigned int reg; |
1674 | int pin; | |
1675 | ||
1676 | pin = entry->pin; | |
1677 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
1678 | /* Is the remote IRR bit set? */ | |
1679 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
1680 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1681 | return true; | |
1682 | } | |
1683 | } | |
1684 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1685 | ||
1686 | return false; | |
1687 | } | |
1688 | ||
4467715a | 1689 | static inline bool ioapic_irqd_mask(struct irq_data *data) |
4da7072a | 1690 | { |
54168ed7 | 1691 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 1692 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
4467715a | 1693 | mask_ioapic_irq(data); |
4da7072a | 1694 | return true; |
54168ed7 | 1695 | } |
4da7072a AG |
1696 | return false; |
1697 | } | |
1698 | ||
4467715a | 1699 | static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked) |
4da7072a AG |
1700 | { |
1701 | if (unlikely(masked)) { | |
1702 | /* Only migrate the irq if the ack has been received. | |
1703 | * | |
1704 | * On rare occasions the broadcast level triggered ack gets | |
1705 | * delayed going to ioapics, and if we reprogram the | |
1706 | * vector while Remote IRR is still set the irq will never | |
1707 | * fire again. | |
1708 | * | |
1709 | * To prevent this scenario we read the Remote IRR bit | |
1710 | * of the ioapic. This has two effects. | |
1711 | * - On any sane system the read of the ioapic will | |
1712 | * flush writes (and acks) going to the ioapic from | |
1713 | * this cpu. | |
1714 | * - We get to see if the ACK has actually been delivered. | |
1715 | * | |
1716 | * Based on failed experiments of reprogramming the | |
1717 | * ioapic entry from outside of irq context starting | |
1718 | * with masking the ioapic entry and then polling until | |
1719 | * Remote IRR was clear before reprogramming the | |
1720 | * ioapic I don't trust the Remote IRR bit to be | |
1721 | * completey accurate. | |
1722 | * | |
1723 | * However there appears to be no other way to plug | |
1724 | * this race, so if the Remote IRR bit is not | |
1725 | * accurate and is causing problems then it is a hardware bug | |
1726 | * and you can go talk to the chipset vendor about it. | |
1727 | */ | |
4467715a | 1728 | if (!io_apic_level_ack_pending(data->chip_data)) |
4da7072a | 1729 | irq_move_masked_irq(data); |
4467715a | 1730 | unmask_ioapic_irq(data); |
4da7072a AG |
1731 | } |
1732 | } | |
1733 | #else | |
4467715a | 1734 | static inline bool ioapic_irqd_mask(struct irq_data *data) |
4da7072a AG |
1735 | { |
1736 | return false; | |
1737 | } | |
4467715a | 1738 | static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked) |
4da7072a AG |
1739 | { |
1740 | } | |
047c8fdb YL |
1741 | #endif |
1742 | ||
4467715a | 1743 | static void ioapic_ack_level(struct irq_data *irq_data) |
4da7072a | 1744 | { |
4467715a | 1745 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
4da7072a AG |
1746 | unsigned long v; |
1747 | bool masked; | |
d32932d0 | 1748 | int i; |
4da7072a AG |
1749 | |
1750 | irq_complete_move(cfg); | |
4467715a | 1751 | masked = ioapic_irqd_mask(irq_data); |
4da7072a | 1752 | |
3eb2cce8 | 1753 | /* |
916a0fe7 JF |
1754 | * It appears there is an erratum which affects at least version 0x11 |
1755 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1756 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1757 | * erroneously delivered as edge-triggered one but the respective IRR | |
1758 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1759 | * message but it will never arrive and further interrupts are blocked | |
1760 | * from the source. The exact reason is so far unknown, but the | |
1761 | * phenomenon was observed when two consecutive interrupt requests | |
1762 | * from a given source get delivered to the same CPU and the source is | |
1763 | * temporarily disabled in between. | |
1764 | * | |
1765 | * A workaround is to simulate an EOI message manually. We achieve it | |
1766 | * by setting the trigger mode to edge and then to level when the edge | |
1767 | * trigger mode gets detected in the TMR of a local APIC for a | |
1768 | * level-triggered interrupt. We mask the source for the time of the | |
1769 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1770 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
1771 | * |
1772 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
1773 | * any unhandled interrupt on the offlined cpu to the new cpu | |
1774 | * destination that is handling the corresponding interrupt. This | |
1775 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
1776 | * level-triggered io-apic interrupt will be seen as an edge | |
1777 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
1778 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
1779 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
1780 | * supporting EOI register, we do an explicit EOI to clear the | |
1781 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
1782 | * we use the above logic (mask+edge followed by unmask+level) from | |
1783 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 1784 | */ |
3145e941 | 1785 | i = cfg->vector; |
3eb2cce8 | 1786 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 1787 | |
54168ed7 IM |
1788 | /* |
1789 | * We must acknowledge the irq before we move it or the acknowledge will | |
1790 | * not propagate properly. | |
1791 | */ | |
1792 | ack_APIC_irq(); | |
1793 | ||
1c83995b SS |
1794 | /* |
1795 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
1796 | * message via io-apic EOI register write or simulating it using | |
1797 | * mask+edge followed by unnask+level logic) manually when the | |
1798 | * level triggered interrupt is seen as the edge triggered interrupt | |
1799 | * at the cpu. | |
1800 | */ | |
ca64c47c MR |
1801 | if (!(v & (1 << (i & 0x1f)))) { |
1802 | atomic_inc(&irq_mis_count); | |
4467715a | 1803 | eoi_ioapic_pin(cfg->vector, irq_data->chip_data); |
ca64c47c MR |
1804 | } |
1805 | ||
4467715a | 1806 | ioapic_irqd_unmask(irq_data, masked); |
3eb2cce8 | 1807 | } |
1d025192 | 1808 | |
d32932d0 JL |
1809 | static void ioapic_ir_ack_level(struct irq_data *irq_data) |
1810 | { | |
1811 | struct mp_chip_data *data = irq_data->chip_data; | |
1812 | ||
1813 | /* | |
1814 | * Intr-remapping uses pin number as the virtual vector | |
1815 | * in the RTE. Actual vector is programmed in | |
1816 | * intr-remapping table entry. Hence for the io-apic | |
1817 | * EOI we use the pin number. | |
1818 | */ | |
1819 | ack_APIC_irq(); | |
4467715a | 1820 | eoi_ioapic_pin(data->entry.vector, data); |
d32932d0 JL |
1821 | } |
1822 | ||
1823 | static int ioapic_set_affinity(struct irq_data *irq_data, | |
1824 | const struct cpumask *mask, bool force) | |
1825 | { | |
1826 | struct irq_data *parent = irq_data->parent_data; | |
1827 | struct mp_chip_data *data = irq_data->chip_data; | |
0be275e3 | 1828 | struct irq_pin_list *entry; |
d32932d0 JL |
1829 | struct irq_cfg *cfg; |
1830 | unsigned long flags; | |
1831 | int ret; | |
1832 | ||
1833 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
1834 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
1835 | if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) { | |
1836 | cfg = irqd_cfg(irq_data); | |
1837 | data->entry.dest = cfg->dest_apicid; | |
1838 | data->entry.vector = cfg->vector; | |
0be275e3 JL |
1839 | for_each_irq_pin(entry, data->irq_2_pin) |
1840 | __ioapic_write_entry(entry->apic, entry->pin, | |
1841 | data->entry); | |
d32932d0 JL |
1842 | } |
1843 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
1844 | ||
1845 | return ret; | |
1846 | } | |
1847 | ||
f5b9ed7a | 1848 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
1849 | .name = "IO-APIC", |
1850 | .irq_startup = startup_ioapic_irq, | |
1851 | .irq_mask = mask_ioapic_irq, | |
1852 | .irq_unmask = unmask_ioapic_irq, | |
d32932d0 JL |
1853 | .irq_ack = irq_chip_ack_parent, |
1854 | .irq_eoi = ioapic_ack_level, | |
1855 | .irq_set_affinity = ioapic_set_affinity, | |
a9b4f087 | 1856 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
d32932d0 JL |
1857 | .flags = IRQCHIP_SKIP_SET_WAKE, |
1858 | }; | |
1859 | ||
1860 | static struct irq_chip ioapic_ir_chip __read_mostly = { | |
1861 | .name = "IR-IO-APIC", | |
1862 | .irq_startup = startup_ioapic_irq, | |
1863 | .irq_mask = mask_ioapic_irq, | |
1864 | .irq_unmask = unmask_ioapic_irq, | |
1865 | .irq_ack = irq_chip_ack_parent, | |
1866 | .irq_eoi = ioapic_ir_ack_level, | |
1867 | .irq_set_affinity = ioapic_set_affinity, | |
a9b4f087 | 1868 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
5613570b | 1869 | .flags = IRQCHIP_SKIP_SET_WAKE, |
1da177e4 LT |
1870 | }; |
1871 | ||
1da177e4 LT |
1872 | static inline void init_IO_APIC_traps(void) |
1873 | { | |
da51a821 | 1874 | struct irq_cfg *cfg; |
ad9f4334 | 1875 | unsigned int irq; |
1da177e4 | 1876 | |
ad9f4334 | 1877 | for_each_active_irq(irq) { |
32f5ef5d | 1878 | cfg = irq_cfg(irq); |
0b8f1efa | 1879 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
1880 | /* |
1881 | * Hmm.. We don't have an entry for this, | |
1882 | * so default to an old-fashioned 8259 | |
1883 | * interrupt if we can.. | |
1884 | */ | |
95d76acc | 1885 | if (irq < nr_legacy_irqs()) |
b81bb373 | 1886 | legacy_pic->make_irq(irq); |
0b8f1efa | 1887 | else |
1da177e4 | 1888 | /* Strange. Oh, well.. */ |
2c778651 | 1889 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
1890 | } |
1891 | } | |
1892 | } | |
1893 | ||
f5b9ed7a IM |
1894 | /* |
1895 | * The local APIC irq-chip implementation: | |
1896 | */ | |
1da177e4 | 1897 | |
90297c5f | 1898 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
1899 | { |
1900 | unsigned long v; | |
1901 | ||
1902 | v = apic_read(APIC_LVT0); | |
593f4a78 | 1903 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
1904 | } |
1905 | ||
90297c5f | 1906 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 1907 | { |
f5b9ed7a | 1908 | unsigned long v; |
1da177e4 | 1909 | |
f5b9ed7a | 1910 | v = apic_read(APIC_LVT0); |
593f4a78 | 1911 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 1912 | } |
1da177e4 | 1913 | |
90297c5f | 1914 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
1915 | { |
1916 | ack_APIC_irq(); | |
1917 | } | |
1918 | ||
f5b9ed7a | 1919 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 1920 | .name = "local-APIC", |
90297c5f TG |
1921 | .irq_mask = mask_lapic_irq, |
1922 | .irq_unmask = unmask_lapic_irq, | |
1923 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
1924 | }; |
1925 | ||
60c69948 | 1926 | static void lapic_register_intr(int irq) |
c88ac1df | 1927 | { |
60c69948 | 1928 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 1929 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 1930 | "edge"); |
c88ac1df MR |
1931 | } |
1932 | ||
1da177e4 LT |
1933 | /* |
1934 | * This looks a bit hackish but it's about the only one way of sending | |
1935 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
1936 | * not support the ExtINT mode, unfortunately. We need to send these | |
1937 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
1938 | * 8259A interrupt line asserted until INTA. --macro | |
1939 | */ | |
28acf285 | 1940 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 1941 | { |
fcfd636a | 1942 | int apic, pin, i; |
1da177e4 LT |
1943 | struct IO_APIC_route_entry entry0, entry1; |
1944 | unsigned char save_control, save_freq_select; | |
1da177e4 | 1945 | |
fcfd636a | 1946 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
1947 | if (pin == -1) { |
1948 | WARN_ON_ONCE(1); | |
1949 | return; | |
1950 | } | |
fcfd636a | 1951 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
1952 | if (apic == -1) { |
1953 | WARN_ON_ONCE(1); | |
1da177e4 | 1954 | return; |
956fb531 | 1955 | } |
1da177e4 | 1956 | |
cf4c6a2f | 1957 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 1958 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
1959 | |
1960 | memset(&entry1, 0, sizeof(entry1)); | |
1961 | ||
335efdf5 TG |
1962 | entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL; |
1963 | entry1.mask = IOAPIC_UNMASKED; | |
d83e94ac | 1964 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
1965 | entry1.delivery_mode = dest_ExtINT; |
1966 | entry1.polarity = entry0.polarity; | |
335efdf5 | 1967 | entry1.trigger = IOAPIC_EDGE; |
1da177e4 LT |
1968 | entry1.vector = 0; |
1969 | ||
cf4c6a2f | 1970 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
1971 | |
1972 | save_control = CMOS_READ(RTC_CONTROL); | |
1973 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
1974 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
1975 | RTC_FREQ_SELECT); | |
1976 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
1977 | ||
1978 | i = 100; | |
1979 | while (i-- > 0) { | |
1980 | mdelay(10); | |
1981 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
1982 | i -= 10; | |
1983 | } | |
1984 | ||
1985 | CMOS_WRITE(save_control, RTC_CONTROL); | |
1986 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 1987 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 1988 | |
cf4c6a2f | 1989 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
1990 | } |
1991 | ||
efa2559f | 1992 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 1993 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 1994 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
1995 | { |
1996 | disable_timer_pin_1 = 1; | |
1997 | return 0; | |
1998 | } | |
54168ed7 | 1999 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f | 2000 | |
d32932d0 JL |
2001 | static int mp_alloc_timer_irq(int ioapic, int pin) |
2002 | { | |
2003 | int irq = -1; | |
d32932d0 JL |
2004 | struct irq_domain *domain = mp_ioapic_irqdomain(ioapic); |
2005 | ||
2006 | if (domain) { | |
4467715a JL |
2007 | struct irq_alloc_info info; |
2008 | ||
d32932d0 JL |
2009 | ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0); |
2010 | info.ioapic_id = mpc_ioapic_id(ioapic); | |
2011 | info.ioapic_pin = pin; | |
2012 | mutex_lock(&ioapic_mutex); | |
2013 | irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); | |
2014 | mutex_unlock(&ioapic_mutex); | |
2015 | } | |
2016 | ||
2017 | return irq; | |
2018 | } | |
2019 | ||
1da177e4 LT |
2020 | /* |
2021 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2022 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2023 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2024 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2025 | * |
2026 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2027 | */ |
8542b200 | 2028 | static inline void __init check_timer(void) |
1da177e4 | 2029 | { |
4467715a JL |
2030 | struct irq_data *irq_data = irq_get_irq_data(0); |
2031 | struct mp_chip_data *data = irq_data->chip_data; | |
2032 | struct irq_cfg *cfg = irqd_cfg(irq_data); | |
f6e9456c | 2033 | int node = cpu_to_node(0); |
fcfd636a | 2034 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2035 | unsigned long flags; |
047c8fdb | 2036 | int no_pin1 = 0; |
4aae0702 IM |
2037 | |
2038 | local_irq_save(flags); | |
d4d25dec | 2039 | |
1da177e4 LT |
2040 | /* |
2041 | * get/set the timer IRQ vector: | |
2042 | */ | |
4305df94 | 2043 | legacy_pic->mask(0); |
1da177e4 LT |
2044 | |
2045 | /* | |
d11d5794 MR |
2046 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2047 | * wire has to be disabled in the local APIC. Also | |
2048 | * timer interrupts need to be acknowledged manually in | |
2049 | * the 8259A for the i82489DX when using the NMI | |
2050 | * watchdog as that APIC treats NMIs as level-triggered. | |
2051 | * The AEOI mode will finish them in the 8259A | |
2052 | * automatically. | |
1da177e4 | 2053 | */ |
593f4a78 | 2054 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2055 | legacy_pic->init(1); |
1da177e4 | 2056 | |
fcfd636a EB |
2057 | pin1 = find_isa_irq_pin(0, mp_INT); |
2058 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2059 | pin2 = ioapic_i8259.pin; | |
2060 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2061 | |
49a66a0b MR |
2062 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2063 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2064 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2065 | |
691874fa MR |
2066 | /* |
2067 | * Some BIOS writers are clueless and report the ExtINTA | |
2068 | * I/O APIC input from the cascaded 8259A as the timer | |
2069 | * interrupt input. So just in case, if only one pin | |
2070 | * was found above, try it both directly and through the | |
2071 | * 8259A. | |
2072 | */ | |
2073 | if (pin1 == -1) { | |
6a9f5de2 | 2074 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2075 | pin1 = pin2; |
2076 | apic1 = apic2; | |
2077 | no_pin1 = 1; | |
2078 | } else if (pin2 == -1) { | |
2079 | pin2 = pin1; | |
2080 | apic2 = apic1; | |
2081 | } | |
2082 | ||
1da177e4 | 2083 | if (pin1 != -1) { |
d32932d0 | 2084 | /* Ok, does IRQ0 through the IOAPIC work? */ |
691874fa | 2085 | if (no_pin1) { |
d32932d0 | 2086 | mp_alloc_timer_irq(apic1, pin1); |
f72dccac | 2087 | } else { |
d32932d0 JL |
2088 | /* |
2089 | * for edge trigger, it's already unmasked, | |
f72dccac YL |
2090 | * so only need to unmask if it is level-trigger |
2091 | * do we really have level trigger timer? | |
2092 | */ | |
2093 | int idx; | |
2094 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2095 | if (idx != -1 && irq_trigger(idx)) | |
e708e35b | 2096 | unmask_ioapic_irq(irq_get_irq_data(0)); |
691874fa | 2097 | } |
aaaec6fc | 2098 | irq_domain_deactivate_irq(irq_data); |
4467715a | 2099 | irq_domain_activate_irq(irq_data); |
1da177e4 | 2100 | if (timer_irq_works()) { |
66759a01 CE |
2101 | if (disable_timer_pin_1 > 0) |
2102 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2103 | goto out; |
1da177e4 | 2104 | } |
6a9f5de2 | 2105 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2106 | local_irq_disable(); |
fcfd636a | 2107 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2108 | if (!no_pin1) |
49a66a0b MR |
2109 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2110 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2111 | |
49a66a0b MR |
2112 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2113 | "(IRQ0) through the 8259A ...\n"); | |
2114 | apic_printk(APIC_QUIET, KERN_INFO | |
2115 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2116 | /* |
2117 | * legacy devices should be connected to IO APIC #0 | |
2118 | */ | |
4467715a | 2119 | replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2); |
aaaec6fc | 2120 | irq_domain_deactivate_irq(irq_data); |
4467715a | 2121 | irq_domain_activate_irq(irq_data); |
4305df94 | 2122 | legacy_pic->unmask(0); |
1da177e4 | 2123 | if (timer_irq_works()) { |
49a66a0b | 2124 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
4aae0702 | 2125 | goto out; |
1da177e4 LT |
2126 | } |
2127 | /* | |
2128 | * Cleanup, just in case ... | |
2129 | */ | |
f72dccac | 2130 | local_irq_disable(); |
4305df94 | 2131 | legacy_pic->mask(0); |
fcfd636a | 2132 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2133 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2134 | } |
1da177e4 | 2135 | |
49a66a0b MR |
2136 | apic_printk(APIC_QUIET, KERN_INFO |
2137 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2138 | |
60c69948 | 2139 | lapic_register_intr(0); |
497c9a19 | 2140 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2141 | legacy_pic->unmask(0); |
1da177e4 LT |
2142 | |
2143 | if (timer_irq_works()) { | |
49a66a0b | 2144 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2145 | goto out; |
1da177e4 | 2146 | } |
f72dccac | 2147 | local_irq_disable(); |
4305df94 | 2148 | legacy_pic->mask(0); |
497c9a19 | 2149 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2150 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2151 | |
49a66a0b MR |
2152 | apic_printk(APIC_QUIET, KERN_INFO |
2153 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2154 | |
b81bb373 JP |
2155 | legacy_pic->init(0); |
2156 | legacy_pic->make_irq(0); | |
593f4a78 | 2157 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2158 | |
2159 | unlock_ExtINT_logic(); | |
2160 | ||
2161 | if (timer_irq_works()) { | |
49a66a0b | 2162 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2163 | goto out; |
1da177e4 | 2164 | } |
f72dccac | 2165 | local_irq_disable(); |
49a66a0b | 2166 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
2ca5b404 | 2167 | if (apic_is_x2apic_enabled()) |
fb209bd8 YL |
2168 | apic_printk(APIC_QUIET, KERN_INFO |
2169 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2170 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2171 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2172 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2173 | out: |
2174 | local_irq_restore(flags); | |
1da177e4 LT |
2175 | } |
2176 | ||
2177 | /* | |
af174783 MR |
2178 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2179 | * to devices. However there may be an I/O APIC pin available for | |
2180 | * this interrupt regardless. The pin may be left unconnected, but | |
2181 | * typically it will be reused as an ExtINT cascade interrupt for | |
2182 | * the master 8259A. In the MPS case such a pin will normally be | |
2183 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2184 | * there is no provision for ExtINT interrupts, and in the absence | |
2185 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2186 | * interrupt, that is edge-triggered and unmasked by default. We | |
2187 | * used to do this, but it caused problems on some systems because | |
2188 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2189 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2190 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2191 | * the I/O APIC in all cases now. No actual device should request | |
2192 | * it anyway. --macro | |
1da177e4 | 2193 | */ |
bc07844a | 2194 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 | 2195 | |
44767bfa JL |
2196 | static int mp_irqdomain_create(int ioapic) |
2197 | { | |
d32932d0 JL |
2198 | struct irq_alloc_info info; |
2199 | struct irq_domain *parent; | |
44767bfa JL |
2200 | int hwirqs = mp_ioapic_pin_count(ioapic); |
2201 | struct ioapic *ip = &ioapics[ioapic]; | |
2202 | struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; | |
2203 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
1b604745 TG |
2204 | struct fwnode_handle *fn; |
2205 | char *name = "IO-APIC"; | |
44767bfa JL |
2206 | |
2207 | if (cfg->type == IOAPIC_DOMAIN_INVALID) | |
2208 | return 0; | |
2209 | ||
d32932d0 JL |
2210 | init_irq_alloc_info(&info, NULL); |
2211 | info.type = X86_IRQ_ALLOC_TYPE_IOAPIC; | |
2212 | info.ioapic_id = mpc_ioapic_id(ioapic); | |
2213 | parent = irq_remapping_get_ir_irq_domain(&info); | |
2214 | if (!parent) | |
2215 | parent = x86_vector_domain; | |
1b604745 TG |
2216 | else |
2217 | name = "IO-APIC-IR"; | |
2218 | ||
2219 | /* Handle device tree enumerated APICs proper */ | |
2220 | if (cfg->dev) { | |
2221 | fn = of_node_to_fwnode(cfg->dev); | |
2222 | } else { | |
2223 | fn = irq_domain_alloc_named_id_fwnode(name, ioapic); | |
2224 | if (!fn) | |
2225 | return -ENOMEM; | |
2226 | } | |
2227 | ||
2228 | ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops, | |
2229 | (void *)(long)ioapic); | |
2230 | ||
2231 | /* Release fw handle if it was allocated above */ | |
2232 | if (!cfg->dev) | |
2233 | irq_domain_free_fwnode(fn); | |
d32932d0 | 2234 | |
b75e818f | 2235 | if (!ip->irqdomain) |
44767bfa | 2236 | return -ENOMEM; |
b75e818f JL |
2237 | |
2238 | ip->irqdomain->parent = parent; | |
44767bfa JL |
2239 | |
2240 | if (cfg->type == IOAPIC_DOMAIN_LEGACY || | |
2241 | cfg->type == IOAPIC_DOMAIN_STRICT) | |
2242 | ioapic_dynirq_base = max(ioapic_dynirq_base, | |
2243 | gsi_cfg->gsi_end + 1); | |
2244 | ||
44767bfa JL |
2245 | return 0; |
2246 | } | |
2247 | ||
15516a3b JL |
2248 | static void ioapic_destroy_irqdomain(int idx) |
2249 | { | |
2250 | if (ioapics[idx].irqdomain) { | |
2251 | irq_domain_remove(ioapics[idx].irqdomain); | |
2252 | ioapics[idx].irqdomain = NULL; | |
2253 | } | |
15516a3b JL |
2254 | } |
2255 | ||
1da177e4 LT |
2256 | void __init setup_IO_APIC(void) |
2257 | { | |
44767bfa | 2258 | int ioapic; |
54168ed7 | 2259 | |
a46f5c89 TG |
2260 | if (skip_ioapic_setup || !nr_ioapics) |
2261 | return; | |
2262 | ||
95d76acc | 2263 | io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2264 | |
54168ed7 | 2265 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
44767bfa JL |
2266 | for_each_ioapic(ioapic) |
2267 | BUG_ON(mp_irqdomain_create(ioapic)); | |
2268 | ||
d6c88a50 | 2269 | /* |
54168ed7 IM |
2270 | * Set up IO-APIC IRQ routing. |
2271 | */ | |
de934103 TG |
2272 | x86_init.mpparse.setup_ioapic_ids(); |
2273 | ||
1da177e4 LT |
2274 | sync_Arb_IDs(); |
2275 | setup_IO_APIC_irqs(); | |
2276 | init_IO_APIC_traps(); | |
95d76acc | 2277 | if (nr_legacy_irqs()) |
bc07844a | 2278 | check_timer(); |
b81975ea JL |
2279 | |
2280 | ioapic_initialized = 1; | |
1da177e4 LT |
2281 | } |
2282 | ||
6f50d45f | 2283 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 2284 | { |
1da177e4 LT |
2285 | unsigned long flags; |
2286 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2287 | |
dade7716 | 2288 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
2289 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2290 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
2291 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
2292 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 2293 | } |
dade7716 | 2294 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2295 | } |
1da177e4 | 2296 | |
f3c6ea1b RW |
2297 | static void ioapic_resume(void) |
2298 | { | |
6f50d45f | 2299 | int ioapic_idx; |
f3c6ea1b | 2300 | |
f44d1692 | 2301 | for_each_ioapic_reverse(ioapic_idx) |
6f50d45f | 2302 | resume_ioapic_id(ioapic_idx); |
15bac20b SS |
2303 | |
2304 | restore_ioapic_entries(); | |
1da177e4 LT |
2305 | } |
2306 | ||
f3c6ea1b | 2307 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2308 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2309 | .resume = ioapic_resume, |
2310 | }; | |
2311 | ||
f3c6ea1b | 2312 | static int __init ioapic_init_ops(void) |
1da177e4 | 2313 | { |
f3c6ea1b RW |
2314 | register_syscore_ops(&ioapic_syscore_ops); |
2315 | ||
1da177e4 LT |
2316 | return 0; |
2317 | } | |
2318 | ||
f3c6ea1b | 2319 | device_initcall(ioapic_init_ops); |
1da177e4 | 2320 | |
67dc5e70 | 2321 | static int io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
2322 | { |
2323 | union IO_APIC_reg_01 reg_01; | |
2324 | unsigned long flags; | |
2325 | ||
dade7716 | 2326 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 2327 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2328 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 2329 | |
4b6b19a1 EB |
2330 | /* The register returns the maximum index redir index |
2331 | * supported, which is one less than the total number of redir | |
2332 | * entries. | |
2333 | */ | |
2334 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
2335 | } |
2336 | ||
62a08ae2 TG |
2337 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
2338 | { | |
b81975ea JL |
2339 | /* |
2340 | * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use | |
2341 | * gsi_top if ioapic_dynirq_base hasn't been initialized yet. | |
2342 | */ | |
2343 | return ioapic_initialized ? ioapic_dynirq_base : gsi_top; | |
62a08ae2 TG |
2344 | } |
2345 | ||
54168ed7 | 2346 | #ifdef CONFIG_X86_32 |
67dc5e70 | 2347 | static int io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2348 | { |
2349 | union IO_APIC_reg_00 reg_00; | |
2350 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2351 | physid_mask_t tmp; | |
2352 | unsigned long flags; | |
2353 | int i = 0; | |
2354 | ||
2355 | /* | |
36062448 PC |
2356 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2357 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2358 | * supports up to 16 on one shared APIC bus. |
36062448 | 2359 | * |
1da177e4 LT |
2360 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2361 | * advantage of new APIC bus architecture. | |
2362 | */ | |
2363 | ||
2364 | if (physids_empty(apic_id_map)) | |
7abc0753 | 2365 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 2366 | |
dade7716 | 2367 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2368 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 2369 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2370 | |
2371 | if (apic_id >= get_physical_broadcast()) { | |
2372 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2373 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2374 | apic_id = reg_00.bits.ID; | |
2375 | } | |
2376 | ||
2377 | /* | |
36062448 | 2378 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2379 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2380 | */ | |
7abc0753 | 2381 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
2382 | |
2383 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 2384 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
2385 | break; |
2386 | } | |
2387 | ||
2388 | if (i == get_physical_broadcast()) | |
2389 | panic("Max apic_id exceeded!\n"); | |
2390 | ||
2391 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2392 | "trying %d\n", ioapic, apic_id, i); | |
2393 | ||
2394 | apic_id = i; | |
36062448 | 2395 | } |
1da177e4 | 2396 | |
7abc0753 | 2397 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
2398 | physids_or(apic_id_map, apic_id_map, tmp); |
2399 | ||
2400 | if (reg_00.bits.ID != apic_id) { | |
2401 | reg_00.bits.ID = apic_id; | |
2402 | ||
dade7716 | 2403 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
2404 | io_apic_write(ioapic, 0, reg_00.raw); |
2405 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 2406 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2407 | |
2408 | /* Sanity check */ | |
6070f9ec | 2409 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
2410 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
2411 | ioapic); | |
6070f9ec AD |
2412 | return -1; |
2413 | } | |
1da177e4 LT |
2414 | } |
2415 | ||
2416 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2417 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2418 | ||
2419 | return apic_id; | |
2420 | } | |
41098ffe | 2421 | |
67dc5e70 | 2422 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe TG |
2423 | { |
2424 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
cff9ab2b | 2425 | !APIC_XAPIC(boot_cpu_apic_version)) |
5411dc4c | 2426 | return io_apic_get_unique_id(idx, id); |
41098ffe TG |
2427 | else |
2428 | return id; | |
2429 | } | |
2430 | #else | |
67dc5e70 | 2431 | static u8 io_apic_unique_id(int idx, u8 id) |
41098ffe | 2432 | { |
5411dc4c | 2433 | union IO_APIC_reg_00 reg_00; |
41098ffe | 2434 | DECLARE_BITMAP(used, 256); |
5411dc4c YL |
2435 | unsigned long flags; |
2436 | u8 new_id; | |
2437 | int i; | |
41098ffe TG |
2438 | |
2439 | bitmap_zero(used, 256); | |
f44d1692 | 2440 | for_each_ioapic(i) |
d5371430 | 2441 | __set_bit(mpc_ioapic_id(i), used); |
5411dc4c YL |
2442 | |
2443 | /* Hand out the requested id if available */ | |
41098ffe TG |
2444 | if (!test_bit(id, used)) |
2445 | return id; | |
5411dc4c YL |
2446 | |
2447 | /* | |
2448 | * Read the current id from the ioapic and keep it if | |
2449 | * available. | |
2450 | */ | |
2451 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2452 | reg_00.raw = io_apic_read(idx, 0); | |
2453 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2454 | new_id = reg_00.bits.ID; | |
2455 | if (!test_bit(new_id, used)) { | |
2456 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2457 | "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", | |
2458 | idx, new_id, id); | |
2459 | return new_id; | |
2460 | } | |
2461 | ||
2462 | /* | |
2463 | * Get the next free id and write it to the ioapic. | |
2464 | */ | |
2465 | new_id = find_first_zero_bit(used, 256); | |
2466 | reg_00.bits.ID = new_id; | |
2467 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2468 | io_apic_write(idx, 0, reg_00.raw); | |
2469 | reg_00.raw = io_apic_read(idx, 0); | |
2470 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2471 | /* Sanity check */ | |
2472 | BUG_ON(reg_00.bits.ID != new_id); | |
2473 | ||
2474 | return new_id; | |
41098ffe | 2475 | } |
58f892e0 | 2476 | #endif |
1da177e4 | 2477 | |
67dc5e70 | 2478 | static int io_apic_get_version(int ioapic) |
1da177e4 LT |
2479 | { |
2480 | union IO_APIC_reg_01 reg_01; | |
2481 | unsigned long flags; | |
2482 | ||
dade7716 | 2483 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 2484 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 2485 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2486 | |
2487 | return reg_01.bits.version; | |
2488 | } | |
2489 | ||
9a0a91bb | 2490 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 2491 | { |
9a0a91bb | 2492 | int ioapic, pin, idx; |
61fd47e0 SL |
2493 | |
2494 | if (skip_ioapic_setup) | |
2495 | return -1; | |
2496 | ||
9a0a91bb EB |
2497 | ioapic = mp_find_ioapic(gsi); |
2498 | if (ioapic < 0) | |
61fd47e0 SL |
2499 | return -1; |
2500 | ||
9a0a91bb EB |
2501 | pin = mp_find_ioapic_pin(ioapic, gsi); |
2502 | if (pin < 0) | |
2503 | return -1; | |
2504 | ||
2505 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
2506 | if (idx < 0) | |
61fd47e0 SL |
2507 | return -1; |
2508 | ||
9a0a91bb EB |
2509 | *trigger = irq_trigger(idx); |
2510 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
2511 | return 0; |
2512 | } | |
2513 | ||
497c9a19 YL |
2514 | /* |
2515 | * This function currently is only a helper for the i386 smp boot process where | |
2516 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 2517 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
2518 | */ |
2519 | #ifdef CONFIG_SMP | |
2520 | void __init setup_ioapic_dest(void) | |
2521 | { | |
fad53995 | 2522 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 2523 | const struct cpumask *mask; |
e23b257c | 2524 | struct irq_desc *desc; |
5451ddc5 | 2525 | struct irq_data *idata; |
4857c91f | 2526 | struct irq_chip *chip; |
497c9a19 YL |
2527 | |
2528 | if (skip_ioapic_setup == 1) | |
2529 | return; | |
2530 | ||
f44d1692 | 2531 | for_each_ioapic_pin(ioapic, pin) { |
b9c61b70 YL |
2532 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
2533 | if (irq_entry == -1) | |
2534 | continue; | |
6c2e9403 | 2535 | |
d7f3d478 JL |
2536 | irq = pin_2_irq(irq_entry, ioapic, pin, 0); |
2537 | if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq)) | |
fad53995 EB |
2538 | continue; |
2539 | ||
e23b257c TG |
2540 | desc = irq_to_desc(irq); |
2541 | raw_spin_lock_irq(&desc->lock); | |
2542 | idata = irq_desc_get_irq_data(desc); | |
6c2e9403 | 2543 | |
b9c61b70 YL |
2544 | /* |
2545 | * Honour affinities which have been set in early boot | |
2546 | */ | |
5451ddc5 | 2547 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
c149e4cd | 2548 | mask = irq_data_get_affinity_mask(idata); |
b9c61b70 YL |
2549 | else |
2550 | mask = apic->target_cpus(); | |
497c9a19 | 2551 | |
4857c91f | 2552 | chip = irq_data_get_irq_chip(idata); |
ababae44 WP |
2553 | /* Might be lapic_chip for irq 0 */ |
2554 | if (chip->irq_set_affinity) | |
2555 | chip->irq_set_affinity(idata, mask, false); | |
e23b257c | 2556 | raw_spin_unlock_irq(&desc->lock); |
497c9a19 YL |
2557 | } |
2558 | } | |
2559 | #endif | |
2560 | ||
54168ed7 IM |
2561 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
2562 | ||
2563 | static struct resource *ioapic_resources; | |
2564 | ||
f44d1692 | 2565 | static struct resource * __init ioapic_setup_resources(void) |
54168ed7 IM |
2566 | { |
2567 | unsigned long n; | |
2568 | struct resource *res; | |
2569 | char *mem; | |
4855531e | 2570 | int i; |
54168ed7 | 2571 | |
4855531e | 2572 | if (nr_ioapics == 0) |
54168ed7 IM |
2573 | return NULL; |
2574 | ||
2575 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4855531e | 2576 | n *= nr_ioapics; |
54168ed7 IM |
2577 | |
2578 | mem = alloc_bootmem(n); | |
2579 | res = (void *)mem; | |
2580 | ||
4855531e | 2581 | mem += sizeof(struct resource) * nr_ioapics; |
54168ed7 | 2582 | |
f44d1692 | 2583 | for_each_ioapic(i) { |
4855531e RW |
2584 | res[i].name = mem; |
2585 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 2586 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 2587 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
4855531e | 2588 | ioapics[i].iomem_res = &res[i]; |
54168ed7 IM |
2589 | } |
2590 | ||
2591 | ioapic_resources = res; | |
2592 | ||
2593 | return res; | |
2594 | } | |
54168ed7 | 2595 | |
ca1b8862 | 2596 | void __init io_apic_init_mappings(void) |
f3294a33 YL |
2597 | { |
2598 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 2599 | struct resource *ioapic_res; |
d6c88a50 | 2600 | int i; |
f3294a33 | 2601 | |
f44d1692 JL |
2602 | ioapic_res = ioapic_setup_resources(); |
2603 | for_each_ioapic(i) { | |
f3294a33 | 2604 | if (smp_found_config) { |
d5371430 | 2605 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 2606 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
2607 | if (!ioapic_phys) { |
2608 | printk(KERN_ERR | |
2609 | "WARNING: bogus zero IO-APIC " | |
2610 | "address found in MPTABLE, " | |
2611 | "disabling IO/APIC support!\n"); | |
2612 | smp_found_config = 0; | |
2613 | skip_ioapic_setup = 1; | |
2614 | goto fake_ioapic_page; | |
2615 | } | |
54168ed7 | 2616 | #endif |
f3294a33 | 2617 | } else { |
54168ed7 | 2618 | #ifdef CONFIG_X86_32 |
f3294a33 | 2619 | fake_ioapic_page: |
54168ed7 | 2620 | #endif |
e79c65a9 | 2621 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
2622 | ioapic_phys = __pa(ioapic_phys); |
2623 | } | |
2624 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
2625 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
2626 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
2627 | ioapic_phys); | |
f3294a33 | 2628 | idx++; |
54168ed7 | 2629 | |
ffc43836 | 2630 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 2631 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 2632 | ioapic_res++; |
f3294a33 YL |
2633 | } |
2634 | } | |
2635 | ||
857fdc53 | 2636 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
2637 | { |
2638 | int i; | |
2639 | struct resource *r = ioapic_resources; | |
2640 | ||
2641 | if (!r) { | |
857fdc53 | 2642 | if (nr_ioapics > 0) |
04c93ce4 BZ |
2643 | printk(KERN_ERR |
2644 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 2645 | return; |
54168ed7 IM |
2646 | } |
2647 | ||
f44d1692 | 2648 | for_each_ioapic(i) { |
54168ed7 IM |
2649 | insert_resource(&iomem_resource, r); |
2650 | r++; | |
2651 | } | |
54168ed7 | 2652 | } |
2a4ab640 | 2653 | |
eddb0c55 | 2654 | int mp_find_ioapic(u32 gsi) |
2a4ab640 | 2655 | { |
f44d1692 | 2656 | int i; |
2a4ab640 | 2657 | |
678301ec PB |
2658 | if (nr_ioapics == 0) |
2659 | return -1; | |
2660 | ||
2a4ab640 | 2661 | /* Find the IOAPIC that manages this GSI. */ |
f44d1692 | 2662 | for_each_ioapic(i) { |
c040aaeb | 2663 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
f44d1692 | 2664 | if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) |
2a4ab640 FT |
2665 | return i; |
2666 | } | |
54168ed7 | 2667 | |
2a4ab640 FT |
2668 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
2669 | return -1; | |
2670 | } | |
2671 | ||
eddb0c55 | 2672 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 2673 | { |
c040aaeb SS |
2674 | struct mp_ioapic_gsi *gsi_cfg; |
2675 | ||
f44d1692 | 2676 | if (WARN_ON(ioapic < 0)) |
2a4ab640 | 2677 | return -1; |
c040aaeb SS |
2678 | |
2679 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2680 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
2681 | return -1; |
2682 | ||
c040aaeb | 2683 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
2684 | } |
2685 | ||
67dc5e70 | 2686 | static int bad_ioapic_register(int idx) |
73d63d03 SS |
2687 | { |
2688 | union IO_APIC_reg_00 reg_00; | |
2689 | union IO_APIC_reg_01 reg_01; | |
2690 | union IO_APIC_reg_02 reg_02; | |
2691 | ||
2692 | reg_00.raw = io_apic_read(idx, 0); | |
2693 | reg_01.raw = io_apic_read(idx, 1); | |
2694 | reg_02.raw = io_apic_read(idx, 2); | |
2695 | ||
2696 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
2697 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
2698 | mpc_ioapic_addr(idx)); | |
2699 | return 1; | |
2700 | } | |
2701 | ||
2702 | return 0; | |
2703 | } | |
2704 | ||
35ef9c94 JL |
2705 | static int find_free_ioapic_entry(void) |
2706 | { | |
7db298cb JL |
2707 | int idx; |
2708 | ||
2709 | for (idx = 0; idx < MAX_IO_APICS; idx++) | |
2710 | if (ioapics[idx].nr_registers == 0) | |
2711 | return idx; | |
2712 | ||
2713 | return MAX_IO_APICS; | |
35ef9c94 JL |
2714 | } |
2715 | ||
2716 | /** | |
2717 | * mp_register_ioapic - Register an IOAPIC device | |
2718 | * @id: hardware IOAPIC ID | |
2719 | * @address: physical address of IOAPIC register area | |
2720 | * @gsi_base: base of GSI associated with the IOAPIC | |
2721 | * @cfg: configuration information for the IOAPIC | |
2722 | */ | |
2723 | int mp_register_ioapic(int id, u32 address, u32 gsi_base, | |
2724 | struct ioapic_domain_cfg *cfg) | |
2a4ab640 | 2725 | { |
7db298cb | 2726 | bool hotplug = !!ioapic_initialized; |
c040aaeb | 2727 | struct mp_ioapic_gsi *gsi_cfg; |
35ef9c94 JL |
2728 | int idx, ioapic, entries; |
2729 | u32 gsi_end; | |
2a4ab640 | 2730 | |
35ef9c94 JL |
2731 | if (!address) { |
2732 | pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); | |
2733 | return -EINVAL; | |
2734 | } | |
2735 | for_each_ioapic(ioapic) | |
2736 | if (ioapics[ioapic].mp_config.apicaddr == address) { | |
2737 | pr_warn("address 0x%x conflicts with IOAPIC%d\n", | |
2738 | address, ioapic); | |
2739 | return -EEXIST; | |
2740 | } | |
2a4ab640 | 2741 | |
35ef9c94 JL |
2742 | idx = find_free_ioapic_entry(); |
2743 | if (idx >= MAX_IO_APICS) { | |
2744 | pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n", | |
2745 | MAX_IO_APICS, idx); | |
2746 | return -ENOSPC; | |
2747 | } | |
2a4ab640 | 2748 | |
d5371430 SS |
2749 | ioapics[idx].mp_config.type = MP_IOAPIC; |
2750 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
2751 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
2752 | |
2753 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
2754 | if (bad_ioapic_register(idx)) { |
2755 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
35ef9c94 | 2756 | return -ENODEV; |
73d63d03 SS |
2757 | } |
2758 | ||
5411dc4c | 2759 | ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id); |
d5371430 | 2760 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); |
2a4ab640 FT |
2761 | |
2762 | /* | |
2763 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
2764 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
2765 | */ | |
7716a5c4 | 2766 | entries = io_apic_get_redir_entries(idx); |
35ef9c94 JL |
2767 | gsi_end = gsi_base + entries - 1; |
2768 | for_each_ioapic(ioapic) { | |
2769 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
2770 | if ((gsi_base >= gsi_cfg->gsi_base && | |
2771 | gsi_base <= gsi_cfg->gsi_end) || | |
2772 | (gsi_end >= gsi_cfg->gsi_base && | |
2773 | gsi_end <= gsi_cfg->gsi_end)) { | |
2774 | pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", | |
2775 | gsi_base, gsi_end, | |
2776 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2777 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
2778 | return -ENOSPC; | |
2779 | } | |
2780 | } | |
c040aaeb SS |
2781 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
2782 | gsi_cfg->gsi_base = gsi_base; | |
35ef9c94 | 2783 | gsi_cfg->gsi_end = gsi_end; |
7716a5c4 | 2784 | |
35ef9c94 JL |
2785 | ioapics[idx].irqdomain = NULL; |
2786 | ioapics[idx].irqdomain_cfg = *cfg; | |
2a4ab640 | 2787 | |
7db298cb JL |
2788 | /* |
2789 | * If mp_register_ioapic() is called during early boot stage when | |
2790 | * walking ACPI/SFI/DT tables, it's too early to create irqdomain, | |
2791 | * we are still using bootmem allocator. So delay it to setup_IO_APIC(). | |
2792 | */ | |
2793 | if (hotplug) { | |
2794 | if (mp_irqdomain_create(idx)) { | |
2795 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
2796 | return -ENOMEM; | |
2797 | } | |
2798 | alloc_ioapic_saved_registers(idx); | |
2799 | } | |
2800 | ||
c040aaeb SS |
2801 | if (gsi_cfg->gsi_end >= gsi_top) |
2802 | gsi_top = gsi_cfg->gsi_end + 1; | |
35ef9c94 JL |
2803 | if (nr_ioapics <= idx) |
2804 | nr_ioapics = idx + 1; | |
2805 | ||
2806 | /* Set nr_registers to mark entry present */ | |
2807 | ioapics[idx].nr_registers = entries; | |
2a4ab640 | 2808 | |
73d63d03 SS |
2809 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
2810 | idx, mpc_ioapic_id(idx), | |
2811 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
2812 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 | 2813 | |
35ef9c94 | 2814 | return 0; |
2a4ab640 | 2815 | } |
05ddafb1 | 2816 | |
15516a3b JL |
2817 | int mp_unregister_ioapic(u32 gsi_base) |
2818 | { | |
2819 | int ioapic, pin; | |
2820 | int found = 0; | |
15516a3b JL |
2821 | |
2822 | for_each_ioapic(ioapic) | |
2823 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) { | |
2824 | found = 1; | |
2825 | break; | |
2826 | } | |
2827 | if (!found) { | |
2828 | pr_warn("can't find IOAPIC for GSI %d\n", gsi_base); | |
2829 | return -ENODEV; | |
2830 | } | |
2831 | ||
2832 | for_each_pin(ioapic, pin) { | |
d32932d0 JL |
2833 | u32 gsi = mp_pin_to_gsi(ioapic, pin); |
2834 | int irq = mp_map_gsi_to_irq(gsi, 0, NULL); | |
2835 | struct mp_chip_data *data; | |
2836 | ||
2837 | if (irq >= 0) { | |
2838 | data = irq_get_chip_data(irq); | |
2839 | if (data && data->count) { | |
2840 | pr_warn("pin%d on IOAPIC%d is still in use.\n", | |
2841 | pin, ioapic); | |
2842 | return -EBUSY; | |
2843 | } | |
15516a3b JL |
2844 | } |
2845 | } | |
2846 | ||
2847 | /* Mark entry not present */ | |
2848 | ioapics[ioapic].nr_registers = 0; | |
2849 | ioapic_destroy_irqdomain(ioapic); | |
2850 | free_ioapic_saved_registers(ioapic); | |
2851 | if (ioapics[ioapic].iomem_res) | |
2852 | release_resource(ioapics[ioapic].iomem_res); | |
2853 | clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic); | |
2854 | memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic])); | |
2855 | ||
2856 | return 0; | |
2857 | } | |
2858 | ||
e89900c9 JL |
2859 | int mp_ioapic_registered(u32 gsi_base) |
2860 | { | |
2861 | int ioapic; | |
2862 | ||
2863 | for_each_ioapic(ioapic) | |
2864 | if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) | |
2865 | return 1; | |
2866 | ||
2867 | return 0; | |
2868 | } | |
2869 | ||
49c7e600 | 2870 | static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data, |
5ad274d4 | 2871 | struct irq_alloc_info *info) |
49c7e600 JL |
2872 | { |
2873 | if (info && info->ioapic_valid) { | |
2874 | data->trigger = info->ioapic_trigger; | |
2875 | data->polarity = info->ioapic_polarity; | |
2876 | } else if (acpi_get_override_irq(gsi, &data->trigger, | |
2877 | &data->polarity) < 0) { | |
335efdf5 TG |
2878 | /* PCI interrupts are always active low level triggered. */ |
2879 | data->trigger = IOAPIC_LEVEL; | |
2880 | data->polarity = IOAPIC_POL_LOW; | |
49c7e600 JL |
2881 | } |
2882 | } | |
2883 | ||
2884 | static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data, | |
2885 | struct IO_APIC_route_entry *entry) | |
2886 | { | |
2887 | memset(entry, 0, sizeof(*entry)); | |
2888 | entry->delivery_mode = apic->irq_delivery_mode; | |
2889 | entry->dest_mode = apic->irq_dest_mode; | |
2890 | entry->dest = cfg->dest_apicid; | |
2891 | entry->vector = cfg->vector; | |
49c7e600 JL |
2892 | entry->trigger = data->trigger; |
2893 | entry->polarity = data->polarity; | |
2894 | /* | |
335efdf5 TG |
2895 | * Mask level triggered irqs. Edge triggered irqs are masked |
2896 | * by the irq core code in case they fire. | |
49c7e600 | 2897 | */ |
335efdf5 TG |
2898 | if (data->trigger == IOAPIC_LEVEL) |
2899 | entry->mask = IOAPIC_MASKED; | |
2900 | else | |
2901 | entry->mask = IOAPIC_UNMASKED; | |
49c7e600 JL |
2902 | } |
2903 | ||
2904 | int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, | |
2905 | unsigned int nr_irqs, void *arg) | |
2906 | { | |
2907 | int ret, ioapic, pin; | |
2908 | struct irq_cfg *cfg; | |
2909 | struct irq_data *irq_data; | |
2910 | struct mp_chip_data *data; | |
2911 | struct irq_alloc_info *info = arg; | |
c0ff971e | 2912 | unsigned long flags; |
49c7e600 JL |
2913 | |
2914 | if (!info || nr_irqs > 1) | |
2915 | return -EINVAL; | |
2916 | irq_data = irq_domain_get_irq_data(domain, virq); | |
2917 | if (!irq_data) | |
2918 | return -EINVAL; | |
2919 | ||
2920 | ioapic = mp_irqdomain_ioapic_idx(domain); | |
2921 | pin = info->ioapic_pin; | |
2922 | if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) | |
2923 | return -EEXIST; | |
2924 | ||
2925 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
2926 | if (!data) | |
2927 | return -ENOMEM; | |
2928 | ||
2929 | info->ioapic_entry = &data->entry; | |
2930 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); | |
2931 | if (ret < 0) { | |
2932 | kfree(data); | |
2933 | return ret; | |
2934 | } | |
2935 | ||
4467715a | 2936 | INIT_LIST_HEAD(&data->irq_2_pin); |
49c7e600 | 2937 | irq_data->hwirq = info->ioapic_pin; |
d32932d0 JL |
2938 | irq_data->chip = (domain->parent == x86_vector_domain) ? |
2939 | &ioapic_chip : &ioapic_ir_chip; | |
49c7e600 JL |
2940 | irq_data->chip_data = data; |
2941 | mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); | |
2942 | ||
2943 | cfg = irqd_cfg(irq_data); | |
4467715a | 2944 | add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin); |
c0ff971e VK |
2945 | |
2946 | local_irq_save(flags); | |
49c7e600 JL |
2947 | if (info->ioapic_entry) |
2948 | mp_setup_entry(cfg, data, info->ioapic_entry); | |
2949 | mp_register_handler(virq, data->trigger); | |
2950 | if (virq < nr_legacy_irqs()) | |
2951 | legacy_pic->mask(virq); | |
c0ff971e | 2952 | local_irq_restore(flags); |
49c7e600 JL |
2953 | |
2954 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
2955 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n", | |
2956 | ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector, | |
2957 | virq, data->trigger, data->polarity, cfg->dest_apicid); | |
2958 | ||
2959 | return 0; | |
2960 | } | |
2961 | ||
2962 | void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq, | |
2963 | unsigned int nr_irqs) | |
2964 | { | |
49c7e600 | 2965 | struct irq_data *irq_data; |
4467715a | 2966 | struct mp_chip_data *data; |
49c7e600 JL |
2967 | |
2968 | BUG_ON(nr_irqs != 1); | |
2969 | irq_data = irq_domain_get_irq_data(domain, virq); | |
2970 | if (irq_data && irq_data->chip_data) { | |
4467715a JL |
2971 | data = irq_data->chip_data; |
2972 | __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), | |
49c7e600 | 2973 | (int)irq_data->hwirq); |
4467715a | 2974 | WARN_ON(!list_empty(&data->irq_2_pin)); |
49c7e600 JL |
2975 | kfree(irq_data->chip_data); |
2976 | } | |
2977 | irq_domain_free_irqs_top(domain, virq, nr_irqs); | |
2978 | } | |
2979 | ||
2980 | void mp_irqdomain_activate(struct irq_domain *domain, | |
2981 | struct irq_data *irq_data) | |
2982 | { | |
2983 | unsigned long flags; | |
2984 | struct irq_pin_list *entry; | |
2985 | struct mp_chip_data *data = irq_data->chip_data; | |
49c7e600 JL |
2986 | |
2987 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
4467715a | 2988 | for_each_irq_pin(entry, data->irq_2_pin) |
49c7e600 JL |
2989 | __ioapic_write_entry(entry->apic, entry->pin, data->entry); |
2990 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2991 | } | |
2992 | ||
2993 | void mp_irqdomain_deactivate(struct irq_domain *domain, | |
2994 | struct irq_data *irq_data) | |
2995 | { | |
2996 | /* It won't be called for IRQ with multiple IOAPIC pins associated */ | |
2997 | ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), | |
2998 | (int)irq_data->hwirq); | |
2999 | } | |
3000 | ||
49c7e600 JL |
3001 | int mp_irqdomain_ioapic_idx(struct irq_domain *domain) |
3002 | { | |
3003 | return (int)(long)domain->host_data; | |
3004 | } | |
f7a0c786 TG |
3005 | |
3006 | const struct irq_domain_ops mp_ioapic_irqdomain_ops = { | |
3007 | .alloc = mp_irqdomain_alloc, | |
3008 | .free = mp_irqdomain_free, | |
3009 | .activate = mp_irqdomain_activate, | |
3010 | .deactivate = mp_irqdomain_deactivate, | |
3011 | }; |