Commit | Line | Data |
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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Local APIC handling, local APIC timers | |
4 | * | |
8f47e163 | 5 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
6 | * |
7 | * Fixes | |
8 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
9 | * thanks to Eric Gilmore | |
10 | * and Rolf G. Tews | |
11 | * for testing these extensively. | |
12 | * Maciej W. Rozycki : Various updates and fixes. | |
13 | * Mikael Pettersson : Power Management for UP-APIC. | |
14 | * Pavel Machek and | |
15 | * Mikael Pettersson : PM converted to driver model. | |
16 | */ | |
17 | ||
cdd6c482 | 18 | #include <linux/perf_event.h> |
1da177e4 | 19 | #include <linux/kernel_stat.h> |
d1de36f5 | 20 | #include <linux/mc146818rtc.h> |
70a20025 | 21 | #include <linux/acpi_pmtmr.h> |
350b5e27 | 22 | #include <linux/bitmap.h> |
d1de36f5 IM |
23 | #include <linux/clockchips.h> |
24 | #include <linux/interrupt.h> | |
57c8a661 | 25 | #include <linux/memblock.h> |
d1de36f5 IM |
26 | #include <linux/ftrace.h> |
27 | #include <linux/ioport.h> | |
186f4360 | 28 | #include <linux/export.h> |
f3c6ea1b | 29 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
30 | #include <linux/delay.h> |
31 | #include <linux/timex.h> | |
334955ef | 32 | #include <linux/i8253.h> |
6e1cb38a | 33 | #include <linux/dmar.h> |
d1de36f5 IM |
34 | #include <linux/init.h> |
35 | #include <linux/cpu.h> | |
36 | #include <linux/dmi.h> | |
d1de36f5 IM |
37 | #include <linux/smp.h> |
38 | #include <linux/mm.h> | |
1da177e4 | 39 | |
965e05ff TG |
40 | #include <xen/xen.h> |
41 | ||
83ab8514 | 42 | #include <asm/trace/irq_vectors.h> |
8a8f422d | 43 | #include <asm/irq_remapping.h> |
fb6a0408 | 44 | #include <asm/pc-conf-reg.h> |
cdd6c482 | 45 | #include <asm/perf_event.h> |
736decac | 46 | #include <asm/x86_init.h> |
60063497 | 47 | #include <linux/atomic.h> |
25a068b8 | 48 | #include <asm/barrier.h> |
1da177e4 | 49 | #include <asm/mpspec.h> |
d1de36f5 | 50 | #include <asm/i8259.h> |
73dea47f | 51 | #include <asm/proto.h> |
ad3bc25a | 52 | #include <asm/traps.h> |
2c8c0e6b | 53 | #include <asm/apic.h> |
13c01139 | 54 | #include <asm/acpi.h> |
7167d08e | 55 | #include <asm/io_apic.h> |
d1de36f5 IM |
56 | #include <asm/desc.h> |
57 | #include <asm/hpet.h> | |
d1de36f5 | 58 | #include <asm/mtrr.h> |
16f871bc | 59 | #include <asm/time.h> |
2bc13797 | 60 | #include <asm/smp.h> |
be71b855 | 61 | #include <asm/mce.h> |
8c3ba8d0 | 62 | #include <asm/tsc.h> |
2904ed8d | 63 | #include <asm/hypervisor.h> |
bd9240a1 PZ |
64 | #include <asm/cpu_device_id.h> |
65 | #include <asm/intel-family.h> | |
447ae316 | 66 | #include <asm/irq_regs.h> |
b8d1d163 | 67 | #include <asm/cpu.h> |
1da177e4 | 68 | |
79c9a17c TG |
69 | #include "local.h" |
70 | ||
ec70de8b | 71 | /* Processor that is doing the boot up */ |
4705243d | 72 | u32 boot_cpu_physical_apicid __ro_after_init = BAD_APICID; |
cc08e04c | 73 | EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); |
5af5573e | 74 | |
6444b40e | 75 | u8 boot_cpu_apic_version __ro_after_init; |
cff9ab2b | 76 | |
b7c4948e HK |
77 | /* |
78 | * This variable controls which CPUs receive external NMIs. By default, | |
79 | * external NMIs are delivered only to the BSP. | |
80 | */ | |
6444b40e | 81 | static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP; |
b7c4948e | 82 | |
ab0f59c6 DW |
83 | /* |
84 | * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID | |
85 | */ | |
86 | static bool virt_ext_dest_id __ro_after_init; | |
87 | ||
bea629d5 TG |
88 | /* For parallel bootup. */ |
89 | unsigned long apic_mmio_base __ro_after_init; | |
90 | ||
78c32000 TG |
91 | static inline bool apic_accessible(void) |
92 | { | |
93 | return x2apic_mode || apic_mmio_base; | |
94 | } | |
95 | ||
b3c51170 | 96 | #ifdef CONFIG_X86_32 |
f28c0ae2 | 97 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
6444b40e | 98 | static int enabled_via_apicbase __ro_after_init; |
f28c0ae2 | 99 | |
c0eaa453 CG |
100 | /* |
101 | * Handle interrupt mode configuration register (IMCR). | |
102 | * This register controls whether the interrupt signals | |
103 | * that reach the BSP come from the master PIC or from the | |
104 | * local APIC. Before entering Symmetric I/O Mode, either | |
105 | * the BIOS or the operating system must switch out of | |
106 | * PIC Mode by changing the IMCR. | |
107 | */ | |
5cda395f | 108 | static inline void imcr_pic_to_apic(void) |
c0eaa453 | 109 | { |
c0eaa453 | 110 | /* NMI and 8259 INTR go through APIC */ |
fb6a0408 | 111 | pc_conf_set(PC_CONF_MPS_IMCR, 0x01); |
c0eaa453 CG |
112 | } |
113 | ||
5cda395f | 114 | static inline void imcr_apic_to_pic(void) |
c0eaa453 | 115 | { |
c0eaa453 | 116 | /* NMI and 8259 INTR go directly to BSP */ |
fb6a0408 | 117 | pc_conf_set(PC_CONF_MPS_IMCR, 0x00); |
c0eaa453 | 118 | } |
b3c51170 YL |
119 | #endif |
120 | ||
279f1461 SS |
121 | /* |
122 | * Knob to control our willingness to enable the local APIC. | |
123 | * | |
124 | * +1=force-enable | |
125 | */ | |
126 | static int force_enable_local_apic __initdata; | |
dc9788f4 | 127 | |
279f1461 SS |
128 | /* |
129 | * APIC command line parameters | |
130 | */ | |
131 | static int __init parse_lapic(char *arg) | |
132 | { | |
97f2645f | 133 | if (IS_ENABLED(CONFIG_X86_32) && !arg) |
279f1461 | 134 | force_enable_local_apic = 1; |
27cf9298 | 135 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
279f1461 SS |
136 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
137 | return 0; | |
138 | } | |
139 | early_param("lapic", parse_lapic); | |
140 | ||
b3c51170 | 141 | #ifdef CONFIG_X86_64 |
bc1d99c1 | 142 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
143 | static __init int setup_apicpmtimer(char *s) |
144 | { | |
145 | apic_calibrate_pmtmr = 1; | |
146 | notsc_setup(NULL); | |
12441ccd | 147 | return 1; |
b3c51170 YL |
148 | } |
149 | __setup("apicpmtimer", setup_apicpmtimer); | |
150 | #endif | |
151 | ||
81287ad6 | 152 | static unsigned long mp_lapic_addr __ro_after_init; |
49062454 | 153 | bool apic_is_disabled __ro_after_init; |
b3c51170 | 154 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
25874a29 | 155 | static int disable_apic_timer __initdata; |
e83a5fdc | 156 | /* Local APIC timer works in C2 */ |
6444b40e | 157 | int local_apic_timer_c2_ok __ro_after_init; |
2e7c2838 LT |
158 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); |
159 | ||
e83a5fdc HS |
160 | /* |
161 | * Debug level, exported for io_apic.c | |
162 | */ | |
6444b40e | 163 | int apic_verbosity __ro_after_init; |
e83a5fdc | 164 | |
6444b40e | 165 | int pic_mode __ro_after_init; |
89c38c28 | 166 | |
bab4b27c | 167 | /* Have we found an MP table */ |
6444b40e | 168 | int smp_found_config __ro_after_init; |
bab4b27c | 169 | |
39928722 AD |
170 | static struct resource lapic_resource = { |
171 | .name = "Local APIC", | |
172 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
173 | }; | |
174 | ||
52ae346b | 175 | unsigned int lapic_timer_period = 0; |
d03030e9 | 176 | |
0e078e2f | 177 | static void apic_pm_activate(void); |
ba7eda4c | 178 | |
0e078e2f TG |
179 | /* |
180 | * Get the LAPIC version | |
181 | */ | |
182 | static inline int lapic_get_version(void) | |
ba7eda4c | 183 | { |
0e078e2f | 184 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
185 | } |
186 | ||
0e078e2f | 187 | /* |
9c803869 | 188 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
189 | */ |
190 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 191 | { |
9c803869 | 192 | return APIC_INTEGRATED(lapic_get_version()); |
ba7eda4c TG |
193 | } |
194 | ||
195 | /* | |
0e078e2f | 196 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 197 | */ |
0e078e2f | 198 | static int modern_apic(void) |
ba7eda4c | 199 | { |
0e078e2f TG |
200 | /* AMD systems use old APIC versions, so check the CPU */ |
201 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
202 | boot_cpu_data.x86 >= 0xf) | |
203 | return 1; | |
da33dfef PW |
204 | |
205 | /* Hygon systems use modern APIC */ | |
206 | if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) | |
207 | return 1; | |
208 | ||
0e078e2f | 209 | return lapic_get_version() >= 0x14; |
ba7eda4c TG |
210 | } |
211 | ||
08306ce6 | 212 | /* |
a933c618 CG |
213 | * right after this call apic become NOOP driven |
214 | * so apic->write/read doesn't do anything | |
08306ce6 | 215 | */ |
25874a29 | 216 | static void __init apic_disable(void) |
08306ce6 | 217 | { |
3af1e415 | 218 | apic_install_driver(&apic_noop); |
08306ce6 CG |
219 | } |
220 | ||
c1eeb2de | 221 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 222 | { |
ea7bdc65 JK |
223 | unsigned long flags; |
224 | ||
225 | local_irq_save(flags); | |
bf348f66 | 226 | apic_write(APIC_ICR2, SET_XAPIC_DEST_FIELD(id)); |
1b374e4d | 227 | apic_write(APIC_ICR, low); |
ea7bdc65 | 228 | local_irq_restore(flags); |
1b374e4d SS |
229 | } |
230 | ||
c1eeb2de | 231 | u64 native_apic_icr_read(void) |
1b374e4d SS |
232 | { |
233 | u32 icr1, icr2; | |
234 | ||
235 | icr2 = apic_read(APIC_ICR2); | |
236 | icr1 = apic_read(APIC_ICR); | |
237 | ||
cf9768d7 | 238 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
239 | } |
240 | ||
0e078e2f TG |
241 | /** |
242 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
243 | */ | |
37e650c7 | 244 | int lapic_get_maxlvt(void) |
1da177e4 | 245 | { |
36a028de CG |
246 | /* |
247 | * - we always have APIC integrated on 64bit mode | |
248 | * - 82489DXs do not report # of LVT entries | |
249 | */ | |
ae41a2a4 | 250 | return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; |
1da177e4 LT |
251 | } |
252 | ||
274cfe59 CG |
253 | /* |
254 | * Local APIC timer | |
255 | */ | |
256 | ||
c40aaec6 | 257 | /* Clock divisor */ |
c40aaec6 | 258 | #define APIC_DIVISOR 16 |
1a9e4c56 | 259 | #define TSC_DIVISOR 8 |
f07f4f90 | 260 | |
daf3af47 TG |
261 | /* i82489DX specific */ |
262 | #define I82489DX_BASE_DIVIDER (((0x2) << 18)) | |
263 | ||
0e078e2f TG |
264 | /* |
265 | * This function sets up the local APIC timer, with a timeout of | |
266 | * 'clocks' APIC bus clock. During calibration we actually call | |
267 | * this function twice on the boot CPU, once with a bogus timeout | |
268 | * value, second time for real. The other (noncalibrating) CPUs | |
269 | * call this function only once, with the real, calibrated value. | |
270 | * | |
271 | * We do reads before writes even if unnecessary, to get around the | |
272 | * P5 APIC double write bug. | |
273 | */ | |
0e078e2f | 274 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 275 | { |
0e078e2f | 276 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 277 | |
0e078e2f TG |
278 | lvtt_value = LOCAL_TIMER_VECTOR; |
279 | if (!oneshot) | |
280 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
279f1461 SS |
281 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
282 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; | |
283 | ||
daf3af47 TG |
284 | /* |
285 | * The i82489DX APIC uses bit 18 and 19 for the base divider. This | |
286 | * overlaps with bit 18 on integrated APICs, but is not documented | |
287 | * in the SDM. No problem though. i82489DX equipped systems do not | |
288 | * have TSC deadline timer. | |
289 | */ | |
f07f4f90 | 290 | if (!lapic_is_integrated()) |
daf3af47 | 291 | lvtt_value |= I82489DX_BASE_DIVIDER; |
f07f4f90 | 292 | |
0e078e2f TG |
293 | if (!irqen) |
294 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 295 | |
0e078e2f | 296 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 | 297 | |
279f1461 | 298 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
5d7c631d SL |
299 | /* |
300 | * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, | |
301 | * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. | |
302 | * According to Intel, MFENCE can do the serialization here. | |
303 | */ | |
304 | asm volatile("mfence" : : : "memory"); | |
279f1461 SS |
305 | return; |
306 | } | |
307 | ||
1da177e4 | 308 | /* |
0e078e2f | 309 | * Divide PICLK by 16 |
1da177e4 | 310 | */ |
0e078e2f | 311 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
312 | apic_write(APIC_TDCR, |
313 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
314 | APIC_TDR_DIV_16); | |
0e078e2f TG |
315 | |
316 | if (!oneshot) | |
f07f4f90 | 317 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
318 | } |
319 | ||
0e078e2f | 320 | /* |
a68c439b | 321 | * Setup extended LVT, AMD specific |
7b83dae7 | 322 | * |
a68c439b RR |
323 | * Software should use the LVT offsets the BIOS provides. The offsets |
324 | * are determined by the subsystems using it like those for MCE | |
325 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
326 | * are supported. Beginning with family 10h at least 4 offsets are | |
327 | * available. | |
286f5718 | 328 | * |
a68c439b RR |
329 | * Since the offsets must be consistent for all cores, we keep track |
330 | * of the LVT offsets in software and reserve the offset for the same | |
331 | * vector also to be used on other cores. An offset is freed by | |
332 | * setting the entry to APIC_EILVT_MASKED. | |
333 | * | |
334 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
335 | * "[Firmware Bug]: ..." error message is generated. However, if | |
336 | * software does not properly determines the offsets, it is not | |
337 | * necessarily a BIOS bug. | |
0e078e2f | 338 | */ |
7b83dae7 | 339 | |
a68c439b RR |
340 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
341 | ||
342 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
343 | { | |
344 | return (old & APIC_EILVT_MASKED) | |
345 | || (new == APIC_EILVT_MASKED) | |
346 | || ((new & ~APIC_EILVT_MASKED) == old); | |
347 | } | |
348 | ||
349 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
350 | { | |
8abc3122 | 351 | unsigned int rsvd, vector; |
a68c439b RR |
352 | |
353 | if (offset >= APIC_EILVT_NR_MAX) | |
354 | return ~0; | |
355 | ||
8abc3122 | 356 | rsvd = atomic_read(&eilvt_offsets[offset]); |
a68c439b | 357 | do { |
8abc3122 RR |
358 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
359 | if (vector && !eilvt_entry_is_changeable(vector, new)) | |
a68c439b RR |
360 | /* may not change if vectors are different */ |
361 | return rsvd; | |
f96fb2df | 362 | } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new)); |
a68c439b | 363 | |
f96fb2df | 364 | rsvd = new & ~APIC_EILVT_MASKED; |
8abc3122 RR |
365 | if (rsvd && rsvd != vector) |
366 | pr_info("LVT offset %d assigned for vector 0x%02x\n", | |
367 | offset, rsvd); | |
368 | ||
a68c439b RR |
369 | return new; |
370 | } | |
371 | ||
372 | /* | |
373 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
374 | * enables the vector. See also the BKDGs. Must be called with |
375 | * preemption disabled. | |
a68c439b RR |
376 | */ |
377 | ||
27afdf20 | 378 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 379 | { |
a68c439b RR |
380 | unsigned long reg = APIC_EILVTn(offset); |
381 | unsigned int new, old, reserved; | |
382 | ||
383 | new = (mask << 16) | (msg_type << 8) | vector; | |
384 | old = apic_read(reg); | |
385 | reserved = reserve_eilvt_offset(offset, new); | |
386 | ||
387 | if (reserved != new) { | |
eb48c9cb RR |
388 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
389 | "vector 0x%x, but the register is already in use for " | |
390 | "vector 0x%x on another cpu\n", | |
391 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
392 | return -EINVAL; |
393 | } | |
394 | ||
395 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
396 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
397 | "vector 0x%x, but the register is already in use for " | |
398 | "vector 0x%x on this cpu\n", | |
399 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
400 | return -EBUSY; |
401 | } | |
402 | ||
403 | apic_write(reg, new); | |
a8fcf1a2 | 404 | |
a68c439b | 405 | return 0; |
1da177e4 | 406 | } |
27afdf20 | 407 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 408 | |
0e078e2f TG |
409 | /* |
410 | * Program the next event, relative to now | |
411 | */ | |
412 | static int lapic_next_event(unsigned long delta, | |
413 | struct clock_event_device *evt) | |
1da177e4 | 414 | { |
0e078e2f TG |
415 | apic_write(APIC_TMICT, delta); |
416 | return 0; | |
1da177e4 LT |
417 | } |
418 | ||
279f1461 SS |
419 | static int lapic_next_deadline(unsigned long delta, |
420 | struct clock_event_device *evt) | |
421 | { | |
422 | u64 tsc; | |
423 | ||
25a068b8 DH |
424 | /* This MSR is special and need a special fence: */ |
425 | weak_wrmsr_fence(); | |
426 | ||
4ea1636b | 427 | tsc = rdtsc(); |
279f1461 SS |
428 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); |
429 | return 0; | |
430 | } | |
431 | ||
b23d8e52 | 432 | static int lapic_timer_shutdown(struct clock_event_device *evt) |
9b7711f0 | 433 | { |
0e078e2f | 434 | unsigned int v; |
9b7711f0 | 435 | |
0e078e2f TG |
436 | /* Lapic used as dummy for broadcast ? */ |
437 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
b23d8e52 | 438 | return 0; |
9b7711f0 | 439 | |
b23d8e52 VK |
440 | v = apic_read(APIC_LVTT); |
441 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
442 | apic_write(APIC_LVTT, v); | |
443 | apic_write(APIC_TMICT, 0); | |
b23d8e52 VK |
444 | return 0; |
445 | } | |
9b7711f0 | 446 | |
b23d8e52 VK |
447 | static inline int |
448 | lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) | |
449 | { | |
b23d8e52 VK |
450 | /* Lapic used as dummy for broadcast ? */ |
451 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
452 | return 0; | |
9b7711f0 | 453 | |
52ae346b | 454 | __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); |
b23d8e52 VK |
455 | return 0; |
456 | } | |
457 | ||
458 | static int lapic_timer_set_periodic(struct clock_event_device *evt) | |
459 | { | |
460 | return lapic_timer_set_periodic_oneshot(evt, false); | |
461 | } | |
462 | ||
463 | static int lapic_timer_set_oneshot(struct clock_event_device *evt) | |
464 | { | |
465 | return lapic_timer_set_periodic_oneshot(evt, true); | |
9b7711f0 HS |
466 | } |
467 | ||
1da177e4 | 468 | /* |
0e078e2f | 469 | * Local APIC timer broadcast function |
1da177e4 | 470 | */ |
9628937d | 471 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 472 | { |
0e078e2f | 473 | #ifdef CONFIG_SMP |
28b82352 | 474 | __apic_send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
475 | #endif |
476 | } | |
1da177e4 | 477 | |
25874a29 HK |
478 | |
479 | /* | |
480 | * The local apic timer can be used for any function which is CPU local. | |
481 | */ | |
482 | static struct clock_event_device lapic_clockevent = { | |
914122c3 FW |
483 | .name = "lapic", |
484 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
485 | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP | |
486 | | CLOCK_EVT_FEAT_DUMMY, | |
487 | .shift = 32, | |
488 | .set_state_shutdown = lapic_timer_shutdown, | |
489 | .set_state_periodic = lapic_timer_set_periodic, | |
490 | .set_state_oneshot = lapic_timer_set_oneshot, | |
491 | .set_state_oneshot_stopped = lapic_timer_shutdown, | |
492 | .set_next_event = lapic_next_event, | |
493 | .broadcast = lapic_timer_broadcast, | |
494 | .rating = 100, | |
495 | .irq = -1, | |
25874a29 HK |
496 | }; |
497 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
498 | ||
66abf238 | 499 | static const struct x86_cpu_id deadline_match[] __initconst = { |
8fb5f44e TL |
500 | X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */ |
501 | X86_MATCH_VFM_STEPPINGS(INTEL_HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */ | |
616dd587 | 502 | |
8fb5f44e | 503 | X86_MATCH_VFM(INTEL_BROADWELL_X, 0x0b000020), |
d9e6dbcf | 504 | |
8fb5f44e TL |
505 | X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011), |
506 | X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e), | |
507 | X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c), | |
508 | X86_MATCH_VFM_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003), | |
616dd587 | 509 | |
8fb5f44e TL |
510 | X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136), |
511 | X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014), | |
512 | X86_MATCH_VFM_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0), | |
bd9240a1 | 513 | |
8fb5f44e TL |
514 | X86_MATCH_VFM(INTEL_HASWELL, 0x22), |
515 | X86_MATCH_VFM(INTEL_HASWELL_L, 0x20), | |
516 | X86_MATCH_VFM(INTEL_HASWELL_G, 0x17), | |
bd9240a1 | 517 | |
8fb5f44e TL |
518 | X86_MATCH_VFM(INTEL_BROADWELL, 0x25), |
519 | X86_MATCH_VFM(INTEL_BROADWELL_G, 0x17), | |
bd9240a1 | 520 | |
8fb5f44e TL |
521 | X86_MATCH_VFM(INTEL_SKYLAKE_L, 0xb2), |
522 | X86_MATCH_VFM(INTEL_SKYLAKE, 0xb2), | |
bd9240a1 | 523 | |
8fb5f44e TL |
524 | X86_MATCH_VFM(INTEL_KABYLAKE_L, 0x52), |
525 | X86_MATCH_VFM(INTEL_KABYLAKE, 0x52), | |
bd9240a1 PZ |
526 | |
527 | {}, | |
528 | }; | |
529 | ||
c84cb373 | 530 | static __init bool apic_validate_deadline_timer(void) |
bd9240a1 | 531 | { |
594a30fb | 532 | const struct x86_cpu_id *m; |
bd9240a1 PZ |
533 | u32 rev; |
534 | ||
c84cb373 TG |
535 | if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
536 | return false; | |
537 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) | |
538 | return true; | |
594a30fb HG |
539 | |
540 | m = x86_match_cpu(deadline_match); | |
bd9240a1 | 541 | if (!m) |
c84cb373 | 542 | return true; |
bd9240a1 | 543 | |
66abf238 | 544 | rev = (u32)m->driver_data; |
bd9240a1 PZ |
545 | |
546 | if (boot_cpu_data.microcode >= rev) | |
c84cb373 | 547 | return true; |
bd9240a1 PZ |
548 | |
549 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); | |
550 | pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " | |
551 | "please update microcode to version: 0x%x (or later)\n", rev); | |
c84cb373 | 552 | return false; |
bd9240a1 PZ |
553 | } |
554 | ||
0e078e2f | 555 | /* |
421f91d2 | 556 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
557 | * of the boot CPU and register the clock event in the framework. |
558 | */ | |
148f9bb8 | 559 | static void setup_APIC_timer(void) |
0e078e2f | 560 | { |
89cbc767 | 561 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
1da177e4 | 562 | |
349c004e | 563 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 | 564 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
d9f6e12f | 565 | /* Make LAPIC timer preferable over percpu HPET */ |
db954b58 VP |
566 | lapic_clockevent.rating = 150; |
567 | } | |
568 | ||
0e078e2f | 569 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 570 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 571 | |
279f1461 | 572 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
c6e9f42b | 573 | levt->name = "lapic-deadline"; |
279f1461 SS |
574 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | |
575 | CLOCK_EVT_FEAT_DUMMY); | |
576 | levt->set_next_event = lapic_next_deadline; | |
577 | clockevents_config_and_register(levt, | |
1a9e4c56 | 578 | tsc_khz * (1000 / TSC_DIVISOR), |
279f1461 SS |
579 | 0xF, ~0UL); |
580 | } else | |
581 | clockevents_register_device(levt); | |
0e078e2f | 582 | } |
1da177e4 | 583 | |
6731b0d6 NS |
584 | /* |
585 | * Install the updated TSC frequency from recalibration at the TSC | |
586 | * deadline clockevent devices. | |
587 | */ | |
588 | static void __lapic_update_tsc_freq(void *info) | |
589 | { | |
590 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); | |
591 | ||
592 | if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) | |
593 | return; | |
594 | ||
595 | clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); | |
596 | } | |
597 | ||
598 | void lapic_update_tsc_freq(void) | |
599 | { | |
600 | /* | |
601 | * The clockevent device's ->mult and ->shift can both be | |
602 | * changed. In order to avoid races, schedule the frequency | |
603 | * update code on each CPU. | |
604 | */ | |
605 | on_each_cpu(__lapic_update_tsc_freq, NULL, 0); | |
606 | } | |
607 | ||
2f04fa88 YL |
608 | /* |
609 | * In this functions we calibrate APIC bus clocks to the external timer. | |
610 | * | |
611 | * We want to do the calibration only once since we want to have local timer | |
d9f6e12f | 612 | * irqs synchronous. CPUs connected by the same APIC bus have the very same bus |
2f04fa88 YL |
613 | * frequency. |
614 | * | |
615 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
616 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
617 | * readout is broken, so it never gets out of the wait loop again. This was | |
618 | * also reported by others. | |
619 | * | |
620 | * Monitoring the jiffies value is inaccurate and the clockevents | |
621 | * infrastructure allows us to do a simple substitution of the interrupt | |
622 | * handler. | |
623 | * | |
624 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
625 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
626 | * back to normal later in the boot process). | |
627 | */ | |
628 | ||
629 | #define LAPIC_CAL_LOOPS (HZ/10) | |
630 | ||
631 | static __initdata int lapic_cal_loops = -1; | |
632 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
633 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
0049f04c | 634 | static __initdata u32 lapic_cal_pm1, lapic_cal_pm2; |
2f04fa88 YL |
635 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; |
636 | ||
637 | /* | |
f897e60a | 638 | * Temporary interrupt handler and polled calibration function. |
2f04fa88 YL |
639 | */ |
640 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
641 | { | |
642 | unsigned long long tsc = 0; | |
643 | long tapic = apic_read(APIC_TMCCT); | |
0049f04c | 644 | u32 pm = acpi_pm_read_early(); |
2f04fa88 | 645 | |
59e21e3d | 646 | if (boot_cpu_has(X86_FEATURE_TSC)) |
4ea1636b | 647 | tsc = rdtsc(); |
2f04fa88 YL |
648 | |
649 | switch (lapic_cal_loops++) { | |
650 | case 0: | |
651 | lapic_cal_t1 = tapic; | |
652 | lapic_cal_tsc1 = tsc; | |
653 | lapic_cal_pm1 = pm; | |
654 | lapic_cal_j1 = jiffies; | |
655 | break; | |
656 | ||
657 | case LAPIC_CAL_LOOPS: | |
658 | lapic_cal_t2 = tapic; | |
659 | lapic_cal_tsc2 = tsc; | |
660 | if (pm < lapic_cal_pm1) | |
661 | pm += ACPI_PM_OVRRUN; | |
662 | lapic_cal_pm2 = pm; | |
663 | lapic_cal_j2 = jiffies; | |
664 | break; | |
665 | } | |
666 | } | |
667 | ||
754ef0cd | 668 | static int __init |
0049f04c | 669 | calibrate_by_pmtimer(u32 deltapm, long *delta, long *deltatsc) |
b189892d CG |
670 | { |
671 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
672 | const long pm_thresh = pm_100ms / 100; | |
673 | unsigned long mult; | |
674 | u64 res; | |
675 | ||
676 | #ifndef CONFIG_X86_PM_TIMER | |
677 | return -1; | |
678 | #endif | |
679 | ||
ac1c9fc1 | 680 | apic_pr_verbose("... PM-Timer delta = %u\n", deltapm); |
b189892d CG |
681 | |
682 | /* Check, if the PM timer is available */ | |
683 | if (!deltapm) | |
684 | return -1; | |
685 | ||
686 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
687 | ||
688 | if (deltapm > (pm_100ms - pm_thresh) && | |
689 | deltapm < (pm_100ms + pm_thresh)) { | |
ac1c9fc1 | 690 | apic_pr_verbose("... PM-Timer result ok\n"); |
754ef0cd YI |
691 | return 0; |
692 | } | |
693 | ||
694 | res = (((u64)deltapm) * mult) >> 22; | |
695 | do_div(res, 1000000); | |
ac1c9fc1 TG |
696 | pr_warn("APIC calibration not consistent with PM-Timer: %ldms instead of 100ms\n", |
697 | (long)res); | |
754ef0cd YI |
698 | |
699 | /* Correct the lapic counter value */ | |
700 | res = (((u64)(*delta)) * pm_100ms); | |
701 | do_div(res, deltapm); | |
702 | pr_info("APIC delta adjusted to PM-Timer: " | |
703 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
704 | *delta = (long)res; | |
705 | ||
706 | /* Correct the tsc counter value */ | |
59e21e3d | 707 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
754ef0cd | 708 | res = (((u64)(*deltatsc)) * pm_100ms); |
b189892d | 709 | do_div(res, deltapm); |
ac1c9fc1 TG |
710 | apic_pr_verbose("TSC delta adjusted to PM-Timer: %lu (%ld)\n", |
711 | (unsigned long)res, *deltatsc); | |
754ef0cd | 712 | *deltatsc = (long)res; |
b189892d CG |
713 | } |
714 | ||
715 | return 0; | |
716 | } | |
717 | ||
6eb4f082 JP |
718 | static int __init lapic_init_clockevent(void) |
719 | { | |
52ae346b | 720 | if (!lapic_timer_period) |
6eb4f082 JP |
721 | return -1; |
722 | ||
723 | /* Calculate the scaled math multiplication factor */ | |
52ae346b | 724 | lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, |
6eb4f082 JP |
725 | TICK_NSEC, lapic_clockevent.shift); |
726 | lapic_clockevent.max_delta_ns = | |
727 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); | |
728 | lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; | |
729 | lapic_clockevent.min_delta_ns = | |
730 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
731 | lapic_clockevent.min_delta_ticks = 0xF; | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
c8c40767 TG |
736 | bool __init apic_needs_pit(void) |
737 | { | |
738 | /* | |
739 | * If the frequencies are not known, PIT is required for both TSC | |
740 | * and apic timer calibration. | |
741 | */ | |
742 | if (!tsc_khz || !cpu_khz) | |
743 | return true; | |
744 | ||
97992387 | 745 | /* Is there an APIC at all or is it disabled? */ |
49062454 | 746 | if (!boot_cpu_has(X86_FEATURE_APIC) || apic_is_disabled) |
97992387 TG |
747 | return true; |
748 | ||
749 | /* | |
750 | * If interrupt delivery mode is legacy PIC or virtual wire without | |
54aa699e | 751 | * configuration, the local APIC timer won't be set up. Make sure |
97992387 TG |
752 | * that the PIT is initialized. |
753 | */ | |
754 | if (apic_intr_mode == APIC_PIC || | |
755 | apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG) | |
c8c40767 TG |
756 | return true; |
757 | ||
afa8b475 JS |
758 | /* Virt guests may lack ARAT, but still have DEADLINE */ |
759 | if (!boot_cpu_has(X86_FEATURE_ARAT)) | |
760 | return true; | |
761 | ||
c8c40767 TG |
762 | /* Deadline timer is based on TSC so no further PIT action required */ |
763 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) | |
764 | return false; | |
765 | ||
766 | /* APIC timer disabled? */ | |
767 | if (disable_apic_timer) | |
768 | return true; | |
769 | /* | |
770 | * The APIC timer frequency is known already, no PIT calibration | |
771 | * required. If unknown, let the PIT be initialized. | |
772 | */ | |
773 | return lapic_timer_period == 0; | |
774 | } | |
775 | ||
2f04fa88 YL |
776 | static int __init calibrate_APIC_clock(void) |
777 | { | |
89cbc767 | 778 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
f897e60a TG |
779 | u64 tsc_perj = 0, tsc_start = 0; |
780 | unsigned long jif_start; | |
2f04fa88 | 781 | unsigned long deltaj; |
754ef0cd | 782 | long delta, deltatsc; |
2f04fa88 YL |
783 | int pm_referenced = 0; |
784 | ||
6eb4f082 JP |
785 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
786 | return 0; | |
787 | ||
788 | /* | |
789 | * Check if lapic timer has already been calibrated by platform | |
790 | * specific routine, such as tsc calibration code. If so just fill | |
1ade93ef JP |
791 | * in the clockevent structure and return. |
792 | */ | |
6eb4f082 | 793 | if (!lapic_init_clockevent()) { |
ac1c9fc1 | 794 | apic_pr_verbose("lapic timer already calibrated %d\n", lapic_timer_period); |
6eb4f082 JP |
795 | /* |
796 | * Direct calibration methods must have an always running | |
797 | * local APIC timer, no need for broadcast timer. | |
798 | */ | |
1ade93ef JP |
799 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
800 | return 0; | |
801 | } | |
802 | ||
ac1c9fc1 | 803 | apic_pr_verbose("Using local APIC timer interrupts. Calibrating APIC timer ...\n"); |
279f1461 | 804 | |
f897e60a TG |
805 | /* |
806 | * There are platforms w/o global clockevent devices. Instead of | |
807 | * making the calibration conditional on that, use a polling based | |
808 | * approach everywhere. | |
809 | */ | |
2f04fa88 YL |
810 | local_irq_disable(); |
811 | ||
2f04fa88 | 812 | /* |
81608f3c | 813 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
814 | * can underflow in the 100ms detection time frame |
815 | */ | |
81608f3c | 816 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 | 817 | |
f897e60a TG |
818 | /* |
819 | * Methods to terminate the calibration loop: | |
820 | * 1) Global clockevent if available (jiffies) | |
821 | * 2) TSC if available and frequency is known | |
822 | */ | |
823 | jif_start = READ_ONCE(jiffies); | |
824 | ||
825 | if (tsc_khz) { | |
826 | tsc_start = rdtsc(); | |
827 | tsc_perj = div_u64((u64)tsc_khz * 1000, HZ); | |
828 | } | |
829 | ||
830 | /* | |
831 | * Enable interrupts so the tick can fire, if a global | |
832 | * clockevent device is available | |
833 | */ | |
2f04fa88 YL |
834 | local_irq_enable(); |
835 | ||
f897e60a TG |
836 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) { |
837 | /* Wait for a tick to elapse */ | |
838 | while (1) { | |
839 | if (tsc_khz) { | |
840 | u64 tsc_now = rdtsc(); | |
841 | if ((tsc_now - tsc_start) >= tsc_perj) { | |
842 | tsc_start += tsc_perj; | |
843 | break; | |
844 | } | |
845 | } else { | |
846 | unsigned long jif_now = READ_ONCE(jiffies); | |
847 | ||
848 | if (time_after(jif_now, jif_start)) { | |
849 | jif_start = jif_now; | |
850 | break; | |
851 | } | |
852 | } | |
853 | cpu_relax(); | |
854 | } | |
2f04fa88 | 855 | |
f897e60a TG |
856 | /* Invoke the calibration routine */ |
857 | local_irq_disable(); | |
858 | lapic_cal_handler(NULL); | |
859 | local_irq_enable(); | |
860 | } | |
2f04fa88 | 861 | |
f897e60a | 862 | local_irq_disable(); |
2f04fa88 YL |
863 | |
864 | /* Build delta t1-t2 as apic timer counts down */ | |
865 | delta = lapic_cal_t1 - lapic_cal_t2; | |
ac1c9fc1 | 866 | apic_pr_verbose("... lapic delta = %ld\n", delta); |
2f04fa88 | 867 | |
754ef0cd YI |
868 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
869 | ||
b189892d CG |
870 | /* we trust the PM based calibration if possible */ |
871 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 872 | &delta, &deltatsc); |
2f04fa88 | 873 | |
52ae346b | 874 | lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
6eb4f082 | 875 | lapic_init_clockevent(); |
2f04fa88 | 876 | |
ac1c9fc1 TG |
877 | apic_pr_verbose("..... delta %ld\n", delta); |
878 | apic_pr_verbose("..... mult: %u\n", lapic_clockevent.mult); | |
879 | apic_pr_verbose("..... calibration result: %u\n", lapic_timer_period); | |
2f04fa88 | 880 | |
59e21e3d | 881 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
ac1c9fc1 TG |
882 | apic_pr_verbose("..... CPU clock speed is %ld.%04ld MHz.\n", |
883 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
884 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
885 | } |
886 | ||
ac1c9fc1 TG |
887 | apic_pr_verbose("..... host bus clock speed is %u.%04u MHz.\n", |
888 | lapic_timer_period / (1000000 / HZ), | |
889 | lapic_timer_period % (1000000 / HZ)); | |
2f04fa88 YL |
890 | |
891 | /* | |
892 | * Do a sanity check on the APIC calibration result | |
893 | */ | |
52ae346b | 894 | if (lapic_timer_period < (1000000 / HZ)) { |
2f04fa88 | 895 | local_irq_enable(); |
8d3bcc44 | 896 | pr_warn("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
897 | return -1; |
898 | } | |
899 | ||
900 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
901 | ||
b189892d | 902 | /* |
f897e60a TG |
903 | * PM timer calibration failed or not turned on so lets try APIC |
904 | * timer based calibration, if a global clockevent device is | |
905 | * available. | |
b189892d | 906 | */ |
f897e60a | 907 | if (!pm_referenced && global_clock_event) { |
ac1c9fc1 | 908 | apic_pr_verbose("... verify APIC timer\n"); |
2f04fa88 YL |
909 | |
910 | /* | |
911 | * Setup the apic timer manually | |
912 | */ | |
913 | levt->event_handler = lapic_cal_handler; | |
b23d8e52 | 914 | lapic_timer_set_periodic(levt); |
2f04fa88 YL |
915 | lapic_cal_loops = -1; |
916 | ||
917 | /* Let the interrupts run */ | |
918 | local_irq_enable(); | |
919 | ||
920 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
921 | cpu_relax(); | |
922 | ||
2f04fa88 | 923 | /* Stop the lapic timer */ |
c948c260 | 924 | local_irq_disable(); |
b23d8e52 | 925 | lapic_timer_shutdown(levt); |
2f04fa88 | 926 | |
2f04fa88 YL |
927 | /* Jiffies delta */ |
928 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
ac1c9fc1 | 929 | apic_pr_verbose("... jiffies delta = %lu\n", deltaj); |
2f04fa88 YL |
930 | |
931 | /* Check, if the jiffies result is consistent */ | |
932 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
ac1c9fc1 | 933 | apic_pr_verbose("... jiffies result ok\n"); |
2f04fa88 YL |
934 | else |
935 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
c948c260 TG |
936 | } |
937 | local_irq_enable(); | |
2f04fa88 YL |
938 | |
939 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
8d3bcc44 | 940 | pr_warn("APIC timer disabled due to verification failure\n"); |
843c4089 | 941 | return -1; |
2f04fa88 YL |
942 | } |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
e83a5fdc HS |
947 | /* |
948 | * Setup the boot APIC | |
949 | * | |
950 | * Calibrate and verify the result. | |
951 | */ | |
0e078e2f TG |
952 | void __init setup_boot_APIC_clock(void) |
953 | { | |
954 | /* | |
274cfe59 CG |
955 | * The local apic timer can be disabled via the kernel |
956 | * commandline or from the CPU detection code. Register the lapic | |
957 | * timer as a dummy clock event source on SMP systems, so the | |
958 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
959 | */ |
960 | if (disable_apic_timer) { | |
ba21ebb6 | 961 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 962 | /* No broadcast on UP ! */ |
9d09951d TG |
963 | if (num_possible_cpus() > 1) { |
964 | lapic_clockevent.mult = 1; | |
0e078e2f | 965 | setup_APIC_timer(); |
9d09951d | 966 | } |
0e078e2f TG |
967 | return; |
968 | } | |
969 | ||
89b3b1f4 | 970 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
971 | /* No broadcast on UP ! */ |
972 | if (num_possible_cpus() > 1) | |
973 | setup_APIC_timer(); | |
974 | return; | |
975 | } | |
976 | ||
0e078e2f TG |
977 | /* |
978 | * If nmi_watchdog is set to IO_APIC, we need the | |
979 | * PIT/HPET going. Otherwise register lapic as a dummy | |
980 | * device. | |
981 | */ | |
072b198a | 982 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 983 | |
274cfe59 | 984 | /* Setup the lapic or request the broadcast */ |
0e078e2f | 985 | setup_APIC_timer(); |
07c94a38 | 986 | amd_e400_c1e_apic_setup(); |
0e078e2f TG |
987 | } |
988 | ||
148f9bb8 | 989 | void setup_secondary_APIC_clock(void) |
0e078e2f | 990 | { |
0e078e2f | 991 | setup_APIC_timer(); |
07c94a38 | 992 | amd_e400_c1e_apic_setup(); |
0e078e2f TG |
993 | } |
994 | ||
995 | /* | |
996 | * The guts of the apic timer interrupt | |
997 | */ | |
998 | static void local_apic_timer_interrupt(void) | |
999 | { | |
3bec6def | 1000 | struct clock_event_device *evt = this_cpu_ptr(&lapic_events); |
0e078e2f TG |
1001 | |
1002 | /* | |
1003 | * Normally we should not be here till LAPIC has been initialized but | |
1004 | * in some cases like kdump, its possible that there is a pending LAPIC | |
1005 | * timer interrupt from previous kernel's context and is delivered in | |
1006 | * new kernel the moment interrupts are enabled. | |
1007 | * | |
1008 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
1009 | * its possible that when we get here evt->event_handler is NULL. | |
1010 | * Check for event_handler being NULL and discard the interrupt as | |
1011 | * spurious. | |
1012 | */ | |
1013 | if (!evt->event_handler) { | |
8d3bcc44 KW |
1014 | pr_warn("Spurious LAPIC timer interrupt on cpu %d\n", |
1015 | smp_processor_id()); | |
0e078e2f | 1016 | /* Switch it off */ |
b23d8e52 | 1017 | lapic_timer_shutdown(evt); |
0e078e2f TG |
1018 | return; |
1019 | } | |
1020 | ||
1021 | /* | |
1022 | * the NMI deadlock-detector uses this. | |
1023 | */ | |
915b0d01 | 1024 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
1025 | |
1026 | evt->event_handler(evt); | |
1027 | } | |
1028 | ||
1029 | /* | |
1030 | * Local APIC timer interrupt. This is the most natural way for doing | |
1031 | * local interrupts, but local timer interrupts can be emulated by | |
1032 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
1033 | * | |
1034 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
1035 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
1036 | */ | |
db0338ee | 1037 | DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt) |
0e078e2f TG |
1038 | { |
1039 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1040 | ||
670c04ad | 1041 | apic_eoi(); |
cf910e83 | 1042 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); |
0e078e2f | 1043 | local_apic_timer_interrupt(); |
cf910e83 | 1044 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
274cfe59 | 1045 | |
0e078e2f TG |
1046 | set_irq_regs(old_regs); |
1047 | } | |
1048 | ||
0e078e2f TG |
1049 | /* |
1050 | * Local APIC start and shutdown | |
1051 | */ | |
1052 | ||
1053 | /** | |
1054 | * clear_local_APIC - shutdown the local APIC | |
1055 | * | |
1056 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
1057 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
1058 | * leftovers during boot. | |
1059 | */ | |
1060 | void clear_local_APIC(void) | |
1061 | { | |
2584a82d | 1062 | int maxlvt; |
0e078e2f TG |
1063 | u32 v; |
1064 | ||
78c32000 | 1065 | if (!apic_accessible()) |
d3432896 AK |
1066 | return; |
1067 | ||
1068 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
1069 | /* |
1070 | * Masking an LVT entry can trigger a local APIC error | |
1071 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1072 | */ | |
1073 | if (maxlvt >= 3) { | |
1074 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
1075 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
1076 | } | |
1077 | /* | |
1078 | * Careful: we have to set masks only first to deassert | |
1079 | * any level-triggered sources. | |
1080 | */ | |
1081 | v = apic_read(APIC_LVTT); | |
1082 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
1083 | v = apic_read(APIC_LVT0); | |
1084 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
1085 | v = apic_read(APIC_LVT1); | |
1086 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
1087 | if (maxlvt >= 4) { | |
1088 | v = apic_read(APIC_LVTPC); | |
1089 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1090 | } | |
1091 | ||
6764014b | 1092 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 1093 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
1094 | if (maxlvt >= 5) { |
1095 | v = apic_read(APIC_LVTTHMR); | |
1096 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
1097 | } | |
1098 | #endif | |
5ca8681c AK |
1099 | #ifdef CONFIG_X86_MCE_INTEL |
1100 | if (maxlvt >= 6) { | |
1101 | v = apic_read(APIC_LVTCMCI); | |
1102 | if (!(v & APIC_LVT_MASKED)) | |
1103 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
1104 | } | |
1105 | #endif | |
1106 | ||
0e078e2f TG |
1107 | /* |
1108 | * Clean APIC state for other OSs: | |
1109 | */ | |
1110 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
1111 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1112 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1113 | if (maxlvt >= 3) | |
1114 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
1115 | if (maxlvt >= 4) | |
1116 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
1117 | |
1118 | /* Integrated APIC (!82489DX) ? */ | |
1119 | if (lapic_is_integrated()) { | |
1120 | if (maxlvt > 3) | |
1121 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
1122 | apic_write(APIC_ESR, 0); | |
1123 | apic_read(APIC_ESR); | |
1124 | } | |
0e078e2f TG |
1125 | } |
1126 | ||
1127 | /** | |
60dcaad5 TG |
1128 | * apic_soft_disable - Clears and software disables the local APIC on hotplug |
1129 | * | |
1130 | * Contrary to disable_local_APIC() this does not touch the enable bit in | |
1131 | * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC | |
1132 | * bus would require a hardware reset as the APIC would lose track of bus | |
1133 | * arbitration. On systems with FSB delivery APICBASE could be disabled, | |
1134 | * but it has to be guaranteed that no interrupt is sent to the APIC while | |
1135 | * in that state and it's not clear from the SDM whether it still responds | |
1136 | * to INIT/SIPI messages. Stay on the safe side and use software disable. | |
0e078e2f | 1137 | */ |
60dcaad5 | 1138 | void apic_soft_disable(void) |
0e078e2f | 1139 | { |
60dcaad5 | 1140 | u32 value; |
4a13ad0b | 1141 | |
0e078e2f TG |
1142 | clear_local_APIC(); |
1143 | ||
60dcaad5 | 1144 | /* Soft disable APIC (implies clearing of registers for 82489DX!). */ |
0e078e2f TG |
1145 | value = apic_read(APIC_SPIV); |
1146 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1147 | apic_write(APIC_SPIV, value); | |
60dcaad5 TG |
1148 | } |
1149 | ||
1150 | /** | |
1151 | * disable_local_APIC - clear and disable the local APIC | |
1152 | */ | |
1153 | void disable_local_APIC(void) | |
1154 | { | |
78c32000 | 1155 | if (!apic_accessible()) |
60dcaad5 TG |
1156 | return; |
1157 | ||
1158 | apic_soft_disable(); | |
990b183e CG |
1159 | |
1160 | #ifdef CONFIG_X86_32 | |
1161 | /* | |
1162 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
1163 | * restore the disabled state. | |
1164 | */ | |
1165 | if (enabled_via_apicbase) { | |
1166 | unsigned int l, h; | |
1167 | ||
1168 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1169 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1170 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1171 | } | |
1172 | #endif | |
0e078e2f TG |
1173 | } |
1174 | ||
fe4024dc CG |
1175 | /* |
1176 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1177 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1178 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1179 | * for the case where Linux didn't enable the LAPIC. | |
1180 | */ | |
0e078e2f TG |
1181 | void lapic_shutdown(void) |
1182 | { | |
1183 | unsigned long flags; | |
1184 | ||
93984fbd | 1185 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
0e078e2f TG |
1186 | return; |
1187 | ||
1188 | local_irq_save(flags); | |
1189 | ||
fe4024dc CG |
1190 | #ifdef CONFIG_X86_32 |
1191 | if (!enabled_via_apicbase) | |
1192 | clear_local_APIC(); | |
1193 | else | |
1194 | #endif | |
1195 | disable_local_APIC(); | |
1196 | ||
0e078e2f TG |
1197 | |
1198 | local_irq_restore(flags); | |
1199 | } | |
1200 | ||
0e078e2f TG |
1201 | /** |
1202 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1203 | */ | |
1da177e4 LT |
1204 | void __init sync_Arb_IDs(void) |
1205 | { | |
296cb951 CG |
1206 | /* |
1207 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1208 | * needed on AMD. | |
1209 | */ | |
1210 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1211 | return; |
1212 | ||
1213 | /* | |
1214 | * Wait for idle. | |
1215 | */ | |
1216 | apic_wait_icr_idle(); | |
1217 | ||
ac1c9fc1 TG |
1218 | apic_pr_debug("Synchronizing Arb IDs.\n"); |
1219 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1220 | } |
1221 | ||
6444b40e | 1222 | enum apic_intr_mode_id apic_intr_mode __ro_after_init; |
0114a8e8 | 1223 | |
97992387 | 1224 | static int __init __apic_intr_mode_select(void) |
1da177e4 | 1225 | { |
0114a8e8 | 1226 | /* Check kernel option */ |
49062454 | 1227 | if (apic_is_disabled) { |
0114a8e8 DL |
1228 | pr_info("APIC disabled via kernel command line\n"); |
1229 | return APIC_PIC; | |
1230 | } | |
1da177e4 | 1231 | |
0114a8e8 DL |
1232 | /* Check BIOS */ |
1233 | #ifdef CONFIG_X86_64 | |
1234 | /* On 64-bit, the APIC must be integrated, Check local APIC only */ | |
1235 | if (!boot_cpu_has(X86_FEATURE_APIC)) { | |
49062454 | 1236 | apic_is_disabled = true; |
0114a8e8 DL |
1237 | pr_info("APIC disabled by BIOS\n"); |
1238 | return APIC_PIC; | |
1239 | } | |
1240 | #else | |
1241 | /* On 32-bit, the APIC may be integrated APIC or 82489DX */ | |
1da177e4 | 1242 | |
0114a8e8 DL |
1243 | /* Neither 82489DX nor integrated APIC ? */ |
1244 | if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { | |
49062454 | 1245 | apic_is_disabled = true; |
0114a8e8 DL |
1246 | return APIC_PIC; |
1247 | } | |
1da177e4 | 1248 | |
0114a8e8 DL |
1249 | /* If the BIOS pretends there is an integrated APIC ? */ |
1250 | if (!boot_cpu_has(X86_FEATURE_APIC) && | |
1251 | APIC_INTEGRATED(boot_cpu_apic_version)) { | |
49062454 | 1252 | apic_is_disabled = true; |
d10a9044 | 1253 | pr_err(FW_BUG "Local APIC not detected, force emulation\n"); |
0114a8e8 DL |
1254 | return APIC_PIC; |
1255 | } | |
1256 | #endif | |
638c0411 | 1257 | |
0114a8e8 DL |
1258 | /* Check MP table or ACPI MADT configuration */ |
1259 | if (!smp_found_config) { | |
1260 | disable_ioapic_support(); | |
3e730dad | 1261 | if (!acpi_lapic) { |
0114a8e8 | 1262 | pr_info("APIC: ACPI MADT or MP tables are not detected\n"); |
3e730dad DL |
1263 | return APIC_VIRTUAL_WIRE_NO_CONFIG; |
1264 | } | |
0114a8e8 DL |
1265 | return APIC_VIRTUAL_WIRE; |
1266 | } | |
1267 | ||
3e730dad DL |
1268 | #ifdef CONFIG_SMP |
1269 | /* If SMP should be disabled, then really disable it! */ | |
1270 | if (!setup_max_cpus) { | |
1271 | pr_info("APIC: SMP mode deactivated\n"); | |
1272 | return APIC_SYMMETRIC_IO_NO_ROUTING; | |
1273 | } | |
638c0411 | 1274 | #endif |
1da177e4 | 1275 | |
0114a8e8 DL |
1276 | return APIC_SYMMETRIC_IO; |
1277 | } | |
1278 | ||
97992387 TG |
1279 | /* Select the interrupt delivery mode for the BSP */ |
1280 | void __init apic_intr_mode_select(void) | |
1281 | { | |
1282 | apic_intr_mode = __apic_intr_mode_select(); | |
1283 | } | |
1284 | ||
fc90ccfd VS |
1285 | /* |
1286 | * An initial setup of the virtual wire mode. | |
1287 | */ | |
1288 | void __init init_bsp_APIC(void) | |
1289 | { | |
1290 | unsigned int value; | |
1291 | ||
1292 | /* | |
1293 | * Don't do the setup now if we have a SMP BIOS as the | |
1294 | * through-I/O-APIC virtual wire mode might be active. | |
1295 | */ | |
1296 | if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) | |
1297 | return; | |
1298 | ||
1299 | /* | |
1300 | * Do not trust the local APIC being empty at bootup. | |
1301 | */ | |
1302 | clear_local_APIC(); | |
1303 | ||
1304 | /* | |
1305 | * Enable APIC. | |
1306 | */ | |
1307 | value = apic_read(APIC_SPIV); | |
1308 | value &= ~APIC_VECTOR_MASK; | |
1309 | value |= APIC_SPIV_APIC_ENABLED; | |
1310 | ||
1311 | #ifdef CONFIG_X86_32 | |
1312 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1313 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1314 | (boot_cpu_data.x86 == 15)) | |
1315 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1316 | else | |
1317 | #endif | |
1318 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1319 | value |= SPURIOUS_APIC_VECTOR; | |
1320 | apic_write(APIC_SPIV, value); | |
1321 | ||
1322 | /* | |
1323 | * Set up the virtual wire mode. | |
1324 | */ | |
1325 | apic_write(APIC_LVT0, APIC_DM_EXTINT); | |
1326 | value = APIC_DM_NMI; | |
1327 | if (!lapic_is_integrated()) /* 82489DX */ | |
1328 | value |= APIC_LVT_LEVEL_TRIGGER; | |
1329 | if (apic_extnmi == APIC_EXTNMI_NONE) | |
1330 | value |= APIC_LVT_MASKED; | |
1331 | apic_write(APIC_LVT1, value); | |
1332 | } | |
1333 | ||
748b170c TG |
1334 | static void __init apic_bsp_setup(bool upmode); |
1335 | ||
4b1669e8 DL |
1336 | /* Init the interrupt delivery mode for the BSP */ |
1337 | void __init apic_intr_mode_init(void) | |
1338 | { | |
0c759131 | 1339 | bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); |
3e730dad | 1340 | |
4f45ed9f | 1341 | switch (apic_intr_mode) { |
4b1669e8 DL |
1342 | case APIC_PIC: |
1343 | pr_info("APIC: Keep in PIC mode(8259)\n"); | |
1344 | return; | |
1345 | case APIC_VIRTUAL_WIRE: | |
1346 | pr_info("APIC: Switch to virtual wire mode setup\n"); | |
3e730dad DL |
1347 | break; |
1348 | case APIC_VIRTUAL_WIRE_NO_CONFIG: | |
1349 | pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); | |
1350 | upmode = true; | |
3e730dad | 1351 | break; |
4b1669e8 | 1352 | case APIC_SYMMETRIC_IO: |
79761ce8 | 1353 | pr_info("APIC: Switch to symmetric I/O mode setup\n"); |
3e730dad DL |
1354 | break; |
1355 | case APIC_SYMMETRIC_IO_NO_ROUTING: | |
79761ce8 | 1356 | pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); |
3e730dad | 1357 | break; |
4b1669e8 | 1358 | } |
3e730dad | 1359 | |
9d87f5b6 TG |
1360 | x86_64_probe_apic(); |
1361 | ||
1362 | x86_32_install_bigsmp(); | |
7a116a2d | 1363 | |
bb733e43 TG |
1364 | if (x86_platform.apic_post_init) |
1365 | x86_platform.apic_post_init(); | |
1366 | ||
3e730dad | 1367 | apic_bsp_setup(upmode); |
1da177e4 LT |
1368 | } |
1369 | ||
148f9bb8 | 1370 | static void lapic_setup_esr(void) |
c43da2f5 | 1371 | { |
9df08f10 CG |
1372 | unsigned int oldvalue, value, maxlvt; |
1373 | ||
1374 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1375 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1376 | return; |
1377 | } | |
c43da2f5 | 1378 | |
08125d3e | 1379 | if (apic->disable_esr) { |
c43da2f5 | 1380 | /* |
9df08f10 CG |
1381 | * Something untraceable is creating bad interrupts on |
1382 | * secondary quads ... for the moment, just leave the | |
1383 | * ESR disabled - we can't do anything useful with the | |
1384 | * errors anyway - mbligh | |
c43da2f5 | 1385 | */ |
ba21ebb6 | 1386 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1387 | return; |
c43da2f5 | 1388 | } |
9df08f10 CG |
1389 | |
1390 | maxlvt = lapic_get_maxlvt(); | |
1391 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1392 | apic_write(APIC_ESR, 0); | |
1393 | oldvalue = apic_read(APIC_ESR); | |
1394 | ||
1395 | /* enables sending errors */ | |
1396 | value = ERROR_APIC_VECTOR; | |
1397 | apic_write(APIC_LVTERR, value); | |
1398 | ||
1399 | /* | |
1400 | * spec says clear errors after enabling vector. | |
1401 | */ | |
1402 | if (maxlvt > 3) | |
1403 | apic_write(APIC_ESR, 0); | |
1404 | value = apic_read(APIC_ESR); | |
ac1c9fc1 TG |
1405 | if (value != oldvalue) { |
1406 | apic_pr_verbose("ESR value before enabling vector: 0x%08x after: 0x%08x\n", | |
1407 | oldvalue, value); | |
1408 | } | |
c43da2f5 CG |
1409 | } |
1410 | ||
cc8bf191 TG |
1411 | #define APIC_IR_REGS APIC_ISR_NR |
1412 | #define APIC_IR_BITS (APIC_IR_REGS * 32) | |
1413 | #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG) | |
1414 | ||
1415 | union apic_ir { | |
1416 | unsigned long map[APIC_IR_MAPSIZE]; | |
1417 | u32 regs[APIC_IR_REGS]; | |
1418 | }; | |
1419 | ||
1420 | static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr) | |
9b217f33 | 1421 | { |
cc8bf191 TG |
1422 | int i, bit; |
1423 | ||
1424 | /* Read the IRRs */ | |
1425 | for (i = 0; i < APIC_IR_REGS; i++) | |
1426 | irr->regs[i] = apic_read(APIC_IRR + i * 0x10); | |
1427 | ||
1428 | /* Read the ISRs */ | |
1429 | for (i = 0; i < APIC_IR_REGS; i++) | |
1430 | isr->regs[i] = apic_read(APIC_ISR + i * 0x10); | |
9b217f33 | 1431 | |
9b217f33 | 1432 | /* |
cc8bf191 TG |
1433 | * If the ISR map is not empty. ACK the APIC and run another round |
1434 | * to verify whether a pending IRR has been unblocked and turned | |
1435 | * into a ISR. | |
9b217f33 | 1436 | */ |
cc8bf191 TG |
1437 | if (!bitmap_empty(isr->map, APIC_IR_BITS)) { |
1438 | /* | |
1439 | * There can be multiple ISR bits set when a high priority | |
1440 | * interrupt preempted a lower priority one. Issue an ACK | |
1441 | * per set bit. | |
1442 | */ | |
1443 | for_each_set_bit(bit, isr->map, APIC_IR_BITS) | |
670c04ad | 1444 | apic_eoi(); |
cc8bf191 TG |
1445 | return true; |
1446 | } | |
1447 | ||
1448 | return !bitmap_empty(irr->map, APIC_IR_BITS); | |
1449 | } | |
1450 | ||
1451 | /* | |
1452 | * After a crash, we no longer service the interrupts and a pending | |
1453 | * interrupt from previous kernel might still have ISR bit set. | |
1454 | * | |
1455 | * Most probably by now the CPU has serviced that pending interrupt and it | |
670c04ad | 1456 | * might not have done the apic_eoi() because it thought, interrupt |
cc8bf191 | 1457 | * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear |
d9f6e12f | 1458 | * the ISR bit and cpu thinks it has already serviced the interrupt. Hence |
cc8bf191 TG |
1459 | * a vector might get locked. It was noticed for timer irq (vector |
1460 | * 0x31). Issue an extra EOI to clear ISR. | |
1461 | * | |
1462 | * If there are pending IRR bits they turn into ISR bits after a higher | |
1463 | * priority ISR bit has been acked. | |
1464 | */ | |
1465 | static void apic_pending_intr_clear(void) | |
1466 | { | |
1467 | union apic_ir irr, isr; | |
1468 | unsigned int i; | |
1469 | ||
1470 | /* 512 loops are way oversized and give the APIC a chance to obey. */ | |
1471 | for (i = 0; i < 512; i++) { | |
1472 | if (!apic_check_and_ack(&irr, &isr)) | |
1473 | return; | |
1474 | } | |
1475 | /* Dump the IRR/ISR content if that failed */ | |
1476 | pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map); | |
9b217f33 DL |
1477 | } |
1478 | ||
0e078e2f TG |
1479 | /** |
1480 | * setup_local_APIC - setup the local APIC | |
0aa002fe | 1481 | * |
543113d2 | 1482 | * Used to setup local APIC while initializing BSP or bringing up APs. |
0aa002fe | 1483 | * Always called with preemption disabled. |
0e078e2f | 1484 | */ |
b753a2b7 | 1485 | static void setup_local_APIC(void) |
1da177e4 | 1486 | { |
0aa002fe | 1487 | int cpu = smp_processor_id(); |
9b217f33 | 1488 | unsigned int value; |
8c3ba8d0 | 1489 | |
49062454 | 1490 | if (apic_is_disabled) { |
7167d08e | 1491 | disable_ioapic_support(); |
f1182638 JB |
1492 | return; |
1493 | } | |
1494 | ||
2640da4c TG |
1495 | /* |
1496 | * If this comes from kexec/kcrash the APIC might be enabled in | |
1497 | * SPIV. Soft disable it before doing further initialization. | |
1498 | */ | |
1499 | value = apic_read(APIC_SPIV); | |
1500 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1501 | apic_write(APIC_SPIV, value); | |
1502 | ||
89c38c28 CG |
1503 | #ifdef CONFIG_X86_32 |
1504 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1505 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1506 | apic_write(APIC_ESR, 0); |
1507 | apic_write(APIC_ESR, 0); | |
1508 | apic_write(APIC_ESR, 0); | |
1509 | apic_write(APIC_ESR, 0); | |
1510 | } | |
1511 | #endif | |
1da177e4 LT |
1512 | /* |
1513 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1514 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
2f6df03f TG |
1515 | * document number 292116). |
1516 | * | |
1517 | * Except for APICs which operate in physical destination mode. | |
1da177e4 | 1518 | */ |
2f6df03f TG |
1519 | if (apic->init_apic_ldr) |
1520 | apic->init_apic_ldr(); | |
1da177e4 LT |
1521 | |
1522 | /* | |
229b969b AL |
1523 | * Set Task Priority to 'accept all except vectors 0-31'. An APIC |
1524 | * vector in the 16-31 range could be delivered if TPR == 0, but we | |
1525 | * would think it's an exception and terrible things will happen. We | |
1526 | * never change this later on. | |
1da177e4 LT |
1527 | */ |
1528 | value = apic_read(APIC_TASKPRI); | |
1529 | value &= ~APIC_TPRI_MASK; | |
229b969b | 1530 | value |= 0x10; |
11a8e778 | 1531 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1532 | |
cc8bf191 | 1533 | /* Clear eventually stale ISR/IRR bits */ |
9b217f33 | 1534 | apic_pending_intr_clear(); |
da7ed9f9 | 1535 | |
1da177e4 LT |
1536 | /* |
1537 | * Now that we are all set up, enable the APIC | |
1538 | */ | |
1539 | value = apic_read(APIC_SPIV); | |
1540 | value &= ~APIC_VECTOR_MASK; | |
1541 | /* | |
1542 | * Enable APIC | |
1543 | */ | |
1544 | value |= APIC_SPIV_APIC_ENABLED; | |
1545 | ||
89c38c28 CG |
1546 | #ifdef CONFIG_X86_32 |
1547 | /* | |
1548 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1549 | * certain networking cards. If high frequency interrupts are | |
1550 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1551 | * entry is masked/unmasked at a high rate as well then sooner or | |
1552 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1553 | * from the device. If focus CPU is disabled then the hang goes | |
1554 | * away, oh well :-( | |
1555 | * | |
1556 | * [ This bug can be reproduced easily with a level-triggered | |
1557 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1558 | * BX chipset. ] | |
1559 | */ | |
1560 | /* | |
1561 | * Actually disabling the focus CPU check just makes the hang less | |
d9f6e12f | 1562 | * frequent as it makes the interrupt distribution model be more |
89c38c28 | 1563 | * like LRU than MRU (the short-term load is more even across CPUs). |
89c38c28 CG |
1564 | */ |
1565 | ||
1566 | /* | |
1567 | * - enable focus processor (bit==0) | |
1568 | * - 64bit mode always use processor focus | |
1569 | * so no need to set it | |
1570 | */ | |
1571 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1572 | #endif | |
3f14c746 | 1573 | |
1da177e4 LT |
1574 | /* |
1575 | * Set spurious IRQ vector | |
1576 | */ | |
1577 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1578 | apic_write(APIC_SPIV, value); |
1da177e4 | 1579 | |
39c89dff TG |
1580 | perf_events_lapic_init(); |
1581 | ||
1da177e4 LT |
1582 | /* |
1583 | * Set up LVT0, LVT1: | |
1584 | * | |
a1652bb8 | 1585 | * set up through-local-APIC on the boot CPU's LINT0. This is not |
1da177e4 LT |
1586 | * strictly necessary in pure symmetric-IO mode, but sometimes |
1587 | * we delegate interrupts to the 8259A. | |
1588 | */ | |
1589 | /* | |
1590 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1591 | */ | |
1592 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
ecf600f8 | 1593 | if (!cpu && (pic_mode || !value || ioapic_is_disabled)) { |
1da177e4 | 1594 | value = APIC_DM_EXTINT; |
ac1c9fc1 | 1595 | apic_pr_verbose("Enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1596 | } else { |
1597 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
ac1c9fc1 | 1598 | apic_pr_verbose("Masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1599 | } |
11a8e778 | 1600 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1601 | |
1602 | /* | |
b7c4948e HK |
1603 | * Only the BSP sees the LINT1 NMI signal by default. This can be |
1604 | * modified by apic_extnmi= boot option. | |
1da177e4 | 1605 | */ |
b7c4948e HK |
1606 | if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || |
1607 | apic_extnmi == APIC_EXTNMI_ALL) | |
1da177e4 LT |
1608 | value = APIC_DM_NMI; |
1609 | else | |
1610 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
ae41a2a4 DL |
1611 | |
1612 | /* Is 82489DX ? */ | |
1613 | if (!lapic_is_integrated()) | |
89c38c28 | 1614 | value |= APIC_LVT_LEVEL_TRIGGER; |
11a8e778 | 1615 | apic_write(APIC_LVT1, value); |
89c38c28 | 1616 | |
be71b855 AK |
1617 | #ifdef CONFIG_X86_MCE_INTEL |
1618 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1619 | if (!cpu) |
be71b855 AK |
1620 | cmci_recheck(); |
1621 | #endif | |
739f33b3 | 1622 | } |
1da177e4 | 1623 | |
05f7e46d | 1624 | static void end_local_APIC_setup(void) |
739f33b3 AK |
1625 | { |
1626 | lapic_setup_esr(); | |
fa6b95fc CG |
1627 | |
1628 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1629 | { |
1630 | unsigned int value; | |
1631 | /* Disable the local apic timer */ | |
1632 | value = apic_read(APIC_LVTT); | |
1633 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1634 | apic_write(APIC_LVTT, value); | |
1635 | } | |
fa6b95fc CG |
1636 | #endif |
1637 | ||
0e078e2f | 1638 | apic_pm_activate(); |
2fb270f3 JB |
1639 | } |
1640 | ||
05f7e46d TG |
1641 | /* |
1642 | * APIC setup function for application processors. Called from smpboot.c | |
1643 | */ | |
1644 | void apic_ap_setup(void) | |
2fb270f3 | 1645 | { |
05f7e46d | 1646 | setup_local_APIC(); |
2fb270f3 | 1647 | end_local_APIC_setup(); |
1da177e4 | 1648 | } |
1da177e4 | 1649 | |
d10a9044 TG |
1650 | static __init void apic_read_boot_cpu_id(bool x2apic) |
1651 | { | |
1652 | /* | |
1653 | * This can be invoked from check_x2apic() before the APIC has been | |
1654 | * selected. But that code knows for sure that the BIOS enabled | |
1655 | * X2APIC. | |
1656 | */ | |
1657 | if (x2apic) { | |
1658 | boot_cpu_physical_apicid = native_apic_msr_read(APIC_ID); | |
1659 | boot_cpu_apic_version = GET_APIC_VERSION(native_apic_msr_read(APIC_LVR)); | |
1660 | } else { | |
1661 | boot_cpu_physical_apicid = read_apic_id(); | |
1662 | boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
1663 | } | |
c0a66c28 TG |
1664 | topology_register_boot_apic(boot_cpu_physical_apicid); |
1665 | x86_32_probe_bigsmp_early(); | |
d10a9044 TG |
1666 | } |
1667 | ||
06cd9a7d | 1668 | #ifdef CONFIG_X86_X2APIC |
bfb05070 | 1669 | int x2apic_mode; |
db7d8e47 | 1670 | EXPORT_SYMBOL_GPL(x2apic_mode); |
12e189d3 TG |
1671 | |
1672 | enum { | |
1673 | X2APIC_OFF, | |
12e189d3 | 1674 | X2APIC_DISABLED, |
b8d1d163 DS |
1675 | /* All states below here have X2APIC enabled */ |
1676 | X2APIC_ON, | |
1677 | X2APIC_ON_LOCKED | |
12e189d3 TG |
1678 | }; |
1679 | static int x2apic_state; | |
1680 | ||
b8d1d163 DS |
1681 | static bool x2apic_hw_locked(void) |
1682 | { | |
d0485730 | 1683 | u64 x86_arch_cap_msr; |
b8d1d163 DS |
1684 | u64 msr; |
1685 | ||
d0485730 IM |
1686 | x86_arch_cap_msr = x86_read_arch_cap_msr(); |
1687 | if (x86_arch_cap_msr & ARCH_CAP_XAPIC_DISABLE) { | |
b8d1d163 DS |
1688 | rdmsrl(MSR_IA32_XAPIC_DISABLE_STATUS, msr); |
1689 | return (msr & LEGACY_XAPIC_DISABLED); | |
1690 | } | |
1691 | return false; | |
1692 | } | |
1693 | ||
d786ad32 | 1694 | static void __x2apic_disable(void) |
44e25ff9 TG |
1695 | { |
1696 | u64 msr; | |
1697 | ||
93984fbd | 1698 | if (!boot_cpu_has(X86_FEATURE_APIC)) |
659006bf TG |
1699 | return; |
1700 | ||
44e25ff9 TG |
1701 | rdmsrl(MSR_IA32_APICBASE, msr); |
1702 | if (!(msr & X2APIC_ENABLE)) | |
1703 | return; | |
1704 | /* Disable xapic and x2apic first and then reenable xapic mode */ | |
1705 | wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1706 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1707 | printk_once(KERN_INFO "x2apic disabled\n"); | |
1708 | } | |
1709 | ||
d786ad32 | 1710 | static void __x2apic_enable(void) |
659006bf TG |
1711 | { |
1712 | u64 msr; | |
1713 | ||
1714 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1715 | if (msr & X2APIC_ENABLE) | |
1716 | return; | |
1717 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); | |
1718 | printk_once(KERN_INFO "x2apic enabled\n"); | |
1719 | } | |
1720 | ||
bfb05070 TG |
1721 | static int __init setup_nox2apic(char *str) |
1722 | { | |
1723 | if (x2apic_enabled()) { | |
4705243d | 1724 | u32 apicid = native_apic_msr_read(APIC_ID); |
bfb05070 TG |
1725 | |
1726 | if (apicid >= 255) { | |
8d3bcc44 KW |
1727 | pr_warn("Apicid: %08x, cannot enforce nox2apic\n", |
1728 | apicid); | |
bfb05070 TG |
1729 | return 0; |
1730 | } | |
b8d1d163 DS |
1731 | if (x2apic_hw_locked()) { |
1732 | pr_warn("APIC locked in x2apic mode, can't disable\n"); | |
1733 | return 0; | |
1734 | } | |
8d3bcc44 | 1735 | pr_warn("x2apic already enabled.\n"); |
44e25ff9 TG |
1736 | __x2apic_disable(); |
1737 | } | |
1738 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
12e189d3 | 1739 | x2apic_state = X2APIC_DISABLED; |
44e25ff9 | 1740 | x2apic_mode = 0; |
bfb05070 TG |
1741 | return 0; |
1742 | } | |
1743 | early_param("nox2apic", setup_nox2apic); | |
1744 | ||
659006bf TG |
1745 | /* Called from cpu_init() to enable x2apic on (secondary) cpus */ |
1746 | void x2apic_setup(void) | |
1747 | { | |
1748 | /* | |
b8d1d163 DS |
1749 | * Try to make the AP's APIC state match that of the BSP, but if the |
1750 | * BSP is unlocked and the AP is locked then there is a state mismatch. | |
1751 | * Warn about the mismatch in case a GP fault occurs due to a locked AP | |
1752 | * trying to be turned off. | |
1753 | */ | |
1754 | if (x2apic_state != X2APIC_ON_LOCKED && x2apic_hw_locked()) | |
1755 | pr_warn("x2apic lock mismatch between BSP and AP.\n"); | |
1756 | /* | |
1757 | * If x2apic is not in ON or LOCKED state, disable it if already enabled | |
659006bf TG |
1758 | * from BIOS. |
1759 | */ | |
b8d1d163 | 1760 | if (x2apic_state < X2APIC_ON) { |
659006bf TG |
1761 | __x2apic_disable(); |
1762 | return; | |
1763 | } | |
1764 | __x2apic_enable(); | |
1765 | } | |
1766 | ||
720a22fd | 1767 | static __init void apic_set_fixmap(bool read_apic); |
5a88f354 | 1768 | |
44e25ff9 | 1769 | static __init void x2apic_disable(void) |
fb209bd8 | 1770 | { |
0ecc5be2 | 1771 | u32 x2apic_id; |
fb209bd8 | 1772 | |
0ecc5be2 | 1773 | if (x2apic_state < X2APIC_ON) |
a57e456a | 1774 | return; |
fb209bd8 | 1775 | |
6d2d49d2 TG |
1776 | x2apic_id = read_apic_id(); |
1777 | if (x2apic_id >= 255) | |
1778 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
9aa16365 | 1779 | |
b8d1d163 DS |
1780 | if (x2apic_hw_locked()) { |
1781 | pr_warn("Cannot disable locked x2apic, id: %08x\n", x2apic_id); | |
1782 | return; | |
1783 | } | |
1784 | ||
6d2d49d2 | 1785 | __x2apic_disable(); |
0ecc5be2 YW |
1786 | |
1787 | x2apic_mode = 0; | |
1788 | x2apic_state = X2APIC_DISABLED; | |
1789 | ||
720a22fd TG |
1790 | /* |
1791 | * Don't reread the APIC ID as it was already done from | |
1792 | * check_x2apic() and the APIC driver still is a x2APIC variant, | |
1793 | * which fails to do the read after x2APIC was disabled. | |
1794 | */ | |
1795 | apic_set_fixmap(false); | |
fb209bd8 YL |
1796 | } |
1797 | ||
659006bf | 1798 | static __init void x2apic_enable(void) |
6e1cb38a | 1799 | { |
659006bf | 1800 | if (x2apic_state != X2APIC_OFF) |
06cd9a7d YL |
1801 | return; |
1802 | ||
659006bf | 1803 | x2apic_mode = 1; |
12e189d3 | 1804 | x2apic_state = X2APIC_ON; |
659006bf | 1805 | __x2apic_enable(); |
6e1cb38a | 1806 | } |
d524165c | 1807 | |
62e61633 | 1808 | static __init void try_to_enable_x2apic(int remap_mode) |
07806c50 | 1809 | { |
659006bf | 1810 | if (x2apic_state == X2APIC_DISABLED) |
07806c50 JL |
1811 | return; |
1812 | ||
62e61633 | 1813 | if (remap_mode != IRQ_REMAP_X2APIC_MODE) { |
ab0f59c6 DW |
1814 | u32 apic_limit = 255; |
1815 | ||
26573a97 DW |
1816 | /* |
1817 | * Using X2APIC without IR is not architecturally supported | |
1818 | * on bare metal but may be supported in guests. | |
07806c50 | 1819 | */ |
26573a97 | 1820 | if (!x86_init.hyper.x2apic_available()) { |
62e61633 | 1821 | pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); |
44e25ff9 | 1822 | x2apic_disable(); |
07806c50 JL |
1823 | return; |
1824 | } | |
1825 | ||
ab0f59c6 DW |
1826 | /* |
1827 | * If the hypervisor supports extended destination ID in | |
1828 | * MSI, that increases the maximum APIC ID that can be | |
1829 | * used for non-remapped IRQ domains. | |
1830 | */ | |
1831 | if (x86_init.hyper.msi_ext_dest_id()) { | |
1832 | virt_ext_dest_id = 1; | |
1833 | apic_limit = 32767; | |
1834 | } | |
1835 | ||
07806c50 | 1836 | /* |
26573a97 | 1837 | * Without IR, all CPUs can be addressed by IOAPIC/MSI only |
d9f6e12f | 1838 | * in physical mode, and CPUs with an APIC ID that cannot |
26573a97 | 1839 | * be addressed must not be brought online. |
07806c50 | 1840 | */ |
ab0f59c6 | 1841 | x2apic_set_max_apicid(apic_limit); |
55eae7de | 1842 | x2apic_phys = 1; |
07806c50 | 1843 | } |
659006bf | 1844 | x2apic_enable(); |
55eae7de TG |
1845 | } |
1846 | ||
1847 | void __init check_x2apic(void) | |
1848 | { | |
1849 | if (x2apic_enabled()) { | |
1850 | pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); | |
1851 | x2apic_mode = 1; | |
b8d1d163 DS |
1852 | if (x2apic_hw_locked()) |
1853 | x2apic_state = X2APIC_ON_LOCKED; | |
1854 | else | |
1855 | x2apic_state = X2APIC_ON; | |
d10a9044 | 1856 | apic_read_boot_cpu_id(true); |
62436a4d | 1857 | } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { |
12e189d3 | 1858 | x2apic_state = X2APIC_DISABLED; |
55eae7de TG |
1859 | } |
1860 | } | |
1861 | #else /* CONFIG_X86_X2APIC */ | |
e3998434 | 1862 | void __init check_x2apic(void) |
55eae7de TG |
1863 | { |
1864 | if (!apic_is_x2apic_enabled()) | |
e3998434 | 1865 | return; |
55eae7de | 1866 | /* |
e3998434 | 1867 | * Checkme: Can we simply turn off x2APIC here instead of disabling the APIC? |
55eae7de | 1868 | */ |
e3998434 MJ |
1869 | pr_err("Kernel does not support x2APIC, please recompile with CONFIG_X86_X2APIC.\n"); |
1870 | pr_err("Disabling APIC, expect reduced performance and functionality.\n"); | |
1871 | ||
49062454 | 1872 | apic_is_disabled = true; |
e3998434 | 1873 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
55eae7de | 1874 | } |
55eae7de | 1875 | |
62e61633 | 1876 | static inline void try_to_enable_x2apic(int remap_mode) { } |
659006bf | 1877 | static inline void __x2apic_enable(void) { } |
55eae7de TG |
1878 | #endif /* !CONFIG_X86_X2APIC */ |
1879 | ||
ce69a784 GN |
1880 | void __init enable_IR_x2apic(void) |
1881 | { | |
1882 | unsigned long flags; | |
07806c50 | 1883 | int ret, ir_stat; |
b7f42ab2 | 1884 | |
ecf600f8 | 1885 | if (ioapic_is_disabled) { |
11277aab | 1886 | pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); |
2e63ad4b | 1887 | return; |
11277aab | 1888 | } |
2e63ad4b | 1889 | |
07806c50 JL |
1890 | ir_stat = irq_remapping_prepare(); |
1891 | if (ir_stat < 0 && !x2apic_supported()) | |
e670761f | 1892 | return; |
ce69a784 | 1893 | |
31dce14a | 1894 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1895 | if (ret) { |
ba21ebb6 | 1896 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1897 | return; |
5ffa4eb2 | 1898 | } |
6e1cb38a | 1899 | |
05c3dc2c | 1900 | local_irq_save(flags); |
b81bb373 | 1901 | legacy_pic->mask_all(); |
31dce14a | 1902 | mask_ioapic_entries(); |
05c3dc2c | 1903 | |
6a6256f9 | 1904 | /* If irq_remapping_prepare() succeeded, try to enable it */ |
07806c50 | 1905 | if (ir_stat >= 0) |
11277aab | 1906 | ir_stat = irq_remapping_enable(); |
07806c50 JL |
1907 | /* ir_stat contains the remap mode or an error code */ |
1908 | try_to_enable_x2apic(ir_stat); | |
a31bc327 | 1909 | |
07806c50 | 1910 | if (ir_stat < 0) |
31dce14a | 1911 | restore_ioapic_entries(); |
b81bb373 | 1912 | legacy_pic->restore_mask(); |
6e1cb38a | 1913 | local_irq_restore(flags); |
6e1cb38a | 1914 | } |
93758238 | 1915 | |
be7a656f | 1916 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1917 | /* |
1918 | * Detect and enable local APICs on non-SMP boards. | |
1919 | * Original code written by Keir Fraser. | |
1920 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1921 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1922 | */ |
1751aded | 1923 | static bool __init detect_init_APIC(void) |
1da177e4 | 1924 | { |
93984fbd | 1925 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
ba21ebb6 | 1926 | pr_info("No local APIC present\n"); |
1751aded | 1927 | return false; |
1da177e4 LT |
1928 | } |
1929 | ||
81287ad6 | 1930 | register_lapic_address(APIC_DEFAULT_PHYS_BASE); |
1751aded | 1931 | return true; |
1da177e4 | 1932 | } |
be7a656f | 1933 | #else |
5a7ae78f | 1934 | |
81287ad6 | 1935 | static bool __init apic_verify(unsigned long addr) |
5a7ae78f TG |
1936 | { |
1937 | u32 features, h, l; | |
1938 | ||
1939 | /* | |
1940 | * The APIC feature bit should now be enabled | |
1941 | * in `cpuid' | |
1942 | */ | |
1943 | features = cpuid_edx(1); | |
1944 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
8d3bcc44 | 1945 | pr_warn("Could not enable APIC!\n"); |
1751aded | 1946 | return false; |
5a7ae78f TG |
1947 | } |
1948 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
5a7ae78f TG |
1949 | |
1950 | /* The BIOS may have set up the APIC at some other address */ | |
cbf2829b BD |
1951 | if (boot_cpu_data.x86 >= 6) { |
1952 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1953 | if (l & MSR_IA32_APICBASE_ENABLE) | |
81287ad6 | 1954 | addr = l & MSR_IA32_APICBASE_BASE; |
cbf2829b | 1955 | } |
5a7ae78f | 1956 | |
81287ad6 | 1957 | register_lapic_address(addr); |
5a7ae78f | 1958 | pr_info("Found and enabled local APIC!\n"); |
1751aded | 1959 | return true; |
5a7ae78f TG |
1960 | } |
1961 | ||
1751aded | 1962 | bool __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
1963 | { |
1964 | u32 h, l; | |
1965 | ||
49062454 | 1966 | if (apic_is_disabled) |
1751aded | 1967 | return false; |
5a7ae78f TG |
1968 | |
1969 | /* | |
1970 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1971 | * MSR. This can only be done in software for Intel P6 or later | |
1972 | * and AMD K7 (Model > 1) or later. | |
1973 | */ | |
cbf2829b BD |
1974 | if (boot_cpu_data.x86 >= 6) { |
1975 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1976 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1977 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
1978 | l &= ~MSR_IA32_APICBASE_BASE; | |
1979 | l |= MSR_IA32_APICBASE_ENABLE | addr; | |
1980 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1981 | enabled_via_apicbase = 1; | |
1982 | } | |
5a7ae78f | 1983 | } |
81287ad6 | 1984 | return apic_verify(addr); |
5a7ae78f TG |
1985 | } |
1986 | ||
be7a656f YL |
1987 | /* |
1988 | * Detect and initialize APIC | |
1989 | */ | |
1751aded | 1990 | static bool __init detect_init_APIC(void) |
be7a656f | 1991 | { |
be7a656f | 1992 | /* Disabled by kernel option? */ |
49062454 | 1993 | if (apic_is_disabled) |
1751aded | 1994 | return false; |
be7a656f YL |
1995 | |
1996 | switch (boot_cpu_data.x86_vendor) { | |
1997 | case X86_VENDOR_AMD: | |
1998 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1999 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
2000 | break; |
2001 | goto no_apic; | |
da33dfef PW |
2002 | case X86_VENDOR_HYGON: |
2003 | break; | |
be7a656f YL |
2004 | case X86_VENDOR_INTEL: |
2005 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
93984fbd | 2006 | (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) |
be7a656f YL |
2007 | break; |
2008 | goto no_apic; | |
2009 | default: | |
2010 | goto no_apic; | |
2011 | } | |
2012 | ||
93984fbd | 2013 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
be7a656f YL |
2014 | /* |
2015 | * Over-ride BIOS and try to enable the local APIC only if | |
2016 | * "lapic" specified. | |
2017 | */ | |
2018 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
2019 | pr_info("Local APIC disabled by BIOS -- " |
2020 | "you can enable it with \"lapic\"\n"); | |
1751aded | 2021 | return false; |
be7a656f | 2022 | } |
1751aded TG |
2023 | if (!apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
2024 | return false; | |
5a7ae78f | 2025 | } else { |
81287ad6 | 2026 | if (!apic_verify(APIC_DEFAULT_PHYS_BASE)) |
1751aded | 2027 | return false; |
be7a656f | 2028 | } |
be7a656f YL |
2029 | |
2030 | apic_pm_activate(); | |
2031 | ||
1751aded | 2032 | return true; |
be7a656f YL |
2033 | |
2034 | no_apic: | |
ba21ebb6 | 2035 | pr_info("No local APIC present or hardware disabled\n"); |
1751aded | 2036 | return false; |
be7a656f YL |
2037 | } |
2038 | #endif | |
1da177e4 | 2039 | |
0e078e2f TG |
2040 | /** |
2041 | * init_apic_mappings - initialize APIC mappings | |
2042 | */ | |
1da177e4 LT |
2043 | void __init init_apic_mappings(void) |
2044 | { | |
c84cb373 | 2045 | if (apic_validate_deadline_timer()) |
de308d18 | 2046 | pr_info("TSC deadline timer available\n"); |
bd9240a1 | 2047 | |
d10a9044 | 2048 | if (x2apic_mode) |
6e1cb38a | 2049 | return; |
6e1cb38a | 2050 | |
e8122513 TG |
2051 | if (!smp_found_config) { |
2052 | if (!detect_init_APIC()) { | |
2053 | pr_info("APIC: disable apic facility\n"); | |
2054 | apic_disable(); | |
2055 | } | |
cec6be6d | 2056 | } |
1da177e4 LT |
2057 | } |
2058 | ||
720a22fd | 2059 | static __init void apic_set_fixmap(bool read_apic) |
5a88f354 TG |
2060 | { |
2061 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); | |
78c32000 | 2062 | apic_mmio_base = APIC_BASE; |
ac1c9fc1 | 2063 | apic_pr_verbose("Mapped APIC to %16lx (%16lx)\n", apic_mmio_base, mp_lapic_addr); |
720a22fd TG |
2064 | if (read_apic) |
2065 | apic_read_boot_cpu_id(false); | |
5a88f354 TG |
2066 | } |
2067 | ||
c0104d38 YL |
2068 | void __init register_lapic_address(unsigned long address) |
2069 | { | |
81287ad6 TG |
2070 | /* This should only happen once */ |
2071 | WARN_ON_ONCE(mp_lapic_addr); | |
c0104d38 YL |
2072 | mp_lapic_addr = address; |
2073 | ||
5a88f354 | 2074 | if (!x2apic_mode) |
720a22fd | 2075 | apic_set_fixmap(true); |
c0104d38 YL |
2076 | } |
2077 | ||
1da177e4 | 2078 | /* |
0e078e2f | 2079 | * Local APIC interrupts |
1da177e4 LT |
2080 | */ |
2081 | ||
3c5e0267 TG |
2082 | /* |
2083 | * Common handling code for spurious_interrupt and spurious_vector entry | |
2084 | * points below. No point in allowing the compiler to inline it twice. | |
0e078e2f | 2085 | */ |
3c5e0267 | 2086 | static noinline void handle_spurious_interrupt(u8 vector) |
1da177e4 | 2087 | { |
dc1528dd YL |
2088 | u32 v; |
2089 | ||
61069de7 TG |
2090 | trace_spurious_apic_entry(vector); |
2091 | ||
f8a8fe61 TG |
2092 | inc_irq_stat(irq_spurious_count); |
2093 | ||
2094 | /* | |
2095 | * If this is a spurious interrupt then do not acknowledge | |
2096 | */ | |
2097 | if (vector == SPURIOUS_APIC_VECTOR) { | |
2098 | /* See SDM vol 3 */ | |
2099 | pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", | |
2100 | smp_processor_id()); | |
2101 | goto out; | |
2102 | } | |
2103 | ||
1da177e4 | 2104 | /* |
f8a8fe61 TG |
2105 | * If it is a vectored one, verify it's set in the ISR. If set, |
2106 | * acknowledge it. | |
1da177e4 | 2107 | */ |
2414e021 | 2108 | v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); |
f8a8fe61 TG |
2109 | if (v & (1 << (vector & 0x1f))) { |
2110 | pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", | |
2111 | vector, smp_processor_id()); | |
670c04ad | 2112 | apic_eoi(); |
f8a8fe61 TG |
2113 | } else { |
2114 | pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", | |
2115 | vector, smp_processor_id()); | |
2116 | } | |
2117 | out: | |
2414e021 | 2118 | trace_spurious_apic_exit(vector); |
0e078e2f | 2119 | } |
1da177e4 | 2120 | |
3c5e0267 TG |
2121 | /** |
2122 | * spurious_interrupt - Catch all for interrupts raised on unused vectors | |
2123 | * @regs: Pointer to pt_regs on stack | |
2124 | * @vector: The vector number | |
2125 | * | |
2126 | * This is invoked from ASM entry code to catch all interrupts which | |
2127 | * trigger on an entry which is routed to the common_spurious idtentry | |
2128 | * point. | |
2129 | */ | |
2130 | DEFINE_IDTENTRY_IRQ(spurious_interrupt) | |
2131 | { | |
2132 | handle_spurious_interrupt(vector); | |
2133 | } | |
2134 | ||
db0338ee | 2135 | DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt) |
633260fa | 2136 | { |
3c5e0267 | 2137 | handle_spurious_interrupt(SPURIOUS_APIC_VECTOR); |
0e078e2f | 2138 | } |
1da177e4 | 2139 | |
0e078e2f TG |
2140 | /* |
2141 | * This interrupt should never happen with our APIC/SMP architecture | |
2142 | */ | |
db0338ee | 2143 | DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt) |
0e078e2f | 2144 | { |
2b398bd9 YS |
2145 | static const char * const error_interrupt_reason[] = { |
2146 | "Send CS error", /* APIC Error Bit 0 */ | |
2147 | "Receive CS error", /* APIC Error Bit 1 */ | |
2148 | "Send accept error", /* APIC Error Bit 2 */ | |
2149 | "Receive accept error", /* APIC Error Bit 3 */ | |
2150 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
2151 | "Send illegal vector", /* APIC Error Bit 5 */ | |
2152 | "Received illegal vector", /* APIC Error Bit 6 */ | |
2153 | "Illegal register address", /* APIC Error Bit 7 */ | |
2154 | }; | |
61069de7 TG |
2155 | u32 v, i = 0; |
2156 | ||
61069de7 | 2157 | trace_error_apic_entry(ERROR_APIC_VECTOR); |
1da177e4 | 2158 | |
0e078e2f | 2159 | /* First tickle the hardware, only then report what went on. -- REW */ |
023de4a0 MR |
2160 | if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ |
2161 | apic_write(APIC_ESR, 0); | |
60283df7 | 2162 | v = apic_read(APIC_ESR); |
670c04ad | 2163 | apic_eoi(); |
0e078e2f | 2164 | atomic_inc(&irq_err_count); |
ba7eda4c | 2165 | |
ac1c9fc1 | 2166 | apic_pr_debug("APIC error on CPU%d: %02x", smp_processor_id(), v); |
2b398bd9 | 2167 | |
60283df7 RW |
2168 | v &= 0xff; |
2169 | while (v) { | |
2170 | if (v & 0x1) | |
ac1c9fc1 | 2171 | apic_pr_debug_cont(" : %s", error_interrupt_reason[i]); |
2b398bd9 | 2172 | i++; |
60283df7 | 2173 | v >>= 1; |
4b8073e4 | 2174 | } |
2b398bd9 | 2175 | |
ac1c9fc1 | 2176 | apic_pr_debug_cont("\n"); |
2b398bd9 | 2177 | |
cf910e83 | 2178 | trace_error_apic_exit(ERROR_APIC_VECTOR); |
1da177e4 LT |
2179 | } |
2180 | ||
b5841765 | 2181 | /** |
36c9d674 CG |
2182 | * connect_bsp_APIC - attach the APIC to the interrupt system |
2183 | */ | |
05f7e46d | 2184 | static void __init connect_bsp_APIC(void) |
b5841765 | 2185 | { |
36c9d674 CG |
2186 | #ifdef CONFIG_X86_32 |
2187 | if (pic_mode) { | |
2188 | /* | |
2189 | * Do not trust the local APIC being empty at bootup. | |
2190 | */ | |
2191 | clear_local_APIC(); | |
2192 | /* | |
2193 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
2194 | * local APIC to INT and NMI lines. | |
2195 | */ | |
ac1c9fc1 | 2196 | apic_pr_verbose("Leaving PIC mode, enabling APIC mode.\n"); |
c0eaa453 | 2197 | imcr_pic_to_apic(); |
36c9d674 CG |
2198 | } |
2199 | #endif | |
b5841765 GC |
2200 | } |
2201 | ||
274cfe59 CG |
2202 | /** |
2203 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
2204 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
2205 | * | |
2206 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
2207 | * APIC is disabled. | |
2208 | */ | |
0e078e2f | 2209 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 2210 | { |
1b4ee4e4 CG |
2211 | unsigned int value; |
2212 | ||
c177b0bc CG |
2213 | #ifdef CONFIG_X86_32 |
2214 | if (pic_mode) { | |
2215 | /* | |
2216 | * Put the board back into PIC mode (has an effect only on | |
2217 | * certain older boards). Note that APIC interrupts, including | |
2218 | * IPIs, won't work beyond this point! The only exception are | |
2219 | * INIT IPIs. | |
2220 | */ | |
ac1c9fc1 | 2221 | apic_pr_verbose("Disabling APIC mode, entering PIC mode.\n"); |
c0eaa453 | 2222 | imcr_apic_to_pic(); |
c177b0bc CG |
2223 | return; |
2224 | } | |
2225 | #endif | |
2226 | ||
0e078e2f | 2227 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 2228 | |
0e078e2f TG |
2229 | /* For the spurious interrupt use vector F, and enable it */ |
2230 | value = apic_read(APIC_SPIV); | |
2231 | value &= ~APIC_VECTOR_MASK; | |
2232 | value |= APIC_SPIV_APIC_ENABLED; | |
2233 | value |= 0xf; | |
2234 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 2235 | |
0e078e2f TG |
2236 | if (!virt_wire_setup) { |
2237 | /* | |
2238 | * For LVT0 make it edge triggered, active high, | |
2239 | * external and enabled | |
2240 | */ | |
2241 | value = apic_read(APIC_LVT0); | |
2242 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2243 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2244 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2245 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2246 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
2247 | apic_write(APIC_LVT0, value); | |
2248 | } else { | |
2249 | /* Disable LVT0 */ | |
2250 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
2251 | } | |
b8ce3359 | 2252 | |
c177b0bc CG |
2253 | /* |
2254 | * For LVT1 make it edge triggered, active high, | |
2255 | * nmi and enabled | |
2256 | */ | |
0e078e2f TG |
2257 | value = apic_read(APIC_LVT1); |
2258 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2259 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2260 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2261 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2262 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
2263 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
2264 | } |
2265 | ||
f598181a DW |
2266 | void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, |
2267 | bool dmar) | |
2268 | { | |
6285aa50 | 2269 | memset(msg, 0, sizeof(*msg)); |
f598181a | 2270 | |
6285aa50 TG |
2271 | msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; |
2272 | msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical; | |
2273 | msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF; | |
f598181a | 2274 | |
6285aa50 TG |
2275 | msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED; |
2276 | msg->arch_data.vector = cfg->vector; | |
f598181a | 2277 | |
6285aa50 | 2278 | msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; |
f598181a DW |
2279 | /* |
2280 | * Only the IOMMU itself can use the trick of putting destination | |
2281 | * APIC ID into the high bits of the address. Anything else would | |
2282 | * just be writing to memory if it tried that, and needs IR to | |
ab0f59c6 DW |
2283 | * address APICs which can't be addressed in the normal 32-bit |
2284 | * address range at 0xFFExxxxx. That is typically just 8 bits, but | |
2285 | * some hypervisors allow the extended destination ID field in bits | |
2286 | * 5-11 to be used, giving support for 15 bits of APIC IDs in total. | |
f598181a DW |
2287 | */ |
2288 | if (dmar) | |
6285aa50 | 2289 | msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8; |
ab0f59c6 DW |
2290 | else if (virt_ext_dest_id && cfg->dest_apicid < 0x8000) |
2291 | msg->arch_addr_lo.virt_destid_8_14 = cfg->dest_apicid >> 8; | |
f598181a | 2292 | else |
6285aa50 | 2293 | WARN_ON_ONCE(cfg->dest_apicid > 0xFF); |
f598181a DW |
2294 | } |
2295 | ||
6285aa50 TG |
2296 | u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid) |
2297 | { | |
2298 | u32 dest = msg->arch_addr_lo.destid_0_7; | |
2299 | ||
2300 | if (extid) | |
2301 | dest |= msg->arch_addr_hi.destid_8_31 << 8; | |
2302 | return dest; | |
2303 | } | |
2304 | EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid); | |
2305 | ||
374aab33 | 2306 | static void __init apic_bsp_up_setup(void) |
05f7e46d | 2307 | { |
350b5e27 | 2308 | reset_phys_cpu_present_map(boot_cpu_physical_apicid); |
05f7e46d TG |
2309 | } |
2310 | ||
2311 | /** | |
2312 | * apic_bsp_setup - Setup function for local apic and io-apic | |
374aab33 | 2313 | * @upmode: Force UP mode (for APIC_init_uniprocessor) |
05f7e46d | 2314 | */ |
748b170c | 2315 | static void __init apic_bsp_setup(bool upmode) |
05f7e46d | 2316 | { |
05f7e46d | 2317 | connect_bsp_APIC(); |
374aab33 TG |
2318 | if (upmode) |
2319 | apic_bsp_up_setup(); | |
05f7e46d TG |
2320 | setup_local_APIC(); |
2321 | ||
05f7e46d | 2322 | enable_IO_APIC(); |
374aab33 TG |
2323 | end_local_APIC_setup(); |
2324 | irq_remap_enable_fault_handling(); | |
05f7e46d | 2325 | setup_IO_APIC(); |
7d65f9e8 | 2326 | lapic_update_legacy_vectors(); |
e714a91f TG |
2327 | } |
2328 | ||
30b8b006 TG |
2329 | #ifdef CONFIG_UP_LATE_INIT |
2330 | void __init up_late_init(void) | |
2331 | { | |
0c759131 DL |
2332 | if (apic_intr_mode == APIC_PIC) |
2333 | return; | |
e714a91f | 2334 | |
a2510d15 DL |
2335 | /* Setup local timer */ |
2336 | x86_init.timers.setup_percpu_clockev(); | |
30b8b006 TG |
2337 | } |
2338 | #endif | |
2339 | ||
89039b37 | 2340 | /* |
0e078e2f | 2341 | * Power management |
89039b37 | 2342 | */ |
0e078e2f TG |
2343 | #ifdef CONFIG_PM |
2344 | ||
2345 | static struct { | |
274cfe59 CG |
2346 | /* |
2347 | * 'active' is true if the local APIC was enabled by us and | |
2348 | * not the BIOS; this signifies that we are also responsible | |
2349 | * for disabling it before entering apm/acpi suspend | |
2350 | */ | |
0e078e2f TG |
2351 | int active; |
2352 | /* r/w apic fields */ | |
4705243d | 2353 | u32 apic_id; |
0e078e2f TG |
2354 | unsigned int apic_taskpri; |
2355 | unsigned int apic_ldr; | |
2356 | unsigned int apic_dfr; | |
2357 | unsigned int apic_spiv; | |
2358 | unsigned int apic_lvtt; | |
2359 | unsigned int apic_lvtpc; | |
2360 | unsigned int apic_lvt0; | |
2361 | unsigned int apic_lvt1; | |
2362 | unsigned int apic_lvterr; | |
2363 | unsigned int apic_tmict; | |
2364 | unsigned int apic_tdcr; | |
2365 | unsigned int apic_thmr; | |
42baa258 | 2366 | unsigned int apic_cmci; |
0e078e2f TG |
2367 | } apic_pm_state; |
2368 | ||
f3c6ea1b | 2369 | static int lapic_suspend(void) |
0e078e2f TG |
2370 | { |
2371 | unsigned long flags; | |
2372 | int maxlvt; | |
89039b37 | 2373 | |
0e078e2f TG |
2374 | if (!apic_pm_state.active) |
2375 | return 0; | |
89039b37 | 2376 | |
0e078e2f | 2377 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2378 | |
2d7a66d0 | 2379 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2380 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2381 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2382 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2383 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2384 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2385 | if (maxlvt >= 4) | |
2386 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2387 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2388 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2389 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2390 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2391 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2392 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2393 | if (maxlvt >= 5) |
2394 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2395 | #endif | |
42baa258 JG |
2396 | #ifdef CONFIG_X86_MCE_INTEL |
2397 | if (maxlvt >= 6) | |
2398 | apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); | |
2399 | #endif | |
24968cfd | 2400 | |
0e078e2f | 2401 | local_irq_save(flags); |
0f378d73 TW |
2402 | |
2403 | /* | |
2404 | * Mask IOAPIC before disabling the local APIC to prevent stale IRR | |
2405 | * entries on some implementations. | |
2406 | */ | |
2407 | mask_ioapic_entries(); | |
2408 | ||
0e078e2f | 2409 | disable_local_APIC(); |
fc1edaf9 | 2410 | |
70733e0c | 2411 | irq_remapping_disable(); |
fc1edaf9 | 2412 | |
0e078e2f TG |
2413 | local_irq_restore(flags); |
2414 | return 0; | |
1da177e4 LT |
2415 | } |
2416 | ||
f3c6ea1b | 2417 | static void lapic_resume(void) |
1da177e4 | 2418 | { |
0e078e2f TG |
2419 | unsigned int l, h; |
2420 | unsigned long flags; | |
31dce14a | 2421 | int maxlvt; |
b24696bc | 2422 | |
0e078e2f | 2423 | if (!apic_pm_state.active) |
f3c6ea1b | 2424 | return; |
89b831ef | 2425 | |
0e078e2f | 2426 | local_irq_save(flags); |
336224ba JR |
2427 | |
2428 | /* | |
2429 | * IO-APIC and PIC have their own resume routines. | |
2430 | * We just mask them here to make sure the interrupt | |
2431 | * subsystem is completely quiet while we enable x2apic | |
2432 | * and interrupt-remapping. | |
2433 | */ | |
2434 | mask_ioapic_entries(); | |
2435 | legacy_pic->mask_all(); | |
92206c90 | 2436 | |
659006bf TG |
2437 | if (x2apic_mode) { |
2438 | __x2apic_enable(); | |
2439 | } else { | |
92206c90 CG |
2440 | /* |
2441 | * Make sure the APICBASE points to the right address | |
2442 | * | |
2443 | * FIXME! This will be wrong if we ever support suspend on | |
2444 | * SMP! We'll need to do this as part of the CPU restore! | |
2445 | */ | |
cbf2829b BD |
2446 | if (boot_cpu_data.x86 >= 6) { |
2447 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2448 | l &= ~MSR_IA32_APICBASE_BASE; | |
2449 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2450 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2451 | } | |
d5e629a6 | 2452 | } |
6e1cb38a | 2453 | |
b24696bc | 2454 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2455 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2456 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2457 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2458 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2459 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2460 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2461 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2462 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
42baa258 | 2463 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2464 | if (maxlvt >= 5) |
2465 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
42baa258 JG |
2466 | #endif |
2467 | #ifdef CONFIG_X86_MCE_INTEL | |
2468 | if (maxlvt >= 6) | |
2469 | apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); | |
0e078e2f TG |
2470 | #endif |
2471 | if (maxlvt >= 4) | |
2472 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2473 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2474 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2475 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2476 | apic_write(APIC_ESR, 0); | |
2477 | apic_read(APIC_ESR); | |
2478 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2479 | apic_write(APIC_ESR, 0); | |
2480 | apic_read(APIC_ESR); | |
92206c90 | 2481 | |
70733e0c | 2482 | irq_remapping_reenable(x2apic_mode); |
31dce14a | 2483 | |
0e078e2f | 2484 | local_irq_restore(flags); |
0e078e2f | 2485 | } |
b8ce3359 | 2486 | |
274cfe59 CG |
2487 | /* |
2488 | * This device has no shutdown method - fully functioning local APICs | |
2489 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2490 | */ | |
2491 | ||
f3c6ea1b | 2492 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2493 | .resume = lapic_resume, |
2494 | .suspend = lapic_suspend, | |
2495 | }; | |
b8ce3359 | 2496 | |
148f9bb8 | 2497 | static void apic_pm_activate(void) |
0e078e2f TG |
2498 | { |
2499 | apic_pm_state.active = 1; | |
1da177e4 LT |
2500 | } |
2501 | ||
0e078e2f | 2502 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2503 | { |
0e078e2f | 2504 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
93984fbd | 2505 | if (boot_cpu_has(X86_FEATURE_APIC)) |
f3c6ea1b | 2506 | register_syscore_ops(&lapic_syscore_ops); |
e83a5fdc | 2507 | |
f3c6ea1b | 2508 | return 0; |
1da177e4 | 2509 | } |
b24696bc FY |
2510 | |
2511 | /* local apic needs to resume before other devices access its registers. */ | |
2512 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2513 | |
2514 | #else /* CONFIG_PM */ | |
2515 | ||
2516 | static void apic_pm_activate(void) { } | |
2517 | ||
2518 | #endif /* CONFIG_PM */ | |
1da177e4 | 2519 | |
f28c0ae2 | 2520 | #ifdef CONFIG_X86_64 |
e0e42142 | 2521 | |
148f9bb8 PG |
2522 | static int multi_checked; |
2523 | static int multi; | |
e0e42142 | 2524 | |
148f9bb8 | 2525 | static int set_multi(const struct dmi_system_id *d) |
e0e42142 YL |
2526 | { |
2527 | if (multi) | |
2528 | return 0; | |
6f0aced6 | 2529 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2530 | multi = 1; |
2531 | return 0; | |
2532 | } | |
2533 | ||
148f9bb8 | 2534 | static const struct dmi_system_id multi_dmi_table[] = { |
e0e42142 YL |
2535 | { |
2536 | .callback = set_multi, | |
2537 | .ident = "IBM System Summit2", | |
2538 | .matches = { | |
2539 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2540 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2541 | }, | |
2542 | }, | |
2543 | {} | |
2544 | }; | |
2545 | ||
148f9bb8 | 2546 | static void dmi_check_multi(void) |
e0e42142 YL |
2547 | { |
2548 | if (multi_checked) | |
2549 | return; | |
2550 | ||
2551 | dmi_check_system(multi_dmi_table); | |
2552 | multi_checked = 1; | |
2553 | } | |
2554 | ||
2555 | /* | |
2556 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2557 | * | |
2558 | * Thus far, the major user of this is IBM's Summit2 series: | |
2559 | * Clustered boxes may have unsynced TSC problems if they are | |
2560 | * multi-chassis. | |
2561 | * Use DMI to check them | |
2562 | */ | |
148f9bb8 | 2563 | int apic_is_clustered_box(void) |
e0e42142 YL |
2564 | { |
2565 | dmi_check_multi(); | |
411cf9ee | 2566 | return multi; |
1da177e4 | 2567 | } |
f28c0ae2 | 2568 | #endif |
1da177e4 LT |
2569 | |
2570 | /* | |
0e078e2f | 2571 | * APIC command line parameters |
1da177e4 | 2572 | */ |
789fa735 | 2573 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2574 | { |
49062454 | 2575 | apic_is_disabled = true; |
9175fc06 | 2576 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2577 | return 0; |
2578 | } | |
2579 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2580 | |
2c8c0e6b | 2581 | /* same as disableapic, for compatibility */ |
789fa735 | 2582 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2583 | { |
789fa735 | 2584 | return setup_disableapic(arg); |
6935d1f9 | 2585 | } |
2c8c0e6b | 2586 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2587 | |
2e7c2838 LT |
2588 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2589 | { | |
2590 | local_apic_timer_c2_ok = 1; | |
2591 | return 0; | |
2592 | } | |
2593 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2594 | ||
36fef094 | 2595 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2596 | { |
1da177e4 | 2597 | disable_apic_timer = 1; |
36fef094 | 2598 | return 0; |
6935d1f9 | 2599 | } |
36fef094 CG |
2600 | early_param("noapictimer", parse_disable_apic_timer); |
2601 | ||
2602 | static int __init parse_nolapic_timer(char *arg) | |
2603 | { | |
2604 | disable_apic_timer = 1; | |
2605 | return 0; | |
6935d1f9 | 2606 | } |
36fef094 | 2607 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2608 | |
79af9bec CG |
2609 | static int __init apic_set_verbosity(char *arg) |
2610 | { | |
2611 | if (!arg) { | |
ecf600f8 TG |
2612 | if (IS_ENABLED(CONFIG_X86_32)) |
2613 | return -EINVAL; | |
2614 | ||
2615 | ioapic_is_disabled = false; | |
79af9bec | 2616 | return 0; |
79af9bec CG |
2617 | } |
2618 | ||
2619 | if (strcmp("debug", arg) == 0) | |
2620 | apic_verbosity = APIC_DEBUG; | |
2621 | else if (strcmp("verbose", arg) == 0) | |
2622 | apic_verbosity = APIC_VERBOSE; | |
4fcab669 | 2623 | #ifdef CONFIG_X86_64 |
79af9bec | 2624 | else { |
8d3bcc44 | 2625 | pr_warn("APIC Verbosity level %s not recognised" |
79af9bec CG |
2626 | " use apic=verbose or apic=debug\n", arg); |
2627 | return -EINVAL; | |
2628 | } | |
4fcab669 | 2629 | #endif |
79af9bec CG |
2630 | |
2631 | return 0; | |
2632 | } | |
2633 | early_param("apic", apic_set_verbosity); | |
2634 | ||
1e934dda YL |
2635 | static int __init lapic_insert_resource(void) |
2636 | { | |
78c32000 | 2637 | if (!apic_mmio_base) |
1e934dda YL |
2638 | return -1; |
2639 | ||
2640 | /* Put local APIC into the resource map. */ | |
78c32000 | 2641 | lapic_resource.start = apic_mmio_base; |
1e934dda YL |
2642 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; |
2643 | insert_resource(&iomem_resource, &lapic_resource); | |
2644 | ||
2645 | return 0; | |
2646 | } | |
2647 | ||
2648 | /* | |
1506c8dc | 2649 | * need call insert after e820__reserve_resources() |
1e934dda YL |
2650 | * that is using request_resource |
2651 | */ | |
2652 | late_initcall(lapic_insert_resource); | |
151e0c7d | 2653 | |
b7c4948e HK |
2654 | static int __init apic_set_extnmi(char *arg) |
2655 | { | |
2656 | if (!arg) | |
2657 | return -EINVAL; | |
2658 | ||
2659 | if (!strncmp("all", arg, 3)) | |
2660 | apic_extnmi = APIC_EXTNMI_ALL; | |
2661 | else if (!strncmp("none", arg, 4)) | |
2662 | apic_extnmi = APIC_EXTNMI_NONE; | |
2663 | else if (!strncmp("bsp", arg, 3)) | |
2664 | apic_extnmi = APIC_EXTNMI_BSP; | |
2665 | else { | |
2666 | pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); | |
2667 | return -EINVAL; | |
2668 | } | |
2669 | ||
2670 | return 0; | |
2671 | } | |
2672 | early_param("apic_extnmi", apic_set_extnmi); |