Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
cdd6c482 | 17 | #include <linux/perf_event.h> |
1da177e4 | 18 | #include <linux/kernel_stat.h> |
d1de36f5 | 19 | #include <linux/mc146818rtc.h> |
70a20025 | 20 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
21 | #include <linux/clockchips.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/ftrace.h> | |
25 | #include <linux/ioport.h> | |
186f4360 | 26 | #include <linux/export.h> |
f3c6ea1b | 27 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
28 | #include <linux/delay.h> |
29 | #include <linux/timex.h> | |
334955ef | 30 | #include <linux/i8253.h> |
6e1cb38a | 31 | #include <linux/dmar.h> |
d1de36f5 IM |
32 | #include <linux/init.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/dmi.h> | |
d1de36f5 IM |
35 | #include <linux/smp.h> |
36 | #include <linux/mm.h> | |
1da177e4 | 37 | |
83ab8514 | 38 | #include <asm/trace/irq_vectors.h> |
8a8f422d | 39 | #include <asm/irq_remapping.h> |
cdd6c482 | 40 | #include <asm/perf_event.h> |
736decac | 41 | #include <asm/x86_init.h> |
1da177e4 | 42 | #include <asm/pgalloc.h> |
60063497 | 43 | #include <linux/atomic.h> |
1da177e4 | 44 | #include <asm/mpspec.h> |
d1de36f5 | 45 | #include <asm/i8259.h> |
73dea47f | 46 | #include <asm/proto.h> |
2c8c0e6b | 47 | #include <asm/apic.h> |
7167d08e | 48 | #include <asm/io_apic.h> |
d1de36f5 IM |
49 | #include <asm/desc.h> |
50 | #include <asm/hpet.h> | |
51 | #include <asm/idle.h> | |
52 | #include <asm/mtrr.h> | |
16f871bc | 53 | #include <asm/time.h> |
2bc13797 | 54 | #include <asm/smp.h> |
be71b855 | 55 | #include <asm/mce.h> |
8c3ba8d0 | 56 | #include <asm/tsc.h> |
2904ed8d | 57 | #include <asm/hypervisor.h> |
1da177e4 | 58 | |
ec70de8b | 59 | unsigned int num_processors; |
fdbecd9f | 60 | |
148f9bb8 | 61 | unsigned disabled_cpus; |
fdbecd9f | 62 | |
ec70de8b BG |
63 | /* Processor that is doing the boot up */ |
64 | unsigned int boot_cpu_physical_apicid = -1U; | |
cc08e04c | 65 | EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); |
5af5573e | 66 | |
cff9ab2b DV |
67 | u8 boot_cpu_apic_version; |
68 | ||
80e5609c | 69 | /* |
fdbecd9f | 70 | * The highest APIC ID seen during enumeration. |
80e5609c | 71 | */ |
a491cc90 | 72 | static unsigned int max_physical_apicid; |
5af5573e | 73 | |
80e5609c | 74 | /* |
fdbecd9f | 75 | * Bitmask of physically existing CPUs: |
80e5609c | 76 | */ |
ec70de8b BG |
77 | physid_mask_t phys_cpu_present_map; |
78 | ||
151e0c7d HD |
79 | /* |
80 | * Processor to be disabled specified by kernel parameter | |
81 | * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to | |
82 | * avoid undefined behaviour caused by sending INIT from AP to BSP. | |
83 | */ | |
5b4d1dbc | 84 | static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; |
151e0c7d | 85 | |
b7c4948e HK |
86 | /* |
87 | * This variable controls which CPUs receive external NMIs. By default, | |
88 | * external NMIs are delivered only to the BSP. | |
89 | */ | |
90 | static int apic_extnmi = APIC_EXTNMI_BSP; | |
91 | ||
ec70de8b BG |
92 | /* |
93 | * Map cpu index to physical APIC ID | |
94 | */ | |
0816b0f0 VZ |
95 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); |
96 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); | |
3e9e57fa | 97 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); |
ec70de8b BG |
98 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
99 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
3e9e57fa | 100 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); |
80e5609c | 101 | |
b3c51170 | 102 | #ifdef CONFIG_X86_32 |
4c321ff8 | 103 | |
4c321ff8 TH |
104 | /* |
105 | * On x86_32, the mapping between cpu and logical apicid may vary | |
106 | * depending on apic in use. The following early percpu variable is | |
107 | * used for the mapping. This is where the behaviors of x86_64 and 32 | |
108 | * actually diverge. Let's keep it ugly for now. | |
109 | */ | |
0816b0f0 | 110 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); |
4c321ff8 | 111 | |
f28c0ae2 YL |
112 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
113 | static int enabled_via_apicbase; | |
114 | ||
c0eaa453 CG |
115 | /* |
116 | * Handle interrupt mode configuration register (IMCR). | |
117 | * This register controls whether the interrupt signals | |
118 | * that reach the BSP come from the master PIC or from the | |
119 | * local APIC. Before entering Symmetric I/O Mode, either | |
120 | * the BIOS or the operating system must switch out of | |
121 | * PIC Mode by changing the IMCR. | |
122 | */ | |
5cda395f | 123 | static inline void imcr_pic_to_apic(void) |
c0eaa453 CG |
124 | { |
125 | /* select IMCR register */ | |
126 | outb(0x70, 0x22); | |
127 | /* NMI and 8259 INTR go through APIC */ | |
128 | outb(0x01, 0x23); | |
129 | } | |
130 | ||
5cda395f | 131 | static inline void imcr_apic_to_pic(void) |
c0eaa453 CG |
132 | { |
133 | /* select IMCR register */ | |
134 | outb(0x70, 0x22); | |
135 | /* NMI and 8259 INTR go directly to BSP */ | |
136 | outb(0x00, 0x23); | |
137 | } | |
b3c51170 YL |
138 | #endif |
139 | ||
279f1461 SS |
140 | /* |
141 | * Knob to control our willingness to enable the local APIC. | |
142 | * | |
143 | * +1=force-enable | |
144 | */ | |
145 | static int force_enable_local_apic __initdata; | |
dc9788f4 | 146 | |
279f1461 SS |
147 | /* |
148 | * APIC command line parameters | |
149 | */ | |
150 | static int __init parse_lapic(char *arg) | |
151 | { | |
97f2645f | 152 | if (IS_ENABLED(CONFIG_X86_32) && !arg) |
279f1461 | 153 | force_enable_local_apic = 1; |
27cf9298 | 154 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
279f1461 SS |
155 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
156 | return 0; | |
157 | } | |
158 | early_param("lapic", parse_lapic); | |
159 | ||
b3c51170 | 160 | #ifdef CONFIG_X86_64 |
bc1d99c1 | 161 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
162 | static __init int setup_apicpmtimer(char *s) |
163 | { | |
164 | apic_calibrate_pmtmr = 1; | |
165 | notsc_setup(NULL); | |
166 | return 0; | |
167 | } | |
168 | __setup("apicpmtimer", setup_apicpmtimer); | |
169 | #endif | |
170 | ||
b3c51170 YL |
171 | unsigned long mp_lapic_addr; |
172 | int disable_apic; | |
173 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
25874a29 | 174 | static int disable_apic_timer __initdata; |
e83a5fdc | 175 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
176 | int local_apic_timer_c2_ok; |
177 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
178 | ||
2414e021 | 179 | int first_system_vector = FIRST_SYSTEM_VECTOR; |
efa2559f | 180 | |
e83a5fdc HS |
181 | /* |
182 | * Debug level, exported for io_apic.c | |
183 | */ | |
baa13188 | 184 | unsigned int apic_verbosity; |
e83a5fdc | 185 | |
89c38c28 CG |
186 | int pic_mode; |
187 | ||
bab4b27c AS |
188 | /* Have we found an MP table */ |
189 | int smp_found_config; | |
190 | ||
39928722 AD |
191 | static struct resource lapic_resource = { |
192 | .name = "Local APIC", | |
193 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
194 | }; | |
195 | ||
1ade93ef | 196 | unsigned int lapic_timer_frequency = 0; |
d03030e9 | 197 | |
0e078e2f | 198 | static void apic_pm_activate(void); |
ba7eda4c | 199 | |
d3432896 AK |
200 | static unsigned long apic_phys; |
201 | ||
0e078e2f TG |
202 | /* |
203 | * Get the LAPIC version | |
204 | */ | |
205 | static inline int lapic_get_version(void) | |
ba7eda4c | 206 | { |
0e078e2f | 207 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
208 | } |
209 | ||
0e078e2f | 210 | /* |
9c803869 | 211 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
212 | */ |
213 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 214 | { |
9c803869 | 215 | #ifdef CONFIG_X86_64 |
0e078e2f | 216 | return 1; |
9c803869 CG |
217 | #else |
218 | return APIC_INTEGRATED(lapic_get_version()); | |
219 | #endif | |
ba7eda4c TG |
220 | } |
221 | ||
222 | /* | |
0e078e2f | 223 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 224 | */ |
0e078e2f | 225 | static int modern_apic(void) |
ba7eda4c | 226 | { |
0e078e2f TG |
227 | /* AMD systems use old APIC versions, so check the CPU */ |
228 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
229 | boot_cpu_data.x86 >= 0xf) | |
230 | return 1; | |
231 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
232 | } |
233 | ||
08306ce6 | 234 | /* |
a933c618 CG |
235 | * right after this call apic become NOOP driven |
236 | * so apic->write/read doesn't do anything | |
08306ce6 | 237 | */ |
25874a29 | 238 | static void __init apic_disable(void) |
08306ce6 | 239 | { |
f88f2b4f | 240 | pr_info("APIC: switched to apic NOOP\n"); |
a933c618 | 241 | apic = &apic_noop; |
08306ce6 CG |
242 | } |
243 | ||
c1eeb2de | 244 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
245 | { |
246 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
247 | cpu_relax(); | |
248 | } | |
249 | ||
c1eeb2de | 250 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 251 | { |
3c6bb07a | 252 | u32 send_status; |
8339e9fb FLV |
253 | int timeout; |
254 | ||
255 | timeout = 0; | |
256 | do { | |
257 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
258 | if (!send_status) | |
259 | break; | |
b49d7d87 | 260 | inc_irq_stat(icr_read_retry_count); |
8339e9fb FLV |
261 | udelay(100); |
262 | } while (timeout++ < 1000); | |
263 | ||
264 | return send_status; | |
265 | } | |
266 | ||
c1eeb2de | 267 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 268 | { |
ea7bdc65 JK |
269 | unsigned long flags; |
270 | ||
271 | local_irq_save(flags); | |
ed4e5ec1 | 272 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d | 273 | apic_write(APIC_ICR, low); |
ea7bdc65 | 274 | local_irq_restore(flags); |
1b374e4d SS |
275 | } |
276 | ||
c1eeb2de | 277 | u64 native_apic_icr_read(void) |
1b374e4d SS |
278 | { |
279 | u32 icr1, icr2; | |
280 | ||
281 | icr2 = apic_read(APIC_ICR2); | |
282 | icr1 = apic_read(APIC_ICR); | |
283 | ||
cf9768d7 | 284 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
285 | } |
286 | ||
7c37e48b CG |
287 | #ifdef CONFIG_X86_32 |
288 | /** | |
289 | * get_physical_broadcast - Get number of physical broadcast IDs | |
290 | */ | |
291 | int get_physical_broadcast(void) | |
292 | { | |
293 | return modern_apic() ? 0xff : 0xf; | |
294 | } | |
295 | #endif | |
296 | ||
0e078e2f TG |
297 | /** |
298 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
299 | */ | |
37e650c7 | 300 | int lapic_get_maxlvt(void) |
1da177e4 | 301 | { |
36a028de | 302 | unsigned int v; |
1da177e4 LT |
303 | |
304 | v = apic_read(APIC_LVR); | |
36a028de CG |
305 | /* |
306 | * - we always have APIC integrated on 64bit mode | |
307 | * - 82489DXs do not report # of LVT entries | |
308 | */ | |
309 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
310 | } |
311 | ||
274cfe59 CG |
312 | /* |
313 | * Local APIC timer | |
314 | */ | |
315 | ||
c40aaec6 | 316 | /* Clock divisor */ |
c40aaec6 | 317 | #define APIC_DIVISOR 16 |
1a9e4c56 | 318 | #define TSC_DIVISOR 8 |
f07f4f90 | 319 | |
0e078e2f TG |
320 | /* |
321 | * This function sets up the local APIC timer, with a timeout of | |
322 | * 'clocks' APIC bus clock. During calibration we actually call | |
323 | * this function twice on the boot CPU, once with a bogus timeout | |
324 | * value, second time for real. The other (noncalibrating) CPUs | |
325 | * call this function only once, with the real, calibrated value. | |
326 | * | |
327 | * We do reads before writes even if unnecessary, to get around the | |
328 | * P5 APIC double write bug. | |
329 | */ | |
0e078e2f | 330 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 331 | { |
0e078e2f | 332 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 333 | |
0e078e2f TG |
334 | lvtt_value = LOCAL_TIMER_VECTOR; |
335 | if (!oneshot) | |
336 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
279f1461 SS |
337 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
338 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; | |
339 | ||
f07f4f90 CG |
340 | if (!lapic_is_integrated()) |
341 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
342 | ||
0e078e2f TG |
343 | if (!irqen) |
344 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 345 | |
0e078e2f | 346 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 | 347 | |
279f1461 | 348 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
5d7c631d SL |
349 | /* |
350 | * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, | |
351 | * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. | |
352 | * According to Intel, MFENCE can do the serialization here. | |
353 | */ | |
354 | asm volatile("mfence" : : : "memory"); | |
355 | ||
279f1461 SS |
356 | printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); |
357 | return; | |
358 | } | |
359 | ||
1da177e4 | 360 | /* |
0e078e2f | 361 | * Divide PICLK by 16 |
1da177e4 | 362 | */ |
0e078e2f | 363 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
364 | apic_write(APIC_TDCR, |
365 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
366 | APIC_TDR_DIV_16); | |
0e078e2f TG |
367 | |
368 | if (!oneshot) | |
f07f4f90 | 369 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
370 | } |
371 | ||
0e078e2f | 372 | /* |
a68c439b | 373 | * Setup extended LVT, AMD specific |
7b83dae7 | 374 | * |
a68c439b RR |
375 | * Software should use the LVT offsets the BIOS provides. The offsets |
376 | * are determined by the subsystems using it like those for MCE | |
377 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
378 | * are supported. Beginning with family 10h at least 4 offsets are | |
379 | * available. | |
286f5718 | 380 | * |
a68c439b RR |
381 | * Since the offsets must be consistent for all cores, we keep track |
382 | * of the LVT offsets in software and reserve the offset for the same | |
383 | * vector also to be used on other cores. An offset is freed by | |
384 | * setting the entry to APIC_EILVT_MASKED. | |
385 | * | |
386 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
387 | * "[Firmware Bug]: ..." error message is generated. However, if | |
388 | * software does not properly determines the offsets, it is not | |
389 | * necessarily a BIOS bug. | |
0e078e2f | 390 | */ |
7b83dae7 | 391 | |
a68c439b RR |
392 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
393 | ||
394 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
395 | { | |
396 | return (old & APIC_EILVT_MASKED) | |
397 | || (new == APIC_EILVT_MASKED) | |
398 | || ((new & ~APIC_EILVT_MASKED) == old); | |
399 | } | |
400 | ||
401 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
402 | { | |
8abc3122 | 403 | unsigned int rsvd, vector; |
a68c439b RR |
404 | |
405 | if (offset >= APIC_EILVT_NR_MAX) | |
406 | return ~0; | |
407 | ||
8abc3122 | 408 | rsvd = atomic_read(&eilvt_offsets[offset]); |
a68c439b | 409 | do { |
8abc3122 RR |
410 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
411 | if (vector && !eilvt_entry_is_changeable(vector, new)) | |
a68c439b RR |
412 | /* may not change if vectors are different */ |
413 | return rsvd; | |
414 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); | |
415 | } while (rsvd != new); | |
416 | ||
8abc3122 RR |
417 | rsvd &= ~APIC_EILVT_MASKED; |
418 | if (rsvd && rsvd != vector) | |
419 | pr_info("LVT offset %d assigned for vector 0x%02x\n", | |
420 | offset, rsvd); | |
421 | ||
a68c439b RR |
422 | return new; |
423 | } | |
424 | ||
425 | /* | |
426 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
427 | * enables the vector. See also the BKDGs. Must be called with |
428 | * preemption disabled. | |
a68c439b RR |
429 | */ |
430 | ||
27afdf20 | 431 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 432 | { |
a68c439b RR |
433 | unsigned long reg = APIC_EILVTn(offset); |
434 | unsigned int new, old, reserved; | |
435 | ||
436 | new = (mask << 16) | (msg_type << 8) | vector; | |
437 | old = apic_read(reg); | |
438 | reserved = reserve_eilvt_offset(offset, new); | |
439 | ||
440 | if (reserved != new) { | |
eb48c9cb RR |
441 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
442 | "vector 0x%x, but the register is already in use for " | |
443 | "vector 0x%x on another cpu\n", | |
444 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
445 | return -EINVAL; |
446 | } | |
447 | ||
448 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
449 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
450 | "vector 0x%x, but the register is already in use for " | |
451 | "vector 0x%x on this cpu\n", | |
452 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
453 | return -EBUSY; |
454 | } | |
455 | ||
456 | apic_write(reg, new); | |
a8fcf1a2 | 457 | |
a68c439b | 458 | return 0; |
1da177e4 | 459 | } |
27afdf20 | 460 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 461 | |
0e078e2f TG |
462 | /* |
463 | * Program the next event, relative to now | |
464 | */ | |
465 | static int lapic_next_event(unsigned long delta, | |
466 | struct clock_event_device *evt) | |
1da177e4 | 467 | { |
0e078e2f TG |
468 | apic_write(APIC_TMICT, delta); |
469 | return 0; | |
1da177e4 LT |
470 | } |
471 | ||
279f1461 SS |
472 | static int lapic_next_deadline(unsigned long delta, |
473 | struct clock_event_device *evt) | |
474 | { | |
475 | u64 tsc; | |
476 | ||
4ea1636b | 477 | tsc = rdtsc(); |
279f1461 SS |
478 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); |
479 | return 0; | |
480 | } | |
481 | ||
b23d8e52 | 482 | static int lapic_timer_shutdown(struct clock_event_device *evt) |
9b7711f0 | 483 | { |
0e078e2f | 484 | unsigned int v; |
9b7711f0 | 485 | |
0e078e2f TG |
486 | /* Lapic used as dummy for broadcast ? */ |
487 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
b23d8e52 | 488 | return 0; |
9b7711f0 | 489 | |
b23d8e52 VK |
490 | v = apic_read(APIC_LVTT); |
491 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
492 | apic_write(APIC_LVTT, v); | |
493 | apic_write(APIC_TMICT, 0); | |
b23d8e52 VK |
494 | return 0; |
495 | } | |
9b7711f0 | 496 | |
b23d8e52 VK |
497 | static inline int |
498 | lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) | |
499 | { | |
b23d8e52 VK |
500 | /* Lapic used as dummy for broadcast ? */ |
501 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
502 | return 0; | |
9b7711f0 | 503 | |
b23d8e52 | 504 | __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); |
b23d8e52 VK |
505 | return 0; |
506 | } | |
507 | ||
508 | static int lapic_timer_set_periodic(struct clock_event_device *evt) | |
509 | { | |
510 | return lapic_timer_set_periodic_oneshot(evt, false); | |
511 | } | |
512 | ||
513 | static int lapic_timer_set_oneshot(struct clock_event_device *evt) | |
514 | { | |
515 | return lapic_timer_set_periodic_oneshot(evt, true); | |
9b7711f0 HS |
516 | } |
517 | ||
1da177e4 | 518 | /* |
0e078e2f | 519 | * Local APIC timer broadcast function |
1da177e4 | 520 | */ |
9628937d | 521 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 522 | { |
0e078e2f | 523 | #ifdef CONFIG_SMP |
dac5f412 | 524 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
525 | #endif |
526 | } | |
1da177e4 | 527 | |
25874a29 HK |
528 | |
529 | /* | |
530 | * The local apic timer can be used for any function which is CPU local. | |
531 | */ | |
532 | static struct clock_event_device lapic_clockevent = { | |
b23d8e52 VK |
533 | .name = "lapic", |
534 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
535 | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP | |
536 | | CLOCK_EVT_FEAT_DUMMY, | |
537 | .shift = 32, | |
538 | .set_state_shutdown = lapic_timer_shutdown, | |
539 | .set_state_periodic = lapic_timer_set_periodic, | |
540 | .set_state_oneshot = lapic_timer_set_oneshot, | |
541 | .set_next_event = lapic_next_event, | |
542 | .broadcast = lapic_timer_broadcast, | |
543 | .rating = 100, | |
544 | .irq = -1, | |
25874a29 HK |
545 | }; |
546 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
547 | ||
0e078e2f | 548 | /* |
421f91d2 | 549 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
550 | * of the boot CPU and register the clock event in the framework. |
551 | */ | |
148f9bb8 | 552 | static void setup_APIC_timer(void) |
0e078e2f | 553 | { |
89cbc767 | 554 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
1da177e4 | 555 | |
349c004e | 556 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 VP |
557 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
558 | /* Make LAPIC timer preferrable over percpu HPET */ | |
559 | lapic_clockevent.rating = 150; | |
560 | } | |
561 | ||
0e078e2f | 562 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 563 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 564 | |
279f1461 SS |
565 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
566 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | | |
567 | CLOCK_EVT_FEAT_DUMMY); | |
568 | levt->set_next_event = lapic_next_deadline; | |
569 | clockevents_config_and_register(levt, | |
1a9e4c56 | 570 | tsc_khz * (1000 / TSC_DIVISOR), |
279f1461 SS |
571 | 0xF, ~0UL); |
572 | } else | |
573 | clockevents_register_device(levt); | |
0e078e2f | 574 | } |
1da177e4 | 575 | |
6731b0d6 NS |
576 | /* |
577 | * Install the updated TSC frequency from recalibration at the TSC | |
578 | * deadline clockevent devices. | |
579 | */ | |
580 | static void __lapic_update_tsc_freq(void *info) | |
581 | { | |
582 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); | |
583 | ||
584 | if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) | |
585 | return; | |
586 | ||
587 | clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); | |
588 | } | |
589 | ||
590 | void lapic_update_tsc_freq(void) | |
591 | { | |
592 | /* | |
593 | * The clockevent device's ->mult and ->shift can both be | |
594 | * changed. In order to avoid races, schedule the frequency | |
595 | * update code on each CPU. | |
596 | */ | |
597 | on_each_cpu(__lapic_update_tsc_freq, NULL, 0); | |
598 | } | |
599 | ||
2f04fa88 YL |
600 | /* |
601 | * In this functions we calibrate APIC bus clocks to the external timer. | |
602 | * | |
603 | * We want to do the calibration only once since we want to have local timer | |
604 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
605 | * frequency. | |
606 | * | |
607 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
608 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
609 | * readout is broken, so it never gets out of the wait loop again. This was | |
610 | * also reported by others. | |
611 | * | |
612 | * Monitoring the jiffies value is inaccurate and the clockevents | |
613 | * infrastructure allows us to do a simple substitution of the interrupt | |
614 | * handler. | |
615 | * | |
616 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
617 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
618 | * back to normal later in the boot process). | |
619 | */ | |
620 | ||
621 | #define LAPIC_CAL_LOOPS (HZ/10) | |
622 | ||
623 | static __initdata int lapic_cal_loops = -1; | |
624 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
625 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
626 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
627 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
628 | ||
629 | /* | |
630 | * Temporary interrupt handler. | |
631 | */ | |
632 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
633 | { | |
634 | unsigned long long tsc = 0; | |
635 | long tapic = apic_read(APIC_TMCCT); | |
636 | unsigned long pm = acpi_pm_read_early(); | |
637 | ||
59e21e3d | 638 | if (boot_cpu_has(X86_FEATURE_TSC)) |
4ea1636b | 639 | tsc = rdtsc(); |
2f04fa88 YL |
640 | |
641 | switch (lapic_cal_loops++) { | |
642 | case 0: | |
643 | lapic_cal_t1 = tapic; | |
644 | lapic_cal_tsc1 = tsc; | |
645 | lapic_cal_pm1 = pm; | |
646 | lapic_cal_j1 = jiffies; | |
647 | break; | |
648 | ||
649 | case LAPIC_CAL_LOOPS: | |
650 | lapic_cal_t2 = tapic; | |
651 | lapic_cal_tsc2 = tsc; | |
652 | if (pm < lapic_cal_pm1) | |
653 | pm += ACPI_PM_OVRRUN; | |
654 | lapic_cal_pm2 = pm; | |
655 | lapic_cal_j2 = jiffies; | |
656 | break; | |
657 | } | |
658 | } | |
659 | ||
754ef0cd YI |
660 | static int __init |
661 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
662 | { |
663 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
664 | const long pm_thresh = pm_100ms / 100; | |
665 | unsigned long mult; | |
666 | u64 res; | |
667 | ||
668 | #ifndef CONFIG_X86_PM_TIMER | |
669 | return -1; | |
670 | #endif | |
671 | ||
39ba5d43 | 672 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
673 | |
674 | /* Check, if the PM timer is available */ | |
675 | if (!deltapm) | |
676 | return -1; | |
677 | ||
678 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
679 | ||
680 | if (deltapm > (pm_100ms - pm_thresh) && | |
681 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 682 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
683 | return 0; |
684 | } | |
685 | ||
686 | res = (((u64)deltapm) * mult) >> 22; | |
687 | do_div(res, 1000000); | |
688 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 689 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
690 | |
691 | /* Correct the lapic counter value */ | |
692 | res = (((u64)(*delta)) * pm_100ms); | |
693 | do_div(res, deltapm); | |
694 | pr_info("APIC delta adjusted to PM-Timer: " | |
695 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
696 | *delta = (long)res; | |
697 | ||
698 | /* Correct the tsc counter value */ | |
59e21e3d | 699 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
754ef0cd | 700 | res = (((u64)(*deltatsc)) * pm_100ms); |
b189892d | 701 | do_div(res, deltapm); |
754ef0cd | 702 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 703 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
704 | (unsigned long)res, *deltatsc); |
705 | *deltatsc = (long)res; | |
b189892d CG |
706 | } |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
2f04fa88 YL |
711 | static int __init calibrate_APIC_clock(void) |
712 | { | |
89cbc767 | 713 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
2f04fa88 YL |
714 | void (*real_handler)(struct clock_event_device *dev); |
715 | unsigned long deltaj; | |
754ef0cd | 716 | long delta, deltatsc; |
2f04fa88 YL |
717 | int pm_referenced = 0; |
718 | ||
1ade93ef JP |
719 | /** |
720 | * check if lapic timer has already been calibrated by platform | |
721 | * specific routine, such as tsc calibration code. if so, we just fill | |
722 | * in the clockevent structure and return. | |
723 | */ | |
724 | ||
279f1461 SS |
725 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
726 | return 0; | |
727 | } else if (lapic_timer_frequency) { | |
1ade93ef JP |
728 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
729 | lapic_timer_frequency); | |
730 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, | |
731 | TICK_NSEC, lapic_clockevent.shift); | |
732 | lapic_clockevent.max_delta_ns = | |
733 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
734 | lapic_clockevent.min_delta_ns = | |
735 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
736 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
737 | return 0; | |
738 | } | |
739 | ||
279f1461 SS |
740 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
741 | "calibrating APIC timer ...\n"); | |
742 | ||
2f04fa88 YL |
743 | local_irq_disable(); |
744 | ||
745 | /* Replace the global interrupt handler */ | |
746 | real_handler = global_clock_event->event_handler; | |
747 | global_clock_event->event_handler = lapic_cal_handler; | |
748 | ||
749 | /* | |
81608f3c | 750 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
751 | * can underflow in the 100ms detection time frame |
752 | */ | |
81608f3c | 753 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
754 | |
755 | /* Let the interrupts run */ | |
756 | local_irq_enable(); | |
757 | ||
758 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
759 | cpu_relax(); | |
760 | ||
761 | local_irq_disable(); | |
762 | ||
763 | /* Restore the real event handler */ | |
764 | global_clock_event->event_handler = real_handler; | |
765 | ||
766 | /* Build delta t1-t2 as apic timer counts down */ | |
767 | delta = lapic_cal_t1 - lapic_cal_t2; | |
768 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
769 | ||
754ef0cd YI |
770 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
771 | ||
b189892d CG |
772 | /* we trust the PM based calibration if possible */ |
773 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 774 | &delta, &deltatsc); |
2f04fa88 YL |
775 | |
776 | /* Calculate the scaled math multiplication factor */ | |
777 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
778 | lapic_clockevent.shift); | |
779 | lapic_clockevent.max_delta_ns = | |
4aed89d6 | 780 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
2f04fa88 YL |
781 | lapic_clockevent.min_delta_ns = |
782 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
783 | ||
1ade93ef | 784 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
2f04fa88 YL |
785 | |
786 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 787 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 | 788 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
1ade93ef | 789 | lapic_timer_frequency); |
2f04fa88 | 790 | |
59e21e3d | 791 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
2f04fa88 YL |
792 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
793 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
794 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
795 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
796 | } |
797 | ||
798 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
799 | "%u.%04u MHz.\n", | |
1ade93ef JP |
800 | lapic_timer_frequency / (1000000 / HZ), |
801 | lapic_timer_frequency % (1000000 / HZ)); | |
2f04fa88 YL |
802 | |
803 | /* | |
804 | * Do a sanity check on the APIC calibration result | |
805 | */ | |
1ade93ef | 806 | if (lapic_timer_frequency < (1000000 / HZ)) { |
2f04fa88 | 807 | local_irq_enable(); |
ba21ebb6 | 808 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
809 | return -1; |
810 | } | |
811 | ||
812 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
813 | ||
b189892d CG |
814 | /* |
815 | * PM timer calibration failed or not turned on | |
816 | * so lets try APIC timer based calibration | |
817 | */ | |
2f04fa88 YL |
818 | if (!pm_referenced) { |
819 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
820 | ||
821 | /* | |
822 | * Setup the apic timer manually | |
823 | */ | |
824 | levt->event_handler = lapic_cal_handler; | |
b23d8e52 | 825 | lapic_timer_set_periodic(levt); |
2f04fa88 YL |
826 | lapic_cal_loops = -1; |
827 | ||
828 | /* Let the interrupts run */ | |
829 | local_irq_enable(); | |
830 | ||
831 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
832 | cpu_relax(); | |
833 | ||
2f04fa88 | 834 | /* Stop the lapic timer */ |
c948c260 | 835 | local_irq_disable(); |
b23d8e52 | 836 | lapic_timer_shutdown(levt); |
2f04fa88 | 837 | |
2f04fa88 YL |
838 | /* Jiffies delta */ |
839 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
840 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
841 | ||
842 | /* Check, if the jiffies result is consistent */ | |
843 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
844 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
845 | else | |
846 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
c948c260 TG |
847 | } |
848 | local_irq_enable(); | |
2f04fa88 YL |
849 | |
850 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 851 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
852 | return -1; |
853 | } | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
e83a5fdc HS |
858 | /* |
859 | * Setup the boot APIC | |
860 | * | |
861 | * Calibrate and verify the result. | |
862 | */ | |
0e078e2f TG |
863 | void __init setup_boot_APIC_clock(void) |
864 | { | |
865 | /* | |
274cfe59 CG |
866 | * The local apic timer can be disabled via the kernel |
867 | * commandline or from the CPU detection code. Register the lapic | |
868 | * timer as a dummy clock event source on SMP systems, so the | |
869 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
870 | */ |
871 | if (disable_apic_timer) { | |
ba21ebb6 | 872 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 873 | /* No broadcast on UP ! */ |
9d09951d TG |
874 | if (num_possible_cpus() > 1) { |
875 | lapic_clockevent.mult = 1; | |
0e078e2f | 876 | setup_APIC_timer(); |
9d09951d | 877 | } |
0e078e2f TG |
878 | return; |
879 | } | |
880 | ||
89b3b1f4 | 881 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
882 | /* No broadcast on UP ! */ |
883 | if (num_possible_cpus() > 1) | |
884 | setup_APIC_timer(); | |
885 | return; | |
886 | } | |
887 | ||
0e078e2f TG |
888 | /* |
889 | * If nmi_watchdog is set to IO_APIC, we need the | |
890 | * PIT/HPET going. Otherwise register lapic as a dummy | |
891 | * device. | |
892 | */ | |
072b198a | 893 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 894 | |
274cfe59 | 895 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
896 | setup_APIC_timer(); |
897 | } | |
898 | ||
148f9bb8 | 899 | void setup_secondary_APIC_clock(void) |
0e078e2f | 900 | { |
0e078e2f TG |
901 | setup_APIC_timer(); |
902 | } | |
903 | ||
904 | /* | |
905 | * The guts of the apic timer interrupt | |
906 | */ | |
907 | static void local_apic_timer_interrupt(void) | |
908 | { | |
909 | int cpu = smp_processor_id(); | |
910 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
911 | ||
912 | /* | |
913 | * Normally we should not be here till LAPIC has been initialized but | |
914 | * in some cases like kdump, its possible that there is a pending LAPIC | |
915 | * timer interrupt from previous kernel's context and is delivered in | |
916 | * new kernel the moment interrupts are enabled. | |
917 | * | |
918 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
919 | * its possible that when we get here evt->event_handler is NULL. | |
920 | * Check for event_handler being NULL and discard the interrupt as | |
921 | * spurious. | |
922 | */ | |
923 | if (!evt->event_handler) { | |
ba21ebb6 | 924 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f | 925 | /* Switch it off */ |
b23d8e52 | 926 | lapic_timer_shutdown(evt); |
0e078e2f TG |
927 | return; |
928 | } | |
929 | ||
930 | /* | |
931 | * the NMI deadlock-detector uses this. | |
932 | */ | |
915b0d01 | 933 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
934 | |
935 | evt->event_handler(evt); | |
936 | } | |
937 | ||
938 | /* | |
939 | * Local APIC timer interrupt. This is the most natural way for doing | |
940 | * local interrupts, but local timer interrupts can be emulated by | |
941 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
942 | * | |
943 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
944 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
945 | */ | |
1d9090e2 | 946 | __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
947 | { |
948 | struct pt_regs *old_regs = set_irq_regs(regs); | |
949 | ||
950 | /* | |
951 | * NOTE! We'd better ACK the irq immediately, | |
952 | * because timer handling can be slow. | |
eddc0e92 | 953 | * |
0e078e2f TG |
954 | * update_process_times() expects us to have done irq_enter(). |
955 | * Besides, if we don't timer interrupts ignore the global | |
956 | * interrupt lock, which is the WrongThing (tm) to do. | |
0e078e2f | 957 | */ |
eddc0e92 | 958 | entering_ack_irq(); |
0e078e2f | 959 | local_apic_timer_interrupt(); |
eddc0e92 | 960 | exiting_irq(); |
274cfe59 | 961 | |
0e078e2f TG |
962 | set_irq_regs(old_regs); |
963 | } | |
964 | ||
1d9090e2 | 965 | __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) |
cf910e83 SA |
966 | { |
967 | struct pt_regs *old_regs = set_irq_regs(regs); | |
968 | ||
0e078e2f | 969 | /* |
cf910e83 SA |
970 | * NOTE! We'd better ACK the irq immediately, |
971 | * because timer handling can be slow. | |
972 | * | |
0e078e2f TG |
973 | * update_process_times() expects us to have done irq_enter(). |
974 | * Besides, if we don't timer interrupts ignore the global | |
975 | * interrupt lock, which is the WrongThing (tm) to do. | |
976 | */ | |
cf910e83 SA |
977 | entering_ack_irq(); |
978 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); | |
0e078e2f | 979 | local_apic_timer_interrupt(); |
cf910e83 SA |
980 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
981 | exiting_irq(); | |
274cfe59 | 982 | |
0e078e2f TG |
983 | set_irq_regs(old_regs); |
984 | } | |
985 | ||
986 | int setup_profiling_timer(unsigned int multiplier) | |
987 | { | |
988 | return -EINVAL; | |
989 | } | |
990 | ||
0e078e2f TG |
991 | /* |
992 | * Local APIC start and shutdown | |
993 | */ | |
994 | ||
995 | /** | |
996 | * clear_local_APIC - shutdown the local APIC | |
997 | * | |
998 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
999 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
1000 | * leftovers during boot. | |
1001 | */ | |
1002 | void clear_local_APIC(void) | |
1003 | { | |
2584a82d | 1004 | int maxlvt; |
0e078e2f TG |
1005 | u32 v; |
1006 | ||
d3432896 | 1007 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 1008 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
1009 | return; |
1010 | ||
1011 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
1012 | /* |
1013 | * Masking an LVT entry can trigger a local APIC error | |
1014 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1015 | */ | |
1016 | if (maxlvt >= 3) { | |
1017 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
1018 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
1019 | } | |
1020 | /* | |
1021 | * Careful: we have to set masks only first to deassert | |
1022 | * any level-triggered sources. | |
1023 | */ | |
1024 | v = apic_read(APIC_LVTT); | |
1025 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
1026 | v = apic_read(APIC_LVT0); | |
1027 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
1028 | v = apic_read(APIC_LVT1); | |
1029 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
1030 | if (maxlvt >= 4) { | |
1031 | v = apic_read(APIC_LVTPC); | |
1032 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1033 | } | |
1034 | ||
6764014b | 1035 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 1036 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
1037 | if (maxlvt >= 5) { |
1038 | v = apic_read(APIC_LVTTHMR); | |
1039 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
1040 | } | |
1041 | #endif | |
5ca8681c AK |
1042 | #ifdef CONFIG_X86_MCE_INTEL |
1043 | if (maxlvt >= 6) { | |
1044 | v = apic_read(APIC_LVTCMCI); | |
1045 | if (!(v & APIC_LVT_MASKED)) | |
1046 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
1047 | } | |
1048 | #endif | |
1049 | ||
0e078e2f TG |
1050 | /* |
1051 | * Clean APIC state for other OSs: | |
1052 | */ | |
1053 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
1054 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1055 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1056 | if (maxlvt >= 3) | |
1057 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
1058 | if (maxlvt >= 4) | |
1059 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
1060 | |
1061 | /* Integrated APIC (!82489DX) ? */ | |
1062 | if (lapic_is_integrated()) { | |
1063 | if (maxlvt > 3) | |
1064 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
1065 | apic_write(APIC_ESR, 0); | |
1066 | apic_read(APIC_ESR); | |
1067 | } | |
0e078e2f TG |
1068 | } |
1069 | ||
1070 | /** | |
1071 | * disable_local_APIC - clear and disable the local APIC | |
1072 | */ | |
1073 | void disable_local_APIC(void) | |
1074 | { | |
1075 | unsigned int value; | |
1076 | ||
4a13ad0b | 1077 | /* APIC hasn't been mapped yet */ |
fd19dce7 | 1078 | if (!x2apic_mode && !apic_phys) |
4a13ad0b JB |
1079 | return; |
1080 | ||
0e078e2f TG |
1081 | clear_local_APIC(); |
1082 | ||
1083 | /* | |
1084 | * Disable APIC (implies clearing of registers | |
1085 | * for 82489DX!). | |
1086 | */ | |
1087 | value = apic_read(APIC_SPIV); | |
1088 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1089 | apic_write(APIC_SPIV, value); | |
990b183e CG |
1090 | |
1091 | #ifdef CONFIG_X86_32 | |
1092 | /* | |
1093 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
1094 | * restore the disabled state. | |
1095 | */ | |
1096 | if (enabled_via_apicbase) { | |
1097 | unsigned int l, h; | |
1098 | ||
1099 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1100 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1101 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1102 | } | |
1103 | #endif | |
0e078e2f TG |
1104 | } |
1105 | ||
fe4024dc CG |
1106 | /* |
1107 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1108 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1109 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1110 | * for the case where Linux didn't enable the LAPIC. | |
1111 | */ | |
0e078e2f TG |
1112 | void lapic_shutdown(void) |
1113 | { | |
1114 | unsigned long flags; | |
1115 | ||
93984fbd | 1116 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
0e078e2f TG |
1117 | return; |
1118 | ||
1119 | local_irq_save(flags); | |
1120 | ||
fe4024dc CG |
1121 | #ifdef CONFIG_X86_32 |
1122 | if (!enabled_via_apicbase) | |
1123 | clear_local_APIC(); | |
1124 | else | |
1125 | #endif | |
1126 | disable_local_APIC(); | |
1127 | ||
0e078e2f TG |
1128 | |
1129 | local_irq_restore(flags); | |
1130 | } | |
1131 | ||
0e078e2f TG |
1132 | /** |
1133 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1134 | */ | |
1da177e4 LT |
1135 | void __init sync_Arb_IDs(void) |
1136 | { | |
296cb951 CG |
1137 | /* |
1138 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1139 | * needed on AMD. | |
1140 | */ | |
1141 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1142 | return; |
1143 | ||
1144 | /* | |
1145 | * Wait for idle. | |
1146 | */ | |
1147 | apic_wait_icr_idle(); | |
1148 | ||
1149 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1150 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1151 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1152 | } |
1153 | ||
1da177e4 LT |
1154 | /* |
1155 | * An initial setup of the virtual wire mode. | |
1156 | */ | |
1157 | void __init init_bsp_APIC(void) | |
1158 | { | |
11a8e778 | 1159 | unsigned int value; |
1da177e4 LT |
1160 | |
1161 | /* | |
1162 | * Don't do the setup now if we have a SMP BIOS as the | |
1163 | * through-I/O-APIC virtual wire mode might be active. | |
1164 | */ | |
93984fbd | 1165 | if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) |
1da177e4 LT |
1166 | return; |
1167 | ||
1da177e4 LT |
1168 | /* |
1169 | * Do not trust the local APIC being empty at bootup. | |
1170 | */ | |
1171 | clear_local_APIC(); | |
1172 | ||
1173 | /* | |
1174 | * Enable APIC. | |
1175 | */ | |
1176 | value = apic_read(APIC_SPIV); | |
1177 | value &= ~APIC_VECTOR_MASK; | |
1178 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1179 | |
1180 | #ifdef CONFIG_X86_32 | |
1181 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1182 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1183 | (boot_cpu_data.x86 == 15)) | |
1184 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1185 | else | |
1186 | #endif | |
1187 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1188 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1189 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1190 | |
1191 | /* | |
1192 | * Set up the virtual wire mode. | |
1193 | */ | |
11a8e778 | 1194 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1195 | value = APIC_DM_NMI; |
638c0411 CG |
1196 | if (!lapic_is_integrated()) /* 82489DX */ |
1197 | value |= APIC_LVT_LEVEL_TRIGGER; | |
b7c4948e HK |
1198 | if (apic_extnmi == APIC_EXTNMI_NONE) |
1199 | value |= APIC_LVT_MASKED; | |
11a8e778 | 1200 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1201 | } |
1202 | ||
148f9bb8 | 1203 | static void lapic_setup_esr(void) |
c43da2f5 | 1204 | { |
9df08f10 CG |
1205 | unsigned int oldvalue, value, maxlvt; |
1206 | ||
1207 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1208 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1209 | return; |
1210 | } | |
c43da2f5 | 1211 | |
08125d3e | 1212 | if (apic->disable_esr) { |
c43da2f5 | 1213 | /* |
9df08f10 CG |
1214 | * Something untraceable is creating bad interrupts on |
1215 | * secondary quads ... for the moment, just leave the | |
1216 | * ESR disabled - we can't do anything useful with the | |
1217 | * errors anyway - mbligh | |
c43da2f5 | 1218 | */ |
ba21ebb6 | 1219 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1220 | return; |
c43da2f5 | 1221 | } |
9df08f10 CG |
1222 | |
1223 | maxlvt = lapic_get_maxlvt(); | |
1224 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1225 | apic_write(APIC_ESR, 0); | |
1226 | oldvalue = apic_read(APIC_ESR); | |
1227 | ||
1228 | /* enables sending errors */ | |
1229 | value = ERROR_APIC_VECTOR; | |
1230 | apic_write(APIC_LVTERR, value); | |
1231 | ||
1232 | /* | |
1233 | * spec says clear errors after enabling vector. | |
1234 | */ | |
1235 | if (maxlvt > 3) | |
1236 | apic_write(APIC_ESR, 0); | |
1237 | value = apic_read(APIC_ESR); | |
1238 | if (value != oldvalue) | |
1239 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1240 | "vector: 0x%08x after: 0x%08x\n", | |
1241 | oldvalue, value); | |
c43da2f5 CG |
1242 | } |
1243 | ||
0e078e2f TG |
1244 | /** |
1245 | * setup_local_APIC - setup the local APIC | |
0aa002fe TH |
1246 | * |
1247 | * Used to setup local APIC while initializing BSP or bringin up APs. | |
1248 | * Always called with preemption disabled. | |
0e078e2f | 1249 | */ |
148f9bb8 | 1250 | void setup_local_APIC(void) |
1da177e4 | 1251 | { |
0aa002fe | 1252 | int cpu = smp_processor_id(); |
8c3ba8d0 KJ |
1253 | unsigned int value, queued; |
1254 | int i, j, acked = 0; | |
1255 | unsigned long long tsc = 0, ntsc; | |
b47dcbdc | 1256 | long long max_loops = cpu_khz ? cpu_khz : 1000000; |
8c3ba8d0 | 1257 | |
59e21e3d | 1258 | if (boot_cpu_has(X86_FEATURE_TSC)) |
4ea1636b | 1259 | tsc = rdtsc(); |
1da177e4 | 1260 | |
f1182638 | 1261 | if (disable_apic) { |
7167d08e | 1262 | disable_ioapic_support(); |
f1182638 JB |
1263 | return; |
1264 | } | |
1265 | ||
89c38c28 CG |
1266 | #ifdef CONFIG_X86_32 |
1267 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1268 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1269 | apic_write(APIC_ESR, 0); |
1270 | apic_write(APIC_ESR, 0); | |
1271 | apic_write(APIC_ESR, 0); | |
1272 | apic_write(APIC_ESR, 0); | |
1273 | } | |
1274 | #endif | |
cdd6c482 | 1275 | perf_events_lapic_init(); |
89c38c28 | 1276 | |
1da177e4 LT |
1277 | /* |
1278 | * Double-check whether this APIC is really registered. | |
1279 | * This is meaningless in clustered apic mode, so we skip it. | |
1280 | */ | |
c2777f98 | 1281 | BUG_ON(!apic->apic_id_registered()); |
1da177e4 LT |
1282 | |
1283 | /* | |
1284 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1285 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1286 | * document number 292116). So here it goes... | |
1287 | */ | |
a5c43296 | 1288 | apic->init_apic_ldr(); |
1da177e4 | 1289 | |
6f802c4b TH |
1290 | #ifdef CONFIG_X86_32 |
1291 | /* | |
acb8bc09 TH |
1292 | * APIC LDR is initialized. If logical_apicid mapping was |
1293 | * initialized during get_smp_config(), make sure it matches the | |
1294 | * actual value. | |
6f802c4b | 1295 | */ |
acb8bc09 TH |
1296 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
1297 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); | |
1298 | /* always use the value from LDR */ | |
6f802c4b TH |
1299 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
1300 | logical_smp_processor_id(); | |
1301 | #endif | |
1302 | ||
1da177e4 LT |
1303 | /* |
1304 | * Set Task Priority to 'accept all'. We never change this | |
1305 | * later on. | |
1306 | */ | |
1307 | value = apic_read(APIC_TASKPRI); | |
1308 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1309 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1310 | |
da7ed9f9 VG |
1311 | /* |
1312 | * After a crash, we no longer service the interrupts and a pending | |
1313 | * interrupt from previous kernel might still have ISR bit set. | |
1314 | * | |
1315 | * Most probably by now CPU has serviced that pending interrupt and | |
1316 | * it might not have done the ack_APIC_irq() because it thought, | |
1317 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1318 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1319 | * the interrupt. Hence a vector might get locked. It was noticed | |
1320 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1321 | */ | |
8c3ba8d0 KJ |
1322 | do { |
1323 | queued = 0; | |
1324 | for (i = APIC_ISR_NR - 1; i >= 0; i--) | |
1325 | queued |= apic_read(APIC_IRR + i*0x10); | |
1326 | ||
1327 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1328 | value = apic_read(APIC_ISR + i*0x10); | |
1329 | for (j = 31; j >= 0; j--) { | |
1330 | if (value & (1<<j)) { | |
1331 | ack_APIC_irq(); | |
1332 | acked++; | |
1333 | } | |
1334 | } | |
da7ed9f9 | 1335 | } |
8c3ba8d0 KJ |
1336 | if (acked > 256) { |
1337 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", | |
1338 | acked); | |
1339 | break; | |
1340 | } | |
42fa4250 | 1341 | if (queued) { |
59e21e3d | 1342 | if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { |
4ea1636b | 1343 | ntsc = rdtsc(); |
42fa4250 SF |
1344 | max_loops = (cpu_khz << 10) - (ntsc - tsc); |
1345 | } else | |
1346 | max_loops--; | |
1347 | } | |
8c3ba8d0 KJ |
1348 | } while (queued && max_loops > 0); |
1349 | WARN_ON(max_loops <= 0); | |
da7ed9f9 | 1350 | |
1da177e4 LT |
1351 | /* |
1352 | * Now that we are all set up, enable the APIC | |
1353 | */ | |
1354 | value = apic_read(APIC_SPIV); | |
1355 | value &= ~APIC_VECTOR_MASK; | |
1356 | /* | |
1357 | * Enable APIC | |
1358 | */ | |
1359 | value |= APIC_SPIV_APIC_ENABLED; | |
1360 | ||
89c38c28 CG |
1361 | #ifdef CONFIG_X86_32 |
1362 | /* | |
1363 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1364 | * certain networking cards. If high frequency interrupts are | |
1365 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1366 | * entry is masked/unmasked at a high rate as well then sooner or | |
1367 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1368 | * from the device. If focus CPU is disabled then the hang goes | |
1369 | * away, oh well :-( | |
1370 | * | |
1371 | * [ This bug can be reproduced easily with a level-triggered | |
1372 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1373 | * BX chipset. ] | |
1374 | */ | |
1375 | /* | |
1376 | * Actually disabling the focus CPU check just makes the hang less | |
1377 | * frequent as it makes the interrupt distributon model be more | |
1378 | * like LRU than MRU (the short-term load is more even across CPUs). | |
89c38c28 CG |
1379 | */ |
1380 | ||
1381 | /* | |
1382 | * - enable focus processor (bit==0) | |
1383 | * - 64bit mode always use processor focus | |
1384 | * so no need to set it | |
1385 | */ | |
1386 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1387 | #endif | |
3f14c746 | 1388 | |
1da177e4 LT |
1389 | /* |
1390 | * Set spurious IRQ vector | |
1391 | */ | |
1392 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1393 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1394 | |
1395 | /* | |
1396 | * Set up LVT0, LVT1: | |
1397 | * | |
1398 | * set up through-local-APIC on the BP's LINT0. This is not | |
1399 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1400 | * we delegate interrupts to the 8259A. | |
1401 | */ | |
1402 | /* | |
1403 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1404 | */ | |
1405 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
0aa002fe | 1406 | if (!cpu && (pic_mode || !value)) { |
1da177e4 | 1407 | value = APIC_DM_EXTINT; |
0aa002fe | 1408 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1409 | } else { |
1410 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
0aa002fe | 1411 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1412 | } |
11a8e778 | 1413 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1414 | |
1415 | /* | |
b7c4948e HK |
1416 | * Only the BSP sees the LINT1 NMI signal by default. This can be |
1417 | * modified by apic_extnmi= boot option. | |
1da177e4 | 1418 | */ |
b7c4948e HK |
1419 | if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || |
1420 | apic_extnmi == APIC_EXTNMI_ALL) | |
1da177e4 LT |
1421 | value = APIC_DM_NMI; |
1422 | else | |
1423 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1424 | if (!lapic_is_integrated()) /* 82489DX */ |
1425 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1426 | apic_write(APIC_LVT1, value); |
89c38c28 | 1427 | |
be71b855 AK |
1428 | #ifdef CONFIG_X86_MCE_INTEL |
1429 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1430 | if (!cpu) |
be71b855 AK |
1431 | cmci_recheck(); |
1432 | #endif | |
739f33b3 | 1433 | } |
1da177e4 | 1434 | |
05f7e46d | 1435 | static void end_local_APIC_setup(void) |
739f33b3 AK |
1436 | { |
1437 | lapic_setup_esr(); | |
fa6b95fc CG |
1438 | |
1439 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1440 | { |
1441 | unsigned int value; | |
1442 | /* Disable the local apic timer */ | |
1443 | value = apic_read(APIC_LVTT); | |
1444 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1445 | apic_write(APIC_LVTT, value); | |
1446 | } | |
fa6b95fc CG |
1447 | #endif |
1448 | ||
0e078e2f | 1449 | apic_pm_activate(); |
2fb270f3 JB |
1450 | } |
1451 | ||
05f7e46d TG |
1452 | /* |
1453 | * APIC setup function for application processors. Called from smpboot.c | |
1454 | */ | |
1455 | void apic_ap_setup(void) | |
2fb270f3 | 1456 | { |
05f7e46d | 1457 | setup_local_APIC(); |
2fb270f3 | 1458 | end_local_APIC_setup(); |
1da177e4 | 1459 | } |
1da177e4 | 1460 | |
06cd9a7d | 1461 | #ifdef CONFIG_X86_X2APIC |
bfb05070 | 1462 | int x2apic_mode; |
12e189d3 TG |
1463 | |
1464 | enum { | |
1465 | X2APIC_OFF, | |
1466 | X2APIC_ON, | |
1467 | X2APIC_DISABLED, | |
1468 | }; | |
1469 | static int x2apic_state; | |
1470 | ||
d786ad32 | 1471 | static void __x2apic_disable(void) |
44e25ff9 TG |
1472 | { |
1473 | u64 msr; | |
1474 | ||
93984fbd | 1475 | if (!boot_cpu_has(X86_FEATURE_APIC)) |
659006bf TG |
1476 | return; |
1477 | ||
44e25ff9 TG |
1478 | rdmsrl(MSR_IA32_APICBASE, msr); |
1479 | if (!(msr & X2APIC_ENABLE)) | |
1480 | return; | |
1481 | /* Disable xapic and x2apic first and then reenable xapic mode */ | |
1482 | wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1483 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1484 | printk_once(KERN_INFO "x2apic disabled\n"); | |
1485 | } | |
1486 | ||
d786ad32 | 1487 | static void __x2apic_enable(void) |
659006bf TG |
1488 | { |
1489 | u64 msr; | |
1490 | ||
1491 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1492 | if (msr & X2APIC_ENABLE) | |
1493 | return; | |
1494 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); | |
1495 | printk_once(KERN_INFO "x2apic enabled\n"); | |
1496 | } | |
1497 | ||
bfb05070 TG |
1498 | static int __init setup_nox2apic(char *str) |
1499 | { | |
1500 | if (x2apic_enabled()) { | |
1501 | int apicid = native_apic_msr_read(APIC_ID); | |
1502 | ||
1503 | if (apicid >= 255) { | |
1504 | pr_warning("Apicid: %08x, cannot enforce nox2apic\n", | |
1505 | apicid); | |
1506 | return 0; | |
1507 | } | |
44e25ff9 TG |
1508 | pr_warning("x2apic already enabled.\n"); |
1509 | __x2apic_disable(); | |
1510 | } | |
1511 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
12e189d3 | 1512 | x2apic_state = X2APIC_DISABLED; |
44e25ff9 | 1513 | x2apic_mode = 0; |
bfb05070 TG |
1514 | return 0; |
1515 | } | |
1516 | early_param("nox2apic", setup_nox2apic); | |
1517 | ||
659006bf TG |
1518 | /* Called from cpu_init() to enable x2apic on (secondary) cpus */ |
1519 | void x2apic_setup(void) | |
1520 | { | |
1521 | /* | |
1522 | * If x2apic is not in ON state, disable it if already enabled | |
1523 | * from BIOS. | |
1524 | */ | |
1525 | if (x2apic_state != X2APIC_ON) { | |
1526 | __x2apic_disable(); | |
1527 | return; | |
1528 | } | |
1529 | __x2apic_enable(); | |
1530 | } | |
1531 | ||
44e25ff9 | 1532 | static __init void x2apic_disable(void) |
fb209bd8 | 1533 | { |
a57e456a | 1534 | u32 x2apic_id, state = x2apic_state; |
fb209bd8 | 1535 | |
a57e456a TG |
1536 | x2apic_mode = 0; |
1537 | x2apic_state = X2APIC_DISABLED; | |
1538 | ||
1539 | if (state != X2APIC_ON) | |
1540 | return; | |
fb209bd8 | 1541 | |
6d2d49d2 TG |
1542 | x2apic_id = read_apic_id(); |
1543 | if (x2apic_id >= 255) | |
1544 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
9aa16365 | 1545 | |
6d2d49d2 TG |
1546 | __x2apic_disable(); |
1547 | register_lapic_address(mp_lapic_addr); | |
fb209bd8 YL |
1548 | } |
1549 | ||
659006bf | 1550 | static __init void x2apic_enable(void) |
6e1cb38a | 1551 | { |
659006bf | 1552 | if (x2apic_state != X2APIC_OFF) |
06cd9a7d YL |
1553 | return; |
1554 | ||
659006bf | 1555 | x2apic_mode = 1; |
12e189d3 | 1556 | x2apic_state = X2APIC_ON; |
659006bf | 1557 | __x2apic_enable(); |
6e1cb38a | 1558 | } |
d524165c | 1559 | |
62e61633 | 1560 | static __init void try_to_enable_x2apic(int remap_mode) |
07806c50 | 1561 | { |
659006bf | 1562 | if (x2apic_state == X2APIC_DISABLED) |
07806c50 JL |
1563 | return; |
1564 | ||
62e61633 | 1565 | if (remap_mode != IRQ_REMAP_X2APIC_MODE) { |
07806c50 JL |
1566 | /* IR is required if there is APIC ID > 255 even when running |
1567 | * under KVM | |
1568 | */ | |
1569 | if (max_physical_apicid > 255 || | |
8329aa9f | 1570 | !hypervisor_x2apic_available()) { |
62e61633 | 1571 | pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); |
44e25ff9 | 1572 | x2apic_disable(); |
07806c50 JL |
1573 | return; |
1574 | } | |
1575 | ||
1576 | /* | |
1577 | * without IR all CPUs can be addressed by IOAPIC/MSI | |
1578 | * only in physical mode | |
1579 | */ | |
55eae7de | 1580 | x2apic_phys = 1; |
07806c50 | 1581 | } |
659006bf | 1582 | x2apic_enable(); |
55eae7de TG |
1583 | } |
1584 | ||
1585 | void __init check_x2apic(void) | |
1586 | { | |
1587 | if (x2apic_enabled()) { | |
1588 | pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); | |
1589 | x2apic_mode = 1; | |
12e189d3 | 1590 | x2apic_state = X2APIC_ON; |
62436a4d | 1591 | } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { |
12e189d3 | 1592 | x2apic_state = X2APIC_DISABLED; |
55eae7de TG |
1593 | } |
1594 | } | |
1595 | #else /* CONFIG_X86_X2APIC */ | |
1596 | static int __init validate_x2apic(void) | |
1597 | { | |
1598 | if (!apic_is_x2apic_enabled()) | |
1599 | return 0; | |
1600 | /* | |
1601 | * Checkme: Can we simply turn off x2apic here instead of panic? | |
1602 | */ | |
1603 | panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); | |
1604 | } | |
1605 | early_initcall(validate_x2apic); | |
1606 | ||
62e61633 | 1607 | static inline void try_to_enable_x2apic(int remap_mode) { } |
659006bf | 1608 | static inline void __x2apic_enable(void) { } |
55eae7de TG |
1609 | #endif /* !CONFIG_X86_X2APIC */ |
1610 | ||
1611 | static int __init try_to_enable_IR(void) | |
1612 | { | |
1613 | #ifdef CONFIG_X86_IO_APIC | |
1614 | if (!x2apic_enabled() && skip_ioapic_setup) { | |
1615 | pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); | |
1616 | return -1; | |
1617 | } | |
ce69a784 | 1618 | #endif |
55eae7de | 1619 | return irq_remapping_enable(); |
ce69a784 GN |
1620 | } |
1621 | ||
1622 | void __init enable_IR_x2apic(void) | |
1623 | { | |
1624 | unsigned long flags; | |
07806c50 | 1625 | int ret, ir_stat; |
b7f42ab2 | 1626 | |
07806c50 JL |
1627 | ir_stat = irq_remapping_prepare(); |
1628 | if (ir_stat < 0 && !x2apic_supported()) | |
e670761f | 1629 | return; |
ce69a784 | 1630 | |
31dce14a | 1631 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1632 | if (ret) { |
ba21ebb6 | 1633 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1634 | return; |
5ffa4eb2 | 1635 | } |
6e1cb38a | 1636 | |
05c3dc2c | 1637 | local_irq_save(flags); |
b81bb373 | 1638 | legacy_pic->mask_all(); |
31dce14a | 1639 | mask_ioapic_entries(); |
05c3dc2c | 1640 | |
6a6256f9 | 1641 | /* If irq_remapping_prepare() succeeded, try to enable it */ |
07806c50 JL |
1642 | if (ir_stat >= 0) |
1643 | ir_stat = try_to_enable_IR(); | |
1644 | /* ir_stat contains the remap mode or an error code */ | |
1645 | try_to_enable_x2apic(ir_stat); | |
a31bc327 | 1646 | |
07806c50 | 1647 | if (ir_stat < 0) |
31dce14a | 1648 | restore_ioapic_entries(); |
b81bb373 | 1649 | legacy_pic->restore_mask(); |
6e1cb38a | 1650 | local_irq_restore(flags); |
6e1cb38a | 1651 | } |
93758238 | 1652 | |
be7a656f | 1653 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1654 | /* |
1655 | * Detect and enable local APICs on non-SMP boards. | |
1656 | * Original code written by Keir Fraser. | |
1657 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1658 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1659 | */ |
0e078e2f | 1660 | static int __init detect_init_APIC(void) |
1da177e4 | 1661 | { |
93984fbd | 1662 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
ba21ebb6 | 1663 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1664 | return -1; |
1665 | } | |
1666 | ||
1667 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
1668 | return 0; |
1669 | } | |
be7a656f | 1670 | #else |
5a7ae78f | 1671 | |
25874a29 | 1672 | static int __init apic_verify(void) |
5a7ae78f TG |
1673 | { |
1674 | u32 features, h, l; | |
1675 | ||
1676 | /* | |
1677 | * The APIC feature bit should now be enabled | |
1678 | * in `cpuid' | |
1679 | */ | |
1680 | features = cpuid_edx(1); | |
1681 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
1682 | pr_warning("Could not enable APIC!\n"); | |
1683 | return -1; | |
1684 | } | |
1685 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1686 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1687 | ||
1688 | /* The BIOS may have set up the APIC at some other address */ | |
cbf2829b BD |
1689 | if (boot_cpu_data.x86 >= 6) { |
1690 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1691 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1692 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1693 | } | |
5a7ae78f TG |
1694 | |
1695 | pr_info("Found and enabled local APIC!\n"); | |
1696 | return 0; | |
1697 | } | |
1698 | ||
25874a29 | 1699 | int __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
1700 | { |
1701 | u32 h, l; | |
1702 | ||
1703 | if (disable_apic) | |
1704 | return -1; | |
1705 | ||
1706 | /* | |
1707 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1708 | * MSR. This can only be done in software for Intel P6 or later | |
1709 | * and AMD K7 (Model > 1) or later. | |
1710 | */ | |
cbf2829b BD |
1711 | if (boot_cpu_data.x86 >= 6) { |
1712 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1713 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1714 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
1715 | l &= ~MSR_IA32_APICBASE_BASE; | |
1716 | l |= MSR_IA32_APICBASE_ENABLE | addr; | |
1717 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1718 | enabled_via_apicbase = 1; | |
1719 | } | |
5a7ae78f TG |
1720 | } |
1721 | return apic_verify(); | |
1722 | } | |
1723 | ||
be7a656f YL |
1724 | /* |
1725 | * Detect and initialize APIC | |
1726 | */ | |
1727 | static int __init detect_init_APIC(void) | |
1728 | { | |
be7a656f YL |
1729 | /* Disabled by kernel option? */ |
1730 | if (disable_apic) | |
1731 | return -1; | |
1732 | ||
1733 | switch (boot_cpu_data.x86_vendor) { | |
1734 | case X86_VENDOR_AMD: | |
1735 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1736 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1737 | break; |
1738 | goto no_apic; | |
1739 | case X86_VENDOR_INTEL: | |
1740 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
93984fbd | 1741 | (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) |
be7a656f YL |
1742 | break; |
1743 | goto no_apic; | |
1744 | default: | |
1745 | goto no_apic; | |
1746 | } | |
1747 | ||
93984fbd | 1748 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
be7a656f YL |
1749 | /* |
1750 | * Over-ride BIOS and try to enable the local APIC only if | |
1751 | * "lapic" specified. | |
1752 | */ | |
1753 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1754 | pr_info("Local APIC disabled by BIOS -- " |
1755 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1756 | return -1; |
1757 | } | |
a906fdaa | 1758 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
5a7ae78f TG |
1759 | return -1; |
1760 | } else { | |
1761 | if (apic_verify()) | |
1762 | return -1; | |
be7a656f | 1763 | } |
be7a656f YL |
1764 | |
1765 | apic_pm_activate(); | |
1766 | ||
1767 | return 0; | |
1768 | ||
1769 | no_apic: | |
ba21ebb6 | 1770 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1771 | return -1; |
1772 | } | |
1773 | #endif | |
1da177e4 | 1774 | |
0e078e2f TG |
1775 | /** |
1776 | * init_apic_mappings - initialize APIC mappings | |
1777 | */ | |
1da177e4 LT |
1778 | void __init init_apic_mappings(void) |
1779 | { | |
4401da61 YL |
1780 | unsigned int new_apicid; |
1781 | ||
fc1edaf9 | 1782 | if (x2apic_mode) { |
4c9961d5 | 1783 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1784 | return; |
1785 | } | |
1786 | ||
4797f6b0 | 1787 | /* If no local APIC can be found return early */ |
1da177e4 | 1788 | if (!smp_found_config && detect_init_APIC()) { |
4797f6b0 YL |
1789 | /* lets NOP'ify apic operations */ |
1790 | pr_info("APIC: disable apic facility\n"); | |
1791 | apic_disable(); | |
1792 | } else { | |
1da177e4 LT |
1793 | apic_phys = mp_lapic_addr; |
1794 | ||
4797f6b0 YL |
1795 | /* |
1796 | * acpi lapic path already maps that address in | |
1797 | * acpi_register_lapic_address() | |
1798 | */ | |
5989cd6a | 1799 | if (!acpi_lapic && !smp_found_config) |
326a2e6b | 1800 | register_lapic_address(apic_phys); |
cec6be6d | 1801 | } |
1da177e4 LT |
1802 | |
1803 | /* | |
1804 | * Fetch the APIC ID of the BSP in case we have a | |
1805 | * default configuration (or the MP table is broken). | |
1806 | */ | |
4401da61 YL |
1807 | new_apicid = read_apic_id(); |
1808 | if (boot_cpu_physical_apicid != new_apicid) { | |
1809 | boot_cpu_physical_apicid = new_apicid; | |
103428e5 CG |
1810 | /* |
1811 | * yeah -- we lie about apic_version | |
1812 | * in case if apic was disabled via boot option | |
1813 | * but it's not a problem for SMP compiled kernel | |
1814 | * since smp_sanity_check is prepared for such a case | |
1815 | * and disable smp mode | |
1816 | */ | |
cff9ab2b | 1817 | boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); |
08306ce6 | 1818 | } |
1da177e4 LT |
1819 | } |
1820 | ||
c0104d38 YL |
1821 | void __init register_lapic_address(unsigned long address) |
1822 | { | |
1823 | mp_lapic_addr = address; | |
1824 | ||
0450193b YL |
1825 | if (!x2apic_mode) { |
1826 | set_fixmap_nocache(FIX_APIC_BASE, address); | |
1827 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
6de42119 | 1828 | APIC_BASE, address); |
0450193b | 1829 | } |
c0104d38 YL |
1830 | if (boot_cpu_physical_apicid == -1U) { |
1831 | boot_cpu_physical_apicid = read_apic_id(); | |
cff9ab2b | 1832 | boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); |
c0104d38 YL |
1833 | } |
1834 | } | |
1835 | ||
1da177e4 | 1836 | /* |
0e078e2f | 1837 | * Local APIC interrupts |
1da177e4 LT |
1838 | */ |
1839 | ||
0e078e2f TG |
1840 | /* |
1841 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1842 | */ | |
d786ad32 | 1843 | static void __smp_spurious_interrupt(u8 vector) |
1da177e4 | 1844 | { |
dc1528dd YL |
1845 | u32 v; |
1846 | ||
1da177e4 | 1847 | /* |
0e078e2f TG |
1848 | * Check if this really is a spurious interrupt and ACK it |
1849 | * if it is a vectored one. Just in case... | |
1850 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1851 | */ |
2414e021 JB |
1852 | v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); |
1853 | if (v & (1 << (vector & 0x1f))) | |
0e078e2f | 1854 | ack_APIC_irq(); |
c4d58cbd | 1855 | |
915b0d01 HS |
1856 | inc_irq_stat(irq_spurious_count); |
1857 | ||
dc1528dd | 1858 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
2414e021 JB |
1859 | pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " |
1860 | "should never happen.\n", vector, smp_processor_id()); | |
eddc0e92 SA |
1861 | } |
1862 | ||
1d9090e2 | 1863 | __visible void smp_spurious_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
1864 | { |
1865 | entering_irq(); | |
2414e021 | 1866 | __smp_spurious_interrupt(~regs->orig_ax); |
eddc0e92 | 1867 | exiting_irq(); |
0e078e2f | 1868 | } |
1da177e4 | 1869 | |
1d9090e2 | 1870 | __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) |
cf910e83 | 1871 | { |
2414e021 JB |
1872 | u8 vector = ~regs->orig_ax; |
1873 | ||
cf910e83 | 1874 | entering_irq(); |
2414e021 JB |
1875 | trace_spurious_apic_entry(vector); |
1876 | __smp_spurious_interrupt(vector); | |
1877 | trace_spurious_apic_exit(vector); | |
cf910e83 | 1878 | exiting_irq(); |
0e078e2f | 1879 | } |
1da177e4 | 1880 | |
0e078e2f TG |
1881 | /* |
1882 | * This interrupt should never happen with our APIC/SMP architecture | |
1883 | */ | |
d786ad32 | 1884 | static void __smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1885 | { |
60283df7 | 1886 | u32 v; |
2b398bd9 YS |
1887 | u32 i = 0; |
1888 | static const char * const error_interrupt_reason[] = { | |
1889 | "Send CS error", /* APIC Error Bit 0 */ | |
1890 | "Receive CS error", /* APIC Error Bit 1 */ | |
1891 | "Send accept error", /* APIC Error Bit 2 */ | |
1892 | "Receive accept error", /* APIC Error Bit 3 */ | |
1893 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
1894 | "Send illegal vector", /* APIC Error Bit 5 */ | |
1895 | "Received illegal vector", /* APIC Error Bit 6 */ | |
1896 | "Illegal register address", /* APIC Error Bit 7 */ | |
1897 | }; | |
1da177e4 | 1898 | |
0e078e2f | 1899 | /* First tickle the hardware, only then report what went on. -- REW */ |
023de4a0 MR |
1900 | if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ |
1901 | apic_write(APIC_ESR, 0); | |
60283df7 | 1902 | v = apic_read(APIC_ESR); |
0e078e2f TG |
1903 | ack_APIC_irq(); |
1904 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1905 | |
60283df7 RW |
1906 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", |
1907 | smp_processor_id(), v); | |
2b398bd9 | 1908 | |
60283df7 RW |
1909 | v &= 0xff; |
1910 | while (v) { | |
1911 | if (v & 0x1) | |
2b398bd9 YS |
1912 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); |
1913 | i++; | |
60283df7 | 1914 | v >>= 1; |
4b8073e4 | 1915 | } |
2b398bd9 YS |
1916 | |
1917 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); | |
1918 | ||
eddc0e92 SA |
1919 | } |
1920 | ||
1d9090e2 | 1921 | __visible void smp_error_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
1922 | { |
1923 | entering_irq(); | |
1924 | __smp_error_interrupt(regs); | |
1925 | exiting_irq(); | |
1da177e4 LT |
1926 | } |
1927 | ||
1d9090e2 | 1928 | __visible void smp_trace_error_interrupt(struct pt_regs *regs) |
cf910e83 SA |
1929 | { |
1930 | entering_irq(); | |
1931 | trace_error_apic_entry(ERROR_APIC_VECTOR); | |
1932 | __smp_error_interrupt(regs); | |
1933 | trace_error_apic_exit(ERROR_APIC_VECTOR); | |
1934 | exiting_irq(); | |
1da177e4 LT |
1935 | } |
1936 | ||
b5841765 | 1937 | /** |
36c9d674 CG |
1938 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1939 | */ | |
05f7e46d | 1940 | static void __init connect_bsp_APIC(void) |
b5841765 | 1941 | { |
36c9d674 CG |
1942 | #ifdef CONFIG_X86_32 |
1943 | if (pic_mode) { | |
1944 | /* | |
1945 | * Do not trust the local APIC being empty at bootup. | |
1946 | */ | |
1947 | clear_local_APIC(); | |
1948 | /* | |
1949 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1950 | * local APIC to INT and NMI lines. | |
1951 | */ | |
1952 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1953 | "enabling APIC mode.\n"); | |
c0eaa453 | 1954 | imcr_pic_to_apic(); |
36c9d674 CG |
1955 | } |
1956 | #endif | |
b5841765 GC |
1957 | } |
1958 | ||
274cfe59 CG |
1959 | /** |
1960 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1961 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1962 | * | |
1963 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1964 | * APIC is disabled. | |
1965 | */ | |
0e078e2f | 1966 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1967 | { |
1b4ee4e4 CG |
1968 | unsigned int value; |
1969 | ||
c177b0bc CG |
1970 | #ifdef CONFIG_X86_32 |
1971 | if (pic_mode) { | |
1972 | /* | |
1973 | * Put the board back into PIC mode (has an effect only on | |
1974 | * certain older boards). Note that APIC interrupts, including | |
1975 | * IPIs, won't work beyond this point! The only exception are | |
1976 | * INIT IPIs. | |
1977 | */ | |
1978 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1979 | "entering PIC mode.\n"); | |
c0eaa453 | 1980 | imcr_apic_to_pic(); |
c177b0bc CG |
1981 | return; |
1982 | } | |
1983 | #endif | |
1984 | ||
0e078e2f | 1985 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1986 | |
0e078e2f TG |
1987 | /* For the spurious interrupt use vector F, and enable it */ |
1988 | value = apic_read(APIC_SPIV); | |
1989 | value &= ~APIC_VECTOR_MASK; | |
1990 | value |= APIC_SPIV_APIC_ENABLED; | |
1991 | value |= 0xf; | |
1992 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1993 | |
0e078e2f TG |
1994 | if (!virt_wire_setup) { |
1995 | /* | |
1996 | * For LVT0 make it edge triggered, active high, | |
1997 | * external and enabled | |
1998 | */ | |
1999 | value = apic_read(APIC_LVT0); | |
2000 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2001 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2002 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2003 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2004 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
2005 | apic_write(APIC_LVT0, value); | |
2006 | } else { | |
2007 | /* Disable LVT0 */ | |
2008 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
2009 | } | |
b8ce3359 | 2010 | |
c177b0bc CG |
2011 | /* |
2012 | * For LVT1 make it edge triggered, active high, | |
2013 | * nmi and enabled | |
2014 | */ | |
0e078e2f TG |
2015 | value = apic_read(APIC_LVT1); |
2016 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2017 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2018 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2019 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2020 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
2021 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
2022 | } |
2023 | ||
f7c28833 | 2024 | static int __generic_processor_info(int apicid, int version, bool enabled) |
be8a5685 | 2025 | { |
14cb6dcf VG |
2026 | int cpu, max = nr_cpu_ids; |
2027 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, | |
2028 | phys_cpu_present_map); | |
2029 | ||
151e0c7d HD |
2030 | /* |
2031 | * boot_cpu_physical_apicid is designed to have the apicid | |
2032 | * returned by read_apic_id(), i.e, the apicid of the | |
2033 | * currently booting-up processor. However, on some platforms, | |
5b4d1dbc | 2034 | * it is temporarily modified by the apicid reported as BSP |
151e0c7d HD |
2035 | * through MP table. Concretely: |
2036 | * | |
2037 | * - arch/x86/kernel/mpparse.c: MP_processor_info() | |
2038 | * - arch/x86/mm/amdtopology.c: amd_numa_init() | |
151e0c7d HD |
2039 | * |
2040 | * This function is executed with the modified | |
2041 | * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel | |
2042 | * parameter doesn't work to disable APs on kdump 2nd kernel. | |
2043 | * | |
2044 | * Since fixing handling of boot_cpu_physical_apicid requires | |
2045 | * another discussion and tests on each platform, we leave it | |
2046 | * for now and here we use read_apic_id() directly in this | |
2047 | * function, generic_processor_info(). | |
2048 | */ | |
2049 | if (disabled_cpu_apicid != BAD_APICID && | |
2050 | disabled_cpu_apicid != read_apic_id() && | |
2051 | disabled_cpu_apicid == apicid) { | |
2052 | int thiscpu = num_processors + disabled_cpus; | |
2053 | ||
5b4d1dbc | 2054 | pr_warning("APIC: Disabling requested cpu." |
151e0c7d HD |
2055 | " Processor %d/0x%x ignored.\n", |
2056 | thiscpu, apicid); | |
2057 | ||
2058 | disabled_cpus++; | |
2059 | return -ENODEV; | |
2060 | } | |
2061 | ||
14cb6dcf VG |
2062 | /* |
2063 | * If boot cpu has not been detected yet, then only allow upto | |
2064 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu | |
2065 | */ | |
2066 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && | |
2067 | apicid != boot_cpu_physical_apicid) { | |
2068 | int thiscpu = max + disabled_cpus - 1; | |
2069 | ||
2070 | pr_warning( | |
3c8fad91 | 2071 | "APIC: NR_CPUS/possible_cpus limit of %i almost" |
14cb6dcf VG |
2072 | " reached. Keeping one slot for boot cpu." |
2073 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2074 | ||
2075 | disabled_cpus++; | |
7e1f85f9 | 2076 | return -ENODEV; |
14cb6dcf | 2077 | } |
be8a5685 | 2078 | |
3b11ce7f | 2079 | if (num_processors >= nr_cpu_ids) { |
3b11ce7f MT |
2080 | int thiscpu = max + disabled_cpus; |
2081 | ||
2082 | pr_warning( | |
3c8fad91 | 2083 | "APIC: NR_CPUS/possible_cpus limit of %i reached." |
3b11ce7f MT |
2084 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); |
2085 | ||
2086 | disabled_cpus++; | |
7e1f85f9 | 2087 | return -EINVAL; |
be8a5685 AS |
2088 | } |
2089 | ||
be8a5685 AS |
2090 | if (apicid == boot_cpu_physical_apicid) { |
2091 | /* | |
2092 | * x86_bios_cpu_apicid is required to have processors listed | |
2093 | * in same order as logical cpu numbers. Hence the first | |
2094 | * entry is BSP, and so on. | |
e5fea868 YL |
2095 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
2096 | * for BSP. | |
be8a5685 AS |
2097 | */ |
2098 | cpu = 0; | |
e5fea868 YL |
2099 | } else |
2100 | cpu = cpumask_next_zero(-1, cpu_present_mask); | |
2101 | ||
1f12e32f TG |
2102 | /* |
2103 | * This can happen on physical hotplug. The sanity check at boot time | |
2104 | * is done from native_smp_prepare_cpus() after num_possible_cpus() is | |
2105 | * established. | |
2106 | */ | |
2107 | if (topology_update_package_map(apicid, cpu) < 0) { | |
2108 | int thiscpu = max + disabled_cpus; | |
2109 | ||
3c8fad91 | 2110 | pr_warning("APIC: Package limit reached. Processor %d/0x%x ignored.\n", |
1f12e32f | 2111 | thiscpu, apicid); |
f7c28833 | 2112 | |
1f12e32f TG |
2113 | disabled_cpus++; |
2114 | return -ENOSPC; | |
2115 | } | |
2116 | ||
e5fea868 YL |
2117 | /* |
2118 | * Validate version | |
2119 | */ | |
2120 | if (version == 0x0) { | |
2121 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", | |
2122 | cpu, apicid); | |
2123 | version = 0x10; | |
be8a5685 | 2124 | } |
e5fea868 | 2125 | |
cff9ab2b | 2126 | if (version != boot_cpu_apic_version) { |
e5fea868 | 2127 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", |
cff9ab2b | 2128 | boot_cpu_apic_version, cpu, version); |
e5fea868 YL |
2129 | } |
2130 | ||
e0da3364 YL |
2131 | if (apicid > max_physical_apicid) |
2132 | max_physical_apicid = apicid; | |
2133 | ||
3e5095d1 | 2134 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
2135 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
2136 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 2137 | #endif |
acb8bc09 TH |
2138 | #ifdef CONFIG_X86_32 |
2139 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = | |
2140 | apic->x86_32_early_logical_apicid(cpu); | |
2141 | #endif | |
1de88cd4 | 2142 | set_cpu_possible(cpu, true); |
f7c28833 GZ |
2143 | |
2144 | if (enabled) { | |
2145 | num_processors++; | |
2146 | physid_set(apicid, phys_cpu_present_map); | |
2147 | set_cpu_present(cpu, true); | |
2148 | } else { | |
2149 | disabled_cpus++; | |
2150 | } | |
7e1f85f9 JL |
2151 | |
2152 | return cpu; | |
be8a5685 AS |
2153 | } |
2154 | ||
f7c28833 GZ |
2155 | int generic_processor_info(int apicid, int version) |
2156 | { | |
2157 | return __generic_processor_info(apicid, version, true); | |
2158 | } | |
2159 | ||
0c81c746 SS |
2160 | int hard_smp_processor_id(void) |
2161 | { | |
2162 | return read_apic_id(); | |
2163 | } | |
1dcdd3d1 IM |
2164 | |
2165 | void default_init_apic_ldr(void) | |
2166 | { | |
2167 | unsigned long val; | |
2168 | ||
2169 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
2170 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
2171 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
2172 | apic_write(APIC_LDR, val); | |
2173 | } | |
2174 | ||
ff164324 AG |
2175 | int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
2176 | const struct cpumask *andmask, | |
2177 | unsigned int *apicid) | |
6398268d | 2178 | { |
ea3807ea | 2179 | unsigned int cpu; |
6398268d AG |
2180 | |
2181 | for_each_cpu_and(cpu, cpumask, andmask) { | |
2182 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | |
2183 | break; | |
2184 | } | |
ff164324 | 2185 | |
ea3807ea | 2186 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
2187 | *apicid = per_cpu(x86_cpu_to_apicid, cpu); |
2188 | return 0; | |
a5a39156 | 2189 | } |
ea3807ea AG |
2190 | |
2191 | return -EINVAL; | |
6398268d AG |
2192 | } |
2193 | ||
1551df64 MT |
2194 | /* |
2195 | * Override the generic EOI implementation with an optimized version. | |
2196 | * Only called during early boot when only one CPU is active and with | |
2197 | * interrupts disabled, so we know this does not race with actual APIC driver | |
2198 | * use. | |
2199 | */ | |
2200 | void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) | |
2201 | { | |
2202 | struct apic **drv; | |
2203 | ||
2204 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { | |
2205 | /* Should happen once for each apic */ | |
2206 | WARN_ON((*drv)->eoi_write == eoi_write); | |
2207 | (*drv)->eoi_write = eoi_write; | |
2208 | } | |
2209 | } | |
2210 | ||
374aab33 | 2211 | static void __init apic_bsp_up_setup(void) |
05f7e46d | 2212 | { |
374aab33 TG |
2213 | #ifdef CONFIG_X86_64 |
2214 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); | |
2215 | #else | |
05f7e46d | 2216 | /* |
374aab33 TG |
2217 | * Hack: In case of kdump, after a crash, kernel might be booting |
2218 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
2219 | * might be zero if read from MP tables. Get it from LAPIC. | |
05f7e46d | 2220 | */ |
374aab33 TG |
2221 | # ifdef CONFIG_CRASH_DUMP |
2222 | boot_cpu_physical_apicid = read_apic_id(); | |
2223 | # endif | |
2224 | #endif | |
2225 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
05f7e46d TG |
2226 | } |
2227 | ||
2228 | /** | |
2229 | * apic_bsp_setup - Setup function for local apic and io-apic | |
374aab33 | 2230 | * @upmode: Force UP mode (for APIC_init_uniprocessor) |
05f7e46d TG |
2231 | * |
2232 | * Returns: | |
2233 | * apic_id of BSP APIC | |
2234 | */ | |
374aab33 | 2235 | int __init apic_bsp_setup(bool upmode) |
05f7e46d TG |
2236 | { |
2237 | int id; | |
2238 | ||
2239 | connect_bsp_APIC(); | |
374aab33 TG |
2240 | if (upmode) |
2241 | apic_bsp_up_setup(); | |
05f7e46d TG |
2242 | setup_local_APIC(); |
2243 | ||
2244 | if (x2apic_mode) | |
2245 | id = apic_read(APIC_LDR); | |
2246 | else | |
2247 | id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
2248 | ||
2249 | enable_IO_APIC(); | |
374aab33 TG |
2250 | end_local_APIC_setup(); |
2251 | irq_remap_enable_fault_handling(); | |
05f7e46d | 2252 | setup_IO_APIC(); |
9c4d9c73 TG |
2253 | /* Setup local timer */ |
2254 | x86_init.timers.setup_percpu_clockev(); | |
05f7e46d TG |
2255 | return id; |
2256 | } | |
2257 | ||
e714a91f TG |
2258 | /* |
2259 | * This initializes the IO-APIC and APIC hardware if this is | |
2260 | * a UP kernel. | |
2261 | */ | |
2262 | int __init APIC_init_uniprocessor(void) | |
2263 | { | |
2264 | if (disable_apic) { | |
2265 | pr_info("Apic disabled\n"); | |
2266 | return -1; | |
2267 | } | |
2268 | #ifdef CONFIG_X86_64 | |
93984fbd | 2269 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
e714a91f TG |
2270 | disable_apic = 1; |
2271 | pr_info("Apic disabled by BIOS\n"); | |
2272 | return -1; | |
2273 | } | |
2274 | #else | |
93984fbd | 2275 | if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC)) |
e714a91f TG |
2276 | return -1; |
2277 | ||
2278 | /* | |
2279 | * Complain if the BIOS pretends there is one. | |
2280 | */ | |
93984fbd | 2281 | if (!boot_cpu_has(X86_FEATURE_APIC) && |
cff9ab2b | 2282 | APIC_INTEGRATED(boot_cpu_apic_version)) { |
e714a91f TG |
2283 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
2284 | boot_cpu_physical_apicid); | |
2285 | return -1; | |
2286 | } | |
2287 | #endif | |
2288 | ||
374aab33 TG |
2289 | if (!smp_found_config) |
2290 | disable_ioapic_support(); | |
e714a91f | 2291 | |
374aab33 | 2292 | default_setup_apic_routing(); |
374aab33 | 2293 | apic_bsp_setup(true); |
e714a91f TG |
2294 | return 0; |
2295 | } | |
2296 | ||
30b8b006 TG |
2297 | #ifdef CONFIG_UP_LATE_INIT |
2298 | void __init up_late_init(void) | |
2299 | { | |
2300 | APIC_init_uniprocessor(); | |
2301 | } | |
2302 | #endif | |
2303 | ||
89039b37 | 2304 | /* |
0e078e2f | 2305 | * Power management |
89039b37 | 2306 | */ |
0e078e2f TG |
2307 | #ifdef CONFIG_PM |
2308 | ||
2309 | static struct { | |
274cfe59 CG |
2310 | /* |
2311 | * 'active' is true if the local APIC was enabled by us and | |
2312 | * not the BIOS; this signifies that we are also responsible | |
2313 | * for disabling it before entering apm/acpi suspend | |
2314 | */ | |
0e078e2f TG |
2315 | int active; |
2316 | /* r/w apic fields */ | |
2317 | unsigned int apic_id; | |
2318 | unsigned int apic_taskpri; | |
2319 | unsigned int apic_ldr; | |
2320 | unsigned int apic_dfr; | |
2321 | unsigned int apic_spiv; | |
2322 | unsigned int apic_lvtt; | |
2323 | unsigned int apic_lvtpc; | |
2324 | unsigned int apic_lvt0; | |
2325 | unsigned int apic_lvt1; | |
2326 | unsigned int apic_lvterr; | |
2327 | unsigned int apic_tmict; | |
2328 | unsigned int apic_tdcr; | |
2329 | unsigned int apic_thmr; | |
42baa258 | 2330 | unsigned int apic_cmci; |
0e078e2f TG |
2331 | } apic_pm_state; |
2332 | ||
f3c6ea1b | 2333 | static int lapic_suspend(void) |
0e078e2f TG |
2334 | { |
2335 | unsigned long flags; | |
2336 | int maxlvt; | |
89039b37 | 2337 | |
0e078e2f TG |
2338 | if (!apic_pm_state.active) |
2339 | return 0; | |
89039b37 | 2340 | |
0e078e2f | 2341 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2342 | |
2d7a66d0 | 2343 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2344 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2345 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2346 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2347 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2348 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2349 | if (maxlvt >= 4) | |
2350 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2351 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2352 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2353 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2354 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2355 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2356 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2357 | if (maxlvt >= 5) |
2358 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2359 | #endif | |
42baa258 JG |
2360 | #ifdef CONFIG_X86_MCE_INTEL |
2361 | if (maxlvt >= 6) | |
2362 | apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); | |
2363 | #endif | |
24968cfd | 2364 | |
0e078e2f TG |
2365 | local_irq_save(flags); |
2366 | disable_local_APIC(); | |
fc1edaf9 | 2367 | |
70733e0c | 2368 | irq_remapping_disable(); |
fc1edaf9 | 2369 | |
0e078e2f TG |
2370 | local_irq_restore(flags); |
2371 | return 0; | |
1da177e4 LT |
2372 | } |
2373 | ||
f3c6ea1b | 2374 | static void lapic_resume(void) |
1da177e4 | 2375 | { |
0e078e2f TG |
2376 | unsigned int l, h; |
2377 | unsigned long flags; | |
31dce14a | 2378 | int maxlvt; |
b24696bc | 2379 | |
0e078e2f | 2380 | if (!apic_pm_state.active) |
f3c6ea1b | 2381 | return; |
89b831ef | 2382 | |
0e078e2f | 2383 | local_irq_save(flags); |
336224ba JR |
2384 | |
2385 | /* | |
2386 | * IO-APIC and PIC have their own resume routines. | |
2387 | * We just mask them here to make sure the interrupt | |
2388 | * subsystem is completely quiet while we enable x2apic | |
2389 | * and interrupt-remapping. | |
2390 | */ | |
2391 | mask_ioapic_entries(); | |
2392 | legacy_pic->mask_all(); | |
92206c90 | 2393 | |
659006bf TG |
2394 | if (x2apic_mode) { |
2395 | __x2apic_enable(); | |
2396 | } else { | |
92206c90 CG |
2397 | /* |
2398 | * Make sure the APICBASE points to the right address | |
2399 | * | |
2400 | * FIXME! This will be wrong if we ever support suspend on | |
2401 | * SMP! We'll need to do this as part of the CPU restore! | |
2402 | */ | |
cbf2829b BD |
2403 | if (boot_cpu_data.x86 >= 6) { |
2404 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2405 | l &= ~MSR_IA32_APICBASE_BASE; | |
2406 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2407 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2408 | } | |
d5e629a6 | 2409 | } |
6e1cb38a | 2410 | |
b24696bc | 2411 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2412 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2413 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2414 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2415 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2416 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2417 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2418 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2419 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
42baa258 | 2420 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2421 | if (maxlvt >= 5) |
2422 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
42baa258 JG |
2423 | #endif |
2424 | #ifdef CONFIG_X86_MCE_INTEL | |
2425 | if (maxlvt >= 6) | |
2426 | apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); | |
0e078e2f TG |
2427 | #endif |
2428 | if (maxlvt >= 4) | |
2429 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2430 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2431 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2432 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2433 | apic_write(APIC_ESR, 0); | |
2434 | apic_read(APIC_ESR); | |
2435 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2436 | apic_write(APIC_ESR, 0); | |
2437 | apic_read(APIC_ESR); | |
92206c90 | 2438 | |
70733e0c | 2439 | irq_remapping_reenable(x2apic_mode); |
31dce14a | 2440 | |
0e078e2f | 2441 | local_irq_restore(flags); |
0e078e2f | 2442 | } |
b8ce3359 | 2443 | |
274cfe59 CG |
2444 | /* |
2445 | * This device has no shutdown method - fully functioning local APICs | |
2446 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2447 | */ | |
2448 | ||
f3c6ea1b | 2449 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2450 | .resume = lapic_resume, |
2451 | .suspend = lapic_suspend, | |
2452 | }; | |
b8ce3359 | 2453 | |
148f9bb8 | 2454 | static void apic_pm_activate(void) |
0e078e2f TG |
2455 | { |
2456 | apic_pm_state.active = 1; | |
1da177e4 LT |
2457 | } |
2458 | ||
0e078e2f | 2459 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2460 | { |
0e078e2f | 2461 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
93984fbd | 2462 | if (boot_cpu_has(X86_FEATURE_APIC)) |
f3c6ea1b | 2463 | register_syscore_ops(&lapic_syscore_ops); |
e83a5fdc | 2464 | |
f3c6ea1b | 2465 | return 0; |
1da177e4 | 2466 | } |
b24696bc FY |
2467 | |
2468 | /* local apic needs to resume before other devices access its registers. */ | |
2469 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2470 | |
2471 | #else /* CONFIG_PM */ | |
2472 | ||
2473 | static void apic_pm_activate(void) { } | |
2474 | ||
2475 | #endif /* CONFIG_PM */ | |
1da177e4 | 2476 | |
f28c0ae2 | 2477 | #ifdef CONFIG_X86_64 |
e0e42142 | 2478 | |
148f9bb8 PG |
2479 | static int multi_checked; |
2480 | static int multi; | |
e0e42142 | 2481 | |
148f9bb8 | 2482 | static int set_multi(const struct dmi_system_id *d) |
e0e42142 YL |
2483 | { |
2484 | if (multi) | |
2485 | return 0; | |
6f0aced6 | 2486 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2487 | multi = 1; |
2488 | return 0; | |
2489 | } | |
2490 | ||
148f9bb8 | 2491 | static const struct dmi_system_id multi_dmi_table[] = { |
e0e42142 YL |
2492 | { |
2493 | .callback = set_multi, | |
2494 | .ident = "IBM System Summit2", | |
2495 | .matches = { | |
2496 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2497 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2498 | }, | |
2499 | }, | |
2500 | {} | |
2501 | }; | |
2502 | ||
148f9bb8 | 2503 | static void dmi_check_multi(void) |
e0e42142 YL |
2504 | { |
2505 | if (multi_checked) | |
2506 | return; | |
2507 | ||
2508 | dmi_check_system(multi_dmi_table); | |
2509 | multi_checked = 1; | |
2510 | } | |
2511 | ||
2512 | /* | |
2513 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2514 | * | |
2515 | * Thus far, the major user of this is IBM's Summit2 series: | |
2516 | * Clustered boxes may have unsynced TSC problems if they are | |
2517 | * multi-chassis. | |
2518 | * Use DMI to check them | |
2519 | */ | |
148f9bb8 | 2520 | int apic_is_clustered_box(void) |
e0e42142 YL |
2521 | { |
2522 | dmi_check_multi(); | |
411cf9ee | 2523 | return multi; |
1da177e4 | 2524 | } |
f28c0ae2 | 2525 | #endif |
1da177e4 LT |
2526 | |
2527 | /* | |
0e078e2f | 2528 | * APIC command line parameters |
1da177e4 | 2529 | */ |
789fa735 | 2530 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2531 | { |
1da177e4 | 2532 | disable_apic = 1; |
9175fc06 | 2533 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2534 | return 0; |
2535 | } | |
2536 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2537 | |
2c8c0e6b | 2538 | /* same as disableapic, for compatibility */ |
789fa735 | 2539 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2540 | { |
789fa735 | 2541 | return setup_disableapic(arg); |
6935d1f9 | 2542 | } |
2c8c0e6b | 2543 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2544 | |
2e7c2838 LT |
2545 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2546 | { | |
2547 | local_apic_timer_c2_ok = 1; | |
2548 | return 0; | |
2549 | } | |
2550 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2551 | ||
36fef094 | 2552 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2553 | { |
1da177e4 | 2554 | disable_apic_timer = 1; |
36fef094 | 2555 | return 0; |
6935d1f9 | 2556 | } |
36fef094 CG |
2557 | early_param("noapictimer", parse_disable_apic_timer); |
2558 | ||
2559 | static int __init parse_nolapic_timer(char *arg) | |
2560 | { | |
2561 | disable_apic_timer = 1; | |
2562 | return 0; | |
6935d1f9 | 2563 | } |
36fef094 | 2564 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2565 | |
79af9bec CG |
2566 | static int __init apic_set_verbosity(char *arg) |
2567 | { | |
2568 | if (!arg) { | |
2569 | #ifdef CONFIG_X86_64 | |
2570 | skip_ioapic_setup = 0; | |
79af9bec CG |
2571 | return 0; |
2572 | #endif | |
2573 | return -EINVAL; | |
2574 | } | |
2575 | ||
2576 | if (strcmp("debug", arg) == 0) | |
2577 | apic_verbosity = APIC_DEBUG; | |
2578 | else if (strcmp("verbose", arg) == 0) | |
2579 | apic_verbosity = APIC_VERBOSE; | |
2580 | else { | |
ba21ebb6 | 2581 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2582 | " use apic=verbose or apic=debug\n", arg); |
2583 | return -EINVAL; | |
2584 | } | |
2585 | ||
2586 | return 0; | |
2587 | } | |
2588 | early_param("apic", apic_set_verbosity); | |
2589 | ||
1e934dda YL |
2590 | static int __init lapic_insert_resource(void) |
2591 | { | |
2592 | if (!apic_phys) | |
2593 | return -1; | |
2594 | ||
2595 | /* Put local APIC into the resource map. */ | |
2596 | lapic_resource.start = apic_phys; | |
2597 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2598 | insert_resource(&iomem_resource, &lapic_resource); | |
2599 | ||
2600 | return 0; | |
2601 | } | |
2602 | ||
2603 | /* | |
2604 | * need call insert after e820_reserve_resources() | |
2605 | * that is using request_resource | |
2606 | */ | |
2607 | late_initcall(lapic_insert_resource); | |
151e0c7d HD |
2608 | |
2609 | static int __init apic_set_disabled_cpu_apicid(char *arg) | |
2610 | { | |
2611 | if (!arg || !get_option(&arg, &disabled_cpu_apicid)) | |
2612 | return -EINVAL; | |
2613 | ||
2614 | return 0; | |
2615 | } | |
2616 | early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); | |
b7c4948e HK |
2617 | |
2618 | static int __init apic_set_extnmi(char *arg) | |
2619 | { | |
2620 | if (!arg) | |
2621 | return -EINVAL; | |
2622 | ||
2623 | if (!strncmp("all", arg, 3)) | |
2624 | apic_extnmi = APIC_EXTNMI_ALL; | |
2625 | else if (!strncmp("none", arg, 4)) | |
2626 | apic_extnmi = APIC_EXTNMI_NONE; | |
2627 | else if (!strncmp("bsp", arg, 3)) | |
2628 | apic_extnmi = APIC_EXTNMI_BSP; | |
2629 | else { | |
2630 | pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); | |
2631 | return -EINVAL; | |
2632 | } | |
2633 | ||
2634 | return 0; | |
2635 | } | |
2636 | early_param("apic_extnmi", apic_set_extnmi); |