Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 | 17 | #include <linux/kernel_stat.h> |
d1de36f5 | 18 | #include <linux/mc146818rtc.h> |
70a20025 | 19 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
20 | #include <linux/clockchips.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/ftrace.h> | |
24 | #include <linux/ioport.h> | |
e83a5fdc | 25 | #include <linux/module.h> |
d1de36f5 IM |
26 | #include <linux/sysdev.h> |
27 | #include <linux/delay.h> | |
28 | #include <linux/timex.h> | |
6e1cb38a | 29 | #include <linux/dmar.h> |
d1de36f5 IM |
30 | #include <linux/init.h> |
31 | #include <linux/cpu.h> | |
32 | #include <linux/dmi.h> | |
e423e33e | 33 | #include <linux/nmi.h> |
d1de36f5 IM |
34 | #include <linux/smp.h> |
35 | #include <linux/mm.h> | |
1da177e4 | 36 | |
1da177e4 | 37 | #include <asm/pgalloc.h> |
1da177e4 | 38 | #include <asm/atomic.h> |
1da177e4 | 39 | #include <asm/mpspec.h> |
773763df | 40 | #include <asm/i8253.h> |
d1de36f5 | 41 | #include <asm/i8259.h> |
73dea47f | 42 | #include <asm/proto.h> |
2c8c0e6b | 43 | #include <asm/apic.h> |
d1de36f5 IM |
44 | #include <asm/desc.h> |
45 | #include <asm/hpet.h> | |
46 | #include <asm/idle.h> | |
47 | #include <asm/mtrr.h> | |
2bc13797 | 48 | #include <asm/smp.h> |
be71b855 | 49 | #include <asm/mce.h> |
1da177e4 | 50 | |
ec70de8b | 51 | unsigned int num_processors; |
fdbecd9f | 52 | |
ec70de8b | 53 | unsigned disabled_cpus __cpuinitdata; |
fdbecd9f | 54 | |
ec70de8b BG |
55 | /* Processor that is doing the boot up */ |
56 | unsigned int boot_cpu_physical_apicid = -1U; | |
5af5573e | 57 | |
80e5609c | 58 | /* |
fdbecd9f IM |
59 | * The highest APIC ID seen during enumeration. |
60 | * | |
61 | * This determines the messaging protocol we can use: if all APIC IDs | |
62 | * are in the 0 ... 7 range, then we can use logical addressing which | |
63 | * has some performance advantages (better broadcasting). | |
64 | * | |
65 | * If there's an APIC ID above 8, we use physical addressing. | |
80e5609c | 66 | */ |
ec70de8b | 67 | unsigned int max_physical_apicid; |
5af5573e | 68 | |
80e5609c | 69 | /* |
fdbecd9f | 70 | * Bitmask of physically existing CPUs: |
80e5609c | 71 | */ |
ec70de8b BG |
72 | physid_mask_t phys_cpu_present_map; |
73 | ||
74 | /* | |
75 | * Map cpu index to physical APIC ID | |
76 | */ | |
77 | DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); | |
78 | DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); | |
79 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
80 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
80e5609c | 81 | |
b3c51170 YL |
82 | #ifdef CONFIG_X86_32 |
83 | /* | |
84 | * Knob to control our willingness to enable the local APIC. | |
85 | * | |
86 | * +1=force-enable | |
87 | */ | |
88 | static int force_enable_local_apic; | |
89 | /* | |
90 | * APIC command line parameters | |
91 | */ | |
92 | static int __init parse_lapic(char *arg) | |
93 | { | |
94 | force_enable_local_apic = 1; | |
95 | return 0; | |
96 | } | |
97 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
98 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
99 | static int enabled_via_apicbase; | |
100 | ||
b3c51170 YL |
101 | #endif |
102 | ||
103 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 104 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
105 | static __init int setup_apicpmtimer(char *s) |
106 | { | |
107 | apic_calibrate_pmtmr = 1; | |
108 | notsc_setup(NULL); | |
109 | return 0; | |
110 | } | |
111 | __setup("apicpmtimer", setup_apicpmtimer); | |
112 | #endif | |
113 | ||
06cd9a7d | 114 | #ifdef CONFIG_X86_X2APIC |
89027d35 | 115 | int x2apic; |
6e1cb38a | 116 | /* x2apic enabled before OS handover */ |
b6b301aa JS |
117 | static int x2apic_preenabled; |
118 | static int disable_x2apic; | |
49899eac YL |
119 | static __init int setup_nox2apic(char *str) |
120 | { | |
121 | disable_x2apic = 1; | |
122 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
123 | return 0; | |
124 | } | |
125 | early_param("nox2apic", setup_nox2apic); | |
126 | #endif | |
1da177e4 | 127 | |
b3c51170 YL |
128 | unsigned long mp_lapic_addr; |
129 | int disable_apic; | |
130 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
131 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 132 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
133 | int local_apic_timer_c2_ok; |
134 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
135 | ||
efa2559f YL |
136 | int first_system_vector = 0xfe; |
137 | ||
e83a5fdc HS |
138 | /* |
139 | * Debug level, exported for io_apic.c | |
140 | */ | |
baa13188 | 141 | unsigned int apic_verbosity; |
e83a5fdc | 142 | |
89c38c28 CG |
143 | int pic_mode; |
144 | ||
bab4b27c AS |
145 | /* Have we found an MP table */ |
146 | int smp_found_config; | |
147 | ||
39928722 AD |
148 | static struct resource lapic_resource = { |
149 | .name = "Local APIC", | |
150 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
151 | }; | |
152 | ||
d03030e9 TG |
153 | static unsigned int calibration_result; |
154 | ||
ba7eda4c TG |
155 | static int lapic_next_event(unsigned long delta, |
156 | struct clock_event_device *evt); | |
157 | static void lapic_timer_setup(enum clock_event_mode mode, | |
158 | struct clock_event_device *evt); | |
9628937d | 159 | static void lapic_timer_broadcast(const struct cpumask *mask); |
0e078e2f | 160 | static void apic_pm_activate(void); |
ba7eda4c | 161 | |
274cfe59 CG |
162 | /* |
163 | * The local apic timer can be used for any function which is CPU local. | |
164 | */ | |
ba7eda4c TG |
165 | static struct clock_event_device lapic_clockevent = { |
166 | .name = "lapic", | |
167 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
168 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
169 | .shift = 32, | |
170 | .set_mode = lapic_timer_setup, | |
171 | .set_next_event = lapic_next_event, | |
172 | .broadcast = lapic_timer_broadcast, | |
173 | .rating = 100, | |
174 | .irq = -1, | |
175 | }; | |
176 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
177 | ||
d3432896 AK |
178 | static unsigned long apic_phys; |
179 | ||
0e078e2f TG |
180 | /* |
181 | * Get the LAPIC version | |
182 | */ | |
183 | static inline int lapic_get_version(void) | |
ba7eda4c | 184 | { |
0e078e2f | 185 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
186 | } |
187 | ||
0e078e2f | 188 | /* |
9c803869 | 189 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
190 | */ |
191 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 192 | { |
9c803869 | 193 | #ifdef CONFIG_X86_64 |
0e078e2f | 194 | return 1; |
9c803869 CG |
195 | #else |
196 | return APIC_INTEGRATED(lapic_get_version()); | |
197 | #endif | |
ba7eda4c TG |
198 | } |
199 | ||
200 | /* | |
0e078e2f | 201 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 202 | */ |
0e078e2f | 203 | static int modern_apic(void) |
ba7eda4c | 204 | { |
0e078e2f TG |
205 | /* AMD systems use old APIC versions, so check the CPU */ |
206 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
207 | boot_cpu_data.x86 >= 0xf) | |
208 | return 1; | |
209 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
210 | } |
211 | ||
c1eeb2de | 212 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
213 | { |
214 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
215 | cpu_relax(); | |
216 | } | |
217 | ||
c1eeb2de | 218 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 219 | { |
3c6bb07a | 220 | u32 send_status; |
8339e9fb FLV |
221 | int timeout; |
222 | ||
223 | timeout = 0; | |
224 | do { | |
225 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
226 | if (!send_status) | |
227 | break; | |
228 | udelay(100); | |
229 | } while (timeout++ < 1000); | |
230 | ||
231 | return send_status; | |
232 | } | |
233 | ||
c1eeb2de | 234 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 235 | { |
ed4e5ec1 | 236 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
237 | apic_write(APIC_ICR, low); |
238 | } | |
239 | ||
c1eeb2de | 240 | u64 native_apic_icr_read(void) |
1b374e4d SS |
241 | { |
242 | u32 icr1, icr2; | |
243 | ||
244 | icr2 = apic_read(APIC_ICR2); | |
245 | icr1 = apic_read(APIC_ICR); | |
246 | ||
cf9768d7 | 247 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
248 | } |
249 | ||
0e078e2f TG |
250 | /** |
251 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
252 | */ | |
e9427101 | 253 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 254 | { |
11a8e778 | 255 | unsigned int v; |
6935d1f9 TG |
256 | |
257 | /* unmask and set to NMI */ | |
258 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
259 | |
260 | /* Level triggered for 82489DX (32bit mode) */ | |
261 | if (!lapic_is_integrated()) | |
262 | v |= APIC_LVT_LEVEL_TRIGGER; | |
263 | ||
11a8e778 | 264 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
265 | } |
266 | ||
7c37e48b CG |
267 | #ifdef CONFIG_X86_32 |
268 | /** | |
269 | * get_physical_broadcast - Get number of physical broadcast IDs | |
270 | */ | |
271 | int get_physical_broadcast(void) | |
272 | { | |
273 | return modern_apic() ? 0xff : 0xf; | |
274 | } | |
275 | #endif | |
276 | ||
0e078e2f TG |
277 | /** |
278 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
279 | */ | |
37e650c7 | 280 | int lapic_get_maxlvt(void) |
1da177e4 | 281 | { |
36a028de | 282 | unsigned int v; |
1da177e4 LT |
283 | |
284 | v = apic_read(APIC_LVR); | |
36a028de CG |
285 | /* |
286 | * - we always have APIC integrated on 64bit mode | |
287 | * - 82489DXs do not report # of LVT entries | |
288 | */ | |
289 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
290 | } |
291 | ||
274cfe59 CG |
292 | /* |
293 | * Local APIC timer | |
294 | */ | |
295 | ||
c40aaec6 | 296 | /* Clock divisor */ |
c40aaec6 | 297 | #define APIC_DIVISOR 16 |
f07f4f90 | 298 | |
0e078e2f TG |
299 | /* |
300 | * This function sets up the local APIC timer, with a timeout of | |
301 | * 'clocks' APIC bus clock. During calibration we actually call | |
302 | * this function twice on the boot CPU, once with a bogus timeout | |
303 | * value, second time for real. The other (noncalibrating) CPUs | |
304 | * call this function only once, with the real, calibrated value. | |
305 | * | |
306 | * We do reads before writes even if unnecessary, to get around the | |
307 | * P5 APIC double write bug. | |
308 | */ | |
0e078e2f | 309 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 310 | { |
0e078e2f | 311 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 312 | |
0e078e2f TG |
313 | lvtt_value = LOCAL_TIMER_VECTOR; |
314 | if (!oneshot) | |
315 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
316 | if (!lapic_is_integrated()) |
317 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
318 | ||
0e078e2f TG |
319 | if (!irqen) |
320 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 321 | |
0e078e2f | 322 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
323 | |
324 | /* | |
0e078e2f | 325 | * Divide PICLK by 16 |
1da177e4 | 326 | */ |
0e078e2f | 327 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
328 | apic_write(APIC_TDCR, |
329 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
330 | APIC_TDR_DIV_16); | |
0e078e2f TG |
331 | |
332 | if (!oneshot) | |
f07f4f90 | 333 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
334 | } |
335 | ||
0e078e2f | 336 | /* |
7b83dae7 RR |
337 | * Setup extended LVT, AMD specific (K8, family 10h) |
338 | * | |
339 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
340 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
341 | * |
342 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
343 | * enables the vector. See also the BKDGs. | |
0e078e2f | 344 | */ |
7b83dae7 RR |
345 | |
346 | #define APIC_EILVT_LVTOFF_MCE 0 | |
347 | #define APIC_EILVT_LVTOFF_IBS 1 | |
348 | ||
349 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 350 | { |
7b83dae7 | 351 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 352 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 353 | |
0e078e2f | 354 | apic_write(reg, v); |
1da177e4 LT |
355 | } |
356 | ||
7b83dae7 RR |
357 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
358 | { | |
359 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
360 | return APIC_EILVT_LVTOFF_MCE; | |
361 | } | |
362 | ||
363 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
364 | { | |
365 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
366 | return APIC_EILVT_LVTOFF_IBS; | |
367 | } | |
6aa360e6 | 368 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 369 | |
0e078e2f TG |
370 | /* |
371 | * Program the next event, relative to now | |
372 | */ | |
373 | static int lapic_next_event(unsigned long delta, | |
374 | struct clock_event_device *evt) | |
1da177e4 | 375 | { |
0e078e2f TG |
376 | apic_write(APIC_TMICT, delta); |
377 | return 0; | |
1da177e4 LT |
378 | } |
379 | ||
0e078e2f TG |
380 | /* |
381 | * Setup the lapic timer in periodic or oneshot mode | |
382 | */ | |
383 | static void lapic_timer_setup(enum clock_event_mode mode, | |
384 | struct clock_event_device *evt) | |
9b7711f0 HS |
385 | { |
386 | unsigned long flags; | |
0e078e2f | 387 | unsigned int v; |
9b7711f0 | 388 | |
0e078e2f TG |
389 | /* Lapic used as dummy for broadcast ? */ |
390 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
391 | return; |
392 | ||
393 | local_irq_save(flags); | |
394 | ||
0e078e2f TG |
395 | switch (mode) { |
396 | case CLOCK_EVT_MODE_PERIODIC: | |
397 | case CLOCK_EVT_MODE_ONESHOT: | |
398 | __setup_APIC_LVTT(calibration_result, | |
399 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
400 | break; | |
401 | case CLOCK_EVT_MODE_UNUSED: | |
402 | case CLOCK_EVT_MODE_SHUTDOWN: | |
403 | v = apic_read(APIC_LVTT); | |
404 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
405 | apic_write(APIC_LVTT, v); | |
a98f8fd2 | 406 | apic_write(APIC_TMICT, 0xffffffff); |
0e078e2f TG |
407 | break; |
408 | case CLOCK_EVT_MODE_RESUME: | |
409 | /* Nothing to do here */ | |
410 | break; | |
411 | } | |
9b7711f0 HS |
412 | |
413 | local_irq_restore(flags); | |
414 | } | |
415 | ||
1da177e4 | 416 | /* |
0e078e2f | 417 | * Local APIC timer broadcast function |
1da177e4 | 418 | */ |
9628937d | 419 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 420 | { |
0e078e2f | 421 | #ifdef CONFIG_SMP |
dac5f412 | 422 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
423 | #endif |
424 | } | |
1da177e4 | 425 | |
0e078e2f TG |
426 | /* |
427 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
428 | * of the boot CPU and register the clock event in the framework. | |
429 | */ | |
db4b5525 | 430 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
431 | { |
432 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 433 | |
0e078e2f | 434 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 435 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 436 | |
0e078e2f TG |
437 | clockevents_register_device(levt); |
438 | } | |
1da177e4 | 439 | |
2f04fa88 YL |
440 | /* |
441 | * In this functions we calibrate APIC bus clocks to the external timer. | |
442 | * | |
443 | * We want to do the calibration only once since we want to have local timer | |
444 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
445 | * frequency. | |
446 | * | |
447 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
448 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
449 | * readout is broken, so it never gets out of the wait loop again. This was | |
450 | * also reported by others. | |
451 | * | |
452 | * Monitoring the jiffies value is inaccurate and the clockevents | |
453 | * infrastructure allows us to do a simple substitution of the interrupt | |
454 | * handler. | |
455 | * | |
456 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
457 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
458 | * back to normal later in the boot process). | |
459 | */ | |
460 | ||
461 | #define LAPIC_CAL_LOOPS (HZ/10) | |
462 | ||
463 | static __initdata int lapic_cal_loops = -1; | |
464 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
465 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
466 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
467 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
468 | ||
469 | /* | |
470 | * Temporary interrupt handler. | |
471 | */ | |
472 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
473 | { | |
474 | unsigned long long tsc = 0; | |
475 | long tapic = apic_read(APIC_TMCCT); | |
476 | unsigned long pm = acpi_pm_read_early(); | |
477 | ||
478 | if (cpu_has_tsc) | |
479 | rdtscll(tsc); | |
480 | ||
481 | switch (lapic_cal_loops++) { | |
482 | case 0: | |
483 | lapic_cal_t1 = tapic; | |
484 | lapic_cal_tsc1 = tsc; | |
485 | lapic_cal_pm1 = pm; | |
486 | lapic_cal_j1 = jiffies; | |
487 | break; | |
488 | ||
489 | case LAPIC_CAL_LOOPS: | |
490 | lapic_cal_t2 = tapic; | |
491 | lapic_cal_tsc2 = tsc; | |
492 | if (pm < lapic_cal_pm1) | |
493 | pm += ACPI_PM_OVRRUN; | |
494 | lapic_cal_pm2 = pm; | |
495 | lapic_cal_j2 = jiffies; | |
496 | break; | |
497 | } | |
498 | } | |
499 | ||
754ef0cd YI |
500 | static int __init |
501 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
502 | { |
503 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
504 | const long pm_thresh = pm_100ms / 100; | |
505 | unsigned long mult; | |
506 | u64 res; | |
507 | ||
508 | #ifndef CONFIG_X86_PM_TIMER | |
509 | return -1; | |
510 | #endif | |
511 | ||
39ba5d43 | 512 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
513 | |
514 | /* Check, if the PM timer is available */ | |
515 | if (!deltapm) | |
516 | return -1; | |
517 | ||
518 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
519 | ||
520 | if (deltapm > (pm_100ms - pm_thresh) && | |
521 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 522 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
523 | return 0; |
524 | } | |
525 | ||
526 | res = (((u64)deltapm) * mult) >> 22; | |
527 | do_div(res, 1000000); | |
528 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 529 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
530 | |
531 | /* Correct the lapic counter value */ | |
532 | res = (((u64)(*delta)) * pm_100ms); | |
533 | do_div(res, deltapm); | |
534 | pr_info("APIC delta adjusted to PM-Timer: " | |
535 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
536 | *delta = (long)res; | |
537 | ||
538 | /* Correct the tsc counter value */ | |
539 | if (cpu_has_tsc) { | |
540 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 541 | do_div(res, deltapm); |
754ef0cd YI |
542 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
543 | "PM-Timer: %lu (%ld) \n", | |
544 | (unsigned long)res, *deltatsc); | |
545 | *deltatsc = (long)res; | |
b189892d CG |
546 | } |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
2f04fa88 YL |
551 | static int __init calibrate_APIC_clock(void) |
552 | { | |
553 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
554 | void (*real_handler)(struct clock_event_device *dev); |
555 | unsigned long deltaj; | |
754ef0cd | 556 | long delta, deltatsc; |
2f04fa88 YL |
557 | int pm_referenced = 0; |
558 | ||
559 | local_irq_disable(); | |
560 | ||
561 | /* Replace the global interrupt handler */ | |
562 | real_handler = global_clock_event->event_handler; | |
563 | global_clock_event->event_handler = lapic_cal_handler; | |
564 | ||
565 | /* | |
81608f3c | 566 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
567 | * can underflow in the 100ms detection time frame |
568 | */ | |
81608f3c | 569 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
570 | |
571 | /* Let the interrupts run */ | |
572 | local_irq_enable(); | |
573 | ||
574 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
575 | cpu_relax(); | |
576 | ||
577 | local_irq_disable(); | |
578 | ||
579 | /* Restore the real event handler */ | |
580 | global_clock_event->event_handler = real_handler; | |
581 | ||
582 | /* Build delta t1-t2 as apic timer counts down */ | |
583 | delta = lapic_cal_t1 - lapic_cal_t2; | |
584 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
585 | ||
754ef0cd YI |
586 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
587 | ||
b189892d CG |
588 | /* we trust the PM based calibration if possible */ |
589 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 590 | &delta, &deltatsc); |
2f04fa88 YL |
591 | |
592 | /* Calculate the scaled math multiplication factor */ | |
593 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
594 | lapic_clockevent.shift); | |
595 | lapic_clockevent.max_delta_ns = | |
596 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
597 | lapic_clockevent.min_delta_ns = | |
598 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
599 | ||
600 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
601 | ||
602 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
603 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); | |
604 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", | |
605 | calibration_result); | |
606 | ||
607 | if (cpu_has_tsc) { | |
2f04fa88 YL |
608 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
609 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
610 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
611 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
612 | } |
613 | ||
614 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
615 | "%u.%04u MHz.\n", | |
616 | calibration_result / (1000000 / HZ), | |
617 | calibration_result % (1000000 / HZ)); | |
618 | ||
619 | /* | |
620 | * Do a sanity check on the APIC calibration result | |
621 | */ | |
622 | if (calibration_result < (1000000 / HZ)) { | |
623 | local_irq_enable(); | |
ba21ebb6 | 624 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
625 | return -1; |
626 | } | |
627 | ||
628 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
629 | ||
b189892d CG |
630 | /* |
631 | * PM timer calibration failed or not turned on | |
632 | * so lets try APIC timer based calibration | |
633 | */ | |
2f04fa88 YL |
634 | if (!pm_referenced) { |
635 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
636 | ||
637 | /* | |
638 | * Setup the apic timer manually | |
639 | */ | |
640 | levt->event_handler = lapic_cal_handler; | |
641 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
642 | lapic_cal_loops = -1; | |
643 | ||
644 | /* Let the interrupts run */ | |
645 | local_irq_enable(); | |
646 | ||
647 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
648 | cpu_relax(); | |
649 | ||
2f04fa88 YL |
650 | /* Stop the lapic timer */ |
651 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
652 | ||
2f04fa88 YL |
653 | /* Jiffies delta */ |
654 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
655 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
656 | ||
657 | /* Check, if the jiffies result is consistent */ | |
658 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
659 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
660 | else | |
661 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
662 | } else | |
663 | local_irq_enable(); | |
664 | ||
665 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 666 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
667 | return -1; |
668 | } | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
e83a5fdc HS |
673 | /* |
674 | * Setup the boot APIC | |
675 | * | |
676 | * Calibrate and verify the result. | |
677 | */ | |
0e078e2f TG |
678 | void __init setup_boot_APIC_clock(void) |
679 | { | |
680 | /* | |
274cfe59 CG |
681 | * The local apic timer can be disabled via the kernel |
682 | * commandline or from the CPU detection code. Register the lapic | |
683 | * timer as a dummy clock event source on SMP systems, so the | |
684 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
685 | */ |
686 | if (disable_apic_timer) { | |
ba21ebb6 | 687 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 688 | /* No broadcast on UP ! */ |
9d09951d TG |
689 | if (num_possible_cpus() > 1) { |
690 | lapic_clockevent.mult = 1; | |
0e078e2f | 691 | setup_APIC_timer(); |
9d09951d | 692 | } |
0e078e2f TG |
693 | return; |
694 | } | |
695 | ||
274cfe59 CG |
696 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
697 | "calibrating APIC timer ...\n"); | |
698 | ||
89b3b1f4 | 699 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
700 | /* No broadcast on UP ! */ |
701 | if (num_possible_cpus() > 1) | |
702 | setup_APIC_timer(); | |
703 | return; | |
704 | } | |
705 | ||
0e078e2f TG |
706 | /* |
707 | * If nmi_watchdog is set to IO_APIC, we need the | |
708 | * PIT/HPET going. Otherwise register lapic as a dummy | |
709 | * device. | |
710 | */ | |
711 | if (nmi_watchdog != NMI_IO_APIC) | |
712 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
713 | else | |
ba21ebb6 | 714 | pr_warning("APIC timer registered as dummy," |
116f570e | 715 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 716 | |
274cfe59 | 717 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
718 | setup_APIC_timer(); |
719 | } | |
720 | ||
0e078e2f TG |
721 | void __cpuinit setup_secondary_APIC_clock(void) |
722 | { | |
0e078e2f TG |
723 | setup_APIC_timer(); |
724 | } | |
725 | ||
726 | /* | |
727 | * The guts of the apic timer interrupt | |
728 | */ | |
729 | static void local_apic_timer_interrupt(void) | |
730 | { | |
731 | int cpu = smp_processor_id(); | |
732 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
733 | ||
734 | /* | |
735 | * Normally we should not be here till LAPIC has been initialized but | |
736 | * in some cases like kdump, its possible that there is a pending LAPIC | |
737 | * timer interrupt from previous kernel's context and is delivered in | |
738 | * new kernel the moment interrupts are enabled. | |
739 | * | |
740 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
741 | * its possible that when we get here evt->event_handler is NULL. | |
742 | * Check for event_handler being NULL and discard the interrupt as | |
743 | * spurious. | |
744 | */ | |
745 | if (!evt->event_handler) { | |
ba21ebb6 | 746 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
747 | /* Switch it off */ |
748 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
749 | return; | |
750 | } | |
751 | ||
752 | /* | |
753 | * the NMI deadlock-detector uses this. | |
754 | */ | |
915b0d01 | 755 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
756 | |
757 | evt->event_handler(evt); | |
758 | } | |
759 | ||
760 | /* | |
761 | * Local APIC timer interrupt. This is the most natural way for doing | |
762 | * local interrupts, but local timer interrupts can be emulated by | |
763 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
764 | * | |
765 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
766 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
767 | */ | |
bcbc4f20 | 768 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
769 | { |
770 | struct pt_regs *old_regs = set_irq_regs(regs); | |
771 | ||
772 | /* | |
773 | * NOTE! We'd better ACK the irq immediately, | |
774 | * because timer handling can be slow. | |
775 | */ | |
776 | ack_APIC_irq(); | |
777 | /* | |
778 | * update_process_times() expects us to have done irq_enter(). | |
779 | * Besides, if we don't timer interrupts ignore the global | |
780 | * interrupt lock, which is the WrongThing (tm) to do. | |
781 | */ | |
782 | exit_idle(); | |
783 | irq_enter(); | |
784 | local_apic_timer_interrupt(); | |
785 | irq_exit(); | |
274cfe59 | 786 | |
0e078e2f TG |
787 | set_irq_regs(old_regs); |
788 | } | |
789 | ||
790 | int setup_profiling_timer(unsigned int multiplier) | |
791 | { | |
792 | return -EINVAL; | |
793 | } | |
794 | ||
0e078e2f TG |
795 | /* |
796 | * Local APIC start and shutdown | |
797 | */ | |
798 | ||
799 | /** | |
800 | * clear_local_APIC - shutdown the local APIC | |
801 | * | |
802 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
803 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
804 | * leftovers during boot. | |
805 | */ | |
806 | void clear_local_APIC(void) | |
807 | { | |
2584a82d | 808 | int maxlvt; |
0e078e2f TG |
809 | u32 v; |
810 | ||
d3432896 | 811 | /* APIC hasn't been mapped yet */ |
cf6567fe | 812 | if (!x2apic && !apic_phys) |
d3432896 AK |
813 | return; |
814 | ||
815 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
816 | /* |
817 | * Masking an LVT entry can trigger a local APIC error | |
818 | * if the vector is zero. Mask LVTERR first to prevent this. | |
819 | */ | |
820 | if (maxlvt >= 3) { | |
821 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
822 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
823 | } | |
824 | /* | |
825 | * Careful: we have to set masks only first to deassert | |
826 | * any level-triggered sources. | |
827 | */ | |
828 | v = apic_read(APIC_LVTT); | |
829 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
830 | v = apic_read(APIC_LVT0); | |
831 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
832 | v = apic_read(APIC_LVT1); | |
833 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
834 | if (maxlvt >= 4) { | |
835 | v = apic_read(APIC_LVTPC); | |
836 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
837 | } | |
838 | ||
6764014b | 839 | /* lets not touch this if we didn't frob it */ |
07db1c14 | 840 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
6764014b CG |
841 | if (maxlvt >= 5) { |
842 | v = apic_read(APIC_LVTTHMR); | |
843 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
844 | } | |
845 | #endif | |
5ca8681c AK |
846 | #ifdef CONFIG_X86_MCE_INTEL |
847 | if (maxlvt >= 6) { | |
848 | v = apic_read(APIC_LVTCMCI); | |
849 | if (!(v & APIC_LVT_MASKED)) | |
850 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
851 | } | |
852 | #endif | |
853 | ||
0e078e2f TG |
854 | /* |
855 | * Clean APIC state for other OSs: | |
856 | */ | |
857 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
858 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
859 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
860 | if (maxlvt >= 3) | |
861 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
862 | if (maxlvt >= 4) | |
863 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
864 | |
865 | /* Integrated APIC (!82489DX) ? */ | |
866 | if (lapic_is_integrated()) { | |
867 | if (maxlvt > 3) | |
868 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
869 | apic_write(APIC_ESR, 0); | |
870 | apic_read(APIC_ESR); | |
871 | } | |
0e078e2f TG |
872 | } |
873 | ||
874 | /** | |
875 | * disable_local_APIC - clear and disable the local APIC | |
876 | */ | |
877 | void disable_local_APIC(void) | |
878 | { | |
879 | unsigned int value; | |
880 | ||
4a13ad0b JB |
881 | /* APIC hasn't been mapped yet */ |
882 | if (!apic_phys) | |
883 | return; | |
884 | ||
0e078e2f TG |
885 | clear_local_APIC(); |
886 | ||
887 | /* | |
888 | * Disable APIC (implies clearing of registers | |
889 | * for 82489DX!). | |
890 | */ | |
891 | value = apic_read(APIC_SPIV); | |
892 | value &= ~APIC_SPIV_APIC_ENABLED; | |
893 | apic_write(APIC_SPIV, value); | |
990b183e CG |
894 | |
895 | #ifdef CONFIG_X86_32 | |
896 | /* | |
897 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
898 | * restore the disabled state. | |
899 | */ | |
900 | if (enabled_via_apicbase) { | |
901 | unsigned int l, h; | |
902 | ||
903 | rdmsr(MSR_IA32_APICBASE, l, h); | |
904 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
905 | wrmsr(MSR_IA32_APICBASE, l, h); | |
906 | } | |
907 | #endif | |
0e078e2f TG |
908 | } |
909 | ||
fe4024dc CG |
910 | /* |
911 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
912 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
913 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
914 | * for the case where Linux didn't enable the LAPIC. | |
915 | */ | |
0e078e2f TG |
916 | void lapic_shutdown(void) |
917 | { | |
918 | unsigned long flags; | |
919 | ||
920 | if (!cpu_has_apic) | |
921 | return; | |
922 | ||
923 | local_irq_save(flags); | |
924 | ||
fe4024dc CG |
925 | #ifdef CONFIG_X86_32 |
926 | if (!enabled_via_apicbase) | |
927 | clear_local_APIC(); | |
928 | else | |
929 | #endif | |
930 | disable_local_APIC(); | |
931 | ||
0e078e2f TG |
932 | |
933 | local_irq_restore(flags); | |
934 | } | |
935 | ||
936 | /* | |
937 | * This is to verify that we're looking at a real local APIC. | |
938 | * Check these against your board if the CPUs aren't getting | |
939 | * started for no apparent reason. | |
940 | */ | |
941 | int __init verify_local_APIC(void) | |
942 | { | |
943 | unsigned int reg0, reg1; | |
944 | ||
945 | /* | |
946 | * The version register is read-only in a real APIC. | |
947 | */ | |
948 | reg0 = apic_read(APIC_LVR); | |
949 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
950 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
951 | reg1 = apic_read(APIC_LVR); | |
952 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
953 | ||
954 | /* | |
955 | * The two version reads above should print the same | |
956 | * numbers. If the second one is different, then we | |
957 | * poke at a non-APIC. | |
958 | */ | |
959 | if (reg1 != reg0) | |
960 | return 0; | |
961 | ||
962 | /* | |
963 | * Check if the version looks reasonably. | |
964 | */ | |
965 | reg1 = GET_APIC_VERSION(reg0); | |
966 | if (reg1 == 0x00 || reg1 == 0xff) | |
967 | return 0; | |
968 | reg1 = lapic_get_maxlvt(); | |
969 | if (reg1 < 0x02 || reg1 == 0xff) | |
970 | return 0; | |
971 | ||
972 | /* | |
973 | * The ID register is read/write in a real APIC. | |
974 | */ | |
2d7a66d0 | 975 | reg0 = apic_read(APIC_ID); |
0e078e2f | 976 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
5b812727 | 977 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
2d7a66d0 | 978 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
979 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
980 | apic_write(APIC_ID, reg0); | |
5b812727 | 981 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
0e078e2f TG |
982 | return 0; |
983 | ||
984 | /* | |
1da177e4 LT |
985 | * The next two are just to see if we have sane values. |
986 | * They're only really relevant if we're in Virtual Wire | |
987 | * compatibility mode, but most boxes are anymore. | |
988 | */ | |
989 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 990 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
991 | reg1 = apic_read(APIC_LVT1); |
992 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
993 | ||
994 | return 1; | |
995 | } | |
996 | ||
0e078e2f TG |
997 | /** |
998 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
999 | */ | |
1da177e4 LT |
1000 | void __init sync_Arb_IDs(void) |
1001 | { | |
296cb951 CG |
1002 | /* |
1003 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1004 | * needed on AMD. | |
1005 | */ | |
1006 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1007 | return; |
1008 | ||
1009 | /* | |
1010 | * Wait for idle. | |
1011 | */ | |
1012 | apic_wait_icr_idle(); | |
1013 | ||
1014 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1015 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1016 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1017 | } |
1018 | ||
1da177e4 LT |
1019 | /* |
1020 | * An initial setup of the virtual wire mode. | |
1021 | */ | |
1022 | void __init init_bsp_APIC(void) | |
1023 | { | |
11a8e778 | 1024 | unsigned int value; |
1da177e4 LT |
1025 | |
1026 | /* | |
1027 | * Don't do the setup now if we have a SMP BIOS as the | |
1028 | * through-I/O-APIC virtual wire mode might be active. | |
1029 | */ | |
1030 | if (smp_found_config || !cpu_has_apic) | |
1031 | return; | |
1032 | ||
1da177e4 LT |
1033 | /* |
1034 | * Do not trust the local APIC being empty at bootup. | |
1035 | */ | |
1036 | clear_local_APIC(); | |
1037 | ||
1038 | /* | |
1039 | * Enable APIC. | |
1040 | */ | |
1041 | value = apic_read(APIC_SPIV); | |
1042 | value &= ~APIC_VECTOR_MASK; | |
1043 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1044 | |
1045 | #ifdef CONFIG_X86_32 | |
1046 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1047 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1048 | (boot_cpu_data.x86 == 15)) | |
1049 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1050 | else | |
1051 | #endif | |
1052 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1053 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1054 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1055 | |
1056 | /* | |
1057 | * Set up the virtual wire mode. | |
1058 | */ | |
11a8e778 | 1059 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1060 | value = APIC_DM_NMI; |
638c0411 CG |
1061 | if (!lapic_is_integrated()) /* 82489DX */ |
1062 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1063 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1064 | } |
1065 | ||
c43da2f5 CG |
1066 | static void __cpuinit lapic_setup_esr(void) |
1067 | { | |
9df08f10 CG |
1068 | unsigned int oldvalue, value, maxlvt; |
1069 | ||
1070 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1071 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1072 | return; |
1073 | } | |
c43da2f5 | 1074 | |
08125d3e | 1075 | if (apic->disable_esr) { |
c43da2f5 | 1076 | /* |
9df08f10 CG |
1077 | * Something untraceable is creating bad interrupts on |
1078 | * secondary quads ... for the moment, just leave the | |
1079 | * ESR disabled - we can't do anything useful with the | |
1080 | * errors anyway - mbligh | |
c43da2f5 | 1081 | */ |
ba21ebb6 | 1082 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1083 | return; |
c43da2f5 | 1084 | } |
9df08f10 CG |
1085 | |
1086 | maxlvt = lapic_get_maxlvt(); | |
1087 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1088 | apic_write(APIC_ESR, 0); | |
1089 | oldvalue = apic_read(APIC_ESR); | |
1090 | ||
1091 | /* enables sending errors */ | |
1092 | value = ERROR_APIC_VECTOR; | |
1093 | apic_write(APIC_LVTERR, value); | |
1094 | ||
1095 | /* | |
1096 | * spec says clear errors after enabling vector. | |
1097 | */ | |
1098 | if (maxlvt > 3) | |
1099 | apic_write(APIC_ESR, 0); | |
1100 | value = apic_read(APIC_ESR); | |
1101 | if (value != oldvalue) | |
1102 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1103 | "vector: 0x%08x after: 0x%08x\n", | |
1104 | oldvalue, value); | |
c43da2f5 CG |
1105 | } |
1106 | ||
1107 | ||
0e078e2f TG |
1108 | /** |
1109 | * setup_local_APIC - setup the local APIC | |
1110 | */ | |
1111 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1112 | { |
739f33b3 | 1113 | unsigned int value; |
da7ed9f9 | 1114 | int i, j; |
1da177e4 | 1115 | |
f1182638 | 1116 | if (disable_apic) { |
65a4e574 | 1117 | arch_disable_smp_support(); |
f1182638 JB |
1118 | return; |
1119 | } | |
1120 | ||
89c38c28 CG |
1121 | #ifdef CONFIG_X86_32 |
1122 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1123 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1124 | apic_write(APIC_ESR, 0); |
1125 | apic_write(APIC_ESR, 0); | |
1126 | apic_write(APIC_ESR, 0); | |
1127 | apic_write(APIC_ESR, 0); | |
1128 | } | |
1129 | #endif | |
1130 | ||
ac23d4ee | 1131 | preempt_disable(); |
1da177e4 | 1132 | |
1da177e4 LT |
1133 | /* |
1134 | * Double-check whether this APIC is really registered. | |
1135 | * This is meaningless in clustered apic mode, so we skip it. | |
1136 | */ | |
7ed248da | 1137 | if (!apic->apic_id_registered()) |
1da177e4 LT |
1138 | BUG(); |
1139 | ||
1140 | /* | |
1141 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1142 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1143 | * document number 292116). So here it goes... | |
1144 | */ | |
a5c43296 | 1145 | apic->init_apic_ldr(); |
1da177e4 LT |
1146 | |
1147 | /* | |
1148 | * Set Task Priority to 'accept all'. We never change this | |
1149 | * later on. | |
1150 | */ | |
1151 | value = apic_read(APIC_TASKPRI); | |
1152 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1153 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1154 | |
da7ed9f9 VG |
1155 | /* |
1156 | * After a crash, we no longer service the interrupts and a pending | |
1157 | * interrupt from previous kernel might still have ISR bit set. | |
1158 | * | |
1159 | * Most probably by now CPU has serviced that pending interrupt and | |
1160 | * it might not have done the ack_APIC_irq() because it thought, | |
1161 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1162 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1163 | * the interrupt. Hence a vector might get locked. It was noticed | |
1164 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1165 | */ | |
1166 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1167 | value = apic_read(APIC_ISR + i*0x10); | |
1168 | for (j = 31; j >= 0; j--) { | |
1169 | if (value & (1<<j)) | |
1170 | ack_APIC_irq(); | |
1171 | } | |
1172 | } | |
1173 | ||
1da177e4 LT |
1174 | /* |
1175 | * Now that we are all set up, enable the APIC | |
1176 | */ | |
1177 | value = apic_read(APIC_SPIV); | |
1178 | value &= ~APIC_VECTOR_MASK; | |
1179 | /* | |
1180 | * Enable APIC | |
1181 | */ | |
1182 | value |= APIC_SPIV_APIC_ENABLED; | |
1183 | ||
89c38c28 CG |
1184 | #ifdef CONFIG_X86_32 |
1185 | /* | |
1186 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1187 | * certain networking cards. If high frequency interrupts are | |
1188 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1189 | * entry is masked/unmasked at a high rate as well then sooner or | |
1190 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1191 | * from the device. If focus CPU is disabled then the hang goes | |
1192 | * away, oh well :-( | |
1193 | * | |
1194 | * [ This bug can be reproduced easily with a level-triggered | |
1195 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1196 | * BX chipset. ] | |
1197 | */ | |
1198 | /* | |
1199 | * Actually disabling the focus CPU check just makes the hang less | |
1200 | * frequent as it makes the interrupt distributon model be more | |
1201 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1202 | * See also the comment in end_level_ioapic_irq(). --macro | |
1203 | */ | |
1204 | ||
1205 | /* | |
1206 | * - enable focus processor (bit==0) | |
1207 | * - 64bit mode always use processor focus | |
1208 | * so no need to set it | |
1209 | */ | |
1210 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1211 | #endif | |
3f14c746 | 1212 | |
1da177e4 LT |
1213 | /* |
1214 | * Set spurious IRQ vector | |
1215 | */ | |
1216 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1217 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1218 | |
1219 | /* | |
1220 | * Set up LVT0, LVT1: | |
1221 | * | |
1222 | * set up through-local-APIC on the BP's LINT0. This is not | |
1223 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1224 | * we delegate interrupts to the 8259A. | |
1225 | */ | |
1226 | /* | |
1227 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1228 | */ | |
1229 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1230 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1231 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1232 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1233 | smp_processor_id()); |
1da177e4 LT |
1234 | } else { |
1235 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1236 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1237 | smp_processor_id()); |
1da177e4 | 1238 | } |
11a8e778 | 1239 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1240 | |
1241 | /* | |
1242 | * only the BP should see the LINT1 NMI signal, obviously. | |
1243 | */ | |
1244 | if (!smp_processor_id()) | |
1245 | value = APIC_DM_NMI; | |
1246 | else | |
1247 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1248 | if (!lapic_is_integrated()) /* 82489DX */ |
1249 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1250 | apic_write(APIC_LVT1, value); |
89c38c28 | 1251 | |
ac23d4ee | 1252 | preempt_enable(); |
be71b855 AK |
1253 | |
1254 | #ifdef CONFIG_X86_MCE_INTEL | |
1255 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
1256 | if (smp_processor_id() == 0) | |
1257 | cmci_recheck(); | |
1258 | #endif | |
739f33b3 | 1259 | } |
1da177e4 | 1260 | |
739f33b3 AK |
1261 | void __cpuinit end_local_APIC_setup(void) |
1262 | { | |
1263 | lapic_setup_esr(); | |
fa6b95fc CG |
1264 | |
1265 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1266 | { |
1267 | unsigned int value; | |
1268 | /* Disable the local apic timer */ | |
1269 | value = apic_read(APIC_LVTT); | |
1270 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1271 | apic_write(APIC_LVTT, value); | |
1272 | } | |
fa6b95fc CG |
1273 | #endif |
1274 | ||
f2802e7f | 1275 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1276 | apic_pm_activate(); |
1da177e4 | 1277 | } |
1da177e4 | 1278 | |
06cd9a7d | 1279 | #ifdef CONFIG_X86_X2APIC |
6e1cb38a SS |
1280 | void check_x2apic(void) |
1281 | { | |
ef1f87aa | 1282 | if (x2apic_enabled()) { |
ba21ebb6 | 1283 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
6e1cb38a | 1284 | x2apic_preenabled = x2apic = 1; |
6e1cb38a SS |
1285 | } |
1286 | } | |
1287 | ||
1288 | void enable_x2apic(void) | |
1289 | { | |
1290 | int msr, msr2; | |
1291 | ||
06cd9a7d YL |
1292 | if (!x2apic) |
1293 | return; | |
1294 | ||
6e1cb38a SS |
1295 | rdmsr(MSR_IA32_APICBASE, msr, msr2); |
1296 | if (!(msr & X2APIC_ENABLE)) { | |
ba21ebb6 | 1297 | pr_info("Enabling x2apic\n"); |
6e1cb38a SS |
1298 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1299 | } | |
1300 | } | |
1301 | ||
2236d252 | 1302 | void __init enable_IR_x2apic(void) |
6e1cb38a SS |
1303 | { |
1304 | #ifdef CONFIG_INTR_REMAP | |
1305 | int ret; | |
1306 | unsigned long flags; | |
b24696bc | 1307 | struct IO_APIC_route_entry **ioapic_entries = NULL; |
6e1cb38a SS |
1308 | |
1309 | if (!cpu_has_x2apic) | |
1310 | return; | |
1311 | ||
1312 | if (!x2apic_preenabled && disable_x2apic) { | |
ba21ebb6 CG |
1313 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1314 | "because of nox2apic\n"); | |
6e1cb38a SS |
1315 | return; |
1316 | } | |
1317 | ||
1318 | if (x2apic_preenabled && disable_x2apic) | |
1319 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1320 | ||
1321 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
ba21ebb6 CG |
1322 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1323 | "because of skipping io-apic setup\n"); | |
6e1cb38a SS |
1324 | return; |
1325 | } | |
1326 | ||
1327 | ret = dmar_table_init(); | |
1328 | if (ret) { | |
ba21ebb6 | 1329 | pr_info("dmar_table_init() failed with %d:\n", ret); |
6e1cb38a SS |
1330 | |
1331 | if (x2apic_preenabled) | |
1332 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1333 | else | |
ba21ebb6 | 1334 | pr_info("Not enabling x2apic,Intr-remapping\n"); |
6e1cb38a SS |
1335 | return; |
1336 | } | |
1337 | ||
b24696bc FY |
1338 | ioapic_entries = alloc_ioapic_entries(); |
1339 | if (!ioapic_entries) { | |
1340 | pr_info("Allocate ioapic_entries failed: %d\n", ret); | |
1341 | goto end; | |
1342 | } | |
1343 | ||
1344 | ret = save_IO_APIC_setup(ioapic_entries); | |
5ffa4eb2 | 1345 | if (ret) { |
ba21ebb6 | 1346 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
5ffa4eb2 CG |
1347 | goto end; |
1348 | } | |
6e1cb38a | 1349 | |
05c3dc2c | 1350 | local_irq_save(flags); |
b24696bc | 1351 | mask_IO_APIC_setup(ioapic_entries); |
05c3dc2c SS |
1352 | mask_8259A(); |
1353 | ||
b24696bc | 1354 | ret = enable_intr_remapping(EIM_32BIT_APIC_ID); |
6e1cb38a SS |
1355 | |
1356 | if (ret && x2apic_preenabled) { | |
1357 | local_irq_restore(flags); | |
1358 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1359 | } | |
1360 | ||
1361 | if (ret) | |
5ffa4eb2 | 1362 | goto end_restore; |
6e1cb38a SS |
1363 | |
1364 | if (!x2apic) { | |
1365 | x2apic = 1; | |
6e1cb38a SS |
1366 | enable_x2apic(); |
1367 | } | |
5ffa4eb2 CG |
1368 | |
1369 | end_restore: | |
6e1cb38a SS |
1370 | if (ret) |
1371 | /* | |
1372 | * IR enabling failed | |
1373 | */ | |
b24696bc | 1374 | restore_IO_APIC_setup(ioapic_entries); |
6e1cb38a | 1375 | else |
b24696bc | 1376 | reinit_intr_remapped_IO_APIC(x2apic_preenabled, ioapic_entries); |
6e1cb38a SS |
1377 | |
1378 | unmask_8259A(); | |
1379 | local_irq_restore(flags); | |
1380 | ||
05c3dc2c | 1381 | end: |
6e1cb38a SS |
1382 | if (!ret) { |
1383 | if (!x2apic_preenabled) | |
ba21ebb6 | 1384 | pr_info("Enabled x2apic and interrupt-remapping\n"); |
6e1cb38a | 1385 | else |
ba21ebb6 | 1386 | pr_info("Enabled Interrupt-remapping\n"); |
6e1cb38a | 1387 | } else |
ba21ebb6 | 1388 | pr_err("Failed to enable Interrupt-remapping and x2apic\n"); |
b24696bc FY |
1389 | if (ioapic_entries) |
1390 | free_ioapic_entries(ioapic_entries); | |
6e1cb38a SS |
1391 | #else |
1392 | if (!cpu_has_x2apic) | |
1393 | return; | |
1394 | ||
1395 | if (x2apic_preenabled) | |
1396 | panic("x2apic enabled prior OS handover," | |
1397 | " enable CONFIG_INTR_REMAP"); | |
1398 | ||
ba21ebb6 CG |
1399 | pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " |
1400 | " and x2apic\n"); | |
6e1cb38a SS |
1401 | #endif |
1402 | ||
1403 | return; | |
1404 | } | |
06cd9a7d | 1405 | #endif /* CONFIG_X86_X2APIC */ |
6e1cb38a | 1406 | |
be7a656f | 1407 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1408 | /* |
1409 | * Detect and enable local APICs on non-SMP boards. | |
1410 | * Original code written by Keir Fraser. | |
1411 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1412 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1413 | */ |
0e078e2f | 1414 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1415 | { |
1416 | if (!cpu_has_apic) { | |
ba21ebb6 | 1417 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1418 | return -1; |
1419 | } | |
1420 | ||
1421 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1422 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1423 | return 0; |
1424 | } | |
be7a656f YL |
1425 | #else |
1426 | /* | |
1427 | * Detect and initialize APIC | |
1428 | */ | |
1429 | static int __init detect_init_APIC(void) | |
1430 | { | |
1431 | u32 h, l, features; | |
1432 | ||
1433 | /* Disabled by kernel option? */ | |
1434 | if (disable_apic) | |
1435 | return -1; | |
1436 | ||
1437 | switch (boot_cpu_data.x86_vendor) { | |
1438 | case X86_VENDOR_AMD: | |
1439 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1440 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1441 | break; |
1442 | goto no_apic; | |
1443 | case X86_VENDOR_INTEL: | |
1444 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1445 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1446 | break; | |
1447 | goto no_apic; | |
1448 | default: | |
1449 | goto no_apic; | |
1450 | } | |
1451 | ||
1452 | if (!cpu_has_apic) { | |
1453 | /* | |
1454 | * Over-ride BIOS and try to enable the local APIC only if | |
1455 | * "lapic" specified. | |
1456 | */ | |
1457 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1458 | pr_info("Local APIC disabled by BIOS -- " |
1459 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1460 | return -1; |
1461 | } | |
1462 | /* | |
1463 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1464 | * MSR. This can only be done in software for Intel P6 or later | |
1465 | * and AMD K7 (Model > 1) or later. | |
1466 | */ | |
1467 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1468 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
ba21ebb6 | 1469 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
be7a656f YL |
1470 | l &= ~MSR_IA32_APICBASE_BASE; |
1471 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1472 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1473 | enabled_via_apicbase = 1; | |
1474 | } | |
1475 | } | |
1476 | /* | |
1477 | * The APIC feature bit should now be enabled | |
1478 | * in `cpuid' | |
1479 | */ | |
1480 | features = cpuid_edx(1); | |
1481 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
ba21ebb6 | 1482 | pr_warning("Could not enable APIC!\n"); |
be7a656f YL |
1483 | return -1; |
1484 | } | |
1485 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1486 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1487 | ||
1488 | /* The BIOS may have set up the APIC at some other address */ | |
1489 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1490 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1491 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1492 | ||
ba21ebb6 | 1493 | pr_info("Found and enabled local APIC!\n"); |
be7a656f YL |
1494 | |
1495 | apic_pm_activate(); | |
1496 | ||
1497 | return 0; | |
1498 | ||
1499 | no_apic: | |
ba21ebb6 | 1500 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1501 | return -1; |
1502 | } | |
1503 | #endif | |
1da177e4 | 1504 | |
f28c0ae2 | 1505 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1506 | void __init early_init_lapic_mapping(void) |
1507 | { | |
431ee79d | 1508 | unsigned long phys_addr; |
8643f9d0 YL |
1509 | |
1510 | /* | |
1511 | * If no local APIC can be found then go out | |
1512 | * : it means there is no mpatable and MADT | |
1513 | */ | |
1514 | if (!smp_found_config) | |
1515 | return; | |
1516 | ||
431ee79d | 1517 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1518 | |
431ee79d | 1519 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1520 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1521 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1522 | |
1523 | /* | |
1524 | * Fetch the APIC ID of the BSP in case we have a | |
1525 | * default configuration (or the MP table is broken). | |
1526 | */ | |
4c9961d5 | 1527 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1528 | } |
f28c0ae2 | 1529 | #endif |
8643f9d0 | 1530 | |
0e078e2f TG |
1531 | /** |
1532 | * init_apic_mappings - initialize APIC mappings | |
1533 | */ | |
1da177e4 LT |
1534 | void __init init_apic_mappings(void) |
1535 | { | |
6e1cb38a | 1536 | if (x2apic) { |
4c9961d5 | 1537 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1538 | return; |
1539 | } | |
1540 | ||
1da177e4 LT |
1541 | /* |
1542 | * If no local APIC can be found then set up a fake all | |
1543 | * zeroes page to simulate the local APIC and another | |
1544 | * one for the IO-APIC. | |
1545 | */ | |
1546 | if (!smp_found_config && detect_init_APIC()) { | |
1547 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1548 | apic_phys = __pa(apic_phys); | |
1549 | } else | |
1550 | apic_phys = mp_lapic_addr; | |
1551 | ||
1552 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
79c09698 | 1553 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
7ffeeb1e | 1554 | APIC_BASE, apic_phys); |
1da177e4 LT |
1555 | |
1556 | /* | |
1557 | * Fetch the APIC ID of the BSP in case we have a | |
1558 | * default configuration (or the MP table is broken). | |
1559 | */ | |
f28c0ae2 YL |
1560 | if (boot_cpu_physical_apicid == -1U) |
1561 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1562 | } |
1563 | ||
1564 | /* | |
0e078e2f TG |
1565 | * This initializes the IO-APIC and APIC hardware if this is |
1566 | * a UP kernel. | |
1da177e4 | 1567 | */ |
1b313f4a CG |
1568 | int apic_version[MAX_APICS]; |
1569 | ||
0e078e2f | 1570 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1571 | { |
0e078e2f | 1572 | if (disable_apic) { |
ba21ebb6 | 1573 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1574 | return -1; |
1575 | } | |
f1182638 | 1576 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1577 | if (!cpu_has_apic) { |
1578 | disable_apic = 1; | |
ba21ebb6 | 1579 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1580 | return -1; |
1581 | } | |
fa2bd35a YL |
1582 | #else |
1583 | if (!smp_found_config && !cpu_has_apic) | |
1584 | return -1; | |
1585 | ||
1586 | /* | |
1587 | * Complain if the BIOS pretends there is one. | |
1588 | */ | |
1589 | if (!cpu_has_apic && | |
1590 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1591 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1592 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1593 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1594 | return -1; | |
1595 | } | |
1596 | #endif | |
1597 | ||
6e1cb38a | 1598 | enable_IR_x2apic(); |
fa2bd35a | 1599 | #ifdef CONFIG_X86_64 |
72ce0165 | 1600 | default_setup_apic_routing(); |
fa2bd35a | 1601 | #endif |
6e1cb38a | 1602 | |
0e078e2f | 1603 | verify_local_APIC(); |
b5841765 GC |
1604 | connect_bsp_APIC(); |
1605 | ||
fa2bd35a | 1606 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1607 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1608 | #else |
1609 | /* | |
1610 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1611 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1612 | * might be zero if read from MP tables. Get it from LAPIC. | |
1613 | */ | |
1614 | # ifdef CONFIG_CRASH_DUMP | |
1615 | boot_cpu_physical_apicid = read_apic_id(); | |
1616 | # endif | |
1617 | #endif | |
1618 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1619 | setup_local_APIC(); |
1da177e4 | 1620 | |
88d0f550 | 1621 | #ifdef CONFIG_X86_IO_APIC |
739f33b3 AK |
1622 | /* |
1623 | * Now enable IO-APICs, actually call clear_IO_APIC | |
98c061b6 | 1624 | * We need clear_IO_APIC before enabling error vector |
739f33b3 AK |
1625 | */ |
1626 | if (!skip_ioapic_setup && nr_ioapics) | |
1627 | enable_IO_APIC(); | |
fa2bd35a | 1628 | #endif |
739f33b3 AK |
1629 | |
1630 | end_local_APIC_setup(); | |
1631 | ||
fa2bd35a | 1632 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1633 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1634 | setup_IO_APIC(); | |
98c061b6 | 1635 | else { |
0e078e2f | 1636 | nr_ioapics = 0; |
98c061b6 YL |
1637 | localise_nmi_watchdog(); |
1638 | } | |
1639 | #else | |
1640 | localise_nmi_watchdog(); | |
fa2bd35a YL |
1641 | #endif |
1642 | ||
98c061b6 | 1643 | setup_boot_clock(); |
fa2bd35a | 1644 | #ifdef CONFIG_X86_64 |
0e078e2f | 1645 | check_nmi_watchdog(); |
fa2bd35a YL |
1646 | #endif |
1647 | ||
0e078e2f | 1648 | return 0; |
1da177e4 LT |
1649 | } |
1650 | ||
1651 | /* | |
0e078e2f | 1652 | * Local APIC interrupts |
1da177e4 LT |
1653 | */ |
1654 | ||
0e078e2f TG |
1655 | /* |
1656 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1657 | */ | |
dc1528dd | 1658 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1659 | { |
dc1528dd YL |
1660 | u32 v; |
1661 | ||
0e078e2f TG |
1662 | exit_idle(); |
1663 | irq_enter(); | |
1da177e4 | 1664 | /* |
0e078e2f TG |
1665 | * Check if this really is a spurious interrupt and ACK it |
1666 | * if it is a vectored one. Just in case... | |
1667 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1668 | */ |
0e078e2f TG |
1669 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1670 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1671 | ack_APIC_irq(); | |
c4d58cbd | 1672 | |
915b0d01 HS |
1673 | inc_irq_stat(irq_spurious_count); |
1674 | ||
dc1528dd | 1675 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1676 | pr_info("spurious APIC interrupt on CPU#%d, " |
1677 | "should never happen.\n", smp_processor_id()); | |
0e078e2f TG |
1678 | irq_exit(); |
1679 | } | |
1da177e4 | 1680 | |
0e078e2f TG |
1681 | /* |
1682 | * This interrupt should never happen with our APIC/SMP architecture | |
1683 | */ | |
dc1528dd | 1684 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1685 | { |
dc1528dd | 1686 | u32 v, v1; |
1da177e4 | 1687 | |
0e078e2f TG |
1688 | exit_idle(); |
1689 | irq_enter(); | |
1690 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1691 | v = apic_read(APIC_ESR); | |
1692 | apic_write(APIC_ESR, 0); | |
1693 | v1 = apic_read(APIC_ESR); | |
1694 | ack_APIC_irq(); | |
1695 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1696 | |
ba21ebb6 CG |
1697 | /* |
1698 | * Here is what the APIC error bits mean: | |
1699 | * 0: Send CS error | |
1700 | * 1: Receive CS error | |
1701 | * 2: Send accept error | |
1702 | * 3: Receive accept error | |
1703 | * 4: Reserved | |
1704 | * 5: Send illegal vector | |
1705 | * 6: Received illegal vector | |
1706 | * 7: Illegal register address | |
1707 | */ | |
1708 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | |
0e078e2f TG |
1709 | smp_processor_id(), v , v1); |
1710 | irq_exit(); | |
1da177e4 LT |
1711 | } |
1712 | ||
b5841765 | 1713 | /** |
36c9d674 CG |
1714 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1715 | */ | |
b5841765 GC |
1716 | void __init connect_bsp_APIC(void) |
1717 | { | |
36c9d674 CG |
1718 | #ifdef CONFIG_X86_32 |
1719 | if (pic_mode) { | |
1720 | /* | |
1721 | * Do not trust the local APIC being empty at bootup. | |
1722 | */ | |
1723 | clear_local_APIC(); | |
1724 | /* | |
1725 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1726 | * local APIC to INT and NMI lines. | |
1727 | */ | |
1728 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1729 | "enabling APIC mode.\n"); | |
1730 | outb(0x70, 0x22); | |
1731 | outb(0x01, 0x23); | |
1732 | } | |
1733 | #endif | |
49040333 IM |
1734 | if (apic->enable_apic_mode) |
1735 | apic->enable_apic_mode(); | |
b5841765 GC |
1736 | } |
1737 | ||
274cfe59 CG |
1738 | /** |
1739 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1740 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1741 | * | |
1742 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1743 | * APIC is disabled. | |
1744 | */ | |
0e078e2f | 1745 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1746 | { |
1b4ee4e4 CG |
1747 | unsigned int value; |
1748 | ||
c177b0bc CG |
1749 | #ifdef CONFIG_X86_32 |
1750 | if (pic_mode) { | |
1751 | /* | |
1752 | * Put the board back into PIC mode (has an effect only on | |
1753 | * certain older boards). Note that APIC interrupts, including | |
1754 | * IPIs, won't work beyond this point! The only exception are | |
1755 | * INIT IPIs. | |
1756 | */ | |
1757 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1758 | "entering PIC mode.\n"); | |
1759 | outb(0x70, 0x22); | |
1760 | outb(0x00, 0x23); | |
1761 | return; | |
1762 | } | |
1763 | #endif | |
1764 | ||
0e078e2f | 1765 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1766 | |
0e078e2f TG |
1767 | /* For the spurious interrupt use vector F, and enable it */ |
1768 | value = apic_read(APIC_SPIV); | |
1769 | value &= ~APIC_VECTOR_MASK; | |
1770 | value |= APIC_SPIV_APIC_ENABLED; | |
1771 | value |= 0xf; | |
1772 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1773 | |
0e078e2f TG |
1774 | if (!virt_wire_setup) { |
1775 | /* | |
1776 | * For LVT0 make it edge triggered, active high, | |
1777 | * external and enabled | |
1778 | */ | |
1779 | value = apic_read(APIC_LVT0); | |
1780 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1781 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1782 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1783 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1784 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1785 | apic_write(APIC_LVT0, value); | |
1786 | } else { | |
1787 | /* Disable LVT0 */ | |
1788 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1789 | } | |
b8ce3359 | 1790 | |
c177b0bc CG |
1791 | /* |
1792 | * For LVT1 make it edge triggered, active high, | |
1793 | * nmi and enabled | |
1794 | */ | |
0e078e2f TG |
1795 | value = apic_read(APIC_LVT1); |
1796 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1797 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1798 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1799 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1800 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1801 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1802 | } |
1803 | ||
be8a5685 AS |
1804 | void __cpuinit generic_processor_info(int apicid, int version) |
1805 | { | |
1806 | int cpu; | |
be8a5685 | 1807 | |
1b313f4a CG |
1808 | /* |
1809 | * Validate version | |
1810 | */ | |
1811 | if (version == 0x0) { | |
ba21ebb6 | 1812 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
3b11ce7f MT |
1813 | "fixing up to 0x10. (tell your hw vendor)\n", |
1814 | version); | |
1b313f4a | 1815 | version = 0x10; |
be8a5685 | 1816 | } |
1b313f4a | 1817 | apic_version[apicid] = version; |
be8a5685 | 1818 | |
3b11ce7f MT |
1819 | if (num_processors >= nr_cpu_ids) { |
1820 | int max = nr_cpu_ids; | |
1821 | int thiscpu = max + disabled_cpus; | |
1822 | ||
1823 | pr_warning( | |
1824 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
1825 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
1826 | ||
1827 | disabled_cpus++; | |
be8a5685 AS |
1828 | return; |
1829 | } | |
1830 | ||
1831 | num_processors++; | |
3b11ce7f | 1832 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
be8a5685 | 1833 | |
b2b815d8 MT |
1834 | if (version != apic_version[boot_cpu_physical_apicid]) |
1835 | WARN_ONCE(1, | |
1836 | "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", | |
1837 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
1838 | ||
be8a5685 AS |
1839 | physid_set(apicid, phys_cpu_present_map); |
1840 | if (apicid == boot_cpu_physical_apicid) { | |
1841 | /* | |
1842 | * x86_bios_cpu_apicid is required to have processors listed | |
1843 | * in same order as logical cpu numbers. Hence the first | |
1844 | * entry is BSP, and so on. | |
1845 | */ | |
1846 | cpu = 0; | |
1847 | } | |
e0da3364 YL |
1848 | if (apicid > max_physical_apicid) |
1849 | max_physical_apicid = apicid; | |
1850 | ||
1b313f4a CG |
1851 | #ifdef CONFIG_X86_32 |
1852 | /* | |
1853 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1854 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1855 | * before this can be done without some confusion. | |
1856 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1857 | * - Ashok Raj <ashok.raj@intel.com> | |
1858 | */ | |
1859 | if (max_physical_apicid >= 8) { | |
1860 | switch (boot_cpu_data.x86_vendor) { | |
1861 | case X86_VENDOR_INTEL: | |
1862 | if (!APIC_XAPIC(version)) { | |
1863 | def_to_bigsmp = 0; | |
1864 | break; | |
1865 | } | |
1866 | /* If P4 and above fall through */ | |
1867 | case X86_VENDOR_AMD: | |
1868 | def_to_bigsmp = 1; | |
1869 | } | |
1870 | } | |
1871 | #endif | |
1872 | ||
3e5095d1 | 1873 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
1874 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
1875 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 1876 | #endif |
be8a5685 | 1877 | |
1de88cd4 MT |
1878 | set_cpu_possible(cpu, true); |
1879 | set_cpu_present(cpu, true); | |
be8a5685 AS |
1880 | } |
1881 | ||
0c81c746 SS |
1882 | int hard_smp_processor_id(void) |
1883 | { | |
1884 | return read_apic_id(); | |
1885 | } | |
1dcdd3d1 IM |
1886 | |
1887 | void default_init_apic_ldr(void) | |
1888 | { | |
1889 | unsigned long val; | |
1890 | ||
1891 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
1892 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
1893 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
1894 | apic_write(APIC_LDR, val); | |
1895 | } | |
1896 | ||
1897 | #ifdef CONFIG_X86_32 | |
1898 | int default_apicid_to_node(int logical_apicid) | |
1899 | { | |
1900 | #ifdef CONFIG_SMP | |
1901 | return apicid_2_node[hard_smp_processor_id()]; | |
1902 | #else | |
1903 | return 0; | |
1904 | #endif | |
1905 | } | |
3491998d | 1906 | #endif |
0c81c746 | 1907 | |
89039b37 | 1908 | /* |
0e078e2f | 1909 | * Power management |
89039b37 | 1910 | */ |
0e078e2f TG |
1911 | #ifdef CONFIG_PM |
1912 | ||
1913 | static struct { | |
274cfe59 CG |
1914 | /* |
1915 | * 'active' is true if the local APIC was enabled by us and | |
1916 | * not the BIOS; this signifies that we are also responsible | |
1917 | * for disabling it before entering apm/acpi suspend | |
1918 | */ | |
0e078e2f TG |
1919 | int active; |
1920 | /* r/w apic fields */ | |
1921 | unsigned int apic_id; | |
1922 | unsigned int apic_taskpri; | |
1923 | unsigned int apic_ldr; | |
1924 | unsigned int apic_dfr; | |
1925 | unsigned int apic_spiv; | |
1926 | unsigned int apic_lvtt; | |
1927 | unsigned int apic_lvtpc; | |
1928 | unsigned int apic_lvt0; | |
1929 | unsigned int apic_lvt1; | |
1930 | unsigned int apic_lvterr; | |
1931 | unsigned int apic_tmict; | |
1932 | unsigned int apic_tdcr; | |
1933 | unsigned int apic_thmr; | |
1934 | } apic_pm_state; | |
1935 | ||
1936 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1937 | { | |
1938 | unsigned long flags; | |
1939 | int maxlvt; | |
89039b37 | 1940 | |
0e078e2f TG |
1941 | if (!apic_pm_state.active) |
1942 | return 0; | |
89039b37 | 1943 | |
0e078e2f | 1944 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1945 | |
2d7a66d0 | 1946 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1947 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1948 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1949 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1950 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1951 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1952 | if (maxlvt >= 4) | |
1953 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1954 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1955 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1956 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1957 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1958 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1959 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1960 | if (maxlvt >= 5) |
1961 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1962 | #endif | |
24968cfd | 1963 | |
0e078e2f TG |
1964 | local_irq_save(flags); |
1965 | disable_local_APIC(); | |
b24696bc FY |
1966 | #ifdef CONFIG_INTR_REMAP |
1967 | if (intr_remapping_enabled) | |
1968 | disable_intr_remapping(); | |
1969 | #endif | |
0e078e2f TG |
1970 | local_irq_restore(flags); |
1971 | return 0; | |
1da177e4 LT |
1972 | } |
1973 | ||
0e078e2f | 1974 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1975 | { |
0e078e2f TG |
1976 | unsigned int l, h; |
1977 | unsigned long flags; | |
1978 | int maxlvt; | |
1da177e4 | 1979 | |
b24696bc FY |
1980 | #ifdef CONFIG_INTR_REMAP |
1981 | int ret; | |
1982 | struct IO_APIC_route_entry **ioapic_entries = NULL; | |
1983 | ||
0e078e2f TG |
1984 | if (!apic_pm_state.active) |
1985 | return 0; | |
89b831ef | 1986 | |
0e078e2f | 1987 | local_irq_save(flags); |
b24696bc FY |
1988 | if (x2apic) { |
1989 | ioapic_entries = alloc_ioapic_entries(); | |
1990 | if (!ioapic_entries) { | |
1991 | WARN(1, "Alloc ioapic_entries in lapic resume failed."); | |
1992 | return -ENOMEM; | |
1993 | } | |
1994 | ||
1995 | ret = save_IO_APIC_setup(ioapic_entries); | |
1996 | if (ret) { | |
1997 | WARN(1, "Saving IO-APIC state failed: %d\n", ret); | |
1998 | free_ioapic_entries(ioapic_entries); | |
1999 | return ret; | |
2000 | } | |
2001 | ||
2002 | mask_IO_APIC_setup(ioapic_entries); | |
2003 | mask_8259A(); | |
2004 | enable_x2apic(); | |
2005 | } | |
2006 | #else | |
2007 | if (!apic_pm_state.active) | |
2008 | return 0; | |
92206c90 | 2009 | |
b24696bc | 2010 | local_irq_save(flags); |
92206c90 CG |
2011 | if (x2apic) |
2012 | enable_x2apic(); | |
b24696bc FY |
2013 | #endif |
2014 | ||
cf6567fe | 2015 | else { |
92206c90 CG |
2016 | /* |
2017 | * Make sure the APICBASE points to the right address | |
2018 | * | |
2019 | * FIXME! This will be wrong if we ever support suspend on | |
2020 | * SMP! We'll need to do this as part of the CPU restore! | |
2021 | */ | |
6e1cb38a SS |
2022 | rdmsr(MSR_IA32_APICBASE, l, h); |
2023 | l &= ~MSR_IA32_APICBASE_BASE; | |
2024 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2025 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 2026 | } |
6e1cb38a | 2027 | |
b24696bc | 2028 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2029 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2030 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2031 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2032 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2033 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2034 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2035 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2036 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2037 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2038 | if (maxlvt >= 5) |
2039 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2040 | #endif | |
2041 | if (maxlvt >= 4) | |
2042 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2043 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2044 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2045 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2046 | apic_write(APIC_ESR, 0); | |
2047 | apic_read(APIC_ESR); | |
2048 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2049 | apic_write(APIC_ESR, 0); | |
2050 | apic_read(APIC_ESR); | |
92206c90 | 2051 | |
b24696bc FY |
2052 | #ifdef CONFIG_INTR_REMAP |
2053 | if (intr_remapping_enabled) | |
2054 | reenable_intr_remapping(EIM_32BIT_APIC_ID); | |
2055 | ||
2056 | if (x2apic) { | |
2057 | unmask_8259A(); | |
2058 | restore_IO_APIC_setup(ioapic_entries); | |
2059 | free_ioapic_entries(ioapic_entries); | |
2060 | } | |
2061 | #endif | |
2062 | ||
0e078e2f | 2063 | local_irq_restore(flags); |
92206c90 | 2064 | |
b24696bc | 2065 | |
0e078e2f TG |
2066 | return 0; |
2067 | } | |
b8ce3359 | 2068 | |
274cfe59 CG |
2069 | /* |
2070 | * This device has no shutdown method - fully functioning local APICs | |
2071 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2072 | */ | |
2073 | ||
0e078e2f TG |
2074 | static struct sysdev_class lapic_sysclass = { |
2075 | .name = "lapic", | |
2076 | .resume = lapic_resume, | |
2077 | .suspend = lapic_suspend, | |
2078 | }; | |
b8ce3359 | 2079 | |
0e078e2f | 2080 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2081 | .id = 0, |
2082 | .cls = &lapic_sysclass, | |
0e078e2f | 2083 | }; |
b8ce3359 | 2084 | |
0e078e2f TG |
2085 | static void __cpuinit apic_pm_activate(void) |
2086 | { | |
2087 | apic_pm_state.active = 1; | |
1da177e4 LT |
2088 | } |
2089 | ||
0e078e2f | 2090 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2091 | { |
0e078e2f | 2092 | int error; |
e83a5fdc | 2093 | |
0e078e2f TG |
2094 | if (!cpu_has_apic) |
2095 | return 0; | |
2096 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2097 | |
0e078e2f TG |
2098 | error = sysdev_class_register(&lapic_sysclass); |
2099 | if (!error) | |
2100 | error = sysdev_register(&device_lapic); | |
2101 | return error; | |
1da177e4 | 2102 | } |
b24696bc FY |
2103 | |
2104 | /* local apic needs to resume before other devices access its registers. */ | |
2105 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2106 | |
2107 | #else /* CONFIG_PM */ | |
2108 | ||
2109 | static void apic_pm_activate(void) { } | |
2110 | ||
2111 | #endif /* CONFIG_PM */ | |
1da177e4 | 2112 | |
f28c0ae2 | 2113 | #ifdef CONFIG_X86_64 |
1da177e4 | 2114 | /* |
f8bf3c65 | 2115 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
2116 | * |
2117 | * Thus far, the major user of this is IBM's Summit2 series: | |
2118 | * | |
637029c6 | 2119 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
2120 | * multi-chassis. Use available data to take a good guess. |
2121 | * If in doubt, go HPET. | |
2122 | */ | |
f8bf3c65 | 2123 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
2124 | { |
2125 | int i, clusters, zeros; | |
2126 | unsigned id; | |
322850af | 2127 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2128 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2129 | ||
322850af YL |
2130 | /* |
2131 | * there is not this kind of box with AMD CPU yet. | |
2132 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
2133 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 2134 | * vsmp box still need checking... |
322850af | 2135 | */ |
1cb68487 | 2136 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
2137 | return 0; |
2138 | ||
23ca4bba | 2139 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2140 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2141 | |
168ef543 | 2142 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2143 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2144 | if (bios_cpu_apicid) { |
2145 | id = bios_cpu_apicid[i]; | |
e423e33e | 2146 | } else if (i < nr_cpu_ids) { |
e8c10ef9 | 2147 | if (cpu_present(i)) |
2148 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2149 | else | |
2150 | continue; | |
e423e33e | 2151 | } else |
e8c10ef9 | 2152 | break; |
2153 | ||
1da177e4 LT |
2154 | if (id != BAD_APICID) |
2155 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2156 | } | |
2157 | ||
2158 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2159 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2160 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2161 | * Since clusters are allocated sequentially, count zeros only if | |
2162 | * they are bounded by ones. | |
1da177e4 LT |
2163 | */ |
2164 | clusters = 0; | |
2165 | zeros = 0; | |
2166 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2167 | if (test_bit(i, clustermap)) { | |
2168 | clusters += 1 + zeros; | |
2169 | zeros = 0; | |
2170 | } else | |
2171 | ++zeros; | |
2172 | } | |
2173 | ||
1cb68487 RT |
2174 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2175 | * not guaranteed to be synced between boards | |
2176 | */ | |
2177 | if (is_vsmp_box() && clusters > 1) | |
2178 | return 1; | |
2179 | ||
1da177e4 | 2180 | /* |
f8bf3c65 | 2181 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
2182 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
2183 | * out, but AFAIK this will work even for them. | |
2184 | */ | |
2185 | return (clusters > 2); | |
2186 | } | |
f28c0ae2 | 2187 | #endif |
1da177e4 LT |
2188 | |
2189 | /* | |
0e078e2f | 2190 | * APIC command line parameters |
1da177e4 | 2191 | */ |
789fa735 | 2192 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2193 | { |
1da177e4 | 2194 | disable_apic = 1; |
9175fc06 | 2195 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2196 | return 0; |
2197 | } | |
2198 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2199 | |
2c8c0e6b | 2200 | /* same as disableapic, for compatibility */ |
789fa735 | 2201 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2202 | { |
789fa735 | 2203 | return setup_disableapic(arg); |
6935d1f9 | 2204 | } |
2c8c0e6b | 2205 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2206 | |
2e7c2838 LT |
2207 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2208 | { | |
2209 | local_apic_timer_c2_ok = 1; | |
2210 | return 0; | |
2211 | } | |
2212 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2213 | ||
36fef094 | 2214 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2215 | { |
1da177e4 | 2216 | disable_apic_timer = 1; |
36fef094 | 2217 | return 0; |
6935d1f9 | 2218 | } |
36fef094 CG |
2219 | early_param("noapictimer", parse_disable_apic_timer); |
2220 | ||
2221 | static int __init parse_nolapic_timer(char *arg) | |
2222 | { | |
2223 | disable_apic_timer = 1; | |
2224 | return 0; | |
6935d1f9 | 2225 | } |
36fef094 | 2226 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2227 | |
79af9bec CG |
2228 | static int __init apic_set_verbosity(char *arg) |
2229 | { | |
2230 | if (!arg) { | |
2231 | #ifdef CONFIG_X86_64 | |
2232 | skip_ioapic_setup = 0; | |
79af9bec CG |
2233 | return 0; |
2234 | #endif | |
2235 | return -EINVAL; | |
2236 | } | |
2237 | ||
2238 | if (strcmp("debug", arg) == 0) | |
2239 | apic_verbosity = APIC_DEBUG; | |
2240 | else if (strcmp("verbose", arg) == 0) | |
2241 | apic_verbosity = APIC_VERBOSE; | |
2242 | else { | |
ba21ebb6 | 2243 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2244 | " use apic=verbose or apic=debug\n", arg); |
2245 | return -EINVAL; | |
2246 | } | |
2247 | ||
2248 | return 0; | |
2249 | } | |
2250 | early_param("apic", apic_set_verbosity); | |
2251 | ||
1e934dda YL |
2252 | static int __init lapic_insert_resource(void) |
2253 | { | |
2254 | if (!apic_phys) | |
2255 | return -1; | |
2256 | ||
2257 | /* Put local APIC into the resource map. */ | |
2258 | lapic_resource.start = apic_phys; | |
2259 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2260 | insert_resource(&iomem_resource, &lapic_resource); | |
2261 | ||
2262 | return 0; | |
2263 | } | |
2264 | ||
2265 | /* | |
2266 | * need call insert after e820_reserve_resources() | |
2267 | * that is using request_resource | |
2268 | */ | |
2269 | late_initcall(lapic_insert_resource); |