Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 | 17 | #include <linux/kernel_stat.h> |
d1de36f5 | 18 | #include <linux/mc146818rtc.h> |
70a20025 | 19 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
20 | #include <linux/clockchips.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/ftrace.h> | |
24 | #include <linux/ioport.h> | |
e83a5fdc | 25 | #include <linux/module.h> |
d1de36f5 IM |
26 | #include <linux/sysdev.h> |
27 | #include <linux/delay.h> | |
28 | #include <linux/timex.h> | |
6e1cb38a | 29 | #include <linux/dmar.h> |
d1de36f5 IM |
30 | #include <linux/init.h> |
31 | #include <linux/cpu.h> | |
32 | #include <linux/dmi.h> | |
e423e33e | 33 | #include <linux/nmi.h> |
d1de36f5 IM |
34 | #include <linux/smp.h> |
35 | #include <linux/mm.h> | |
1da177e4 | 36 | |
1da177e4 | 37 | #include <asm/pgalloc.h> |
1da177e4 | 38 | #include <asm/atomic.h> |
1da177e4 | 39 | #include <asm/mpspec.h> |
773763df | 40 | #include <asm/i8253.h> |
d1de36f5 | 41 | #include <asm/i8259.h> |
73dea47f | 42 | #include <asm/proto.h> |
2c8c0e6b | 43 | #include <asm/apic.h> |
d1de36f5 IM |
44 | #include <asm/desc.h> |
45 | #include <asm/hpet.h> | |
46 | #include <asm/idle.h> | |
47 | #include <asm/mtrr.h> | |
2bc13797 | 48 | #include <asm/smp.h> |
be71b855 | 49 | #include <asm/mce.h> |
1da177e4 | 50 | |
ec70de8b | 51 | unsigned int num_processors; |
fdbecd9f | 52 | |
ec70de8b | 53 | unsigned disabled_cpus __cpuinitdata; |
fdbecd9f | 54 | |
ec70de8b BG |
55 | /* Processor that is doing the boot up */ |
56 | unsigned int boot_cpu_physical_apicid = -1U; | |
5af5573e | 57 | |
80e5609c | 58 | /* |
fdbecd9f IM |
59 | * The highest APIC ID seen during enumeration. |
60 | * | |
61 | * This determines the messaging protocol we can use: if all APIC IDs | |
62 | * are in the 0 ... 7 range, then we can use logical addressing which | |
63 | * has some performance advantages (better broadcasting). | |
64 | * | |
65 | * If there's an APIC ID above 8, we use physical addressing. | |
80e5609c | 66 | */ |
ec70de8b | 67 | unsigned int max_physical_apicid; |
5af5573e | 68 | |
80e5609c | 69 | /* |
fdbecd9f | 70 | * Bitmask of physically existing CPUs: |
80e5609c | 71 | */ |
ec70de8b BG |
72 | physid_mask_t phys_cpu_present_map; |
73 | ||
74 | /* | |
75 | * Map cpu index to physical APIC ID | |
76 | */ | |
77 | DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); | |
78 | DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); | |
79 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
80 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
80e5609c | 81 | |
b3c51170 YL |
82 | #ifdef CONFIG_X86_32 |
83 | /* | |
84 | * Knob to control our willingness to enable the local APIC. | |
85 | * | |
86 | * +1=force-enable | |
87 | */ | |
88 | static int force_enable_local_apic; | |
89 | /* | |
90 | * APIC command line parameters | |
91 | */ | |
92 | static int __init parse_lapic(char *arg) | |
93 | { | |
94 | force_enable_local_apic = 1; | |
95 | return 0; | |
96 | } | |
97 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
98 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
99 | static int enabled_via_apicbase; | |
100 | ||
c0eaa453 CG |
101 | /* |
102 | * Handle interrupt mode configuration register (IMCR). | |
103 | * This register controls whether the interrupt signals | |
104 | * that reach the BSP come from the master PIC or from the | |
105 | * local APIC. Before entering Symmetric I/O Mode, either | |
106 | * the BIOS or the operating system must switch out of | |
107 | * PIC Mode by changing the IMCR. | |
108 | */ | |
109 | static inline imcr_pic_to_apic(void) | |
110 | { | |
111 | /* select IMCR register */ | |
112 | outb(0x70, 0x22); | |
113 | /* NMI and 8259 INTR go through APIC */ | |
114 | outb(0x01, 0x23); | |
115 | } | |
116 | ||
117 | static inline imcr_apic_to_pic(void) | |
118 | { | |
119 | /* select IMCR register */ | |
120 | outb(0x70, 0x22); | |
121 | /* NMI and 8259 INTR go directly to BSP */ | |
122 | outb(0x00, 0x23); | |
123 | } | |
b3c51170 YL |
124 | #endif |
125 | ||
126 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 127 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
128 | static __init int setup_apicpmtimer(char *s) |
129 | { | |
130 | apic_calibrate_pmtmr = 1; | |
131 | notsc_setup(NULL); | |
132 | return 0; | |
133 | } | |
134 | __setup("apicpmtimer", setup_apicpmtimer); | |
135 | #endif | |
136 | ||
06cd9a7d | 137 | #ifdef CONFIG_X86_X2APIC |
89027d35 | 138 | int x2apic; |
6e1cb38a | 139 | /* x2apic enabled before OS handover */ |
b6b301aa JS |
140 | static int x2apic_preenabled; |
141 | static int disable_x2apic; | |
49899eac YL |
142 | static __init int setup_nox2apic(char *str) |
143 | { | |
144 | disable_x2apic = 1; | |
145 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
146 | return 0; | |
147 | } | |
148 | early_param("nox2apic", setup_nox2apic); | |
149 | #endif | |
1da177e4 | 150 | |
b3c51170 YL |
151 | unsigned long mp_lapic_addr; |
152 | int disable_apic; | |
153 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
154 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 155 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
156 | int local_apic_timer_c2_ok; |
157 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
158 | ||
efa2559f YL |
159 | int first_system_vector = 0xfe; |
160 | ||
e83a5fdc HS |
161 | /* |
162 | * Debug level, exported for io_apic.c | |
163 | */ | |
baa13188 | 164 | unsigned int apic_verbosity; |
e83a5fdc | 165 | |
89c38c28 CG |
166 | int pic_mode; |
167 | ||
bab4b27c AS |
168 | /* Have we found an MP table */ |
169 | int smp_found_config; | |
170 | ||
39928722 AD |
171 | static struct resource lapic_resource = { |
172 | .name = "Local APIC", | |
173 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
174 | }; | |
175 | ||
d03030e9 TG |
176 | static unsigned int calibration_result; |
177 | ||
ba7eda4c TG |
178 | static int lapic_next_event(unsigned long delta, |
179 | struct clock_event_device *evt); | |
180 | static void lapic_timer_setup(enum clock_event_mode mode, | |
181 | struct clock_event_device *evt); | |
9628937d | 182 | static void lapic_timer_broadcast(const struct cpumask *mask); |
0e078e2f | 183 | static void apic_pm_activate(void); |
ba7eda4c | 184 | |
274cfe59 CG |
185 | /* |
186 | * The local apic timer can be used for any function which is CPU local. | |
187 | */ | |
ba7eda4c TG |
188 | static struct clock_event_device lapic_clockevent = { |
189 | .name = "lapic", | |
190 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
191 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
192 | .shift = 32, | |
193 | .set_mode = lapic_timer_setup, | |
194 | .set_next_event = lapic_next_event, | |
195 | .broadcast = lapic_timer_broadcast, | |
196 | .rating = 100, | |
197 | .irq = -1, | |
198 | }; | |
199 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
200 | ||
d3432896 AK |
201 | static unsigned long apic_phys; |
202 | ||
0e078e2f TG |
203 | /* |
204 | * Get the LAPIC version | |
205 | */ | |
206 | static inline int lapic_get_version(void) | |
ba7eda4c | 207 | { |
0e078e2f | 208 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
209 | } |
210 | ||
0e078e2f | 211 | /* |
9c803869 | 212 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
213 | */ |
214 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 215 | { |
9c803869 | 216 | #ifdef CONFIG_X86_64 |
0e078e2f | 217 | return 1; |
9c803869 CG |
218 | #else |
219 | return APIC_INTEGRATED(lapic_get_version()); | |
220 | #endif | |
ba7eda4c TG |
221 | } |
222 | ||
223 | /* | |
0e078e2f | 224 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 225 | */ |
0e078e2f | 226 | static int modern_apic(void) |
ba7eda4c | 227 | { |
0e078e2f TG |
228 | /* AMD systems use old APIC versions, so check the CPU */ |
229 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
230 | boot_cpu_data.x86 >= 0xf) | |
231 | return 1; | |
232 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
233 | } |
234 | ||
c1eeb2de | 235 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
236 | { |
237 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
238 | cpu_relax(); | |
239 | } | |
240 | ||
c1eeb2de | 241 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 242 | { |
3c6bb07a | 243 | u32 send_status; |
8339e9fb FLV |
244 | int timeout; |
245 | ||
246 | timeout = 0; | |
247 | do { | |
248 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
249 | if (!send_status) | |
250 | break; | |
251 | udelay(100); | |
252 | } while (timeout++ < 1000); | |
253 | ||
254 | return send_status; | |
255 | } | |
256 | ||
c1eeb2de | 257 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 258 | { |
ed4e5ec1 | 259 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
260 | apic_write(APIC_ICR, low); |
261 | } | |
262 | ||
c1eeb2de | 263 | u64 native_apic_icr_read(void) |
1b374e4d SS |
264 | { |
265 | u32 icr1, icr2; | |
266 | ||
267 | icr2 = apic_read(APIC_ICR2); | |
268 | icr1 = apic_read(APIC_ICR); | |
269 | ||
cf9768d7 | 270 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
271 | } |
272 | ||
0e078e2f TG |
273 | /** |
274 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
275 | */ | |
e9427101 | 276 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 277 | { |
11a8e778 | 278 | unsigned int v; |
6935d1f9 TG |
279 | |
280 | /* unmask and set to NMI */ | |
281 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
282 | |
283 | /* Level triggered for 82489DX (32bit mode) */ | |
284 | if (!lapic_is_integrated()) | |
285 | v |= APIC_LVT_LEVEL_TRIGGER; | |
286 | ||
11a8e778 | 287 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
288 | } |
289 | ||
7c37e48b CG |
290 | #ifdef CONFIG_X86_32 |
291 | /** | |
292 | * get_physical_broadcast - Get number of physical broadcast IDs | |
293 | */ | |
294 | int get_physical_broadcast(void) | |
295 | { | |
296 | return modern_apic() ? 0xff : 0xf; | |
297 | } | |
298 | #endif | |
299 | ||
0e078e2f TG |
300 | /** |
301 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
302 | */ | |
37e650c7 | 303 | int lapic_get_maxlvt(void) |
1da177e4 | 304 | { |
36a028de | 305 | unsigned int v; |
1da177e4 LT |
306 | |
307 | v = apic_read(APIC_LVR); | |
36a028de CG |
308 | /* |
309 | * - we always have APIC integrated on 64bit mode | |
310 | * - 82489DXs do not report # of LVT entries | |
311 | */ | |
312 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
313 | } |
314 | ||
274cfe59 CG |
315 | /* |
316 | * Local APIC timer | |
317 | */ | |
318 | ||
c40aaec6 | 319 | /* Clock divisor */ |
c40aaec6 | 320 | #define APIC_DIVISOR 16 |
f07f4f90 | 321 | |
0e078e2f TG |
322 | /* |
323 | * This function sets up the local APIC timer, with a timeout of | |
324 | * 'clocks' APIC bus clock. During calibration we actually call | |
325 | * this function twice on the boot CPU, once with a bogus timeout | |
326 | * value, second time for real. The other (noncalibrating) CPUs | |
327 | * call this function only once, with the real, calibrated value. | |
328 | * | |
329 | * We do reads before writes even if unnecessary, to get around the | |
330 | * P5 APIC double write bug. | |
331 | */ | |
0e078e2f | 332 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 333 | { |
0e078e2f | 334 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 335 | |
0e078e2f TG |
336 | lvtt_value = LOCAL_TIMER_VECTOR; |
337 | if (!oneshot) | |
338 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
339 | if (!lapic_is_integrated()) |
340 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
341 | ||
0e078e2f TG |
342 | if (!irqen) |
343 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 344 | |
0e078e2f | 345 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
346 | |
347 | /* | |
0e078e2f | 348 | * Divide PICLK by 16 |
1da177e4 | 349 | */ |
0e078e2f | 350 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
351 | apic_write(APIC_TDCR, |
352 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
353 | APIC_TDR_DIV_16); | |
0e078e2f TG |
354 | |
355 | if (!oneshot) | |
f07f4f90 | 356 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
357 | } |
358 | ||
0e078e2f | 359 | /* |
7b83dae7 RR |
360 | * Setup extended LVT, AMD specific (K8, family 10h) |
361 | * | |
362 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
363 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
364 | * |
365 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
366 | * enables the vector. See also the BKDGs. | |
0e078e2f | 367 | */ |
7b83dae7 RR |
368 | |
369 | #define APIC_EILVT_LVTOFF_MCE 0 | |
370 | #define APIC_EILVT_LVTOFF_IBS 1 | |
371 | ||
372 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 373 | { |
7b83dae7 | 374 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 375 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 376 | |
0e078e2f | 377 | apic_write(reg, v); |
1da177e4 LT |
378 | } |
379 | ||
7b83dae7 RR |
380 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
381 | { | |
382 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
383 | return APIC_EILVT_LVTOFF_MCE; | |
384 | } | |
385 | ||
386 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
387 | { | |
388 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
389 | return APIC_EILVT_LVTOFF_IBS; | |
390 | } | |
6aa360e6 | 391 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 392 | |
0e078e2f TG |
393 | /* |
394 | * Program the next event, relative to now | |
395 | */ | |
396 | static int lapic_next_event(unsigned long delta, | |
397 | struct clock_event_device *evt) | |
1da177e4 | 398 | { |
0e078e2f TG |
399 | apic_write(APIC_TMICT, delta); |
400 | return 0; | |
1da177e4 LT |
401 | } |
402 | ||
0e078e2f TG |
403 | /* |
404 | * Setup the lapic timer in periodic or oneshot mode | |
405 | */ | |
406 | static void lapic_timer_setup(enum clock_event_mode mode, | |
407 | struct clock_event_device *evt) | |
9b7711f0 HS |
408 | { |
409 | unsigned long flags; | |
0e078e2f | 410 | unsigned int v; |
9b7711f0 | 411 | |
0e078e2f TG |
412 | /* Lapic used as dummy for broadcast ? */ |
413 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
414 | return; |
415 | ||
416 | local_irq_save(flags); | |
417 | ||
0e078e2f TG |
418 | switch (mode) { |
419 | case CLOCK_EVT_MODE_PERIODIC: | |
420 | case CLOCK_EVT_MODE_ONESHOT: | |
421 | __setup_APIC_LVTT(calibration_result, | |
422 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
423 | break; | |
424 | case CLOCK_EVT_MODE_UNUSED: | |
425 | case CLOCK_EVT_MODE_SHUTDOWN: | |
426 | v = apic_read(APIC_LVTT); | |
427 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
428 | apic_write(APIC_LVTT, v); | |
a98f8fd2 | 429 | apic_write(APIC_TMICT, 0xffffffff); |
0e078e2f TG |
430 | break; |
431 | case CLOCK_EVT_MODE_RESUME: | |
432 | /* Nothing to do here */ | |
433 | break; | |
434 | } | |
9b7711f0 HS |
435 | |
436 | local_irq_restore(flags); | |
437 | } | |
438 | ||
1da177e4 | 439 | /* |
0e078e2f | 440 | * Local APIC timer broadcast function |
1da177e4 | 441 | */ |
9628937d | 442 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 443 | { |
0e078e2f | 444 | #ifdef CONFIG_SMP |
dac5f412 | 445 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
446 | #endif |
447 | } | |
1da177e4 | 448 | |
0e078e2f TG |
449 | /* |
450 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
451 | * of the boot CPU and register the clock event in the framework. | |
452 | */ | |
db4b5525 | 453 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
454 | { |
455 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 456 | |
0e078e2f | 457 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 458 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 459 | |
0e078e2f TG |
460 | clockevents_register_device(levt); |
461 | } | |
1da177e4 | 462 | |
2f04fa88 YL |
463 | /* |
464 | * In this functions we calibrate APIC bus clocks to the external timer. | |
465 | * | |
466 | * We want to do the calibration only once since we want to have local timer | |
467 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
468 | * frequency. | |
469 | * | |
470 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
471 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
472 | * readout is broken, so it never gets out of the wait loop again. This was | |
473 | * also reported by others. | |
474 | * | |
475 | * Monitoring the jiffies value is inaccurate and the clockevents | |
476 | * infrastructure allows us to do a simple substitution of the interrupt | |
477 | * handler. | |
478 | * | |
479 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
480 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
481 | * back to normal later in the boot process). | |
482 | */ | |
483 | ||
484 | #define LAPIC_CAL_LOOPS (HZ/10) | |
485 | ||
486 | static __initdata int lapic_cal_loops = -1; | |
487 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
488 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
489 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
490 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
491 | ||
492 | /* | |
493 | * Temporary interrupt handler. | |
494 | */ | |
495 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
496 | { | |
497 | unsigned long long tsc = 0; | |
498 | long tapic = apic_read(APIC_TMCCT); | |
499 | unsigned long pm = acpi_pm_read_early(); | |
500 | ||
501 | if (cpu_has_tsc) | |
502 | rdtscll(tsc); | |
503 | ||
504 | switch (lapic_cal_loops++) { | |
505 | case 0: | |
506 | lapic_cal_t1 = tapic; | |
507 | lapic_cal_tsc1 = tsc; | |
508 | lapic_cal_pm1 = pm; | |
509 | lapic_cal_j1 = jiffies; | |
510 | break; | |
511 | ||
512 | case LAPIC_CAL_LOOPS: | |
513 | lapic_cal_t2 = tapic; | |
514 | lapic_cal_tsc2 = tsc; | |
515 | if (pm < lapic_cal_pm1) | |
516 | pm += ACPI_PM_OVRRUN; | |
517 | lapic_cal_pm2 = pm; | |
518 | lapic_cal_j2 = jiffies; | |
519 | break; | |
520 | } | |
521 | } | |
522 | ||
754ef0cd YI |
523 | static int __init |
524 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
525 | { |
526 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
527 | const long pm_thresh = pm_100ms / 100; | |
528 | unsigned long mult; | |
529 | u64 res; | |
530 | ||
531 | #ifndef CONFIG_X86_PM_TIMER | |
532 | return -1; | |
533 | #endif | |
534 | ||
39ba5d43 | 535 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
536 | |
537 | /* Check, if the PM timer is available */ | |
538 | if (!deltapm) | |
539 | return -1; | |
540 | ||
541 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
542 | ||
543 | if (deltapm > (pm_100ms - pm_thresh) && | |
544 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 545 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
546 | return 0; |
547 | } | |
548 | ||
549 | res = (((u64)deltapm) * mult) >> 22; | |
550 | do_div(res, 1000000); | |
551 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 552 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
553 | |
554 | /* Correct the lapic counter value */ | |
555 | res = (((u64)(*delta)) * pm_100ms); | |
556 | do_div(res, deltapm); | |
557 | pr_info("APIC delta adjusted to PM-Timer: " | |
558 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
559 | *delta = (long)res; | |
560 | ||
561 | /* Correct the tsc counter value */ | |
562 | if (cpu_has_tsc) { | |
563 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 564 | do_div(res, deltapm); |
754ef0cd YI |
565 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
566 | "PM-Timer: %lu (%ld) \n", | |
567 | (unsigned long)res, *deltatsc); | |
568 | *deltatsc = (long)res; | |
b189892d CG |
569 | } |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
2f04fa88 YL |
574 | static int __init calibrate_APIC_clock(void) |
575 | { | |
576 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
577 | void (*real_handler)(struct clock_event_device *dev); |
578 | unsigned long deltaj; | |
754ef0cd | 579 | long delta, deltatsc; |
2f04fa88 YL |
580 | int pm_referenced = 0; |
581 | ||
582 | local_irq_disable(); | |
583 | ||
584 | /* Replace the global interrupt handler */ | |
585 | real_handler = global_clock_event->event_handler; | |
586 | global_clock_event->event_handler = lapic_cal_handler; | |
587 | ||
588 | /* | |
81608f3c | 589 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
590 | * can underflow in the 100ms detection time frame |
591 | */ | |
81608f3c | 592 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
593 | |
594 | /* Let the interrupts run */ | |
595 | local_irq_enable(); | |
596 | ||
597 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
598 | cpu_relax(); | |
599 | ||
600 | local_irq_disable(); | |
601 | ||
602 | /* Restore the real event handler */ | |
603 | global_clock_event->event_handler = real_handler; | |
604 | ||
605 | /* Build delta t1-t2 as apic timer counts down */ | |
606 | delta = lapic_cal_t1 - lapic_cal_t2; | |
607 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
608 | ||
754ef0cd YI |
609 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
610 | ||
b189892d CG |
611 | /* we trust the PM based calibration if possible */ |
612 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 613 | &delta, &deltatsc); |
2f04fa88 YL |
614 | |
615 | /* Calculate the scaled math multiplication factor */ | |
616 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
617 | lapic_clockevent.shift); | |
618 | lapic_clockevent.max_delta_ns = | |
619 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
620 | lapic_clockevent.min_delta_ns = | |
621 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
622 | ||
623 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
624 | ||
625 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
626 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); | |
627 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", | |
628 | calibration_result); | |
629 | ||
630 | if (cpu_has_tsc) { | |
2f04fa88 YL |
631 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
632 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
633 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
634 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
635 | } |
636 | ||
637 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
638 | "%u.%04u MHz.\n", | |
639 | calibration_result / (1000000 / HZ), | |
640 | calibration_result % (1000000 / HZ)); | |
641 | ||
642 | /* | |
643 | * Do a sanity check on the APIC calibration result | |
644 | */ | |
645 | if (calibration_result < (1000000 / HZ)) { | |
646 | local_irq_enable(); | |
ba21ebb6 | 647 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
648 | return -1; |
649 | } | |
650 | ||
651 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
652 | ||
b189892d CG |
653 | /* |
654 | * PM timer calibration failed or not turned on | |
655 | * so lets try APIC timer based calibration | |
656 | */ | |
2f04fa88 YL |
657 | if (!pm_referenced) { |
658 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
659 | ||
660 | /* | |
661 | * Setup the apic timer manually | |
662 | */ | |
663 | levt->event_handler = lapic_cal_handler; | |
664 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
665 | lapic_cal_loops = -1; | |
666 | ||
667 | /* Let the interrupts run */ | |
668 | local_irq_enable(); | |
669 | ||
670 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
671 | cpu_relax(); | |
672 | ||
2f04fa88 YL |
673 | /* Stop the lapic timer */ |
674 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
675 | ||
2f04fa88 YL |
676 | /* Jiffies delta */ |
677 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
678 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
679 | ||
680 | /* Check, if the jiffies result is consistent */ | |
681 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
682 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
683 | else | |
684 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
685 | } else | |
686 | local_irq_enable(); | |
687 | ||
688 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 689 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
690 | return -1; |
691 | } | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
e83a5fdc HS |
696 | /* |
697 | * Setup the boot APIC | |
698 | * | |
699 | * Calibrate and verify the result. | |
700 | */ | |
0e078e2f TG |
701 | void __init setup_boot_APIC_clock(void) |
702 | { | |
703 | /* | |
274cfe59 CG |
704 | * The local apic timer can be disabled via the kernel |
705 | * commandline or from the CPU detection code. Register the lapic | |
706 | * timer as a dummy clock event source on SMP systems, so the | |
707 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
708 | */ |
709 | if (disable_apic_timer) { | |
ba21ebb6 | 710 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 711 | /* No broadcast on UP ! */ |
9d09951d TG |
712 | if (num_possible_cpus() > 1) { |
713 | lapic_clockevent.mult = 1; | |
0e078e2f | 714 | setup_APIC_timer(); |
9d09951d | 715 | } |
0e078e2f TG |
716 | return; |
717 | } | |
718 | ||
274cfe59 CG |
719 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
720 | "calibrating APIC timer ...\n"); | |
721 | ||
89b3b1f4 | 722 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
723 | /* No broadcast on UP ! */ |
724 | if (num_possible_cpus() > 1) | |
725 | setup_APIC_timer(); | |
726 | return; | |
727 | } | |
728 | ||
0e078e2f TG |
729 | /* |
730 | * If nmi_watchdog is set to IO_APIC, we need the | |
731 | * PIT/HPET going. Otherwise register lapic as a dummy | |
732 | * device. | |
733 | */ | |
734 | if (nmi_watchdog != NMI_IO_APIC) | |
735 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
736 | else | |
ba21ebb6 | 737 | pr_warning("APIC timer registered as dummy," |
116f570e | 738 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 739 | |
274cfe59 | 740 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
741 | setup_APIC_timer(); |
742 | } | |
743 | ||
0e078e2f TG |
744 | void __cpuinit setup_secondary_APIC_clock(void) |
745 | { | |
0e078e2f TG |
746 | setup_APIC_timer(); |
747 | } | |
748 | ||
749 | /* | |
750 | * The guts of the apic timer interrupt | |
751 | */ | |
752 | static void local_apic_timer_interrupt(void) | |
753 | { | |
754 | int cpu = smp_processor_id(); | |
755 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
756 | ||
757 | /* | |
758 | * Normally we should not be here till LAPIC has been initialized but | |
759 | * in some cases like kdump, its possible that there is a pending LAPIC | |
760 | * timer interrupt from previous kernel's context and is delivered in | |
761 | * new kernel the moment interrupts are enabled. | |
762 | * | |
763 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
764 | * its possible that when we get here evt->event_handler is NULL. | |
765 | * Check for event_handler being NULL and discard the interrupt as | |
766 | * spurious. | |
767 | */ | |
768 | if (!evt->event_handler) { | |
ba21ebb6 | 769 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
770 | /* Switch it off */ |
771 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
772 | return; | |
773 | } | |
774 | ||
775 | /* | |
776 | * the NMI deadlock-detector uses this. | |
777 | */ | |
915b0d01 | 778 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
779 | |
780 | evt->event_handler(evt); | |
781 | } | |
782 | ||
783 | /* | |
784 | * Local APIC timer interrupt. This is the most natural way for doing | |
785 | * local interrupts, but local timer interrupts can be emulated by | |
786 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
787 | * | |
788 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
789 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
790 | */ | |
bcbc4f20 | 791 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
792 | { |
793 | struct pt_regs *old_regs = set_irq_regs(regs); | |
794 | ||
795 | /* | |
796 | * NOTE! We'd better ACK the irq immediately, | |
797 | * because timer handling can be slow. | |
798 | */ | |
799 | ack_APIC_irq(); | |
800 | /* | |
801 | * update_process_times() expects us to have done irq_enter(). | |
802 | * Besides, if we don't timer interrupts ignore the global | |
803 | * interrupt lock, which is the WrongThing (tm) to do. | |
804 | */ | |
805 | exit_idle(); | |
806 | irq_enter(); | |
807 | local_apic_timer_interrupt(); | |
808 | irq_exit(); | |
274cfe59 | 809 | |
0e078e2f TG |
810 | set_irq_regs(old_regs); |
811 | } | |
812 | ||
813 | int setup_profiling_timer(unsigned int multiplier) | |
814 | { | |
815 | return -EINVAL; | |
816 | } | |
817 | ||
0e078e2f TG |
818 | /* |
819 | * Local APIC start and shutdown | |
820 | */ | |
821 | ||
822 | /** | |
823 | * clear_local_APIC - shutdown the local APIC | |
824 | * | |
825 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
826 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
827 | * leftovers during boot. | |
828 | */ | |
829 | void clear_local_APIC(void) | |
830 | { | |
2584a82d | 831 | int maxlvt; |
0e078e2f TG |
832 | u32 v; |
833 | ||
d3432896 | 834 | /* APIC hasn't been mapped yet */ |
cf6567fe | 835 | if (!x2apic && !apic_phys) |
d3432896 AK |
836 | return; |
837 | ||
838 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
839 | /* |
840 | * Masking an LVT entry can trigger a local APIC error | |
841 | * if the vector is zero. Mask LVTERR first to prevent this. | |
842 | */ | |
843 | if (maxlvt >= 3) { | |
844 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
845 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
846 | } | |
847 | /* | |
848 | * Careful: we have to set masks only first to deassert | |
849 | * any level-triggered sources. | |
850 | */ | |
851 | v = apic_read(APIC_LVTT); | |
852 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
853 | v = apic_read(APIC_LVT0); | |
854 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
855 | v = apic_read(APIC_LVT1); | |
856 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
857 | if (maxlvt >= 4) { | |
858 | v = apic_read(APIC_LVTPC); | |
859 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
860 | } | |
861 | ||
6764014b | 862 | /* lets not touch this if we didn't frob it */ |
07db1c14 | 863 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
6764014b CG |
864 | if (maxlvt >= 5) { |
865 | v = apic_read(APIC_LVTTHMR); | |
866 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
867 | } | |
868 | #endif | |
5ca8681c AK |
869 | #ifdef CONFIG_X86_MCE_INTEL |
870 | if (maxlvt >= 6) { | |
871 | v = apic_read(APIC_LVTCMCI); | |
872 | if (!(v & APIC_LVT_MASKED)) | |
873 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
874 | } | |
875 | #endif | |
876 | ||
0e078e2f TG |
877 | /* |
878 | * Clean APIC state for other OSs: | |
879 | */ | |
880 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
881 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
882 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
883 | if (maxlvt >= 3) | |
884 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
885 | if (maxlvt >= 4) | |
886 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
887 | |
888 | /* Integrated APIC (!82489DX) ? */ | |
889 | if (lapic_is_integrated()) { | |
890 | if (maxlvt > 3) | |
891 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
892 | apic_write(APIC_ESR, 0); | |
893 | apic_read(APIC_ESR); | |
894 | } | |
0e078e2f TG |
895 | } |
896 | ||
897 | /** | |
898 | * disable_local_APIC - clear and disable the local APIC | |
899 | */ | |
900 | void disable_local_APIC(void) | |
901 | { | |
902 | unsigned int value; | |
903 | ||
4a13ad0b JB |
904 | /* APIC hasn't been mapped yet */ |
905 | if (!apic_phys) | |
906 | return; | |
907 | ||
0e078e2f TG |
908 | clear_local_APIC(); |
909 | ||
910 | /* | |
911 | * Disable APIC (implies clearing of registers | |
912 | * for 82489DX!). | |
913 | */ | |
914 | value = apic_read(APIC_SPIV); | |
915 | value &= ~APIC_SPIV_APIC_ENABLED; | |
916 | apic_write(APIC_SPIV, value); | |
990b183e CG |
917 | |
918 | #ifdef CONFIG_X86_32 | |
919 | /* | |
920 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
921 | * restore the disabled state. | |
922 | */ | |
923 | if (enabled_via_apicbase) { | |
924 | unsigned int l, h; | |
925 | ||
926 | rdmsr(MSR_IA32_APICBASE, l, h); | |
927 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
928 | wrmsr(MSR_IA32_APICBASE, l, h); | |
929 | } | |
930 | #endif | |
0e078e2f TG |
931 | } |
932 | ||
fe4024dc CG |
933 | /* |
934 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
935 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
936 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
937 | * for the case where Linux didn't enable the LAPIC. | |
938 | */ | |
0e078e2f TG |
939 | void lapic_shutdown(void) |
940 | { | |
941 | unsigned long flags; | |
942 | ||
943 | if (!cpu_has_apic) | |
944 | return; | |
945 | ||
946 | local_irq_save(flags); | |
947 | ||
fe4024dc CG |
948 | #ifdef CONFIG_X86_32 |
949 | if (!enabled_via_apicbase) | |
950 | clear_local_APIC(); | |
951 | else | |
952 | #endif | |
953 | disable_local_APIC(); | |
954 | ||
0e078e2f TG |
955 | |
956 | local_irq_restore(flags); | |
957 | } | |
958 | ||
959 | /* | |
960 | * This is to verify that we're looking at a real local APIC. | |
961 | * Check these against your board if the CPUs aren't getting | |
962 | * started for no apparent reason. | |
963 | */ | |
964 | int __init verify_local_APIC(void) | |
965 | { | |
966 | unsigned int reg0, reg1; | |
967 | ||
968 | /* | |
969 | * The version register is read-only in a real APIC. | |
970 | */ | |
971 | reg0 = apic_read(APIC_LVR); | |
972 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
973 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
974 | reg1 = apic_read(APIC_LVR); | |
975 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
976 | ||
977 | /* | |
978 | * The two version reads above should print the same | |
979 | * numbers. If the second one is different, then we | |
980 | * poke at a non-APIC. | |
981 | */ | |
982 | if (reg1 != reg0) | |
983 | return 0; | |
984 | ||
985 | /* | |
986 | * Check if the version looks reasonably. | |
987 | */ | |
988 | reg1 = GET_APIC_VERSION(reg0); | |
989 | if (reg1 == 0x00 || reg1 == 0xff) | |
990 | return 0; | |
991 | reg1 = lapic_get_maxlvt(); | |
992 | if (reg1 < 0x02 || reg1 == 0xff) | |
993 | return 0; | |
994 | ||
995 | /* | |
996 | * The ID register is read/write in a real APIC. | |
997 | */ | |
2d7a66d0 | 998 | reg0 = apic_read(APIC_ID); |
0e078e2f | 999 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
5b812727 | 1000 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
2d7a66d0 | 1001 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1002 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1003 | apic_write(APIC_ID, reg0); | |
5b812727 | 1004 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
0e078e2f TG |
1005 | return 0; |
1006 | ||
1007 | /* | |
1da177e4 LT |
1008 | * The next two are just to see if we have sane values. |
1009 | * They're only really relevant if we're in Virtual Wire | |
1010 | * compatibility mode, but most boxes are anymore. | |
1011 | */ | |
1012 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1013 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1014 | reg1 = apic_read(APIC_LVT1); |
1015 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1016 | ||
1017 | return 1; | |
1018 | } | |
1019 | ||
0e078e2f TG |
1020 | /** |
1021 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1022 | */ | |
1da177e4 LT |
1023 | void __init sync_Arb_IDs(void) |
1024 | { | |
296cb951 CG |
1025 | /* |
1026 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1027 | * needed on AMD. | |
1028 | */ | |
1029 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1030 | return; |
1031 | ||
1032 | /* | |
1033 | * Wait for idle. | |
1034 | */ | |
1035 | apic_wait_icr_idle(); | |
1036 | ||
1037 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1038 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1039 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1040 | } |
1041 | ||
1da177e4 LT |
1042 | /* |
1043 | * An initial setup of the virtual wire mode. | |
1044 | */ | |
1045 | void __init init_bsp_APIC(void) | |
1046 | { | |
11a8e778 | 1047 | unsigned int value; |
1da177e4 LT |
1048 | |
1049 | /* | |
1050 | * Don't do the setup now if we have a SMP BIOS as the | |
1051 | * through-I/O-APIC virtual wire mode might be active. | |
1052 | */ | |
1053 | if (smp_found_config || !cpu_has_apic) | |
1054 | return; | |
1055 | ||
1da177e4 LT |
1056 | /* |
1057 | * Do not trust the local APIC being empty at bootup. | |
1058 | */ | |
1059 | clear_local_APIC(); | |
1060 | ||
1061 | /* | |
1062 | * Enable APIC. | |
1063 | */ | |
1064 | value = apic_read(APIC_SPIV); | |
1065 | value &= ~APIC_VECTOR_MASK; | |
1066 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1067 | |
1068 | #ifdef CONFIG_X86_32 | |
1069 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1070 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1071 | (boot_cpu_data.x86 == 15)) | |
1072 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1073 | else | |
1074 | #endif | |
1075 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1076 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1077 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1078 | |
1079 | /* | |
1080 | * Set up the virtual wire mode. | |
1081 | */ | |
11a8e778 | 1082 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1083 | value = APIC_DM_NMI; |
638c0411 CG |
1084 | if (!lapic_is_integrated()) /* 82489DX */ |
1085 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1086 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1087 | } |
1088 | ||
c43da2f5 CG |
1089 | static void __cpuinit lapic_setup_esr(void) |
1090 | { | |
9df08f10 CG |
1091 | unsigned int oldvalue, value, maxlvt; |
1092 | ||
1093 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1094 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1095 | return; |
1096 | } | |
c43da2f5 | 1097 | |
08125d3e | 1098 | if (apic->disable_esr) { |
c43da2f5 | 1099 | /* |
9df08f10 CG |
1100 | * Something untraceable is creating bad interrupts on |
1101 | * secondary quads ... for the moment, just leave the | |
1102 | * ESR disabled - we can't do anything useful with the | |
1103 | * errors anyway - mbligh | |
c43da2f5 | 1104 | */ |
ba21ebb6 | 1105 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1106 | return; |
c43da2f5 | 1107 | } |
9df08f10 CG |
1108 | |
1109 | maxlvt = lapic_get_maxlvt(); | |
1110 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1111 | apic_write(APIC_ESR, 0); | |
1112 | oldvalue = apic_read(APIC_ESR); | |
1113 | ||
1114 | /* enables sending errors */ | |
1115 | value = ERROR_APIC_VECTOR; | |
1116 | apic_write(APIC_LVTERR, value); | |
1117 | ||
1118 | /* | |
1119 | * spec says clear errors after enabling vector. | |
1120 | */ | |
1121 | if (maxlvt > 3) | |
1122 | apic_write(APIC_ESR, 0); | |
1123 | value = apic_read(APIC_ESR); | |
1124 | if (value != oldvalue) | |
1125 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1126 | "vector: 0x%08x after: 0x%08x\n", | |
1127 | oldvalue, value); | |
c43da2f5 CG |
1128 | } |
1129 | ||
1130 | ||
0e078e2f TG |
1131 | /** |
1132 | * setup_local_APIC - setup the local APIC | |
1133 | */ | |
1134 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1135 | { |
739f33b3 | 1136 | unsigned int value; |
da7ed9f9 | 1137 | int i, j; |
1da177e4 | 1138 | |
f1182638 | 1139 | if (disable_apic) { |
65a4e574 | 1140 | arch_disable_smp_support(); |
f1182638 JB |
1141 | return; |
1142 | } | |
1143 | ||
89c38c28 CG |
1144 | #ifdef CONFIG_X86_32 |
1145 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1146 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1147 | apic_write(APIC_ESR, 0); |
1148 | apic_write(APIC_ESR, 0); | |
1149 | apic_write(APIC_ESR, 0); | |
1150 | apic_write(APIC_ESR, 0); | |
1151 | } | |
1152 | #endif | |
1153 | ||
ac23d4ee | 1154 | preempt_disable(); |
1da177e4 | 1155 | |
1da177e4 LT |
1156 | /* |
1157 | * Double-check whether this APIC is really registered. | |
1158 | * This is meaningless in clustered apic mode, so we skip it. | |
1159 | */ | |
7ed248da | 1160 | if (!apic->apic_id_registered()) |
1da177e4 LT |
1161 | BUG(); |
1162 | ||
1163 | /* | |
1164 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1165 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1166 | * document number 292116). So here it goes... | |
1167 | */ | |
a5c43296 | 1168 | apic->init_apic_ldr(); |
1da177e4 LT |
1169 | |
1170 | /* | |
1171 | * Set Task Priority to 'accept all'. We never change this | |
1172 | * later on. | |
1173 | */ | |
1174 | value = apic_read(APIC_TASKPRI); | |
1175 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1176 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1177 | |
da7ed9f9 VG |
1178 | /* |
1179 | * After a crash, we no longer service the interrupts and a pending | |
1180 | * interrupt from previous kernel might still have ISR bit set. | |
1181 | * | |
1182 | * Most probably by now CPU has serviced that pending interrupt and | |
1183 | * it might not have done the ack_APIC_irq() because it thought, | |
1184 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1185 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1186 | * the interrupt. Hence a vector might get locked. It was noticed | |
1187 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1188 | */ | |
1189 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1190 | value = apic_read(APIC_ISR + i*0x10); | |
1191 | for (j = 31; j >= 0; j--) { | |
1192 | if (value & (1<<j)) | |
1193 | ack_APIC_irq(); | |
1194 | } | |
1195 | } | |
1196 | ||
1da177e4 LT |
1197 | /* |
1198 | * Now that we are all set up, enable the APIC | |
1199 | */ | |
1200 | value = apic_read(APIC_SPIV); | |
1201 | value &= ~APIC_VECTOR_MASK; | |
1202 | /* | |
1203 | * Enable APIC | |
1204 | */ | |
1205 | value |= APIC_SPIV_APIC_ENABLED; | |
1206 | ||
89c38c28 CG |
1207 | #ifdef CONFIG_X86_32 |
1208 | /* | |
1209 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1210 | * certain networking cards. If high frequency interrupts are | |
1211 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1212 | * entry is masked/unmasked at a high rate as well then sooner or | |
1213 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1214 | * from the device. If focus CPU is disabled then the hang goes | |
1215 | * away, oh well :-( | |
1216 | * | |
1217 | * [ This bug can be reproduced easily with a level-triggered | |
1218 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1219 | * BX chipset. ] | |
1220 | */ | |
1221 | /* | |
1222 | * Actually disabling the focus CPU check just makes the hang less | |
1223 | * frequent as it makes the interrupt distributon model be more | |
1224 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1225 | * See also the comment in end_level_ioapic_irq(). --macro | |
1226 | */ | |
1227 | ||
1228 | /* | |
1229 | * - enable focus processor (bit==0) | |
1230 | * - 64bit mode always use processor focus | |
1231 | * so no need to set it | |
1232 | */ | |
1233 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1234 | #endif | |
3f14c746 | 1235 | |
1da177e4 LT |
1236 | /* |
1237 | * Set spurious IRQ vector | |
1238 | */ | |
1239 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1240 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1241 | |
1242 | /* | |
1243 | * Set up LVT0, LVT1: | |
1244 | * | |
1245 | * set up through-local-APIC on the BP's LINT0. This is not | |
1246 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1247 | * we delegate interrupts to the 8259A. | |
1248 | */ | |
1249 | /* | |
1250 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1251 | */ | |
1252 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1253 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1254 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1255 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1256 | smp_processor_id()); |
1da177e4 LT |
1257 | } else { |
1258 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1259 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1260 | smp_processor_id()); |
1da177e4 | 1261 | } |
11a8e778 | 1262 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1263 | |
1264 | /* | |
1265 | * only the BP should see the LINT1 NMI signal, obviously. | |
1266 | */ | |
1267 | if (!smp_processor_id()) | |
1268 | value = APIC_DM_NMI; | |
1269 | else | |
1270 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1271 | if (!lapic_is_integrated()) /* 82489DX */ |
1272 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1273 | apic_write(APIC_LVT1, value); |
89c38c28 | 1274 | |
ac23d4ee | 1275 | preempt_enable(); |
be71b855 AK |
1276 | |
1277 | #ifdef CONFIG_X86_MCE_INTEL | |
1278 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
1279 | if (smp_processor_id() == 0) | |
1280 | cmci_recheck(); | |
1281 | #endif | |
739f33b3 | 1282 | } |
1da177e4 | 1283 | |
739f33b3 AK |
1284 | void __cpuinit end_local_APIC_setup(void) |
1285 | { | |
1286 | lapic_setup_esr(); | |
fa6b95fc CG |
1287 | |
1288 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1289 | { |
1290 | unsigned int value; | |
1291 | /* Disable the local apic timer */ | |
1292 | value = apic_read(APIC_LVTT); | |
1293 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1294 | apic_write(APIC_LVTT, value); | |
1295 | } | |
fa6b95fc CG |
1296 | #endif |
1297 | ||
f2802e7f | 1298 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1299 | apic_pm_activate(); |
1da177e4 | 1300 | } |
1da177e4 | 1301 | |
06cd9a7d | 1302 | #ifdef CONFIG_X86_X2APIC |
6e1cb38a SS |
1303 | void check_x2apic(void) |
1304 | { | |
ef1f87aa | 1305 | if (x2apic_enabled()) { |
ba21ebb6 | 1306 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
6e1cb38a | 1307 | x2apic_preenabled = x2apic = 1; |
6e1cb38a SS |
1308 | } |
1309 | } | |
1310 | ||
1311 | void enable_x2apic(void) | |
1312 | { | |
1313 | int msr, msr2; | |
1314 | ||
06cd9a7d YL |
1315 | if (!x2apic) |
1316 | return; | |
1317 | ||
6e1cb38a SS |
1318 | rdmsr(MSR_IA32_APICBASE, msr, msr2); |
1319 | if (!(msr & X2APIC_ENABLE)) { | |
ba21ebb6 | 1320 | pr_info("Enabling x2apic\n"); |
6e1cb38a SS |
1321 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1322 | } | |
1323 | } | |
1324 | ||
2236d252 | 1325 | void __init enable_IR_x2apic(void) |
6e1cb38a SS |
1326 | { |
1327 | #ifdef CONFIG_INTR_REMAP | |
1328 | int ret; | |
1329 | unsigned long flags; | |
b24696bc | 1330 | struct IO_APIC_route_entry **ioapic_entries = NULL; |
6e1cb38a SS |
1331 | |
1332 | if (!cpu_has_x2apic) | |
1333 | return; | |
1334 | ||
1335 | if (!x2apic_preenabled && disable_x2apic) { | |
ba21ebb6 CG |
1336 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1337 | "because of nox2apic\n"); | |
6e1cb38a SS |
1338 | return; |
1339 | } | |
1340 | ||
1341 | if (x2apic_preenabled && disable_x2apic) | |
1342 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1343 | ||
1344 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
ba21ebb6 CG |
1345 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1346 | "because of skipping io-apic setup\n"); | |
6e1cb38a SS |
1347 | return; |
1348 | } | |
1349 | ||
1350 | ret = dmar_table_init(); | |
1351 | if (ret) { | |
ba21ebb6 | 1352 | pr_info("dmar_table_init() failed with %d:\n", ret); |
6e1cb38a SS |
1353 | |
1354 | if (x2apic_preenabled) | |
1355 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1356 | else | |
ba21ebb6 | 1357 | pr_info("Not enabling x2apic,Intr-remapping\n"); |
6e1cb38a SS |
1358 | return; |
1359 | } | |
1360 | ||
b24696bc FY |
1361 | ioapic_entries = alloc_ioapic_entries(); |
1362 | if (!ioapic_entries) { | |
1363 | pr_info("Allocate ioapic_entries failed: %d\n", ret); | |
1364 | goto end; | |
1365 | } | |
1366 | ||
1367 | ret = save_IO_APIC_setup(ioapic_entries); | |
5ffa4eb2 | 1368 | if (ret) { |
ba21ebb6 | 1369 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
5ffa4eb2 CG |
1370 | goto end; |
1371 | } | |
6e1cb38a | 1372 | |
05c3dc2c | 1373 | local_irq_save(flags); |
b24696bc | 1374 | mask_IO_APIC_setup(ioapic_entries); |
05c3dc2c SS |
1375 | mask_8259A(); |
1376 | ||
b24696bc | 1377 | ret = enable_intr_remapping(EIM_32BIT_APIC_ID); |
6e1cb38a SS |
1378 | |
1379 | if (ret && x2apic_preenabled) { | |
1380 | local_irq_restore(flags); | |
1381 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1382 | } | |
1383 | ||
1384 | if (ret) | |
5ffa4eb2 | 1385 | goto end_restore; |
6e1cb38a SS |
1386 | |
1387 | if (!x2apic) { | |
1388 | x2apic = 1; | |
6e1cb38a SS |
1389 | enable_x2apic(); |
1390 | } | |
5ffa4eb2 CG |
1391 | |
1392 | end_restore: | |
6e1cb38a SS |
1393 | if (ret) |
1394 | /* | |
1395 | * IR enabling failed | |
1396 | */ | |
b24696bc | 1397 | restore_IO_APIC_setup(ioapic_entries); |
6e1cb38a | 1398 | else |
b24696bc | 1399 | reinit_intr_remapped_IO_APIC(x2apic_preenabled, ioapic_entries); |
6e1cb38a SS |
1400 | |
1401 | unmask_8259A(); | |
1402 | local_irq_restore(flags); | |
1403 | ||
05c3dc2c | 1404 | end: |
6e1cb38a SS |
1405 | if (!ret) { |
1406 | if (!x2apic_preenabled) | |
ba21ebb6 | 1407 | pr_info("Enabled x2apic and interrupt-remapping\n"); |
6e1cb38a | 1408 | else |
ba21ebb6 | 1409 | pr_info("Enabled Interrupt-remapping\n"); |
6e1cb38a | 1410 | } else |
ba21ebb6 | 1411 | pr_err("Failed to enable Interrupt-remapping and x2apic\n"); |
b24696bc FY |
1412 | if (ioapic_entries) |
1413 | free_ioapic_entries(ioapic_entries); | |
6e1cb38a SS |
1414 | #else |
1415 | if (!cpu_has_x2apic) | |
1416 | return; | |
1417 | ||
1418 | if (x2apic_preenabled) | |
1419 | panic("x2apic enabled prior OS handover," | |
1420 | " enable CONFIG_INTR_REMAP"); | |
1421 | ||
ba21ebb6 CG |
1422 | pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " |
1423 | " and x2apic\n"); | |
6e1cb38a SS |
1424 | #endif |
1425 | ||
1426 | return; | |
1427 | } | |
06cd9a7d | 1428 | #endif /* CONFIG_X86_X2APIC */ |
6e1cb38a | 1429 | |
be7a656f | 1430 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1431 | /* |
1432 | * Detect and enable local APICs on non-SMP boards. | |
1433 | * Original code written by Keir Fraser. | |
1434 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1435 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1436 | */ |
0e078e2f | 1437 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1438 | { |
1439 | if (!cpu_has_apic) { | |
ba21ebb6 | 1440 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1441 | return -1; |
1442 | } | |
1443 | ||
1444 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1445 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1446 | return 0; |
1447 | } | |
be7a656f YL |
1448 | #else |
1449 | /* | |
1450 | * Detect and initialize APIC | |
1451 | */ | |
1452 | static int __init detect_init_APIC(void) | |
1453 | { | |
1454 | u32 h, l, features; | |
1455 | ||
1456 | /* Disabled by kernel option? */ | |
1457 | if (disable_apic) | |
1458 | return -1; | |
1459 | ||
1460 | switch (boot_cpu_data.x86_vendor) { | |
1461 | case X86_VENDOR_AMD: | |
1462 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1463 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1464 | break; |
1465 | goto no_apic; | |
1466 | case X86_VENDOR_INTEL: | |
1467 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1468 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1469 | break; | |
1470 | goto no_apic; | |
1471 | default: | |
1472 | goto no_apic; | |
1473 | } | |
1474 | ||
1475 | if (!cpu_has_apic) { | |
1476 | /* | |
1477 | * Over-ride BIOS and try to enable the local APIC only if | |
1478 | * "lapic" specified. | |
1479 | */ | |
1480 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1481 | pr_info("Local APIC disabled by BIOS -- " |
1482 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1483 | return -1; |
1484 | } | |
1485 | /* | |
1486 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1487 | * MSR. This can only be done in software for Intel P6 or later | |
1488 | * and AMD K7 (Model > 1) or later. | |
1489 | */ | |
1490 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1491 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
ba21ebb6 | 1492 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
be7a656f YL |
1493 | l &= ~MSR_IA32_APICBASE_BASE; |
1494 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1495 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1496 | enabled_via_apicbase = 1; | |
1497 | } | |
1498 | } | |
1499 | /* | |
1500 | * The APIC feature bit should now be enabled | |
1501 | * in `cpuid' | |
1502 | */ | |
1503 | features = cpuid_edx(1); | |
1504 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
ba21ebb6 | 1505 | pr_warning("Could not enable APIC!\n"); |
be7a656f YL |
1506 | return -1; |
1507 | } | |
1508 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1509 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1510 | ||
1511 | /* The BIOS may have set up the APIC at some other address */ | |
1512 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1513 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1514 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1515 | ||
ba21ebb6 | 1516 | pr_info("Found and enabled local APIC!\n"); |
be7a656f YL |
1517 | |
1518 | apic_pm_activate(); | |
1519 | ||
1520 | return 0; | |
1521 | ||
1522 | no_apic: | |
ba21ebb6 | 1523 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1524 | return -1; |
1525 | } | |
1526 | #endif | |
1da177e4 | 1527 | |
f28c0ae2 | 1528 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1529 | void __init early_init_lapic_mapping(void) |
1530 | { | |
431ee79d | 1531 | unsigned long phys_addr; |
8643f9d0 YL |
1532 | |
1533 | /* | |
1534 | * If no local APIC can be found then go out | |
1535 | * : it means there is no mpatable and MADT | |
1536 | */ | |
1537 | if (!smp_found_config) | |
1538 | return; | |
1539 | ||
431ee79d | 1540 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1541 | |
431ee79d | 1542 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1543 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1544 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1545 | |
1546 | /* | |
1547 | * Fetch the APIC ID of the BSP in case we have a | |
1548 | * default configuration (or the MP table is broken). | |
1549 | */ | |
4c9961d5 | 1550 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1551 | } |
f28c0ae2 | 1552 | #endif |
8643f9d0 | 1553 | |
0e078e2f TG |
1554 | /** |
1555 | * init_apic_mappings - initialize APIC mappings | |
1556 | */ | |
1da177e4 LT |
1557 | void __init init_apic_mappings(void) |
1558 | { | |
6e1cb38a | 1559 | if (x2apic) { |
4c9961d5 | 1560 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1561 | return; |
1562 | } | |
1563 | ||
1da177e4 LT |
1564 | /* |
1565 | * If no local APIC can be found then set up a fake all | |
1566 | * zeroes page to simulate the local APIC and another | |
1567 | * one for the IO-APIC. | |
1568 | */ | |
1569 | if (!smp_found_config && detect_init_APIC()) { | |
1570 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1571 | apic_phys = __pa(apic_phys); | |
1572 | } else | |
1573 | apic_phys = mp_lapic_addr; | |
1574 | ||
1575 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
79c09698 | 1576 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
7ffeeb1e | 1577 | APIC_BASE, apic_phys); |
1da177e4 LT |
1578 | |
1579 | /* | |
1580 | * Fetch the APIC ID of the BSP in case we have a | |
1581 | * default configuration (or the MP table is broken). | |
1582 | */ | |
f28c0ae2 YL |
1583 | if (boot_cpu_physical_apicid == -1U) |
1584 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1585 | } |
1586 | ||
1587 | /* | |
0e078e2f TG |
1588 | * This initializes the IO-APIC and APIC hardware if this is |
1589 | * a UP kernel. | |
1da177e4 | 1590 | */ |
1b313f4a CG |
1591 | int apic_version[MAX_APICS]; |
1592 | ||
0e078e2f | 1593 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1594 | { |
0e078e2f | 1595 | if (disable_apic) { |
ba21ebb6 | 1596 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1597 | return -1; |
1598 | } | |
f1182638 | 1599 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1600 | if (!cpu_has_apic) { |
1601 | disable_apic = 1; | |
ba21ebb6 | 1602 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1603 | return -1; |
1604 | } | |
fa2bd35a YL |
1605 | #else |
1606 | if (!smp_found_config && !cpu_has_apic) | |
1607 | return -1; | |
1608 | ||
1609 | /* | |
1610 | * Complain if the BIOS pretends there is one. | |
1611 | */ | |
1612 | if (!cpu_has_apic && | |
1613 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1614 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1615 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1616 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1617 | return -1; | |
1618 | } | |
1619 | #endif | |
1620 | ||
6e1cb38a | 1621 | enable_IR_x2apic(); |
fa2bd35a | 1622 | #ifdef CONFIG_X86_64 |
72ce0165 | 1623 | default_setup_apic_routing(); |
fa2bd35a | 1624 | #endif |
6e1cb38a | 1625 | |
0e078e2f | 1626 | verify_local_APIC(); |
b5841765 GC |
1627 | connect_bsp_APIC(); |
1628 | ||
fa2bd35a | 1629 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1630 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1631 | #else |
1632 | /* | |
1633 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1634 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1635 | * might be zero if read from MP tables. Get it from LAPIC. | |
1636 | */ | |
1637 | # ifdef CONFIG_CRASH_DUMP | |
1638 | boot_cpu_physical_apicid = read_apic_id(); | |
1639 | # endif | |
1640 | #endif | |
1641 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1642 | setup_local_APIC(); |
1da177e4 | 1643 | |
88d0f550 | 1644 | #ifdef CONFIG_X86_IO_APIC |
739f33b3 AK |
1645 | /* |
1646 | * Now enable IO-APICs, actually call clear_IO_APIC | |
98c061b6 | 1647 | * We need clear_IO_APIC before enabling error vector |
739f33b3 AK |
1648 | */ |
1649 | if (!skip_ioapic_setup && nr_ioapics) | |
1650 | enable_IO_APIC(); | |
fa2bd35a | 1651 | #endif |
739f33b3 AK |
1652 | |
1653 | end_local_APIC_setup(); | |
1654 | ||
fa2bd35a | 1655 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1656 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1657 | setup_IO_APIC(); | |
98c061b6 | 1658 | else { |
0e078e2f | 1659 | nr_ioapics = 0; |
98c061b6 YL |
1660 | localise_nmi_watchdog(); |
1661 | } | |
1662 | #else | |
1663 | localise_nmi_watchdog(); | |
fa2bd35a YL |
1664 | #endif |
1665 | ||
98c061b6 | 1666 | setup_boot_clock(); |
fa2bd35a | 1667 | #ifdef CONFIG_X86_64 |
0e078e2f | 1668 | check_nmi_watchdog(); |
fa2bd35a YL |
1669 | #endif |
1670 | ||
0e078e2f | 1671 | return 0; |
1da177e4 LT |
1672 | } |
1673 | ||
1674 | /* | |
0e078e2f | 1675 | * Local APIC interrupts |
1da177e4 LT |
1676 | */ |
1677 | ||
0e078e2f TG |
1678 | /* |
1679 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1680 | */ | |
dc1528dd | 1681 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1682 | { |
dc1528dd YL |
1683 | u32 v; |
1684 | ||
0e078e2f TG |
1685 | exit_idle(); |
1686 | irq_enter(); | |
1da177e4 | 1687 | /* |
0e078e2f TG |
1688 | * Check if this really is a spurious interrupt and ACK it |
1689 | * if it is a vectored one. Just in case... | |
1690 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1691 | */ |
0e078e2f TG |
1692 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1693 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1694 | ack_APIC_irq(); | |
c4d58cbd | 1695 | |
915b0d01 HS |
1696 | inc_irq_stat(irq_spurious_count); |
1697 | ||
dc1528dd | 1698 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1699 | pr_info("spurious APIC interrupt on CPU#%d, " |
1700 | "should never happen.\n", smp_processor_id()); | |
0e078e2f TG |
1701 | irq_exit(); |
1702 | } | |
1da177e4 | 1703 | |
0e078e2f TG |
1704 | /* |
1705 | * This interrupt should never happen with our APIC/SMP architecture | |
1706 | */ | |
dc1528dd | 1707 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1708 | { |
dc1528dd | 1709 | u32 v, v1; |
1da177e4 | 1710 | |
0e078e2f TG |
1711 | exit_idle(); |
1712 | irq_enter(); | |
1713 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1714 | v = apic_read(APIC_ESR); | |
1715 | apic_write(APIC_ESR, 0); | |
1716 | v1 = apic_read(APIC_ESR); | |
1717 | ack_APIC_irq(); | |
1718 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1719 | |
ba21ebb6 CG |
1720 | /* |
1721 | * Here is what the APIC error bits mean: | |
1722 | * 0: Send CS error | |
1723 | * 1: Receive CS error | |
1724 | * 2: Send accept error | |
1725 | * 3: Receive accept error | |
1726 | * 4: Reserved | |
1727 | * 5: Send illegal vector | |
1728 | * 6: Received illegal vector | |
1729 | * 7: Illegal register address | |
1730 | */ | |
1731 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | |
0e078e2f TG |
1732 | smp_processor_id(), v , v1); |
1733 | irq_exit(); | |
1da177e4 LT |
1734 | } |
1735 | ||
b5841765 | 1736 | /** |
36c9d674 CG |
1737 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1738 | */ | |
b5841765 GC |
1739 | void __init connect_bsp_APIC(void) |
1740 | { | |
36c9d674 CG |
1741 | #ifdef CONFIG_X86_32 |
1742 | if (pic_mode) { | |
1743 | /* | |
1744 | * Do not trust the local APIC being empty at bootup. | |
1745 | */ | |
1746 | clear_local_APIC(); | |
1747 | /* | |
1748 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1749 | * local APIC to INT and NMI lines. | |
1750 | */ | |
1751 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1752 | "enabling APIC mode.\n"); | |
c0eaa453 | 1753 | imcr_pic_to_apic(); |
36c9d674 CG |
1754 | } |
1755 | #endif | |
49040333 IM |
1756 | if (apic->enable_apic_mode) |
1757 | apic->enable_apic_mode(); | |
b5841765 GC |
1758 | } |
1759 | ||
274cfe59 CG |
1760 | /** |
1761 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1762 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1763 | * | |
1764 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1765 | * APIC is disabled. | |
1766 | */ | |
0e078e2f | 1767 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1768 | { |
1b4ee4e4 CG |
1769 | unsigned int value; |
1770 | ||
c177b0bc CG |
1771 | #ifdef CONFIG_X86_32 |
1772 | if (pic_mode) { | |
1773 | /* | |
1774 | * Put the board back into PIC mode (has an effect only on | |
1775 | * certain older boards). Note that APIC interrupts, including | |
1776 | * IPIs, won't work beyond this point! The only exception are | |
1777 | * INIT IPIs. | |
1778 | */ | |
1779 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1780 | "entering PIC mode.\n"); | |
c0eaa453 | 1781 | imcr_apic_to_pic(); |
c177b0bc CG |
1782 | return; |
1783 | } | |
1784 | #endif | |
1785 | ||
0e078e2f | 1786 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1787 | |
0e078e2f TG |
1788 | /* For the spurious interrupt use vector F, and enable it */ |
1789 | value = apic_read(APIC_SPIV); | |
1790 | value &= ~APIC_VECTOR_MASK; | |
1791 | value |= APIC_SPIV_APIC_ENABLED; | |
1792 | value |= 0xf; | |
1793 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1794 | |
0e078e2f TG |
1795 | if (!virt_wire_setup) { |
1796 | /* | |
1797 | * For LVT0 make it edge triggered, active high, | |
1798 | * external and enabled | |
1799 | */ | |
1800 | value = apic_read(APIC_LVT0); | |
1801 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1802 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1803 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1804 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1805 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1806 | apic_write(APIC_LVT0, value); | |
1807 | } else { | |
1808 | /* Disable LVT0 */ | |
1809 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1810 | } | |
b8ce3359 | 1811 | |
c177b0bc CG |
1812 | /* |
1813 | * For LVT1 make it edge triggered, active high, | |
1814 | * nmi and enabled | |
1815 | */ | |
0e078e2f TG |
1816 | value = apic_read(APIC_LVT1); |
1817 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1818 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1819 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1820 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1821 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1822 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1823 | } |
1824 | ||
be8a5685 AS |
1825 | void __cpuinit generic_processor_info(int apicid, int version) |
1826 | { | |
1827 | int cpu; | |
be8a5685 | 1828 | |
1b313f4a CG |
1829 | /* |
1830 | * Validate version | |
1831 | */ | |
1832 | if (version == 0x0) { | |
ba21ebb6 | 1833 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
3b11ce7f MT |
1834 | "fixing up to 0x10. (tell your hw vendor)\n", |
1835 | version); | |
1b313f4a | 1836 | version = 0x10; |
be8a5685 | 1837 | } |
1b313f4a | 1838 | apic_version[apicid] = version; |
be8a5685 | 1839 | |
3b11ce7f MT |
1840 | if (num_processors >= nr_cpu_ids) { |
1841 | int max = nr_cpu_ids; | |
1842 | int thiscpu = max + disabled_cpus; | |
1843 | ||
1844 | pr_warning( | |
1845 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
1846 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
1847 | ||
1848 | disabled_cpus++; | |
be8a5685 AS |
1849 | return; |
1850 | } | |
1851 | ||
1852 | num_processors++; | |
3b11ce7f | 1853 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
be8a5685 | 1854 | |
b2b815d8 MT |
1855 | if (version != apic_version[boot_cpu_physical_apicid]) |
1856 | WARN_ONCE(1, | |
1857 | "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", | |
1858 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
1859 | ||
be8a5685 AS |
1860 | physid_set(apicid, phys_cpu_present_map); |
1861 | if (apicid == boot_cpu_physical_apicid) { | |
1862 | /* | |
1863 | * x86_bios_cpu_apicid is required to have processors listed | |
1864 | * in same order as logical cpu numbers. Hence the first | |
1865 | * entry is BSP, and so on. | |
1866 | */ | |
1867 | cpu = 0; | |
1868 | } | |
e0da3364 YL |
1869 | if (apicid > max_physical_apicid) |
1870 | max_physical_apicid = apicid; | |
1871 | ||
1b313f4a CG |
1872 | #ifdef CONFIG_X86_32 |
1873 | /* | |
1874 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1875 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1876 | * before this can be done without some confusion. | |
1877 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1878 | * - Ashok Raj <ashok.raj@intel.com> | |
1879 | */ | |
1880 | if (max_physical_apicid >= 8) { | |
1881 | switch (boot_cpu_data.x86_vendor) { | |
1882 | case X86_VENDOR_INTEL: | |
1883 | if (!APIC_XAPIC(version)) { | |
1884 | def_to_bigsmp = 0; | |
1885 | break; | |
1886 | } | |
1887 | /* If P4 and above fall through */ | |
1888 | case X86_VENDOR_AMD: | |
1889 | def_to_bigsmp = 1; | |
1890 | } | |
1891 | } | |
1892 | #endif | |
1893 | ||
3e5095d1 | 1894 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
1895 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
1896 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 1897 | #endif |
be8a5685 | 1898 | |
1de88cd4 MT |
1899 | set_cpu_possible(cpu, true); |
1900 | set_cpu_present(cpu, true); | |
be8a5685 AS |
1901 | } |
1902 | ||
0c81c746 SS |
1903 | int hard_smp_processor_id(void) |
1904 | { | |
1905 | return read_apic_id(); | |
1906 | } | |
1dcdd3d1 IM |
1907 | |
1908 | void default_init_apic_ldr(void) | |
1909 | { | |
1910 | unsigned long val; | |
1911 | ||
1912 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
1913 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
1914 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
1915 | apic_write(APIC_LDR, val); | |
1916 | } | |
1917 | ||
1918 | #ifdef CONFIG_X86_32 | |
1919 | int default_apicid_to_node(int logical_apicid) | |
1920 | { | |
1921 | #ifdef CONFIG_SMP | |
1922 | return apicid_2_node[hard_smp_processor_id()]; | |
1923 | #else | |
1924 | return 0; | |
1925 | #endif | |
1926 | } | |
3491998d | 1927 | #endif |
0c81c746 | 1928 | |
89039b37 | 1929 | /* |
0e078e2f | 1930 | * Power management |
89039b37 | 1931 | */ |
0e078e2f TG |
1932 | #ifdef CONFIG_PM |
1933 | ||
1934 | static struct { | |
274cfe59 CG |
1935 | /* |
1936 | * 'active' is true if the local APIC was enabled by us and | |
1937 | * not the BIOS; this signifies that we are also responsible | |
1938 | * for disabling it before entering apm/acpi suspend | |
1939 | */ | |
0e078e2f TG |
1940 | int active; |
1941 | /* r/w apic fields */ | |
1942 | unsigned int apic_id; | |
1943 | unsigned int apic_taskpri; | |
1944 | unsigned int apic_ldr; | |
1945 | unsigned int apic_dfr; | |
1946 | unsigned int apic_spiv; | |
1947 | unsigned int apic_lvtt; | |
1948 | unsigned int apic_lvtpc; | |
1949 | unsigned int apic_lvt0; | |
1950 | unsigned int apic_lvt1; | |
1951 | unsigned int apic_lvterr; | |
1952 | unsigned int apic_tmict; | |
1953 | unsigned int apic_tdcr; | |
1954 | unsigned int apic_thmr; | |
1955 | } apic_pm_state; | |
1956 | ||
1957 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1958 | { | |
1959 | unsigned long flags; | |
1960 | int maxlvt; | |
89039b37 | 1961 | |
0e078e2f TG |
1962 | if (!apic_pm_state.active) |
1963 | return 0; | |
89039b37 | 1964 | |
0e078e2f | 1965 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1966 | |
2d7a66d0 | 1967 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1968 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1969 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1970 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1971 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1972 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1973 | if (maxlvt >= 4) | |
1974 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1975 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1976 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1977 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1978 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1979 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1980 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1981 | if (maxlvt >= 5) |
1982 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1983 | #endif | |
24968cfd | 1984 | |
0e078e2f TG |
1985 | local_irq_save(flags); |
1986 | disable_local_APIC(); | |
b24696bc FY |
1987 | #ifdef CONFIG_INTR_REMAP |
1988 | if (intr_remapping_enabled) | |
1989 | disable_intr_remapping(); | |
1990 | #endif | |
0e078e2f TG |
1991 | local_irq_restore(flags); |
1992 | return 0; | |
1da177e4 LT |
1993 | } |
1994 | ||
0e078e2f | 1995 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1996 | { |
0e078e2f TG |
1997 | unsigned int l, h; |
1998 | unsigned long flags; | |
1999 | int maxlvt; | |
1da177e4 | 2000 | |
b24696bc FY |
2001 | #ifdef CONFIG_INTR_REMAP |
2002 | int ret; | |
2003 | struct IO_APIC_route_entry **ioapic_entries = NULL; | |
2004 | ||
0e078e2f TG |
2005 | if (!apic_pm_state.active) |
2006 | return 0; | |
89b831ef | 2007 | |
0e078e2f | 2008 | local_irq_save(flags); |
b24696bc FY |
2009 | if (x2apic) { |
2010 | ioapic_entries = alloc_ioapic_entries(); | |
2011 | if (!ioapic_entries) { | |
2012 | WARN(1, "Alloc ioapic_entries in lapic resume failed."); | |
2013 | return -ENOMEM; | |
2014 | } | |
2015 | ||
2016 | ret = save_IO_APIC_setup(ioapic_entries); | |
2017 | if (ret) { | |
2018 | WARN(1, "Saving IO-APIC state failed: %d\n", ret); | |
2019 | free_ioapic_entries(ioapic_entries); | |
2020 | return ret; | |
2021 | } | |
2022 | ||
2023 | mask_IO_APIC_setup(ioapic_entries); | |
2024 | mask_8259A(); | |
2025 | enable_x2apic(); | |
2026 | } | |
2027 | #else | |
2028 | if (!apic_pm_state.active) | |
2029 | return 0; | |
92206c90 | 2030 | |
b24696bc | 2031 | local_irq_save(flags); |
92206c90 CG |
2032 | if (x2apic) |
2033 | enable_x2apic(); | |
b24696bc FY |
2034 | #endif |
2035 | ||
cf6567fe | 2036 | else { |
92206c90 CG |
2037 | /* |
2038 | * Make sure the APICBASE points to the right address | |
2039 | * | |
2040 | * FIXME! This will be wrong if we ever support suspend on | |
2041 | * SMP! We'll need to do this as part of the CPU restore! | |
2042 | */ | |
6e1cb38a SS |
2043 | rdmsr(MSR_IA32_APICBASE, l, h); |
2044 | l &= ~MSR_IA32_APICBASE_BASE; | |
2045 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2046 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 2047 | } |
6e1cb38a | 2048 | |
b24696bc | 2049 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2050 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2051 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2052 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2053 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2054 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2055 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2056 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2057 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2058 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2059 | if (maxlvt >= 5) |
2060 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2061 | #endif | |
2062 | if (maxlvt >= 4) | |
2063 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2064 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2065 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2066 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2067 | apic_write(APIC_ESR, 0); | |
2068 | apic_read(APIC_ESR); | |
2069 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2070 | apic_write(APIC_ESR, 0); | |
2071 | apic_read(APIC_ESR); | |
92206c90 | 2072 | |
b24696bc FY |
2073 | #ifdef CONFIG_INTR_REMAP |
2074 | if (intr_remapping_enabled) | |
2075 | reenable_intr_remapping(EIM_32BIT_APIC_ID); | |
2076 | ||
2077 | if (x2apic) { | |
2078 | unmask_8259A(); | |
2079 | restore_IO_APIC_setup(ioapic_entries); | |
2080 | free_ioapic_entries(ioapic_entries); | |
2081 | } | |
2082 | #endif | |
2083 | ||
0e078e2f | 2084 | local_irq_restore(flags); |
92206c90 | 2085 | |
b24696bc | 2086 | |
0e078e2f TG |
2087 | return 0; |
2088 | } | |
b8ce3359 | 2089 | |
274cfe59 CG |
2090 | /* |
2091 | * This device has no shutdown method - fully functioning local APICs | |
2092 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2093 | */ | |
2094 | ||
0e078e2f TG |
2095 | static struct sysdev_class lapic_sysclass = { |
2096 | .name = "lapic", | |
2097 | .resume = lapic_resume, | |
2098 | .suspend = lapic_suspend, | |
2099 | }; | |
b8ce3359 | 2100 | |
0e078e2f | 2101 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2102 | .id = 0, |
2103 | .cls = &lapic_sysclass, | |
0e078e2f | 2104 | }; |
b8ce3359 | 2105 | |
0e078e2f TG |
2106 | static void __cpuinit apic_pm_activate(void) |
2107 | { | |
2108 | apic_pm_state.active = 1; | |
1da177e4 LT |
2109 | } |
2110 | ||
0e078e2f | 2111 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2112 | { |
0e078e2f | 2113 | int error; |
e83a5fdc | 2114 | |
0e078e2f TG |
2115 | if (!cpu_has_apic) |
2116 | return 0; | |
2117 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2118 | |
0e078e2f TG |
2119 | error = sysdev_class_register(&lapic_sysclass); |
2120 | if (!error) | |
2121 | error = sysdev_register(&device_lapic); | |
2122 | return error; | |
1da177e4 | 2123 | } |
b24696bc FY |
2124 | |
2125 | /* local apic needs to resume before other devices access its registers. */ | |
2126 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2127 | |
2128 | #else /* CONFIG_PM */ | |
2129 | ||
2130 | static void apic_pm_activate(void) { } | |
2131 | ||
2132 | #endif /* CONFIG_PM */ | |
1da177e4 | 2133 | |
f28c0ae2 | 2134 | #ifdef CONFIG_X86_64 |
1da177e4 | 2135 | /* |
f8bf3c65 | 2136 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
2137 | * |
2138 | * Thus far, the major user of this is IBM's Summit2 series: | |
2139 | * | |
637029c6 | 2140 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
2141 | * multi-chassis. Use available data to take a good guess. |
2142 | * If in doubt, go HPET. | |
2143 | */ | |
f8bf3c65 | 2144 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
2145 | { |
2146 | int i, clusters, zeros; | |
2147 | unsigned id; | |
322850af | 2148 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2149 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2150 | ||
322850af YL |
2151 | /* |
2152 | * there is not this kind of box with AMD CPU yet. | |
2153 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
2154 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 2155 | * vsmp box still need checking... |
322850af | 2156 | */ |
1cb68487 | 2157 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
2158 | return 0; |
2159 | ||
23ca4bba | 2160 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2161 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2162 | |
168ef543 | 2163 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2164 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2165 | if (bios_cpu_apicid) { |
2166 | id = bios_cpu_apicid[i]; | |
e423e33e | 2167 | } else if (i < nr_cpu_ids) { |
e8c10ef9 | 2168 | if (cpu_present(i)) |
2169 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2170 | else | |
2171 | continue; | |
e423e33e | 2172 | } else |
e8c10ef9 | 2173 | break; |
2174 | ||
1da177e4 LT |
2175 | if (id != BAD_APICID) |
2176 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2177 | } | |
2178 | ||
2179 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2180 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2181 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2182 | * Since clusters are allocated sequentially, count zeros only if | |
2183 | * they are bounded by ones. | |
1da177e4 LT |
2184 | */ |
2185 | clusters = 0; | |
2186 | zeros = 0; | |
2187 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2188 | if (test_bit(i, clustermap)) { | |
2189 | clusters += 1 + zeros; | |
2190 | zeros = 0; | |
2191 | } else | |
2192 | ++zeros; | |
2193 | } | |
2194 | ||
1cb68487 RT |
2195 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2196 | * not guaranteed to be synced between boards | |
2197 | */ | |
2198 | if (is_vsmp_box() && clusters > 1) | |
2199 | return 1; | |
2200 | ||
1da177e4 | 2201 | /* |
f8bf3c65 | 2202 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
2203 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
2204 | * out, but AFAIK this will work even for them. | |
2205 | */ | |
2206 | return (clusters > 2); | |
2207 | } | |
f28c0ae2 | 2208 | #endif |
1da177e4 LT |
2209 | |
2210 | /* | |
0e078e2f | 2211 | * APIC command line parameters |
1da177e4 | 2212 | */ |
789fa735 | 2213 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2214 | { |
1da177e4 | 2215 | disable_apic = 1; |
9175fc06 | 2216 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2217 | return 0; |
2218 | } | |
2219 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2220 | |
2c8c0e6b | 2221 | /* same as disableapic, for compatibility */ |
789fa735 | 2222 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2223 | { |
789fa735 | 2224 | return setup_disableapic(arg); |
6935d1f9 | 2225 | } |
2c8c0e6b | 2226 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2227 | |
2e7c2838 LT |
2228 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2229 | { | |
2230 | local_apic_timer_c2_ok = 1; | |
2231 | return 0; | |
2232 | } | |
2233 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2234 | ||
36fef094 | 2235 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2236 | { |
1da177e4 | 2237 | disable_apic_timer = 1; |
36fef094 | 2238 | return 0; |
6935d1f9 | 2239 | } |
36fef094 CG |
2240 | early_param("noapictimer", parse_disable_apic_timer); |
2241 | ||
2242 | static int __init parse_nolapic_timer(char *arg) | |
2243 | { | |
2244 | disable_apic_timer = 1; | |
2245 | return 0; | |
6935d1f9 | 2246 | } |
36fef094 | 2247 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2248 | |
79af9bec CG |
2249 | static int __init apic_set_verbosity(char *arg) |
2250 | { | |
2251 | if (!arg) { | |
2252 | #ifdef CONFIG_X86_64 | |
2253 | skip_ioapic_setup = 0; | |
79af9bec CG |
2254 | return 0; |
2255 | #endif | |
2256 | return -EINVAL; | |
2257 | } | |
2258 | ||
2259 | if (strcmp("debug", arg) == 0) | |
2260 | apic_verbosity = APIC_DEBUG; | |
2261 | else if (strcmp("verbose", arg) == 0) | |
2262 | apic_verbosity = APIC_VERBOSE; | |
2263 | else { | |
ba21ebb6 | 2264 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2265 | " use apic=verbose or apic=debug\n", arg); |
2266 | return -EINVAL; | |
2267 | } | |
2268 | ||
2269 | return 0; | |
2270 | } | |
2271 | early_param("apic", apic_set_verbosity); | |
2272 | ||
1e934dda YL |
2273 | static int __init lapic_insert_resource(void) |
2274 | { | |
2275 | if (!apic_phys) | |
2276 | return -1; | |
2277 | ||
2278 | /* Put local APIC into the resource map. */ | |
2279 | lapic_resource.start = apic_phys; | |
2280 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2281 | insert_resource(&iomem_resource, &lapic_resource); | |
2282 | ||
2283 | return 0; | |
2284 | } | |
2285 | ||
2286 | /* | |
2287 | * need call insert after e820_reserve_resources() | |
2288 | * that is using request_resource | |
2289 | */ | |
2290 | late_initcall(lapic_insert_resource); |