Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 | 17 | #include <linux/kernel_stat.h> |
d1de36f5 | 18 | #include <linux/mc146818rtc.h> |
70a20025 | 19 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
20 | #include <linux/clockchips.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/ftrace.h> | |
24 | #include <linux/ioport.h> | |
e83a5fdc | 25 | #include <linux/module.h> |
d1de36f5 IM |
26 | #include <linux/sysdev.h> |
27 | #include <linux/delay.h> | |
28 | #include <linux/timex.h> | |
6e1cb38a | 29 | #include <linux/dmar.h> |
d1de36f5 IM |
30 | #include <linux/init.h> |
31 | #include <linux/cpu.h> | |
32 | #include <linux/dmi.h> | |
e423e33e | 33 | #include <linux/nmi.h> |
d1de36f5 IM |
34 | #include <linux/smp.h> |
35 | #include <linux/mm.h> | |
1da177e4 | 36 | |
1da177e4 | 37 | #include <asm/pgalloc.h> |
1da177e4 | 38 | #include <asm/atomic.h> |
1da177e4 | 39 | #include <asm/mpspec.h> |
773763df | 40 | #include <asm/i8253.h> |
d1de36f5 | 41 | #include <asm/i8259.h> |
73dea47f | 42 | #include <asm/proto.h> |
2c8c0e6b | 43 | #include <asm/apic.h> |
d1de36f5 IM |
44 | #include <asm/desc.h> |
45 | #include <asm/hpet.h> | |
46 | #include <asm/idle.h> | |
47 | #include <asm/mtrr.h> | |
2bc13797 | 48 | #include <asm/smp.h> |
be71b855 | 49 | #include <asm/mce.h> |
1da177e4 | 50 | |
ec70de8b | 51 | unsigned int num_processors; |
fdbecd9f | 52 | |
ec70de8b | 53 | unsigned disabled_cpus __cpuinitdata; |
fdbecd9f | 54 | |
ec70de8b BG |
55 | /* Processor that is doing the boot up */ |
56 | unsigned int boot_cpu_physical_apicid = -1U; | |
5af5573e | 57 | |
80e5609c | 58 | /* |
fdbecd9f IM |
59 | * The highest APIC ID seen during enumeration. |
60 | * | |
61 | * This determines the messaging protocol we can use: if all APIC IDs | |
62 | * are in the 0 ... 7 range, then we can use logical addressing which | |
63 | * has some performance advantages (better broadcasting). | |
64 | * | |
65 | * If there's an APIC ID above 8, we use physical addressing. | |
80e5609c | 66 | */ |
ec70de8b | 67 | unsigned int max_physical_apicid; |
5af5573e | 68 | |
80e5609c | 69 | /* |
fdbecd9f | 70 | * Bitmask of physically existing CPUs: |
80e5609c | 71 | */ |
ec70de8b BG |
72 | physid_mask_t phys_cpu_present_map; |
73 | ||
74 | /* | |
75 | * Map cpu index to physical APIC ID | |
76 | */ | |
77 | DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); | |
78 | DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); | |
79 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
80 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
80e5609c | 81 | |
b3c51170 YL |
82 | #ifdef CONFIG_X86_32 |
83 | /* | |
84 | * Knob to control our willingness to enable the local APIC. | |
85 | * | |
86 | * +1=force-enable | |
87 | */ | |
88 | static int force_enable_local_apic; | |
89 | /* | |
90 | * APIC command line parameters | |
91 | */ | |
92 | static int __init parse_lapic(char *arg) | |
93 | { | |
94 | force_enable_local_apic = 1; | |
95 | return 0; | |
96 | } | |
97 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
98 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
99 | static int enabled_via_apicbase; | |
100 | ||
c0eaa453 CG |
101 | /* |
102 | * Handle interrupt mode configuration register (IMCR). | |
103 | * This register controls whether the interrupt signals | |
104 | * that reach the BSP come from the master PIC or from the | |
105 | * local APIC. Before entering Symmetric I/O Mode, either | |
106 | * the BIOS or the operating system must switch out of | |
107 | * PIC Mode by changing the IMCR. | |
108 | */ | |
5cda395f | 109 | static inline void imcr_pic_to_apic(void) |
c0eaa453 CG |
110 | { |
111 | /* select IMCR register */ | |
112 | outb(0x70, 0x22); | |
113 | /* NMI and 8259 INTR go through APIC */ | |
114 | outb(0x01, 0x23); | |
115 | } | |
116 | ||
5cda395f | 117 | static inline void imcr_apic_to_pic(void) |
c0eaa453 CG |
118 | { |
119 | /* select IMCR register */ | |
120 | outb(0x70, 0x22); | |
121 | /* NMI and 8259 INTR go directly to BSP */ | |
122 | outb(0x00, 0x23); | |
123 | } | |
b3c51170 YL |
124 | #endif |
125 | ||
126 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 127 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
128 | static __init int setup_apicpmtimer(char *s) |
129 | { | |
130 | apic_calibrate_pmtmr = 1; | |
131 | notsc_setup(NULL); | |
132 | return 0; | |
133 | } | |
134 | __setup("apicpmtimer", setup_apicpmtimer); | |
135 | #endif | |
136 | ||
fc1edaf9 | 137 | int x2apic_mode; |
06cd9a7d | 138 | #ifdef CONFIG_X86_X2APIC |
6e1cb38a | 139 | /* x2apic enabled before OS handover */ |
b6b301aa JS |
140 | static int x2apic_preenabled; |
141 | static int disable_x2apic; | |
49899eac YL |
142 | static __init int setup_nox2apic(char *str) |
143 | { | |
39d83a5d SS |
144 | if (x2apic_enabled()) { |
145 | pr_warning("Bios already enabled x2apic, " | |
146 | "can't enforce nox2apic"); | |
147 | return 0; | |
148 | } | |
149 | ||
49899eac YL |
150 | disable_x2apic = 1; |
151 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
152 | return 0; | |
153 | } | |
154 | early_param("nox2apic", setup_nox2apic); | |
155 | #endif | |
1da177e4 | 156 | |
b3c51170 YL |
157 | unsigned long mp_lapic_addr; |
158 | int disable_apic; | |
159 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
160 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 161 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
162 | int local_apic_timer_c2_ok; |
163 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
164 | ||
efa2559f YL |
165 | int first_system_vector = 0xfe; |
166 | ||
e83a5fdc HS |
167 | /* |
168 | * Debug level, exported for io_apic.c | |
169 | */ | |
baa13188 | 170 | unsigned int apic_verbosity; |
e83a5fdc | 171 | |
89c38c28 CG |
172 | int pic_mode; |
173 | ||
bab4b27c AS |
174 | /* Have we found an MP table */ |
175 | int smp_found_config; | |
176 | ||
39928722 AD |
177 | static struct resource lapic_resource = { |
178 | .name = "Local APIC", | |
179 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
180 | }; | |
181 | ||
d03030e9 TG |
182 | static unsigned int calibration_result; |
183 | ||
ba7eda4c TG |
184 | static int lapic_next_event(unsigned long delta, |
185 | struct clock_event_device *evt); | |
186 | static void lapic_timer_setup(enum clock_event_mode mode, | |
187 | struct clock_event_device *evt); | |
9628937d | 188 | static void lapic_timer_broadcast(const struct cpumask *mask); |
0e078e2f | 189 | static void apic_pm_activate(void); |
ba7eda4c | 190 | |
274cfe59 CG |
191 | /* |
192 | * The local apic timer can be used for any function which is CPU local. | |
193 | */ | |
ba7eda4c TG |
194 | static struct clock_event_device lapic_clockevent = { |
195 | .name = "lapic", | |
196 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
197 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
198 | .shift = 32, | |
199 | .set_mode = lapic_timer_setup, | |
200 | .set_next_event = lapic_next_event, | |
201 | .broadcast = lapic_timer_broadcast, | |
202 | .rating = 100, | |
203 | .irq = -1, | |
204 | }; | |
205 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
206 | ||
d3432896 AK |
207 | static unsigned long apic_phys; |
208 | ||
0e078e2f TG |
209 | /* |
210 | * Get the LAPIC version | |
211 | */ | |
212 | static inline int lapic_get_version(void) | |
ba7eda4c | 213 | { |
0e078e2f | 214 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
215 | } |
216 | ||
0e078e2f | 217 | /* |
9c803869 | 218 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
219 | */ |
220 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 221 | { |
9c803869 | 222 | #ifdef CONFIG_X86_64 |
0e078e2f | 223 | return 1; |
9c803869 CG |
224 | #else |
225 | return APIC_INTEGRATED(lapic_get_version()); | |
226 | #endif | |
ba7eda4c TG |
227 | } |
228 | ||
229 | /* | |
0e078e2f | 230 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 231 | */ |
0e078e2f | 232 | static int modern_apic(void) |
ba7eda4c | 233 | { |
0e078e2f TG |
234 | /* AMD systems use old APIC versions, so check the CPU */ |
235 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
236 | boot_cpu_data.x86 >= 0xf) | |
237 | return 1; | |
238 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
239 | } |
240 | ||
08306ce6 CG |
241 | /* |
242 | * bare function to substitute write operation | |
243 | * and it's _that_ fast :) | |
244 | */ | |
245 | void native_apic_write_dummy(u32 reg, u32 v) | |
246 | { | |
247 | WARN_ON_ONCE((cpu_has_apic || !disable_apic)); | |
248 | } | |
249 | ||
250 | /* | |
251 | * right after this call apic->write doesn't do anything | |
252 | * note that there is no restore operation it works one way | |
253 | */ | |
254 | void apic_disable(void) | |
255 | { | |
256 | apic->write = native_apic_write_dummy; | |
257 | } | |
258 | ||
c1eeb2de | 259 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
260 | { |
261 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
262 | cpu_relax(); | |
263 | } | |
264 | ||
c1eeb2de | 265 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 266 | { |
3c6bb07a | 267 | u32 send_status; |
8339e9fb FLV |
268 | int timeout; |
269 | ||
270 | timeout = 0; | |
271 | do { | |
272 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
273 | if (!send_status) | |
274 | break; | |
275 | udelay(100); | |
276 | } while (timeout++ < 1000); | |
277 | ||
278 | return send_status; | |
279 | } | |
280 | ||
c1eeb2de | 281 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 282 | { |
ed4e5ec1 | 283 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
284 | apic_write(APIC_ICR, low); |
285 | } | |
286 | ||
c1eeb2de | 287 | u64 native_apic_icr_read(void) |
1b374e4d SS |
288 | { |
289 | u32 icr1, icr2; | |
290 | ||
291 | icr2 = apic_read(APIC_ICR2); | |
292 | icr1 = apic_read(APIC_ICR); | |
293 | ||
cf9768d7 | 294 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
295 | } |
296 | ||
0e078e2f TG |
297 | /** |
298 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
299 | */ | |
e9427101 | 300 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 301 | { |
11a8e778 | 302 | unsigned int v; |
6935d1f9 TG |
303 | |
304 | /* unmask and set to NMI */ | |
305 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
306 | |
307 | /* Level triggered for 82489DX (32bit mode) */ | |
308 | if (!lapic_is_integrated()) | |
309 | v |= APIC_LVT_LEVEL_TRIGGER; | |
310 | ||
11a8e778 | 311 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
312 | } |
313 | ||
7c37e48b CG |
314 | #ifdef CONFIG_X86_32 |
315 | /** | |
316 | * get_physical_broadcast - Get number of physical broadcast IDs | |
317 | */ | |
318 | int get_physical_broadcast(void) | |
319 | { | |
320 | return modern_apic() ? 0xff : 0xf; | |
321 | } | |
322 | #endif | |
323 | ||
0e078e2f TG |
324 | /** |
325 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
326 | */ | |
37e650c7 | 327 | int lapic_get_maxlvt(void) |
1da177e4 | 328 | { |
36a028de | 329 | unsigned int v; |
1da177e4 LT |
330 | |
331 | v = apic_read(APIC_LVR); | |
36a028de CG |
332 | /* |
333 | * - we always have APIC integrated on 64bit mode | |
334 | * - 82489DXs do not report # of LVT entries | |
335 | */ | |
336 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
337 | } |
338 | ||
274cfe59 CG |
339 | /* |
340 | * Local APIC timer | |
341 | */ | |
342 | ||
c40aaec6 | 343 | /* Clock divisor */ |
c40aaec6 | 344 | #define APIC_DIVISOR 16 |
f07f4f90 | 345 | |
0e078e2f TG |
346 | /* |
347 | * This function sets up the local APIC timer, with a timeout of | |
348 | * 'clocks' APIC bus clock. During calibration we actually call | |
349 | * this function twice on the boot CPU, once with a bogus timeout | |
350 | * value, second time for real. The other (noncalibrating) CPUs | |
351 | * call this function only once, with the real, calibrated value. | |
352 | * | |
353 | * We do reads before writes even if unnecessary, to get around the | |
354 | * P5 APIC double write bug. | |
355 | */ | |
0e078e2f | 356 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 357 | { |
0e078e2f | 358 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 359 | |
0e078e2f TG |
360 | lvtt_value = LOCAL_TIMER_VECTOR; |
361 | if (!oneshot) | |
362 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
363 | if (!lapic_is_integrated()) |
364 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
365 | ||
0e078e2f TG |
366 | if (!irqen) |
367 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 368 | |
0e078e2f | 369 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
370 | |
371 | /* | |
0e078e2f | 372 | * Divide PICLK by 16 |
1da177e4 | 373 | */ |
0e078e2f | 374 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
375 | apic_write(APIC_TDCR, |
376 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
377 | APIC_TDR_DIV_16); | |
0e078e2f TG |
378 | |
379 | if (!oneshot) | |
f07f4f90 | 380 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
381 | } |
382 | ||
0e078e2f | 383 | /* |
7b83dae7 RR |
384 | * Setup extended LVT, AMD specific (K8, family 10h) |
385 | * | |
386 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
387 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
388 | * |
389 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
390 | * enables the vector. See also the BKDGs. | |
0e078e2f | 391 | */ |
7b83dae7 RR |
392 | |
393 | #define APIC_EILVT_LVTOFF_MCE 0 | |
394 | #define APIC_EILVT_LVTOFF_IBS 1 | |
395 | ||
396 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 397 | { |
7b83dae7 | 398 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 399 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 400 | |
0e078e2f | 401 | apic_write(reg, v); |
1da177e4 LT |
402 | } |
403 | ||
7b83dae7 RR |
404 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
405 | { | |
406 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
407 | return APIC_EILVT_LVTOFF_MCE; | |
408 | } | |
409 | ||
410 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
411 | { | |
412 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
413 | return APIC_EILVT_LVTOFF_IBS; | |
414 | } | |
6aa360e6 | 415 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 416 | |
0e078e2f TG |
417 | /* |
418 | * Program the next event, relative to now | |
419 | */ | |
420 | static int lapic_next_event(unsigned long delta, | |
421 | struct clock_event_device *evt) | |
1da177e4 | 422 | { |
0e078e2f TG |
423 | apic_write(APIC_TMICT, delta); |
424 | return 0; | |
1da177e4 LT |
425 | } |
426 | ||
0e078e2f TG |
427 | /* |
428 | * Setup the lapic timer in periodic or oneshot mode | |
429 | */ | |
430 | static void lapic_timer_setup(enum clock_event_mode mode, | |
431 | struct clock_event_device *evt) | |
9b7711f0 HS |
432 | { |
433 | unsigned long flags; | |
0e078e2f | 434 | unsigned int v; |
9b7711f0 | 435 | |
0e078e2f TG |
436 | /* Lapic used as dummy for broadcast ? */ |
437 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
438 | return; |
439 | ||
440 | local_irq_save(flags); | |
441 | ||
0e078e2f TG |
442 | switch (mode) { |
443 | case CLOCK_EVT_MODE_PERIODIC: | |
444 | case CLOCK_EVT_MODE_ONESHOT: | |
445 | __setup_APIC_LVTT(calibration_result, | |
446 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
447 | break; | |
448 | case CLOCK_EVT_MODE_UNUSED: | |
449 | case CLOCK_EVT_MODE_SHUTDOWN: | |
450 | v = apic_read(APIC_LVTT); | |
451 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
452 | apic_write(APIC_LVTT, v); | |
a98f8fd2 | 453 | apic_write(APIC_TMICT, 0xffffffff); |
0e078e2f TG |
454 | break; |
455 | case CLOCK_EVT_MODE_RESUME: | |
456 | /* Nothing to do here */ | |
457 | break; | |
458 | } | |
9b7711f0 HS |
459 | |
460 | local_irq_restore(flags); | |
461 | } | |
462 | ||
1da177e4 | 463 | /* |
0e078e2f | 464 | * Local APIC timer broadcast function |
1da177e4 | 465 | */ |
9628937d | 466 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 467 | { |
0e078e2f | 468 | #ifdef CONFIG_SMP |
dac5f412 | 469 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
470 | #endif |
471 | } | |
1da177e4 | 472 | |
0e078e2f TG |
473 | /* |
474 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
475 | * of the boot CPU and register the clock event in the framework. | |
476 | */ | |
db4b5525 | 477 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
478 | { |
479 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 480 | |
db954b58 VP |
481 | if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { |
482 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; | |
483 | /* Make LAPIC timer preferrable over percpu HPET */ | |
484 | lapic_clockevent.rating = 150; | |
485 | } | |
486 | ||
0e078e2f | 487 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 488 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 489 | |
0e078e2f TG |
490 | clockevents_register_device(levt); |
491 | } | |
1da177e4 | 492 | |
2f04fa88 YL |
493 | /* |
494 | * In this functions we calibrate APIC bus clocks to the external timer. | |
495 | * | |
496 | * We want to do the calibration only once since we want to have local timer | |
497 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
498 | * frequency. | |
499 | * | |
500 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
501 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
502 | * readout is broken, so it never gets out of the wait loop again. This was | |
503 | * also reported by others. | |
504 | * | |
505 | * Monitoring the jiffies value is inaccurate and the clockevents | |
506 | * infrastructure allows us to do a simple substitution of the interrupt | |
507 | * handler. | |
508 | * | |
509 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
510 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
511 | * back to normal later in the boot process). | |
512 | */ | |
513 | ||
514 | #define LAPIC_CAL_LOOPS (HZ/10) | |
515 | ||
516 | static __initdata int lapic_cal_loops = -1; | |
517 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
518 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
519 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
520 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
521 | ||
522 | /* | |
523 | * Temporary interrupt handler. | |
524 | */ | |
525 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
526 | { | |
527 | unsigned long long tsc = 0; | |
528 | long tapic = apic_read(APIC_TMCCT); | |
529 | unsigned long pm = acpi_pm_read_early(); | |
530 | ||
531 | if (cpu_has_tsc) | |
532 | rdtscll(tsc); | |
533 | ||
534 | switch (lapic_cal_loops++) { | |
535 | case 0: | |
536 | lapic_cal_t1 = tapic; | |
537 | lapic_cal_tsc1 = tsc; | |
538 | lapic_cal_pm1 = pm; | |
539 | lapic_cal_j1 = jiffies; | |
540 | break; | |
541 | ||
542 | case LAPIC_CAL_LOOPS: | |
543 | lapic_cal_t2 = tapic; | |
544 | lapic_cal_tsc2 = tsc; | |
545 | if (pm < lapic_cal_pm1) | |
546 | pm += ACPI_PM_OVRRUN; | |
547 | lapic_cal_pm2 = pm; | |
548 | lapic_cal_j2 = jiffies; | |
549 | break; | |
550 | } | |
551 | } | |
552 | ||
754ef0cd YI |
553 | static int __init |
554 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
555 | { |
556 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
557 | const long pm_thresh = pm_100ms / 100; | |
558 | unsigned long mult; | |
559 | u64 res; | |
560 | ||
561 | #ifndef CONFIG_X86_PM_TIMER | |
562 | return -1; | |
563 | #endif | |
564 | ||
39ba5d43 | 565 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
566 | |
567 | /* Check, if the PM timer is available */ | |
568 | if (!deltapm) | |
569 | return -1; | |
570 | ||
571 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
572 | ||
573 | if (deltapm > (pm_100ms - pm_thresh) && | |
574 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 575 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
576 | return 0; |
577 | } | |
578 | ||
579 | res = (((u64)deltapm) * mult) >> 22; | |
580 | do_div(res, 1000000); | |
581 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 582 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
583 | |
584 | /* Correct the lapic counter value */ | |
585 | res = (((u64)(*delta)) * pm_100ms); | |
586 | do_div(res, deltapm); | |
587 | pr_info("APIC delta adjusted to PM-Timer: " | |
588 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
589 | *delta = (long)res; | |
590 | ||
591 | /* Correct the tsc counter value */ | |
592 | if (cpu_has_tsc) { | |
593 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 594 | do_div(res, deltapm); |
754ef0cd YI |
595 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
596 | "PM-Timer: %lu (%ld) \n", | |
597 | (unsigned long)res, *deltatsc); | |
598 | *deltatsc = (long)res; | |
b189892d CG |
599 | } |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
2f04fa88 YL |
604 | static int __init calibrate_APIC_clock(void) |
605 | { | |
606 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
607 | void (*real_handler)(struct clock_event_device *dev); |
608 | unsigned long deltaj; | |
754ef0cd | 609 | long delta, deltatsc; |
2f04fa88 YL |
610 | int pm_referenced = 0; |
611 | ||
612 | local_irq_disable(); | |
613 | ||
614 | /* Replace the global interrupt handler */ | |
615 | real_handler = global_clock_event->event_handler; | |
616 | global_clock_event->event_handler = lapic_cal_handler; | |
617 | ||
618 | /* | |
81608f3c | 619 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
620 | * can underflow in the 100ms detection time frame |
621 | */ | |
81608f3c | 622 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
623 | |
624 | /* Let the interrupts run */ | |
625 | local_irq_enable(); | |
626 | ||
627 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
628 | cpu_relax(); | |
629 | ||
630 | local_irq_disable(); | |
631 | ||
632 | /* Restore the real event handler */ | |
633 | global_clock_event->event_handler = real_handler; | |
634 | ||
635 | /* Build delta t1-t2 as apic timer counts down */ | |
636 | delta = lapic_cal_t1 - lapic_cal_t2; | |
637 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
638 | ||
754ef0cd YI |
639 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
640 | ||
b189892d CG |
641 | /* we trust the PM based calibration if possible */ |
642 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 643 | &delta, &deltatsc); |
2f04fa88 YL |
644 | |
645 | /* Calculate the scaled math multiplication factor */ | |
646 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
647 | lapic_clockevent.shift); | |
648 | lapic_clockevent.max_delta_ns = | |
649 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
650 | lapic_clockevent.min_delta_ns = | |
651 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
652 | ||
653 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
654 | ||
655 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
656 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); | |
657 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", | |
658 | calibration_result); | |
659 | ||
660 | if (cpu_has_tsc) { | |
2f04fa88 YL |
661 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
662 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
663 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
664 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
665 | } |
666 | ||
667 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
668 | "%u.%04u MHz.\n", | |
669 | calibration_result / (1000000 / HZ), | |
670 | calibration_result % (1000000 / HZ)); | |
671 | ||
672 | /* | |
673 | * Do a sanity check on the APIC calibration result | |
674 | */ | |
675 | if (calibration_result < (1000000 / HZ)) { | |
676 | local_irq_enable(); | |
ba21ebb6 | 677 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
678 | return -1; |
679 | } | |
680 | ||
681 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
682 | ||
b189892d CG |
683 | /* |
684 | * PM timer calibration failed or not turned on | |
685 | * so lets try APIC timer based calibration | |
686 | */ | |
2f04fa88 YL |
687 | if (!pm_referenced) { |
688 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
689 | ||
690 | /* | |
691 | * Setup the apic timer manually | |
692 | */ | |
693 | levt->event_handler = lapic_cal_handler; | |
694 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
695 | lapic_cal_loops = -1; | |
696 | ||
697 | /* Let the interrupts run */ | |
698 | local_irq_enable(); | |
699 | ||
700 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
701 | cpu_relax(); | |
702 | ||
2f04fa88 YL |
703 | /* Stop the lapic timer */ |
704 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
705 | ||
2f04fa88 YL |
706 | /* Jiffies delta */ |
707 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
708 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
709 | ||
710 | /* Check, if the jiffies result is consistent */ | |
711 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
712 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
713 | else | |
714 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
715 | } else | |
716 | local_irq_enable(); | |
717 | ||
718 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 719 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
720 | return -1; |
721 | } | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
e83a5fdc HS |
726 | /* |
727 | * Setup the boot APIC | |
728 | * | |
729 | * Calibrate and verify the result. | |
730 | */ | |
0e078e2f TG |
731 | void __init setup_boot_APIC_clock(void) |
732 | { | |
733 | /* | |
274cfe59 CG |
734 | * The local apic timer can be disabled via the kernel |
735 | * commandline or from the CPU detection code. Register the lapic | |
736 | * timer as a dummy clock event source on SMP systems, so the | |
737 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
738 | */ |
739 | if (disable_apic_timer) { | |
ba21ebb6 | 740 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 741 | /* No broadcast on UP ! */ |
9d09951d TG |
742 | if (num_possible_cpus() > 1) { |
743 | lapic_clockevent.mult = 1; | |
0e078e2f | 744 | setup_APIC_timer(); |
9d09951d | 745 | } |
0e078e2f TG |
746 | return; |
747 | } | |
748 | ||
274cfe59 CG |
749 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
750 | "calibrating APIC timer ...\n"); | |
751 | ||
89b3b1f4 | 752 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
753 | /* No broadcast on UP ! */ |
754 | if (num_possible_cpus() > 1) | |
755 | setup_APIC_timer(); | |
756 | return; | |
757 | } | |
758 | ||
0e078e2f TG |
759 | /* |
760 | * If nmi_watchdog is set to IO_APIC, we need the | |
761 | * PIT/HPET going. Otherwise register lapic as a dummy | |
762 | * device. | |
763 | */ | |
764 | if (nmi_watchdog != NMI_IO_APIC) | |
765 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
766 | else | |
ba21ebb6 | 767 | pr_warning("APIC timer registered as dummy," |
116f570e | 768 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 769 | |
274cfe59 | 770 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
771 | setup_APIC_timer(); |
772 | } | |
773 | ||
0e078e2f TG |
774 | void __cpuinit setup_secondary_APIC_clock(void) |
775 | { | |
0e078e2f TG |
776 | setup_APIC_timer(); |
777 | } | |
778 | ||
779 | /* | |
780 | * The guts of the apic timer interrupt | |
781 | */ | |
782 | static void local_apic_timer_interrupt(void) | |
783 | { | |
784 | int cpu = smp_processor_id(); | |
785 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
786 | ||
787 | /* | |
788 | * Normally we should not be here till LAPIC has been initialized but | |
789 | * in some cases like kdump, its possible that there is a pending LAPIC | |
790 | * timer interrupt from previous kernel's context and is delivered in | |
791 | * new kernel the moment interrupts are enabled. | |
792 | * | |
793 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
794 | * its possible that when we get here evt->event_handler is NULL. | |
795 | * Check for event_handler being NULL and discard the interrupt as | |
796 | * spurious. | |
797 | */ | |
798 | if (!evt->event_handler) { | |
ba21ebb6 | 799 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
800 | /* Switch it off */ |
801 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
802 | return; | |
803 | } | |
804 | ||
805 | /* | |
806 | * the NMI deadlock-detector uses this. | |
807 | */ | |
915b0d01 | 808 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
809 | |
810 | evt->event_handler(evt); | |
811 | } | |
812 | ||
813 | /* | |
814 | * Local APIC timer interrupt. This is the most natural way for doing | |
815 | * local interrupts, but local timer interrupts can be emulated by | |
816 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
817 | * | |
818 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
819 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
820 | */ | |
bcbc4f20 | 821 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
822 | { |
823 | struct pt_regs *old_regs = set_irq_regs(regs); | |
824 | ||
825 | /* | |
826 | * NOTE! We'd better ACK the irq immediately, | |
827 | * because timer handling can be slow. | |
828 | */ | |
829 | ack_APIC_irq(); | |
830 | /* | |
831 | * update_process_times() expects us to have done irq_enter(). | |
832 | * Besides, if we don't timer interrupts ignore the global | |
833 | * interrupt lock, which is the WrongThing (tm) to do. | |
834 | */ | |
835 | exit_idle(); | |
836 | irq_enter(); | |
837 | local_apic_timer_interrupt(); | |
838 | irq_exit(); | |
274cfe59 | 839 | |
0e078e2f TG |
840 | set_irq_regs(old_regs); |
841 | } | |
842 | ||
843 | int setup_profiling_timer(unsigned int multiplier) | |
844 | { | |
845 | return -EINVAL; | |
846 | } | |
847 | ||
0e078e2f TG |
848 | /* |
849 | * Local APIC start and shutdown | |
850 | */ | |
851 | ||
852 | /** | |
853 | * clear_local_APIC - shutdown the local APIC | |
854 | * | |
855 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
856 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
857 | * leftovers during boot. | |
858 | */ | |
859 | void clear_local_APIC(void) | |
860 | { | |
2584a82d | 861 | int maxlvt; |
0e078e2f TG |
862 | u32 v; |
863 | ||
d3432896 | 864 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 865 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
866 | return; |
867 | ||
868 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
869 | /* |
870 | * Masking an LVT entry can trigger a local APIC error | |
871 | * if the vector is zero. Mask LVTERR first to prevent this. | |
872 | */ | |
873 | if (maxlvt >= 3) { | |
874 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
875 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
876 | } | |
877 | /* | |
878 | * Careful: we have to set masks only first to deassert | |
879 | * any level-triggered sources. | |
880 | */ | |
881 | v = apic_read(APIC_LVTT); | |
882 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
883 | v = apic_read(APIC_LVT0); | |
884 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
885 | v = apic_read(APIC_LVT1); | |
886 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
887 | if (maxlvt >= 4) { | |
888 | v = apic_read(APIC_LVTPC); | |
889 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
890 | } | |
891 | ||
6764014b | 892 | /* lets not touch this if we didn't frob it */ |
07db1c14 | 893 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
6764014b CG |
894 | if (maxlvt >= 5) { |
895 | v = apic_read(APIC_LVTTHMR); | |
896 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
897 | } | |
898 | #endif | |
5ca8681c AK |
899 | #ifdef CONFIG_X86_MCE_INTEL |
900 | if (maxlvt >= 6) { | |
901 | v = apic_read(APIC_LVTCMCI); | |
902 | if (!(v & APIC_LVT_MASKED)) | |
903 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
904 | } | |
905 | #endif | |
906 | ||
0e078e2f TG |
907 | /* |
908 | * Clean APIC state for other OSs: | |
909 | */ | |
910 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
911 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
912 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
913 | if (maxlvt >= 3) | |
914 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
915 | if (maxlvt >= 4) | |
916 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
917 | |
918 | /* Integrated APIC (!82489DX) ? */ | |
919 | if (lapic_is_integrated()) { | |
920 | if (maxlvt > 3) | |
921 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
922 | apic_write(APIC_ESR, 0); | |
923 | apic_read(APIC_ESR); | |
924 | } | |
0e078e2f TG |
925 | } |
926 | ||
927 | /** | |
928 | * disable_local_APIC - clear and disable the local APIC | |
929 | */ | |
930 | void disable_local_APIC(void) | |
931 | { | |
932 | unsigned int value; | |
933 | ||
4a13ad0b JB |
934 | /* APIC hasn't been mapped yet */ |
935 | if (!apic_phys) | |
936 | return; | |
937 | ||
0e078e2f TG |
938 | clear_local_APIC(); |
939 | ||
940 | /* | |
941 | * Disable APIC (implies clearing of registers | |
942 | * for 82489DX!). | |
943 | */ | |
944 | value = apic_read(APIC_SPIV); | |
945 | value &= ~APIC_SPIV_APIC_ENABLED; | |
946 | apic_write(APIC_SPIV, value); | |
990b183e CG |
947 | |
948 | #ifdef CONFIG_X86_32 | |
949 | /* | |
950 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
951 | * restore the disabled state. | |
952 | */ | |
953 | if (enabled_via_apicbase) { | |
954 | unsigned int l, h; | |
955 | ||
956 | rdmsr(MSR_IA32_APICBASE, l, h); | |
957 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
958 | wrmsr(MSR_IA32_APICBASE, l, h); | |
959 | } | |
960 | #endif | |
0e078e2f TG |
961 | } |
962 | ||
fe4024dc CG |
963 | /* |
964 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
965 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
966 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
967 | * for the case where Linux didn't enable the LAPIC. | |
968 | */ | |
0e078e2f TG |
969 | void lapic_shutdown(void) |
970 | { | |
971 | unsigned long flags; | |
972 | ||
973 | if (!cpu_has_apic) | |
974 | return; | |
975 | ||
976 | local_irq_save(flags); | |
977 | ||
fe4024dc CG |
978 | #ifdef CONFIG_X86_32 |
979 | if (!enabled_via_apicbase) | |
980 | clear_local_APIC(); | |
981 | else | |
982 | #endif | |
983 | disable_local_APIC(); | |
984 | ||
0e078e2f TG |
985 | |
986 | local_irq_restore(flags); | |
987 | } | |
988 | ||
989 | /* | |
990 | * This is to verify that we're looking at a real local APIC. | |
991 | * Check these against your board if the CPUs aren't getting | |
992 | * started for no apparent reason. | |
993 | */ | |
994 | int __init verify_local_APIC(void) | |
995 | { | |
996 | unsigned int reg0, reg1; | |
997 | ||
998 | /* | |
999 | * The version register is read-only in a real APIC. | |
1000 | */ | |
1001 | reg0 = apic_read(APIC_LVR); | |
1002 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
1003 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
1004 | reg1 = apic_read(APIC_LVR); | |
1005 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
1006 | ||
1007 | /* | |
1008 | * The two version reads above should print the same | |
1009 | * numbers. If the second one is different, then we | |
1010 | * poke at a non-APIC. | |
1011 | */ | |
1012 | if (reg1 != reg0) | |
1013 | return 0; | |
1014 | ||
1015 | /* | |
1016 | * Check if the version looks reasonably. | |
1017 | */ | |
1018 | reg1 = GET_APIC_VERSION(reg0); | |
1019 | if (reg1 == 0x00 || reg1 == 0xff) | |
1020 | return 0; | |
1021 | reg1 = lapic_get_maxlvt(); | |
1022 | if (reg1 < 0x02 || reg1 == 0xff) | |
1023 | return 0; | |
1024 | ||
1025 | /* | |
1026 | * The ID register is read/write in a real APIC. | |
1027 | */ | |
2d7a66d0 | 1028 | reg0 = apic_read(APIC_ID); |
0e078e2f | 1029 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
5b812727 | 1030 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
2d7a66d0 | 1031 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1032 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1033 | apic_write(APIC_ID, reg0); | |
5b812727 | 1034 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
0e078e2f TG |
1035 | return 0; |
1036 | ||
1037 | /* | |
1da177e4 LT |
1038 | * The next two are just to see if we have sane values. |
1039 | * They're only really relevant if we're in Virtual Wire | |
1040 | * compatibility mode, but most boxes are anymore. | |
1041 | */ | |
1042 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1043 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1044 | reg1 = apic_read(APIC_LVT1); |
1045 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1046 | ||
1047 | return 1; | |
1048 | } | |
1049 | ||
0e078e2f TG |
1050 | /** |
1051 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1052 | */ | |
1da177e4 LT |
1053 | void __init sync_Arb_IDs(void) |
1054 | { | |
296cb951 CG |
1055 | /* |
1056 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1057 | * needed on AMD. | |
1058 | */ | |
1059 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1060 | return; |
1061 | ||
1062 | /* | |
1063 | * Wait for idle. | |
1064 | */ | |
1065 | apic_wait_icr_idle(); | |
1066 | ||
1067 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1068 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1069 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1070 | } |
1071 | ||
1da177e4 LT |
1072 | /* |
1073 | * An initial setup of the virtual wire mode. | |
1074 | */ | |
1075 | void __init init_bsp_APIC(void) | |
1076 | { | |
11a8e778 | 1077 | unsigned int value; |
1da177e4 LT |
1078 | |
1079 | /* | |
1080 | * Don't do the setup now if we have a SMP BIOS as the | |
1081 | * through-I/O-APIC virtual wire mode might be active. | |
1082 | */ | |
1083 | if (smp_found_config || !cpu_has_apic) | |
1084 | return; | |
1085 | ||
1da177e4 LT |
1086 | /* |
1087 | * Do not trust the local APIC being empty at bootup. | |
1088 | */ | |
1089 | clear_local_APIC(); | |
1090 | ||
1091 | /* | |
1092 | * Enable APIC. | |
1093 | */ | |
1094 | value = apic_read(APIC_SPIV); | |
1095 | value &= ~APIC_VECTOR_MASK; | |
1096 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1097 | |
1098 | #ifdef CONFIG_X86_32 | |
1099 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1100 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1101 | (boot_cpu_data.x86 == 15)) | |
1102 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1103 | else | |
1104 | #endif | |
1105 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1106 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1107 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1108 | |
1109 | /* | |
1110 | * Set up the virtual wire mode. | |
1111 | */ | |
11a8e778 | 1112 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1113 | value = APIC_DM_NMI; |
638c0411 CG |
1114 | if (!lapic_is_integrated()) /* 82489DX */ |
1115 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1116 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1117 | } |
1118 | ||
c43da2f5 CG |
1119 | static void __cpuinit lapic_setup_esr(void) |
1120 | { | |
9df08f10 CG |
1121 | unsigned int oldvalue, value, maxlvt; |
1122 | ||
1123 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1124 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1125 | return; |
1126 | } | |
c43da2f5 | 1127 | |
08125d3e | 1128 | if (apic->disable_esr) { |
c43da2f5 | 1129 | /* |
9df08f10 CG |
1130 | * Something untraceable is creating bad interrupts on |
1131 | * secondary quads ... for the moment, just leave the | |
1132 | * ESR disabled - we can't do anything useful with the | |
1133 | * errors anyway - mbligh | |
c43da2f5 | 1134 | */ |
ba21ebb6 | 1135 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1136 | return; |
c43da2f5 | 1137 | } |
9df08f10 CG |
1138 | |
1139 | maxlvt = lapic_get_maxlvt(); | |
1140 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1141 | apic_write(APIC_ESR, 0); | |
1142 | oldvalue = apic_read(APIC_ESR); | |
1143 | ||
1144 | /* enables sending errors */ | |
1145 | value = ERROR_APIC_VECTOR; | |
1146 | apic_write(APIC_LVTERR, value); | |
1147 | ||
1148 | /* | |
1149 | * spec says clear errors after enabling vector. | |
1150 | */ | |
1151 | if (maxlvt > 3) | |
1152 | apic_write(APIC_ESR, 0); | |
1153 | value = apic_read(APIC_ESR); | |
1154 | if (value != oldvalue) | |
1155 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1156 | "vector: 0x%08x after: 0x%08x\n", | |
1157 | oldvalue, value); | |
c43da2f5 CG |
1158 | } |
1159 | ||
1160 | ||
0e078e2f TG |
1161 | /** |
1162 | * setup_local_APIC - setup the local APIC | |
1163 | */ | |
1164 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1165 | { |
739f33b3 | 1166 | unsigned int value; |
da7ed9f9 | 1167 | int i, j; |
1da177e4 | 1168 | |
f1182638 | 1169 | if (disable_apic) { |
65a4e574 | 1170 | arch_disable_smp_support(); |
f1182638 JB |
1171 | return; |
1172 | } | |
1173 | ||
89c38c28 CG |
1174 | #ifdef CONFIG_X86_32 |
1175 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1176 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1177 | apic_write(APIC_ESR, 0); |
1178 | apic_write(APIC_ESR, 0); | |
1179 | apic_write(APIC_ESR, 0); | |
1180 | apic_write(APIC_ESR, 0); | |
1181 | } | |
1182 | #endif | |
1183 | ||
ac23d4ee | 1184 | preempt_disable(); |
1da177e4 | 1185 | |
1da177e4 LT |
1186 | /* |
1187 | * Double-check whether this APIC is really registered. | |
1188 | * This is meaningless in clustered apic mode, so we skip it. | |
1189 | */ | |
7ed248da | 1190 | if (!apic->apic_id_registered()) |
1da177e4 LT |
1191 | BUG(); |
1192 | ||
1193 | /* | |
1194 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1195 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1196 | * document number 292116). So here it goes... | |
1197 | */ | |
a5c43296 | 1198 | apic->init_apic_ldr(); |
1da177e4 LT |
1199 | |
1200 | /* | |
1201 | * Set Task Priority to 'accept all'. We never change this | |
1202 | * later on. | |
1203 | */ | |
1204 | value = apic_read(APIC_TASKPRI); | |
1205 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1206 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1207 | |
da7ed9f9 VG |
1208 | /* |
1209 | * After a crash, we no longer service the interrupts and a pending | |
1210 | * interrupt from previous kernel might still have ISR bit set. | |
1211 | * | |
1212 | * Most probably by now CPU has serviced that pending interrupt and | |
1213 | * it might not have done the ack_APIC_irq() because it thought, | |
1214 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1215 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1216 | * the interrupt. Hence a vector might get locked. It was noticed | |
1217 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1218 | */ | |
1219 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1220 | value = apic_read(APIC_ISR + i*0x10); | |
1221 | for (j = 31; j >= 0; j--) { | |
1222 | if (value & (1<<j)) | |
1223 | ack_APIC_irq(); | |
1224 | } | |
1225 | } | |
1226 | ||
1da177e4 LT |
1227 | /* |
1228 | * Now that we are all set up, enable the APIC | |
1229 | */ | |
1230 | value = apic_read(APIC_SPIV); | |
1231 | value &= ~APIC_VECTOR_MASK; | |
1232 | /* | |
1233 | * Enable APIC | |
1234 | */ | |
1235 | value |= APIC_SPIV_APIC_ENABLED; | |
1236 | ||
89c38c28 CG |
1237 | #ifdef CONFIG_X86_32 |
1238 | /* | |
1239 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1240 | * certain networking cards. If high frequency interrupts are | |
1241 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1242 | * entry is masked/unmasked at a high rate as well then sooner or | |
1243 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1244 | * from the device. If focus CPU is disabled then the hang goes | |
1245 | * away, oh well :-( | |
1246 | * | |
1247 | * [ This bug can be reproduced easily with a level-triggered | |
1248 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1249 | * BX chipset. ] | |
1250 | */ | |
1251 | /* | |
1252 | * Actually disabling the focus CPU check just makes the hang less | |
1253 | * frequent as it makes the interrupt distributon model be more | |
1254 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1255 | * See also the comment in end_level_ioapic_irq(). --macro | |
1256 | */ | |
1257 | ||
1258 | /* | |
1259 | * - enable focus processor (bit==0) | |
1260 | * - 64bit mode always use processor focus | |
1261 | * so no need to set it | |
1262 | */ | |
1263 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1264 | #endif | |
3f14c746 | 1265 | |
1da177e4 LT |
1266 | /* |
1267 | * Set spurious IRQ vector | |
1268 | */ | |
1269 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1270 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1271 | |
1272 | /* | |
1273 | * Set up LVT0, LVT1: | |
1274 | * | |
1275 | * set up through-local-APIC on the BP's LINT0. This is not | |
1276 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1277 | * we delegate interrupts to the 8259A. | |
1278 | */ | |
1279 | /* | |
1280 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1281 | */ | |
1282 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1283 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1284 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1285 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1286 | smp_processor_id()); |
1da177e4 LT |
1287 | } else { |
1288 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1289 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1290 | smp_processor_id()); |
1da177e4 | 1291 | } |
11a8e778 | 1292 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1293 | |
1294 | /* | |
1295 | * only the BP should see the LINT1 NMI signal, obviously. | |
1296 | */ | |
1297 | if (!smp_processor_id()) | |
1298 | value = APIC_DM_NMI; | |
1299 | else | |
1300 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1301 | if (!lapic_is_integrated()) /* 82489DX */ |
1302 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1303 | apic_write(APIC_LVT1, value); |
89c38c28 | 1304 | |
ac23d4ee | 1305 | preempt_enable(); |
be71b855 AK |
1306 | |
1307 | #ifdef CONFIG_X86_MCE_INTEL | |
1308 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
1309 | if (smp_processor_id() == 0) | |
1310 | cmci_recheck(); | |
1311 | #endif | |
739f33b3 | 1312 | } |
1da177e4 | 1313 | |
739f33b3 AK |
1314 | void __cpuinit end_local_APIC_setup(void) |
1315 | { | |
1316 | lapic_setup_esr(); | |
fa6b95fc CG |
1317 | |
1318 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1319 | { |
1320 | unsigned int value; | |
1321 | /* Disable the local apic timer */ | |
1322 | value = apic_read(APIC_LVTT); | |
1323 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1324 | apic_write(APIC_LVTT, value); | |
1325 | } | |
fa6b95fc CG |
1326 | #endif |
1327 | ||
f2802e7f | 1328 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1329 | apic_pm_activate(); |
1da177e4 | 1330 | } |
1da177e4 | 1331 | |
06cd9a7d | 1332 | #ifdef CONFIG_X86_X2APIC |
6e1cb38a SS |
1333 | void check_x2apic(void) |
1334 | { | |
ef1f87aa | 1335 | if (x2apic_enabled()) { |
ba21ebb6 | 1336 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
fc1edaf9 | 1337 | x2apic_preenabled = x2apic_mode = 1; |
6e1cb38a SS |
1338 | } |
1339 | } | |
1340 | ||
1341 | void enable_x2apic(void) | |
1342 | { | |
1343 | int msr, msr2; | |
1344 | ||
fc1edaf9 | 1345 | if (!x2apic_mode) |
06cd9a7d YL |
1346 | return; |
1347 | ||
6e1cb38a SS |
1348 | rdmsr(MSR_IA32_APICBASE, msr, msr2); |
1349 | if (!(msr & X2APIC_ENABLE)) { | |
ba21ebb6 | 1350 | pr_info("Enabling x2apic\n"); |
6e1cb38a SS |
1351 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1352 | } | |
1353 | } | |
93758238 | 1354 | #endif /* CONFIG_X86_X2APIC */ |
6e1cb38a | 1355 | |
2236d252 | 1356 | void __init enable_IR_x2apic(void) |
6e1cb38a SS |
1357 | { |
1358 | #ifdef CONFIG_INTR_REMAP | |
1359 | int ret; | |
1360 | unsigned long flags; | |
b24696bc | 1361 | struct IO_APIC_route_entry **ioapic_entries = NULL; |
6e1cb38a | 1362 | |
93758238 WH |
1363 | ret = dmar_table_init(); |
1364 | if (ret) { | |
1365 | pr_debug("dmar_table_init() failed with %d:\n", ret); | |
1366 | goto ir_failed; | |
6e1cb38a SS |
1367 | } |
1368 | ||
93758238 WH |
1369 | if (!intr_remapping_supported()) { |
1370 | pr_debug("intr-remapping not supported\n"); | |
1371 | goto ir_failed; | |
6e1cb38a SS |
1372 | } |
1373 | ||
6e1cb38a | 1374 | |
93758238 WH |
1375 | if (!x2apic_preenabled && skip_ioapic_setup) { |
1376 | pr_info("Skipped enabling intr-remap because of skipping " | |
1377 | "io-apic setup\n"); | |
6e1cb38a SS |
1378 | return; |
1379 | } | |
1380 | ||
b24696bc FY |
1381 | ioapic_entries = alloc_ioapic_entries(); |
1382 | if (!ioapic_entries) { | |
1383 | pr_info("Allocate ioapic_entries failed: %d\n", ret); | |
1384 | goto end; | |
1385 | } | |
1386 | ||
1387 | ret = save_IO_APIC_setup(ioapic_entries); | |
5ffa4eb2 | 1388 | if (ret) { |
ba21ebb6 | 1389 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
5ffa4eb2 CG |
1390 | goto end; |
1391 | } | |
6e1cb38a | 1392 | |
05c3dc2c | 1393 | local_irq_save(flags); |
b24696bc | 1394 | mask_IO_APIC_setup(ioapic_entries); |
05c3dc2c SS |
1395 | mask_8259A(); |
1396 | ||
fc1edaf9 | 1397 | ret = enable_intr_remapping(x2apic_supported()); |
6e1cb38a | 1398 | if (ret) |
5ffa4eb2 | 1399 | goto end_restore; |
6e1cb38a | 1400 | |
93758238 WH |
1401 | pr_info("Enabled Interrupt-remapping\n"); |
1402 | ||
fc1edaf9 SS |
1403 | if (x2apic_supported() && !x2apic_mode) { |
1404 | x2apic_mode = 1; | |
6e1cb38a | 1405 | enable_x2apic(); |
93758238 | 1406 | pr_info("Enabled x2apic\n"); |
6e1cb38a | 1407 | } |
5ffa4eb2 CG |
1408 | |
1409 | end_restore: | |
6e1cb38a SS |
1410 | if (ret) |
1411 | /* | |
1412 | * IR enabling failed | |
1413 | */ | |
b24696bc | 1414 | restore_IO_APIC_setup(ioapic_entries); |
6e1cb38a SS |
1415 | |
1416 | unmask_8259A(); | |
1417 | local_irq_restore(flags); | |
1418 | ||
05c3dc2c | 1419 | end: |
b24696bc FY |
1420 | if (ioapic_entries) |
1421 | free_ioapic_entries(ioapic_entries); | |
93758238 WH |
1422 | |
1423 | if (!ret) | |
1424 | return; | |
1425 | ||
1426 | ir_failed: | |
1427 | if (x2apic_preenabled) | |
1428 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1429 | else if (cpu_has_x2apic) | |
1430 | pr_info("Not enabling x2apic,Intr-remapping\n"); | |
6e1cb38a SS |
1431 | #else |
1432 | if (!cpu_has_x2apic) | |
1433 | return; | |
1434 | ||
1435 | if (x2apic_preenabled) | |
1436 | panic("x2apic enabled prior OS handover," | |
93758238 | 1437 | " enable CONFIG_X86_X2APIC, CONFIG_INTR_REMAP"); |
6e1cb38a SS |
1438 | #endif |
1439 | ||
1440 | return; | |
1441 | } | |
93758238 | 1442 | |
6e1cb38a | 1443 | |
be7a656f | 1444 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1445 | /* |
1446 | * Detect and enable local APICs on non-SMP boards. | |
1447 | * Original code written by Keir Fraser. | |
1448 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1449 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1450 | */ |
0e078e2f | 1451 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1452 | { |
1453 | if (!cpu_has_apic) { | |
ba21ebb6 | 1454 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1455 | return -1; |
1456 | } | |
1457 | ||
1458 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1459 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1460 | return 0; |
1461 | } | |
be7a656f YL |
1462 | #else |
1463 | /* | |
1464 | * Detect and initialize APIC | |
1465 | */ | |
1466 | static int __init detect_init_APIC(void) | |
1467 | { | |
1468 | u32 h, l, features; | |
1469 | ||
1470 | /* Disabled by kernel option? */ | |
1471 | if (disable_apic) | |
1472 | return -1; | |
1473 | ||
1474 | switch (boot_cpu_data.x86_vendor) { | |
1475 | case X86_VENDOR_AMD: | |
1476 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1477 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1478 | break; |
1479 | goto no_apic; | |
1480 | case X86_VENDOR_INTEL: | |
1481 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1482 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1483 | break; | |
1484 | goto no_apic; | |
1485 | default: | |
1486 | goto no_apic; | |
1487 | } | |
1488 | ||
1489 | if (!cpu_has_apic) { | |
1490 | /* | |
1491 | * Over-ride BIOS and try to enable the local APIC only if | |
1492 | * "lapic" specified. | |
1493 | */ | |
1494 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1495 | pr_info("Local APIC disabled by BIOS -- " |
1496 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1497 | return -1; |
1498 | } | |
1499 | /* | |
1500 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1501 | * MSR. This can only be done in software for Intel P6 or later | |
1502 | * and AMD K7 (Model > 1) or later. | |
1503 | */ | |
1504 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1505 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
ba21ebb6 | 1506 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
be7a656f YL |
1507 | l &= ~MSR_IA32_APICBASE_BASE; |
1508 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1509 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1510 | enabled_via_apicbase = 1; | |
1511 | } | |
1512 | } | |
1513 | /* | |
1514 | * The APIC feature bit should now be enabled | |
1515 | * in `cpuid' | |
1516 | */ | |
1517 | features = cpuid_edx(1); | |
1518 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
ba21ebb6 | 1519 | pr_warning("Could not enable APIC!\n"); |
be7a656f YL |
1520 | return -1; |
1521 | } | |
1522 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1523 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1524 | ||
1525 | /* The BIOS may have set up the APIC at some other address */ | |
1526 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1527 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1528 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1529 | ||
ba21ebb6 | 1530 | pr_info("Found and enabled local APIC!\n"); |
be7a656f YL |
1531 | |
1532 | apic_pm_activate(); | |
1533 | ||
1534 | return 0; | |
1535 | ||
1536 | no_apic: | |
ba21ebb6 | 1537 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1538 | return -1; |
1539 | } | |
1540 | #endif | |
1da177e4 | 1541 | |
f28c0ae2 | 1542 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1543 | void __init early_init_lapic_mapping(void) |
1544 | { | |
431ee79d | 1545 | unsigned long phys_addr; |
8643f9d0 YL |
1546 | |
1547 | /* | |
1548 | * If no local APIC can be found then go out | |
1549 | * : it means there is no mpatable and MADT | |
1550 | */ | |
1551 | if (!smp_found_config) | |
1552 | return; | |
1553 | ||
431ee79d | 1554 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1555 | |
431ee79d | 1556 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1557 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1558 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1559 | |
1560 | /* | |
1561 | * Fetch the APIC ID of the BSP in case we have a | |
1562 | * default configuration (or the MP table is broken). | |
1563 | */ | |
4c9961d5 | 1564 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1565 | } |
f28c0ae2 | 1566 | #endif |
8643f9d0 | 1567 | |
0e078e2f TG |
1568 | /** |
1569 | * init_apic_mappings - initialize APIC mappings | |
1570 | */ | |
1da177e4 LT |
1571 | void __init init_apic_mappings(void) |
1572 | { | |
fc1edaf9 | 1573 | if (x2apic_mode) { |
4c9961d5 | 1574 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1575 | return; |
1576 | } | |
1577 | ||
1da177e4 LT |
1578 | /* |
1579 | * If no local APIC can be found then set up a fake all | |
1580 | * zeroes page to simulate the local APIC and another | |
1581 | * one for the IO-APIC. | |
1582 | */ | |
1583 | if (!smp_found_config && detect_init_APIC()) { | |
1584 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1585 | apic_phys = __pa(apic_phys); | |
1586 | } else | |
1587 | apic_phys = mp_lapic_addr; | |
1588 | ||
1589 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
79c09698 | 1590 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
7ffeeb1e | 1591 | APIC_BASE, apic_phys); |
1da177e4 LT |
1592 | |
1593 | /* | |
1594 | * Fetch the APIC ID of the BSP in case we have a | |
1595 | * default configuration (or the MP table is broken). | |
1596 | */ | |
f28c0ae2 YL |
1597 | if (boot_cpu_physical_apicid == -1U) |
1598 | boot_cpu_physical_apicid = read_apic_id(); | |
08306ce6 CG |
1599 | |
1600 | /* lets check if we may to NOP'ify apic operations */ | |
1601 | if (!cpu_has_apic) { | |
1602 | pr_info("APIC: disable apic facility\n"); | |
1603 | apic_disable(); | |
1604 | } | |
1da177e4 LT |
1605 | } |
1606 | ||
1607 | /* | |
0e078e2f TG |
1608 | * This initializes the IO-APIC and APIC hardware if this is |
1609 | * a UP kernel. | |
1da177e4 | 1610 | */ |
1b313f4a CG |
1611 | int apic_version[MAX_APICS]; |
1612 | ||
0e078e2f | 1613 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1614 | { |
0e078e2f | 1615 | if (disable_apic) { |
ba21ebb6 | 1616 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1617 | return -1; |
1618 | } | |
f1182638 | 1619 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1620 | if (!cpu_has_apic) { |
1621 | disable_apic = 1; | |
ba21ebb6 | 1622 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1623 | return -1; |
1624 | } | |
fa2bd35a YL |
1625 | #else |
1626 | if (!smp_found_config && !cpu_has_apic) | |
1627 | return -1; | |
1628 | ||
1629 | /* | |
1630 | * Complain if the BIOS pretends there is one. | |
1631 | */ | |
1632 | if (!cpu_has_apic && | |
1633 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1634 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1635 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1636 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1637 | return -1; | |
1638 | } | |
1639 | #endif | |
1640 | ||
6e1cb38a | 1641 | enable_IR_x2apic(); |
fa2bd35a | 1642 | #ifdef CONFIG_X86_64 |
72ce0165 | 1643 | default_setup_apic_routing(); |
fa2bd35a | 1644 | #endif |
6e1cb38a | 1645 | |
0e078e2f | 1646 | verify_local_APIC(); |
b5841765 GC |
1647 | connect_bsp_APIC(); |
1648 | ||
fa2bd35a | 1649 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1650 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1651 | #else |
1652 | /* | |
1653 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1654 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1655 | * might be zero if read from MP tables. Get it from LAPIC. | |
1656 | */ | |
1657 | # ifdef CONFIG_CRASH_DUMP | |
1658 | boot_cpu_physical_apicid = read_apic_id(); | |
1659 | # endif | |
1660 | #endif | |
1661 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1662 | setup_local_APIC(); |
1da177e4 | 1663 | |
88d0f550 | 1664 | #ifdef CONFIG_X86_IO_APIC |
739f33b3 AK |
1665 | /* |
1666 | * Now enable IO-APICs, actually call clear_IO_APIC | |
98c061b6 | 1667 | * We need clear_IO_APIC before enabling error vector |
739f33b3 AK |
1668 | */ |
1669 | if (!skip_ioapic_setup && nr_ioapics) | |
1670 | enable_IO_APIC(); | |
fa2bd35a | 1671 | #endif |
739f33b3 AK |
1672 | |
1673 | end_local_APIC_setup(); | |
1674 | ||
fa2bd35a | 1675 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1676 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1677 | setup_IO_APIC(); | |
98c061b6 | 1678 | else { |
0e078e2f | 1679 | nr_ioapics = 0; |
98c061b6 YL |
1680 | localise_nmi_watchdog(); |
1681 | } | |
1682 | #else | |
1683 | localise_nmi_watchdog(); | |
fa2bd35a YL |
1684 | #endif |
1685 | ||
98c061b6 | 1686 | setup_boot_clock(); |
fa2bd35a | 1687 | #ifdef CONFIG_X86_64 |
0e078e2f | 1688 | check_nmi_watchdog(); |
fa2bd35a YL |
1689 | #endif |
1690 | ||
0e078e2f | 1691 | return 0; |
1da177e4 LT |
1692 | } |
1693 | ||
1694 | /* | |
0e078e2f | 1695 | * Local APIC interrupts |
1da177e4 LT |
1696 | */ |
1697 | ||
0e078e2f TG |
1698 | /* |
1699 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1700 | */ | |
dc1528dd | 1701 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1702 | { |
dc1528dd YL |
1703 | u32 v; |
1704 | ||
0e078e2f TG |
1705 | exit_idle(); |
1706 | irq_enter(); | |
1da177e4 | 1707 | /* |
0e078e2f TG |
1708 | * Check if this really is a spurious interrupt and ACK it |
1709 | * if it is a vectored one. Just in case... | |
1710 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1711 | */ |
0e078e2f TG |
1712 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1713 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1714 | ack_APIC_irq(); | |
c4d58cbd | 1715 | |
915b0d01 HS |
1716 | inc_irq_stat(irq_spurious_count); |
1717 | ||
dc1528dd | 1718 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1719 | pr_info("spurious APIC interrupt on CPU#%d, " |
1720 | "should never happen.\n", smp_processor_id()); | |
0e078e2f TG |
1721 | irq_exit(); |
1722 | } | |
1da177e4 | 1723 | |
0e078e2f TG |
1724 | /* |
1725 | * This interrupt should never happen with our APIC/SMP architecture | |
1726 | */ | |
dc1528dd | 1727 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1728 | { |
dc1528dd | 1729 | u32 v, v1; |
1da177e4 | 1730 | |
0e078e2f TG |
1731 | exit_idle(); |
1732 | irq_enter(); | |
1733 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1734 | v = apic_read(APIC_ESR); | |
1735 | apic_write(APIC_ESR, 0); | |
1736 | v1 = apic_read(APIC_ESR); | |
1737 | ack_APIC_irq(); | |
1738 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1739 | |
ba21ebb6 CG |
1740 | /* |
1741 | * Here is what the APIC error bits mean: | |
1742 | * 0: Send CS error | |
1743 | * 1: Receive CS error | |
1744 | * 2: Send accept error | |
1745 | * 3: Receive accept error | |
1746 | * 4: Reserved | |
1747 | * 5: Send illegal vector | |
1748 | * 6: Received illegal vector | |
1749 | * 7: Illegal register address | |
1750 | */ | |
1751 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | |
0e078e2f TG |
1752 | smp_processor_id(), v , v1); |
1753 | irq_exit(); | |
1da177e4 LT |
1754 | } |
1755 | ||
b5841765 | 1756 | /** |
36c9d674 CG |
1757 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1758 | */ | |
b5841765 GC |
1759 | void __init connect_bsp_APIC(void) |
1760 | { | |
36c9d674 CG |
1761 | #ifdef CONFIG_X86_32 |
1762 | if (pic_mode) { | |
1763 | /* | |
1764 | * Do not trust the local APIC being empty at bootup. | |
1765 | */ | |
1766 | clear_local_APIC(); | |
1767 | /* | |
1768 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1769 | * local APIC to INT and NMI lines. | |
1770 | */ | |
1771 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1772 | "enabling APIC mode.\n"); | |
c0eaa453 | 1773 | imcr_pic_to_apic(); |
36c9d674 CG |
1774 | } |
1775 | #endif | |
49040333 IM |
1776 | if (apic->enable_apic_mode) |
1777 | apic->enable_apic_mode(); | |
b5841765 GC |
1778 | } |
1779 | ||
274cfe59 CG |
1780 | /** |
1781 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1782 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1783 | * | |
1784 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1785 | * APIC is disabled. | |
1786 | */ | |
0e078e2f | 1787 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1788 | { |
1b4ee4e4 CG |
1789 | unsigned int value; |
1790 | ||
c177b0bc CG |
1791 | #ifdef CONFIG_X86_32 |
1792 | if (pic_mode) { | |
1793 | /* | |
1794 | * Put the board back into PIC mode (has an effect only on | |
1795 | * certain older boards). Note that APIC interrupts, including | |
1796 | * IPIs, won't work beyond this point! The only exception are | |
1797 | * INIT IPIs. | |
1798 | */ | |
1799 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1800 | "entering PIC mode.\n"); | |
c0eaa453 | 1801 | imcr_apic_to_pic(); |
c177b0bc CG |
1802 | return; |
1803 | } | |
1804 | #endif | |
1805 | ||
0e078e2f | 1806 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1807 | |
0e078e2f TG |
1808 | /* For the spurious interrupt use vector F, and enable it */ |
1809 | value = apic_read(APIC_SPIV); | |
1810 | value &= ~APIC_VECTOR_MASK; | |
1811 | value |= APIC_SPIV_APIC_ENABLED; | |
1812 | value |= 0xf; | |
1813 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1814 | |
0e078e2f TG |
1815 | if (!virt_wire_setup) { |
1816 | /* | |
1817 | * For LVT0 make it edge triggered, active high, | |
1818 | * external and enabled | |
1819 | */ | |
1820 | value = apic_read(APIC_LVT0); | |
1821 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1822 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1823 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1824 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1825 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1826 | apic_write(APIC_LVT0, value); | |
1827 | } else { | |
1828 | /* Disable LVT0 */ | |
1829 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1830 | } | |
b8ce3359 | 1831 | |
c177b0bc CG |
1832 | /* |
1833 | * For LVT1 make it edge triggered, active high, | |
1834 | * nmi and enabled | |
1835 | */ | |
0e078e2f TG |
1836 | value = apic_read(APIC_LVT1); |
1837 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1838 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1839 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1840 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1841 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1842 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1843 | } |
1844 | ||
be8a5685 AS |
1845 | void __cpuinit generic_processor_info(int apicid, int version) |
1846 | { | |
1847 | int cpu; | |
be8a5685 | 1848 | |
1b313f4a CG |
1849 | /* |
1850 | * Validate version | |
1851 | */ | |
1852 | if (version == 0x0) { | |
ba21ebb6 | 1853 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
3b11ce7f MT |
1854 | "fixing up to 0x10. (tell your hw vendor)\n", |
1855 | version); | |
1b313f4a | 1856 | version = 0x10; |
be8a5685 | 1857 | } |
1b313f4a | 1858 | apic_version[apicid] = version; |
be8a5685 | 1859 | |
3b11ce7f MT |
1860 | if (num_processors >= nr_cpu_ids) { |
1861 | int max = nr_cpu_ids; | |
1862 | int thiscpu = max + disabled_cpus; | |
1863 | ||
1864 | pr_warning( | |
1865 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
1866 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
1867 | ||
1868 | disabled_cpus++; | |
be8a5685 AS |
1869 | return; |
1870 | } | |
1871 | ||
1872 | num_processors++; | |
3b11ce7f | 1873 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
be8a5685 | 1874 | |
b2b815d8 MT |
1875 | if (version != apic_version[boot_cpu_physical_apicid]) |
1876 | WARN_ONCE(1, | |
1877 | "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", | |
1878 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
1879 | ||
be8a5685 AS |
1880 | physid_set(apicid, phys_cpu_present_map); |
1881 | if (apicid == boot_cpu_physical_apicid) { | |
1882 | /* | |
1883 | * x86_bios_cpu_apicid is required to have processors listed | |
1884 | * in same order as logical cpu numbers. Hence the first | |
1885 | * entry is BSP, and so on. | |
1886 | */ | |
1887 | cpu = 0; | |
1888 | } | |
e0da3364 YL |
1889 | if (apicid > max_physical_apicid) |
1890 | max_physical_apicid = apicid; | |
1891 | ||
1b313f4a CG |
1892 | #ifdef CONFIG_X86_32 |
1893 | /* | |
1894 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1895 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1896 | * before this can be done without some confusion. | |
1897 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1898 | * - Ashok Raj <ashok.raj@intel.com> | |
1899 | */ | |
1900 | if (max_physical_apicid >= 8) { | |
1901 | switch (boot_cpu_data.x86_vendor) { | |
1902 | case X86_VENDOR_INTEL: | |
1903 | if (!APIC_XAPIC(version)) { | |
1904 | def_to_bigsmp = 0; | |
1905 | break; | |
1906 | } | |
1907 | /* If P4 and above fall through */ | |
1908 | case X86_VENDOR_AMD: | |
1909 | def_to_bigsmp = 1; | |
1910 | } | |
1911 | } | |
1912 | #endif | |
1913 | ||
3e5095d1 | 1914 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
1915 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
1916 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 1917 | #endif |
be8a5685 | 1918 | |
1de88cd4 MT |
1919 | set_cpu_possible(cpu, true); |
1920 | set_cpu_present(cpu, true); | |
be8a5685 AS |
1921 | } |
1922 | ||
0c81c746 SS |
1923 | int hard_smp_processor_id(void) |
1924 | { | |
1925 | return read_apic_id(); | |
1926 | } | |
1dcdd3d1 IM |
1927 | |
1928 | void default_init_apic_ldr(void) | |
1929 | { | |
1930 | unsigned long val; | |
1931 | ||
1932 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
1933 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
1934 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
1935 | apic_write(APIC_LDR, val); | |
1936 | } | |
1937 | ||
1938 | #ifdef CONFIG_X86_32 | |
1939 | int default_apicid_to_node(int logical_apicid) | |
1940 | { | |
1941 | #ifdef CONFIG_SMP | |
1942 | return apicid_2_node[hard_smp_processor_id()]; | |
1943 | #else | |
1944 | return 0; | |
1945 | #endif | |
1946 | } | |
3491998d | 1947 | #endif |
0c81c746 | 1948 | |
89039b37 | 1949 | /* |
0e078e2f | 1950 | * Power management |
89039b37 | 1951 | */ |
0e078e2f TG |
1952 | #ifdef CONFIG_PM |
1953 | ||
1954 | static struct { | |
274cfe59 CG |
1955 | /* |
1956 | * 'active' is true if the local APIC was enabled by us and | |
1957 | * not the BIOS; this signifies that we are also responsible | |
1958 | * for disabling it before entering apm/acpi suspend | |
1959 | */ | |
0e078e2f TG |
1960 | int active; |
1961 | /* r/w apic fields */ | |
1962 | unsigned int apic_id; | |
1963 | unsigned int apic_taskpri; | |
1964 | unsigned int apic_ldr; | |
1965 | unsigned int apic_dfr; | |
1966 | unsigned int apic_spiv; | |
1967 | unsigned int apic_lvtt; | |
1968 | unsigned int apic_lvtpc; | |
1969 | unsigned int apic_lvt0; | |
1970 | unsigned int apic_lvt1; | |
1971 | unsigned int apic_lvterr; | |
1972 | unsigned int apic_tmict; | |
1973 | unsigned int apic_tdcr; | |
1974 | unsigned int apic_thmr; | |
1975 | } apic_pm_state; | |
1976 | ||
1977 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1978 | { | |
1979 | unsigned long flags; | |
1980 | int maxlvt; | |
89039b37 | 1981 | |
0e078e2f TG |
1982 | if (!apic_pm_state.active) |
1983 | return 0; | |
89039b37 | 1984 | |
0e078e2f | 1985 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1986 | |
2d7a66d0 | 1987 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1988 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1989 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1990 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1991 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1992 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1993 | if (maxlvt >= 4) | |
1994 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1995 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1996 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1997 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1998 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1999 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 2000 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2001 | if (maxlvt >= 5) |
2002 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2003 | #endif | |
24968cfd | 2004 | |
0e078e2f TG |
2005 | local_irq_save(flags); |
2006 | disable_local_APIC(); | |
fc1edaf9 | 2007 | |
b24696bc FY |
2008 | if (intr_remapping_enabled) |
2009 | disable_intr_remapping(); | |
fc1edaf9 | 2010 | |
0e078e2f TG |
2011 | local_irq_restore(flags); |
2012 | return 0; | |
1da177e4 LT |
2013 | } |
2014 | ||
0e078e2f | 2015 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 2016 | { |
0e078e2f TG |
2017 | unsigned int l, h; |
2018 | unsigned long flags; | |
2019 | int maxlvt; | |
b24696bc FY |
2020 | int ret; |
2021 | struct IO_APIC_route_entry **ioapic_entries = NULL; | |
2022 | ||
0e078e2f TG |
2023 | if (!apic_pm_state.active) |
2024 | return 0; | |
89b831ef | 2025 | |
0e078e2f | 2026 | local_irq_save(flags); |
9a2755c3 | 2027 | if (intr_remapping_enabled) { |
b24696bc FY |
2028 | ioapic_entries = alloc_ioapic_entries(); |
2029 | if (!ioapic_entries) { | |
2030 | WARN(1, "Alloc ioapic_entries in lapic resume failed."); | |
2031 | return -ENOMEM; | |
2032 | } | |
2033 | ||
2034 | ret = save_IO_APIC_setup(ioapic_entries); | |
2035 | if (ret) { | |
2036 | WARN(1, "Saving IO-APIC state failed: %d\n", ret); | |
2037 | free_ioapic_entries(ioapic_entries); | |
2038 | return ret; | |
2039 | } | |
2040 | ||
2041 | mask_IO_APIC_setup(ioapic_entries); | |
2042 | mask_8259A(); | |
b24696bc | 2043 | } |
9a2755c3 | 2044 | |
fc1edaf9 | 2045 | if (x2apic_mode) |
9a2755c3 | 2046 | enable_x2apic(); |
cf6567fe | 2047 | else { |
92206c90 CG |
2048 | /* |
2049 | * Make sure the APICBASE points to the right address | |
2050 | * | |
2051 | * FIXME! This will be wrong if we ever support suspend on | |
2052 | * SMP! We'll need to do this as part of the CPU restore! | |
2053 | */ | |
6e1cb38a SS |
2054 | rdmsr(MSR_IA32_APICBASE, l, h); |
2055 | l &= ~MSR_IA32_APICBASE_BASE; | |
2056 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2057 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 2058 | } |
6e1cb38a | 2059 | |
b24696bc | 2060 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2061 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2062 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2063 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2064 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2065 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2066 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2067 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2068 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2069 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2070 | if (maxlvt >= 5) |
2071 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2072 | #endif | |
2073 | if (maxlvt >= 4) | |
2074 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2075 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2076 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2077 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2078 | apic_write(APIC_ESR, 0); | |
2079 | apic_read(APIC_ESR); | |
2080 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2081 | apic_write(APIC_ESR, 0); | |
2082 | apic_read(APIC_ESR); | |
92206c90 | 2083 | |
9a2755c3 | 2084 | if (intr_remapping_enabled) { |
fc1edaf9 | 2085 | reenable_intr_remapping(x2apic_mode); |
b24696bc FY |
2086 | unmask_8259A(); |
2087 | restore_IO_APIC_setup(ioapic_entries); | |
2088 | free_ioapic_entries(ioapic_entries); | |
2089 | } | |
b24696bc | 2090 | |
0e078e2f | 2091 | local_irq_restore(flags); |
92206c90 | 2092 | |
0e078e2f TG |
2093 | return 0; |
2094 | } | |
b8ce3359 | 2095 | |
274cfe59 CG |
2096 | /* |
2097 | * This device has no shutdown method - fully functioning local APICs | |
2098 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2099 | */ | |
2100 | ||
0e078e2f TG |
2101 | static struct sysdev_class lapic_sysclass = { |
2102 | .name = "lapic", | |
2103 | .resume = lapic_resume, | |
2104 | .suspend = lapic_suspend, | |
2105 | }; | |
b8ce3359 | 2106 | |
0e078e2f | 2107 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2108 | .id = 0, |
2109 | .cls = &lapic_sysclass, | |
0e078e2f | 2110 | }; |
b8ce3359 | 2111 | |
0e078e2f TG |
2112 | static void __cpuinit apic_pm_activate(void) |
2113 | { | |
2114 | apic_pm_state.active = 1; | |
1da177e4 LT |
2115 | } |
2116 | ||
0e078e2f | 2117 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2118 | { |
0e078e2f | 2119 | int error; |
e83a5fdc | 2120 | |
0e078e2f TG |
2121 | if (!cpu_has_apic) |
2122 | return 0; | |
2123 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2124 | |
0e078e2f TG |
2125 | error = sysdev_class_register(&lapic_sysclass); |
2126 | if (!error) | |
2127 | error = sysdev_register(&device_lapic); | |
2128 | return error; | |
1da177e4 | 2129 | } |
b24696bc FY |
2130 | |
2131 | /* local apic needs to resume before other devices access its registers. */ | |
2132 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2133 | |
2134 | #else /* CONFIG_PM */ | |
2135 | ||
2136 | static void apic_pm_activate(void) { } | |
2137 | ||
2138 | #endif /* CONFIG_PM */ | |
1da177e4 | 2139 | |
f28c0ae2 | 2140 | #ifdef CONFIG_X86_64 |
e0e42142 YL |
2141 | |
2142 | static int __cpuinit apic_cluster_num(void) | |
1da177e4 LT |
2143 | { |
2144 | int i, clusters, zeros; | |
2145 | unsigned id; | |
322850af | 2146 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2147 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2148 | ||
23ca4bba | 2149 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2150 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2151 | |
168ef543 | 2152 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2153 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2154 | if (bios_cpu_apicid) { |
2155 | id = bios_cpu_apicid[i]; | |
e423e33e | 2156 | } else if (i < nr_cpu_ids) { |
e8c10ef9 | 2157 | if (cpu_present(i)) |
2158 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2159 | else | |
2160 | continue; | |
e423e33e | 2161 | } else |
e8c10ef9 | 2162 | break; |
2163 | ||
1da177e4 LT |
2164 | if (id != BAD_APICID) |
2165 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2166 | } | |
2167 | ||
2168 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2169 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2170 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2171 | * Since clusters are allocated sequentially, count zeros only if | |
2172 | * they are bounded by ones. | |
1da177e4 LT |
2173 | */ |
2174 | clusters = 0; | |
2175 | zeros = 0; | |
2176 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2177 | if (test_bit(i, clustermap)) { | |
2178 | clusters += 1 + zeros; | |
2179 | zeros = 0; | |
2180 | } else | |
2181 | ++zeros; | |
2182 | } | |
2183 | ||
e0e42142 YL |
2184 | return clusters; |
2185 | } | |
2186 | ||
2187 | static int __cpuinitdata multi_checked; | |
2188 | static int __cpuinitdata multi; | |
2189 | ||
2190 | static int __cpuinit set_multi(const struct dmi_system_id *d) | |
2191 | { | |
2192 | if (multi) | |
2193 | return 0; | |
6f0aced6 | 2194 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2195 | multi = 1; |
2196 | return 0; | |
2197 | } | |
2198 | ||
2199 | static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { | |
2200 | { | |
2201 | .callback = set_multi, | |
2202 | .ident = "IBM System Summit2", | |
2203 | .matches = { | |
2204 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2205 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2206 | }, | |
2207 | }, | |
2208 | {} | |
2209 | }; | |
2210 | ||
2211 | static void __cpuinit dmi_check_multi(void) | |
2212 | { | |
2213 | if (multi_checked) | |
2214 | return; | |
2215 | ||
2216 | dmi_check_system(multi_dmi_table); | |
2217 | multi_checked = 1; | |
2218 | } | |
2219 | ||
2220 | /* | |
2221 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2222 | * | |
2223 | * Thus far, the major user of this is IBM's Summit2 series: | |
2224 | * Clustered boxes may have unsynced TSC problems if they are | |
2225 | * multi-chassis. | |
2226 | * Use DMI to check them | |
2227 | */ | |
2228 | __cpuinit int apic_is_clustered_box(void) | |
2229 | { | |
2230 | dmi_check_multi(); | |
2231 | if (multi) | |
1cb68487 RT |
2232 | return 1; |
2233 | ||
e0e42142 YL |
2234 | if (!is_vsmp_box()) |
2235 | return 0; | |
2236 | ||
1da177e4 | 2237 | /* |
e0e42142 YL |
2238 | * ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2239 | * not guaranteed to be synced between boards | |
1da177e4 | 2240 | */ |
e0e42142 YL |
2241 | if (apic_cluster_num() > 1) |
2242 | return 1; | |
2243 | ||
2244 | return 0; | |
1da177e4 | 2245 | } |
f28c0ae2 | 2246 | #endif |
1da177e4 LT |
2247 | |
2248 | /* | |
0e078e2f | 2249 | * APIC command line parameters |
1da177e4 | 2250 | */ |
789fa735 | 2251 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2252 | { |
1da177e4 | 2253 | disable_apic = 1; |
9175fc06 | 2254 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2255 | return 0; |
2256 | } | |
2257 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2258 | |
2c8c0e6b | 2259 | /* same as disableapic, for compatibility */ |
789fa735 | 2260 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2261 | { |
789fa735 | 2262 | return setup_disableapic(arg); |
6935d1f9 | 2263 | } |
2c8c0e6b | 2264 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2265 | |
2e7c2838 LT |
2266 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2267 | { | |
2268 | local_apic_timer_c2_ok = 1; | |
2269 | return 0; | |
2270 | } | |
2271 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2272 | ||
36fef094 | 2273 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2274 | { |
1da177e4 | 2275 | disable_apic_timer = 1; |
36fef094 | 2276 | return 0; |
6935d1f9 | 2277 | } |
36fef094 CG |
2278 | early_param("noapictimer", parse_disable_apic_timer); |
2279 | ||
2280 | static int __init parse_nolapic_timer(char *arg) | |
2281 | { | |
2282 | disable_apic_timer = 1; | |
2283 | return 0; | |
6935d1f9 | 2284 | } |
36fef094 | 2285 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2286 | |
79af9bec CG |
2287 | static int __init apic_set_verbosity(char *arg) |
2288 | { | |
2289 | if (!arg) { | |
2290 | #ifdef CONFIG_X86_64 | |
2291 | skip_ioapic_setup = 0; | |
79af9bec CG |
2292 | return 0; |
2293 | #endif | |
2294 | return -EINVAL; | |
2295 | } | |
2296 | ||
2297 | if (strcmp("debug", arg) == 0) | |
2298 | apic_verbosity = APIC_DEBUG; | |
2299 | else if (strcmp("verbose", arg) == 0) | |
2300 | apic_verbosity = APIC_VERBOSE; | |
2301 | else { | |
ba21ebb6 | 2302 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2303 | " use apic=verbose or apic=debug\n", arg); |
2304 | return -EINVAL; | |
2305 | } | |
2306 | ||
2307 | return 0; | |
2308 | } | |
2309 | early_param("apic", apic_set_verbosity); | |
2310 | ||
1e934dda YL |
2311 | static int __init lapic_insert_resource(void) |
2312 | { | |
2313 | if (!apic_phys) | |
2314 | return -1; | |
2315 | ||
2316 | /* Put local APIC into the resource map. */ | |
2317 | lapic_resource.start = apic_phys; | |
2318 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2319 | insert_resource(&iomem_resource, &lapic_resource); | |
2320 | ||
2321 | return 0; | |
2322 | } | |
2323 | ||
2324 | /* | |
2325 | * need call insert after e820_reserve_resources() | |
2326 | * that is using request_resource | |
2327 | */ | |
2328 | late_initcall(lapic_insert_resource); |