Commit | Line | Data |
---|---|---|
457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Local APIC handling, local APIC timers | |
4 | * | |
8f47e163 | 5 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
6 | * |
7 | * Fixes | |
8 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
9 | * thanks to Eric Gilmore | |
10 | * and Rolf G. Tews | |
11 | * for testing these extensively. | |
12 | * Maciej W. Rozycki : Various updates and fixes. | |
13 | * Mikael Pettersson : Power Management for UP-APIC. | |
14 | * Pavel Machek and | |
15 | * Mikael Pettersson : PM converted to driver model. | |
16 | */ | |
17 | ||
cdd6c482 | 18 | #include <linux/perf_event.h> |
1da177e4 | 19 | #include <linux/kernel_stat.h> |
d1de36f5 | 20 | #include <linux/mc146818rtc.h> |
70a20025 | 21 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
22 | #include <linux/clockchips.h> |
23 | #include <linux/interrupt.h> | |
57c8a661 | 24 | #include <linux/memblock.h> |
d1de36f5 IM |
25 | #include <linux/ftrace.h> |
26 | #include <linux/ioport.h> | |
186f4360 | 27 | #include <linux/export.h> |
f3c6ea1b | 28 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
29 | #include <linux/delay.h> |
30 | #include <linux/timex.h> | |
334955ef | 31 | #include <linux/i8253.h> |
6e1cb38a | 32 | #include <linux/dmar.h> |
d1de36f5 IM |
33 | #include <linux/init.h> |
34 | #include <linux/cpu.h> | |
35 | #include <linux/dmi.h> | |
d1de36f5 IM |
36 | #include <linux/smp.h> |
37 | #include <linux/mm.h> | |
1da177e4 | 38 | |
83ab8514 | 39 | #include <asm/trace/irq_vectors.h> |
8a8f422d | 40 | #include <asm/irq_remapping.h> |
fb6a0408 | 41 | #include <asm/pc-conf-reg.h> |
cdd6c482 | 42 | #include <asm/perf_event.h> |
736decac | 43 | #include <asm/x86_init.h> |
60063497 | 44 | #include <linux/atomic.h> |
25a068b8 | 45 | #include <asm/barrier.h> |
1da177e4 | 46 | #include <asm/mpspec.h> |
d1de36f5 | 47 | #include <asm/i8259.h> |
73dea47f | 48 | #include <asm/proto.h> |
ad3bc25a | 49 | #include <asm/traps.h> |
2c8c0e6b | 50 | #include <asm/apic.h> |
13c01139 | 51 | #include <asm/acpi.h> |
7167d08e | 52 | #include <asm/io_apic.h> |
d1de36f5 IM |
53 | #include <asm/desc.h> |
54 | #include <asm/hpet.h> | |
d1de36f5 | 55 | #include <asm/mtrr.h> |
16f871bc | 56 | #include <asm/time.h> |
2bc13797 | 57 | #include <asm/smp.h> |
be71b855 | 58 | #include <asm/mce.h> |
8c3ba8d0 | 59 | #include <asm/tsc.h> |
2904ed8d | 60 | #include <asm/hypervisor.h> |
bd9240a1 PZ |
61 | #include <asm/cpu_device_id.h> |
62 | #include <asm/intel-family.h> | |
447ae316 | 63 | #include <asm/irq_regs.h> |
b8d1d163 | 64 | #include <asm/cpu.h> |
1da177e4 | 65 | |
ec70de8b | 66 | unsigned int num_processors; |
fdbecd9f | 67 | |
148f9bb8 | 68 | unsigned disabled_cpus; |
fdbecd9f | 69 | |
ec70de8b | 70 | /* Processor that is doing the boot up */ |
6444b40e | 71 | unsigned int boot_cpu_physical_apicid __ro_after_init = -1U; |
cc08e04c | 72 | EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); |
5af5573e | 73 | |
6444b40e | 74 | u8 boot_cpu_apic_version __ro_after_init; |
cff9ab2b | 75 | |
80e5609c | 76 | /* |
fdbecd9f | 77 | * Bitmask of physically existing CPUs: |
80e5609c | 78 | */ |
ec70de8b BG |
79 | physid_mask_t phys_cpu_present_map; |
80 | ||
151e0c7d HD |
81 | /* |
82 | * Processor to be disabled specified by kernel parameter | |
83 | * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to | |
84 | * avoid undefined behaviour caused by sending INIT from AP to BSP. | |
85 | */ | |
6444b40e | 86 | static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID; |
151e0c7d | 87 | |
b7c4948e HK |
88 | /* |
89 | * This variable controls which CPUs receive external NMIs. By default, | |
90 | * external NMIs are delivered only to the BSP. | |
91 | */ | |
6444b40e | 92 | static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP; |
b7c4948e | 93 | |
ab0f59c6 DW |
94 | /* |
95 | * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID | |
96 | */ | |
97 | static bool virt_ext_dest_id __ro_after_init; | |
98 | ||
bea629d5 TG |
99 | /* For parallel bootup. */ |
100 | unsigned long apic_mmio_base __ro_after_init; | |
101 | ||
ec70de8b BG |
102 | /* |
103 | * Map cpu index to physical APIC ID | |
104 | */ | |
0816b0f0 | 105 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); |
3e9e57fa | 106 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); |
ec70de8b | 107 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
3e9e57fa | 108 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); |
80e5609c | 109 | |
b3c51170 | 110 | #ifdef CONFIG_X86_32 |
4c321ff8 | 111 | |
4c321ff8 TH |
112 | /* |
113 | * On x86_32, the mapping between cpu and logical apicid may vary | |
114 | * depending on apic in use. The following early percpu variable is | |
115 | * used for the mapping. This is where the behaviors of x86_64 and 32 | |
116 | * actually diverge. Let's keep it ugly for now. | |
117 | */ | |
0816b0f0 | 118 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); |
4c321ff8 | 119 | |
f28c0ae2 | 120 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
6444b40e | 121 | static int enabled_via_apicbase __ro_after_init; |
f28c0ae2 | 122 | |
c0eaa453 CG |
123 | /* |
124 | * Handle interrupt mode configuration register (IMCR). | |
125 | * This register controls whether the interrupt signals | |
126 | * that reach the BSP come from the master PIC or from the | |
127 | * local APIC. Before entering Symmetric I/O Mode, either | |
128 | * the BIOS or the operating system must switch out of | |
129 | * PIC Mode by changing the IMCR. | |
130 | */ | |
5cda395f | 131 | static inline void imcr_pic_to_apic(void) |
c0eaa453 | 132 | { |
c0eaa453 | 133 | /* NMI and 8259 INTR go through APIC */ |
fb6a0408 | 134 | pc_conf_set(PC_CONF_MPS_IMCR, 0x01); |
c0eaa453 CG |
135 | } |
136 | ||
5cda395f | 137 | static inline void imcr_apic_to_pic(void) |
c0eaa453 | 138 | { |
c0eaa453 | 139 | /* NMI and 8259 INTR go directly to BSP */ |
fb6a0408 | 140 | pc_conf_set(PC_CONF_MPS_IMCR, 0x00); |
c0eaa453 | 141 | } |
b3c51170 YL |
142 | #endif |
143 | ||
279f1461 SS |
144 | /* |
145 | * Knob to control our willingness to enable the local APIC. | |
146 | * | |
147 | * +1=force-enable | |
148 | */ | |
149 | static int force_enable_local_apic __initdata; | |
dc9788f4 | 150 | |
279f1461 SS |
151 | /* |
152 | * APIC command line parameters | |
153 | */ | |
154 | static int __init parse_lapic(char *arg) | |
155 | { | |
97f2645f | 156 | if (IS_ENABLED(CONFIG_X86_32) && !arg) |
279f1461 | 157 | force_enable_local_apic = 1; |
27cf9298 | 158 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
279f1461 SS |
159 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
160 | return 0; | |
161 | } | |
162 | early_param("lapic", parse_lapic); | |
163 | ||
b3c51170 | 164 | #ifdef CONFIG_X86_64 |
bc1d99c1 | 165 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
166 | static __init int setup_apicpmtimer(char *s) |
167 | { | |
168 | apic_calibrate_pmtmr = 1; | |
169 | notsc_setup(NULL); | |
12441ccd | 170 | return 1; |
b3c51170 YL |
171 | } |
172 | __setup("apicpmtimer", setup_apicpmtimer); | |
173 | #endif | |
174 | ||
6444b40e | 175 | unsigned long mp_lapic_addr __ro_after_init; |
49062454 | 176 | bool apic_is_disabled __ro_after_init; |
b3c51170 | 177 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
25874a29 | 178 | static int disable_apic_timer __initdata; |
e83a5fdc | 179 | /* Local APIC timer works in C2 */ |
6444b40e | 180 | int local_apic_timer_c2_ok __ro_after_init; |
2e7c2838 LT |
181 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); |
182 | ||
e83a5fdc HS |
183 | /* |
184 | * Debug level, exported for io_apic.c | |
185 | */ | |
6444b40e | 186 | int apic_verbosity __ro_after_init; |
e83a5fdc | 187 | |
6444b40e | 188 | int pic_mode __ro_after_init; |
89c38c28 | 189 | |
bab4b27c | 190 | /* Have we found an MP table */ |
6444b40e | 191 | int smp_found_config __ro_after_init; |
bab4b27c | 192 | |
39928722 AD |
193 | static struct resource lapic_resource = { |
194 | .name = "Local APIC", | |
195 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
196 | }; | |
197 | ||
52ae346b | 198 | unsigned int lapic_timer_period = 0; |
d03030e9 | 199 | |
0e078e2f | 200 | static void apic_pm_activate(void); |
ba7eda4c | 201 | |
6444b40e | 202 | static unsigned long apic_phys __ro_after_init; |
d3432896 | 203 | |
0e078e2f TG |
204 | /* |
205 | * Get the LAPIC version | |
206 | */ | |
207 | static inline int lapic_get_version(void) | |
ba7eda4c | 208 | { |
0e078e2f | 209 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
210 | } |
211 | ||
0e078e2f | 212 | /* |
9c803869 | 213 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
214 | */ |
215 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 216 | { |
9c803869 | 217 | return APIC_INTEGRATED(lapic_get_version()); |
ba7eda4c TG |
218 | } |
219 | ||
220 | /* | |
0e078e2f | 221 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 222 | */ |
0e078e2f | 223 | static int modern_apic(void) |
ba7eda4c | 224 | { |
0e078e2f TG |
225 | /* AMD systems use old APIC versions, so check the CPU */ |
226 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
227 | boot_cpu_data.x86 >= 0xf) | |
228 | return 1; | |
da33dfef PW |
229 | |
230 | /* Hygon systems use modern APIC */ | |
231 | if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) | |
232 | return 1; | |
233 | ||
0e078e2f | 234 | return lapic_get_version() >= 0x14; |
ba7eda4c TG |
235 | } |
236 | ||
08306ce6 | 237 | /* |
a933c618 CG |
238 | * right after this call apic become NOOP driven |
239 | * so apic->write/read doesn't do anything | |
08306ce6 | 240 | */ |
25874a29 | 241 | static void __init apic_disable(void) |
08306ce6 | 242 | { |
f88f2b4f | 243 | pr_info("APIC: switched to apic NOOP\n"); |
a933c618 | 244 | apic = &apic_noop; |
08306ce6 CG |
245 | } |
246 | ||
c1eeb2de | 247 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
248 | { |
249 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
250 | cpu_relax(); | |
251 | } | |
252 | ||
c1eeb2de | 253 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 254 | { |
3c6bb07a | 255 | u32 send_status; |
8339e9fb FLV |
256 | int timeout; |
257 | ||
258 | timeout = 0; | |
259 | do { | |
260 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
261 | if (!send_status) | |
262 | break; | |
b49d7d87 | 263 | inc_irq_stat(icr_read_retry_count); |
8339e9fb FLV |
264 | udelay(100); |
265 | } while (timeout++ < 1000); | |
266 | ||
267 | return send_status; | |
268 | } | |
269 | ||
c1eeb2de | 270 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 271 | { |
ea7bdc65 JK |
272 | unsigned long flags; |
273 | ||
274 | local_irq_save(flags); | |
bf348f66 | 275 | apic_write(APIC_ICR2, SET_XAPIC_DEST_FIELD(id)); |
1b374e4d | 276 | apic_write(APIC_ICR, low); |
ea7bdc65 | 277 | local_irq_restore(flags); |
1b374e4d SS |
278 | } |
279 | ||
c1eeb2de | 280 | u64 native_apic_icr_read(void) |
1b374e4d SS |
281 | { |
282 | u32 icr1, icr2; | |
283 | ||
284 | icr2 = apic_read(APIC_ICR2); | |
285 | icr1 = apic_read(APIC_ICR); | |
286 | ||
cf9768d7 | 287 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
288 | } |
289 | ||
7c37e48b CG |
290 | #ifdef CONFIG_X86_32 |
291 | /** | |
292 | * get_physical_broadcast - Get number of physical broadcast IDs | |
293 | */ | |
294 | int get_physical_broadcast(void) | |
295 | { | |
296 | return modern_apic() ? 0xff : 0xf; | |
297 | } | |
298 | #endif | |
299 | ||
0e078e2f TG |
300 | /** |
301 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
302 | */ | |
37e650c7 | 303 | int lapic_get_maxlvt(void) |
1da177e4 | 304 | { |
36a028de CG |
305 | /* |
306 | * - we always have APIC integrated on 64bit mode | |
307 | * - 82489DXs do not report # of LVT entries | |
308 | */ | |
ae41a2a4 | 309 | return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; |
1da177e4 LT |
310 | } |
311 | ||
274cfe59 CG |
312 | /* |
313 | * Local APIC timer | |
314 | */ | |
315 | ||
c40aaec6 | 316 | /* Clock divisor */ |
c40aaec6 | 317 | #define APIC_DIVISOR 16 |
1a9e4c56 | 318 | #define TSC_DIVISOR 8 |
f07f4f90 | 319 | |
daf3af47 TG |
320 | /* i82489DX specific */ |
321 | #define I82489DX_BASE_DIVIDER (((0x2) << 18)) | |
322 | ||
0e078e2f TG |
323 | /* |
324 | * This function sets up the local APIC timer, with a timeout of | |
325 | * 'clocks' APIC bus clock. During calibration we actually call | |
326 | * this function twice on the boot CPU, once with a bogus timeout | |
327 | * value, second time for real. The other (noncalibrating) CPUs | |
328 | * call this function only once, with the real, calibrated value. | |
329 | * | |
330 | * We do reads before writes even if unnecessary, to get around the | |
331 | * P5 APIC double write bug. | |
332 | */ | |
0e078e2f | 333 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 334 | { |
0e078e2f | 335 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 336 | |
0e078e2f TG |
337 | lvtt_value = LOCAL_TIMER_VECTOR; |
338 | if (!oneshot) | |
339 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
279f1461 SS |
340 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
341 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; | |
342 | ||
daf3af47 TG |
343 | /* |
344 | * The i82489DX APIC uses bit 18 and 19 for the base divider. This | |
345 | * overlaps with bit 18 on integrated APICs, but is not documented | |
346 | * in the SDM. No problem though. i82489DX equipped systems do not | |
347 | * have TSC deadline timer. | |
348 | */ | |
f07f4f90 | 349 | if (!lapic_is_integrated()) |
daf3af47 | 350 | lvtt_value |= I82489DX_BASE_DIVIDER; |
f07f4f90 | 351 | |
0e078e2f TG |
352 | if (!irqen) |
353 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 354 | |
0e078e2f | 355 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 | 356 | |
279f1461 | 357 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
5d7c631d SL |
358 | /* |
359 | * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, | |
360 | * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. | |
361 | * According to Intel, MFENCE can do the serialization here. | |
362 | */ | |
363 | asm volatile("mfence" : : : "memory"); | |
279f1461 SS |
364 | return; |
365 | } | |
366 | ||
1da177e4 | 367 | /* |
0e078e2f | 368 | * Divide PICLK by 16 |
1da177e4 | 369 | */ |
0e078e2f | 370 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
371 | apic_write(APIC_TDCR, |
372 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
373 | APIC_TDR_DIV_16); | |
0e078e2f TG |
374 | |
375 | if (!oneshot) | |
f07f4f90 | 376 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
377 | } |
378 | ||
0e078e2f | 379 | /* |
a68c439b | 380 | * Setup extended LVT, AMD specific |
7b83dae7 | 381 | * |
a68c439b RR |
382 | * Software should use the LVT offsets the BIOS provides. The offsets |
383 | * are determined by the subsystems using it like those for MCE | |
384 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
385 | * are supported. Beginning with family 10h at least 4 offsets are | |
386 | * available. | |
286f5718 | 387 | * |
a68c439b RR |
388 | * Since the offsets must be consistent for all cores, we keep track |
389 | * of the LVT offsets in software and reserve the offset for the same | |
390 | * vector also to be used on other cores. An offset is freed by | |
391 | * setting the entry to APIC_EILVT_MASKED. | |
392 | * | |
393 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
394 | * "[Firmware Bug]: ..." error message is generated. However, if | |
395 | * software does not properly determines the offsets, it is not | |
396 | * necessarily a BIOS bug. | |
0e078e2f | 397 | */ |
7b83dae7 | 398 | |
a68c439b RR |
399 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
400 | ||
401 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
402 | { | |
403 | return (old & APIC_EILVT_MASKED) | |
404 | || (new == APIC_EILVT_MASKED) | |
405 | || ((new & ~APIC_EILVT_MASKED) == old); | |
406 | } | |
407 | ||
408 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
409 | { | |
8abc3122 | 410 | unsigned int rsvd, vector; |
a68c439b RR |
411 | |
412 | if (offset >= APIC_EILVT_NR_MAX) | |
413 | return ~0; | |
414 | ||
8abc3122 | 415 | rsvd = atomic_read(&eilvt_offsets[offset]); |
a68c439b | 416 | do { |
8abc3122 RR |
417 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
418 | if (vector && !eilvt_entry_is_changeable(vector, new)) | |
a68c439b RR |
419 | /* may not change if vectors are different */ |
420 | return rsvd; | |
f96fb2df | 421 | } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new)); |
a68c439b | 422 | |
f96fb2df | 423 | rsvd = new & ~APIC_EILVT_MASKED; |
8abc3122 RR |
424 | if (rsvd && rsvd != vector) |
425 | pr_info("LVT offset %d assigned for vector 0x%02x\n", | |
426 | offset, rsvd); | |
427 | ||
a68c439b RR |
428 | return new; |
429 | } | |
430 | ||
431 | /* | |
432 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
433 | * enables the vector. See also the BKDGs. Must be called with |
434 | * preemption disabled. | |
a68c439b RR |
435 | */ |
436 | ||
27afdf20 | 437 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 438 | { |
a68c439b RR |
439 | unsigned long reg = APIC_EILVTn(offset); |
440 | unsigned int new, old, reserved; | |
441 | ||
442 | new = (mask << 16) | (msg_type << 8) | vector; | |
443 | old = apic_read(reg); | |
444 | reserved = reserve_eilvt_offset(offset, new); | |
445 | ||
446 | if (reserved != new) { | |
eb48c9cb RR |
447 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
448 | "vector 0x%x, but the register is already in use for " | |
449 | "vector 0x%x on another cpu\n", | |
450 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
451 | return -EINVAL; |
452 | } | |
453 | ||
454 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
455 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
456 | "vector 0x%x, but the register is already in use for " | |
457 | "vector 0x%x on this cpu\n", | |
458 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
459 | return -EBUSY; |
460 | } | |
461 | ||
462 | apic_write(reg, new); | |
a8fcf1a2 | 463 | |
a68c439b | 464 | return 0; |
1da177e4 | 465 | } |
27afdf20 | 466 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 467 | |
0e078e2f TG |
468 | /* |
469 | * Program the next event, relative to now | |
470 | */ | |
471 | static int lapic_next_event(unsigned long delta, | |
472 | struct clock_event_device *evt) | |
1da177e4 | 473 | { |
0e078e2f TG |
474 | apic_write(APIC_TMICT, delta); |
475 | return 0; | |
1da177e4 LT |
476 | } |
477 | ||
279f1461 SS |
478 | static int lapic_next_deadline(unsigned long delta, |
479 | struct clock_event_device *evt) | |
480 | { | |
481 | u64 tsc; | |
482 | ||
25a068b8 DH |
483 | /* This MSR is special and need a special fence: */ |
484 | weak_wrmsr_fence(); | |
485 | ||
4ea1636b | 486 | tsc = rdtsc(); |
279f1461 SS |
487 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); |
488 | return 0; | |
489 | } | |
490 | ||
b23d8e52 | 491 | static int lapic_timer_shutdown(struct clock_event_device *evt) |
9b7711f0 | 492 | { |
0e078e2f | 493 | unsigned int v; |
9b7711f0 | 494 | |
0e078e2f TG |
495 | /* Lapic used as dummy for broadcast ? */ |
496 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
b23d8e52 | 497 | return 0; |
9b7711f0 | 498 | |
b23d8e52 VK |
499 | v = apic_read(APIC_LVTT); |
500 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
501 | apic_write(APIC_LVTT, v); | |
502 | apic_write(APIC_TMICT, 0); | |
b23d8e52 VK |
503 | return 0; |
504 | } | |
9b7711f0 | 505 | |
b23d8e52 VK |
506 | static inline int |
507 | lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) | |
508 | { | |
b23d8e52 VK |
509 | /* Lapic used as dummy for broadcast ? */ |
510 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
511 | return 0; | |
9b7711f0 | 512 | |
52ae346b | 513 | __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); |
b23d8e52 VK |
514 | return 0; |
515 | } | |
516 | ||
517 | static int lapic_timer_set_periodic(struct clock_event_device *evt) | |
518 | { | |
519 | return lapic_timer_set_periodic_oneshot(evt, false); | |
520 | } | |
521 | ||
522 | static int lapic_timer_set_oneshot(struct clock_event_device *evt) | |
523 | { | |
524 | return lapic_timer_set_periodic_oneshot(evt, true); | |
9b7711f0 HS |
525 | } |
526 | ||
1da177e4 | 527 | /* |
0e078e2f | 528 | * Local APIC timer broadcast function |
1da177e4 | 529 | */ |
9628937d | 530 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 531 | { |
0e078e2f | 532 | #ifdef CONFIG_SMP |
dac5f412 | 533 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
534 | #endif |
535 | } | |
1da177e4 | 536 | |
25874a29 HK |
537 | |
538 | /* | |
539 | * The local apic timer can be used for any function which is CPU local. | |
540 | */ | |
541 | static struct clock_event_device lapic_clockevent = { | |
914122c3 FW |
542 | .name = "lapic", |
543 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
544 | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP | |
545 | | CLOCK_EVT_FEAT_DUMMY, | |
546 | .shift = 32, | |
547 | .set_state_shutdown = lapic_timer_shutdown, | |
548 | .set_state_periodic = lapic_timer_set_periodic, | |
549 | .set_state_oneshot = lapic_timer_set_oneshot, | |
550 | .set_state_oneshot_stopped = lapic_timer_shutdown, | |
551 | .set_next_event = lapic_next_event, | |
552 | .broadcast = lapic_timer_broadcast, | |
553 | .rating = 100, | |
554 | .irq = -1, | |
25874a29 HK |
555 | }; |
556 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
557 | ||
66abf238 BP |
558 | static const struct x86_cpu_id deadline_match[] __initconst = { |
559 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */ | |
560 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */ | |
616dd587 | 561 | |
66abf238 | 562 | X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020), |
d9e6dbcf | 563 | |
66abf238 BP |
564 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011), |
565 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e), | |
566 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c), | |
567 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003), | |
616dd587 | 568 | |
66abf238 BP |
569 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136), |
570 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014), | |
571 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0), | |
bd9240a1 | 572 | |
adefe55e TG |
573 | X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22), |
574 | X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20), | |
575 | X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17), | |
bd9240a1 | 576 | |
adefe55e TG |
577 | X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25), |
578 | X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17), | |
bd9240a1 | 579 | |
adefe55e TG |
580 | X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2), |
581 | X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2), | |
bd9240a1 | 582 | |
adefe55e TG |
583 | X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52), |
584 | X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52), | |
bd9240a1 PZ |
585 | |
586 | {}, | |
587 | }; | |
588 | ||
c84cb373 | 589 | static __init bool apic_validate_deadline_timer(void) |
bd9240a1 | 590 | { |
594a30fb | 591 | const struct x86_cpu_id *m; |
bd9240a1 PZ |
592 | u32 rev; |
593 | ||
c84cb373 TG |
594 | if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
595 | return false; | |
596 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) | |
597 | return true; | |
594a30fb HG |
598 | |
599 | m = x86_match_cpu(deadline_match); | |
bd9240a1 | 600 | if (!m) |
c84cb373 | 601 | return true; |
bd9240a1 | 602 | |
66abf238 | 603 | rev = (u32)m->driver_data; |
bd9240a1 PZ |
604 | |
605 | if (boot_cpu_data.microcode >= rev) | |
c84cb373 | 606 | return true; |
bd9240a1 PZ |
607 | |
608 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); | |
609 | pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " | |
610 | "please update microcode to version: 0x%x (or later)\n", rev); | |
c84cb373 | 611 | return false; |
bd9240a1 PZ |
612 | } |
613 | ||
0e078e2f | 614 | /* |
421f91d2 | 615 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
616 | * of the boot CPU and register the clock event in the framework. |
617 | */ | |
148f9bb8 | 618 | static void setup_APIC_timer(void) |
0e078e2f | 619 | { |
89cbc767 | 620 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
1da177e4 | 621 | |
349c004e | 622 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 | 623 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
d9f6e12f | 624 | /* Make LAPIC timer preferable over percpu HPET */ |
db954b58 VP |
625 | lapic_clockevent.rating = 150; |
626 | } | |
627 | ||
0e078e2f | 628 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 629 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 630 | |
279f1461 | 631 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
c6e9f42b | 632 | levt->name = "lapic-deadline"; |
279f1461 SS |
633 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | |
634 | CLOCK_EVT_FEAT_DUMMY); | |
635 | levt->set_next_event = lapic_next_deadline; | |
636 | clockevents_config_and_register(levt, | |
1a9e4c56 | 637 | tsc_khz * (1000 / TSC_DIVISOR), |
279f1461 SS |
638 | 0xF, ~0UL); |
639 | } else | |
640 | clockevents_register_device(levt); | |
0e078e2f | 641 | } |
1da177e4 | 642 | |
6731b0d6 NS |
643 | /* |
644 | * Install the updated TSC frequency from recalibration at the TSC | |
645 | * deadline clockevent devices. | |
646 | */ | |
647 | static void __lapic_update_tsc_freq(void *info) | |
648 | { | |
649 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); | |
650 | ||
651 | if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) | |
652 | return; | |
653 | ||
654 | clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); | |
655 | } | |
656 | ||
657 | void lapic_update_tsc_freq(void) | |
658 | { | |
659 | /* | |
660 | * The clockevent device's ->mult and ->shift can both be | |
661 | * changed. In order to avoid races, schedule the frequency | |
662 | * update code on each CPU. | |
663 | */ | |
664 | on_each_cpu(__lapic_update_tsc_freq, NULL, 0); | |
665 | } | |
666 | ||
2f04fa88 YL |
667 | /* |
668 | * In this functions we calibrate APIC bus clocks to the external timer. | |
669 | * | |
670 | * We want to do the calibration only once since we want to have local timer | |
d9f6e12f | 671 | * irqs synchronous. CPUs connected by the same APIC bus have the very same bus |
2f04fa88 YL |
672 | * frequency. |
673 | * | |
674 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
675 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
676 | * readout is broken, so it never gets out of the wait loop again. This was | |
677 | * also reported by others. | |
678 | * | |
679 | * Monitoring the jiffies value is inaccurate and the clockevents | |
680 | * infrastructure allows us to do a simple substitution of the interrupt | |
681 | * handler. | |
682 | * | |
683 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
684 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
685 | * back to normal later in the boot process). | |
686 | */ | |
687 | ||
688 | #define LAPIC_CAL_LOOPS (HZ/10) | |
689 | ||
690 | static __initdata int lapic_cal_loops = -1; | |
691 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
692 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
693 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
694 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
695 | ||
696 | /* | |
f897e60a | 697 | * Temporary interrupt handler and polled calibration function. |
2f04fa88 YL |
698 | */ |
699 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
700 | { | |
701 | unsigned long long tsc = 0; | |
702 | long tapic = apic_read(APIC_TMCCT); | |
703 | unsigned long pm = acpi_pm_read_early(); | |
704 | ||
59e21e3d | 705 | if (boot_cpu_has(X86_FEATURE_TSC)) |
4ea1636b | 706 | tsc = rdtsc(); |
2f04fa88 YL |
707 | |
708 | switch (lapic_cal_loops++) { | |
709 | case 0: | |
710 | lapic_cal_t1 = tapic; | |
711 | lapic_cal_tsc1 = tsc; | |
712 | lapic_cal_pm1 = pm; | |
713 | lapic_cal_j1 = jiffies; | |
714 | break; | |
715 | ||
716 | case LAPIC_CAL_LOOPS: | |
717 | lapic_cal_t2 = tapic; | |
718 | lapic_cal_tsc2 = tsc; | |
719 | if (pm < lapic_cal_pm1) | |
720 | pm += ACPI_PM_OVRRUN; | |
721 | lapic_cal_pm2 = pm; | |
722 | lapic_cal_j2 = jiffies; | |
723 | break; | |
724 | } | |
725 | } | |
726 | ||
754ef0cd YI |
727 | static int __init |
728 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
729 | { |
730 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
731 | const long pm_thresh = pm_100ms / 100; | |
732 | unsigned long mult; | |
733 | u64 res; | |
734 | ||
735 | #ifndef CONFIG_X86_PM_TIMER | |
736 | return -1; | |
737 | #endif | |
738 | ||
39ba5d43 | 739 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
740 | |
741 | /* Check, if the PM timer is available */ | |
742 | if (!deltapm) | |
743 | return -1; | |
744 | ||
745 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
746 | ||
747 | if (deltapm > (pm_100ms - pm_thresh) && | |
748 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 749 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
750 | return 0; |
751 | } | |
752 | ||
753 | res = (((u64)deltapm) * mult) >> 22; | |
754 | do_div(res, 1000000); | |
8d3bcc44 KW |
755 | pr_warn("APIC calibration not consistent " |
756 | "with PM-Timer: %ldms instead of 100ms\n", (long)res); | |
754ef0cd YI |
757 | |
758 | /* Correct the lapic counter value */ | |
759 | res = (((u64)(*delta)) * pm_100ms); | |
760 | do_div(res, deltapm); | |
761 | pr_info("APIC delta adjusted to PM-Timer: " | |
762 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
763 | *delta = (long)res; | |
764 | ||
765 | /* Correct the tsc counter value */ | |
59e21e3d | 766 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
754ef0cd | 767 | res = (((u64)(*deltatsc)) * pm_100ms); |
b189892d | 768 | do_div(res, deltapm); |
754ef0cd | 769 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 770 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
771 | (unsigned long)res, *deltatsc); |
772 | *deltatsc = (long)res; | |
b189892d CG |
773 | } |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
6eb4f082 JP |
778 | static int __init lapic_init_clockevent(void) |
779 | { | |
52ae346b | 780 | if (!lapic_timer_period) |
6eb4f082 JP |
781 | return -1; |
782 | ||
783 | /* Calculate the scaled math multiplication factor */ | |
52ae346b | 784 | lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, |
6eb4f082 JP |
785 | TICK_NSEC, lapic_clockevent.shift); |
786 | lapic_clockevent.max_delta_ns = | |
787 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); | |
788 | lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; | |
789 | lapic_clockevent.min_delta_ns = | |
790 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
791 | lapic_clockevent.min_delta_ticks = 0xF; | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
c8c40767 TG |
796 | bool __init apic_needs_pit(void) |
797 | { | |
798 | /* | |
799 | * If the frequencies are not known, PIT is required for both TSC | |
800 | * and apic timer calibration. | |
801 | */ | |
802 | if (!tsc_khz || !cpu_khz) | |
803 | return true; | |
804 | ||
97992387 | 805 | /* Is there an APIC at all or is it disabled? */ |
49062454 | 806 | if (!boot_cpu_has(X86_FEATURE_APIC) || apic_is_disabled) |
97992387 TG |
807 | return true; |
808 | ||
809 | /* | |
810 | * If interrupt delivery mode is legacy PIC or virtual wire without | |
811 | * configuration, the local APIC timer wont be set up. Make sure | |
812 | * that the PIT is initialized. | |
813 | */ | |
814 | if (apic_intr_mode == APIC_PIC || | |
815 | apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG) | |
c8c40767 TG |
816 | return true; |
817 | ||
afa8b475 JS |
818 | /* Virt guests may lack ARAT, but still have DEADLINE */ |
819 | if (!boot_cpu_has(X86_FEATURE_ARAT)) | |
820 | return true; | |
821 | ||
c8c40767 TG |
822 | /* Deadline timer is based on TSC so no further PIT action required */ |
823 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) | |
824 | return false; | |
825 | ||
826 | /* APIC timer disabled? */ | |
827 | if (disable_apic_timer) | |
828 | return true; | |
829 | /* | |
830 | * The APIC timer frequency is known already, no PIT calibration | |
831 | * required. If unknown, let the PIT be initialized. | |
832 | */ | |
833 | return lapic_timer_period == 0; | |
834 | } | |
835 | ||
2f04fa88 YL |
836 | static int __init calibrate_APIC_clock(void) |
837 | { | |
89cbc767 | 838 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
f897e60a TG |
839 | u64 tsc_perj = 0, tsc_start = 0; |
840 | unsigned long jif_start; | |
2f04fa88 | 841 | unsigned long deltaj; |
754ef0cd | 842 | long delta, deltatsc; |
2f04fa88 YL |
843 | int pm_referenced = 0; |
844 | ||
6eb4f082 JP |
845 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
846 | return 0; | |
847 | ||
848 | /* | |
849 | * Check if lapic timer has already been calibrated by platform | |
850 | * specific routine, such as tsc calibration code. If so just fill | |
1ade93ef JP |
851 | * in the clockevent structure and return. |
852 | */ | |
6eb4f082 | 853 | if (!lapic_init_clockevent()) { |
1ade93ef | 854 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
52ae346b | 855 | lapic_timer_period); |
6eb4f082 JP |
856 | /* |
857 | * Direct calibration methods must have an always running | |
858 | * local APIC timer, no need for broadcast timer. | |
859 | */ | |
1ade93ef JP |
860 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
861 | return 0; | |
862 | } | |
863 | ||
279f1461 SS |
864 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
865 | "calibrating APIC timer ...\n"); | |
866 | ||
f897e60a TG |
867 | /* |
868 | * There are platforms w/o global clockevent devices. Instead of | |
869 | * making the calibration conditional on that, use a polling based | |
870 | * approach everywhere. | |
871 | */ | |
2f04fa88 YL |
872 | local_irq_disable(); |
873 | ||
2f04fa88 | 874 | /* |
81608f3c | 875 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
876 | * can underflow in the 100ms detection time frame |
877 | */ | |
81608f3c | 878 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 | 879 | |
f897e60a TG |
880 | /* |
881 | * Methods to terminate the calibration loop: | |
882 | * 1) Global clockevent if available (jiffies) | |
883 | * 2) TSC if available and frequency is known | |
884 | */ | |
885 | jif_start = READ_ONCE(jiffies); | |
886 | ||
887 | if (tsc_khz) { | |
888 | tsc_start = rdtsc(); | |
889 | tsc_perj = div_u64((u64)tsc_khz * 1000, HZ); | |
890 | } | |
891 | ||
892 | /* | |
893 | * Enable interrupts so the tick can fire, if a global | |
894 | * clockevent device is available | |
895 | */ | |
2f04fa88 YL |
896 | local_irq_enable(); |
897 | ||
f897e60a TG |
898 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) { |
899 | /* Wait for a tick to elapse */ | |
900 | while (1) { | |
901 | if (tsc_khz) { | |
902 | u64 tsc_now = rdtsc(); | |
903 | if ((tsc_now - tsc_start) >= tsc_perj) { | |
904 | tsc_start += tsc_perj; | |
905 | break; | |
906 | } | |
907 | } else { | |
908 | unsigned long jif_now = READ_ONCE(jiffies); | |
909 | ||
910 | if (time_after(jif_now, jif_start)) { | |
911 | jif_start = jif_now; | |
912 | break; | |
913 | } | |
914 | } | |
915 | cpu_relax(); | |
916 | } | |
2f04fa88 | 917 | |
f897e60a TG |
918 | /* Invoke the calibration routine */ |
919 | local_irq_disable(); | |
920 | lapic_cal_handler(NULL); | |
921 | local_irq_enable(); | |
922 | } | |
2f04fa88 | 923 | |
f897e60a | 924 | local_irq_disable(); |
2f04fa88 YL |
925 | |
926 | /* Build delta t1-t2 as apic timer counts down */ | |
927 | delta = lapic_cal_t1 - lapic_cal_t2; | |
928 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
929 | ||
754ef0cd YI |
930 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
931 | ||
b189892d CG |
932 | /* we trust the PM based calibration if possible */ |
933 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 934 | &delta, &deltatsc); |
2f04fa88 | 935 | |
52ae346b | 936 | lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
6eb4f082 | 937 | lapic_init_clockevent(); |
2f04fa88 YL |
938 | |
939 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 940 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 | 941 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
52ae346b | 942 | lapic_timer_period); |
2f04fa88 | 943 | |
59e21e3d | 944 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
2f04fa88 YL |
945 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
946 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
947 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
948 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
949 | } |
950 | ||
951 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
952 | "%u.%04u MHz.\n", | |
52ae346b DD |
953 | lapic_timer_period / (1000000 / HZ), |
954 | lapic_timer_period % (1000000 / HZ)); | |
2f04fa88 YL |
955 | |
956 | /* | |
957 | * Do a sanity check on the APIC calibration result | |
958 | */ | |
52ae346b | 959 | if (lapic_timer_period < (1000000 / HZ)) { |
2f04fa88 | 960 | local_irq_enable(); |
8d3bcc44 | 961 | pr_warn("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
962 | return -1; |
963 | } | |
964 | ||
965 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
966 | ||
b189892d | 967 | /* |
f897e60a TG |
968 | * PM timer calibration failed or not turned on so lets try APIC |
969 | * timer based calibration, if a global clockevent device is | |
970 | * available. | |
b189892d | 971 | */ |
f897e60a | 972 | if (!pm_referenced && global_clock_event) { |
2f04fa88 YL |
973 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); |
974 | ||
975 | /* | |
976 | * Setup the apic timer manually | |
977 | */ | |
978 | levt->event_handler = lapic_cal_handler; | |
b23d8e52 | 979 | lapic_timer_set_periodic(levt); |
2f04fa88 YL |
980 | lapic_cal_loops = -1; |
981 | ||
982 | /* Let the interrupts run */ | |
983 | local_irq_enable(); | |
984 | ||
985 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
986 | cpu_relax(); | |
987 | ||
2f04fa88 | 988 | /* Stop the lapic timer */ |
c948c260 | 989 | local_irq_disable(); |
b23d8e52 | 990 | lapic_timer_shutdown(levt); |
2f04fa88 | 991 | |
2f04fa88 YL |
992 | /* Jiffies delta */ |
993 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
994 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
995 | ||
996 | /* Check, if the jiffies result is consistent */ | |
997 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
998 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
999 | else | |
1000 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
c948c260 TG |
1001 | } |
1002 | local_irq_enable(); | |
2f04fa88 YL |
1003 | |
1004 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
8d3bcc44 | 1005 | pr_warn("APIC timer disabled due to verification failure\n"); |
843c4089 | 1006 | return -1; |
2f04fa88 YL |
1007 | } |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | ||
e83a5fdc HS |
1012 | /* |
1013 | * Setup the boot APIC | |
1014 | * | |
1015 | * Calibrate and verify the result. | |
1016 | */ | |
0e078e2f TG |
1017 | void __init setup_boot_APIC_clock(void) |
1018 | { | |
1019 | /* | |
274cfe59 CG |
1020 | * The local apic timer can be disabled via the kernel |
1021 | * commandline or from the CPU detection code. Register the lapic | |
1022 | * timer as a dummy clock event source on SMP systems, so the | |
1023 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
1024 | */ |
1025 | if (disable_apic_timer) { | |
ba21ebb6 | 1026 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 1027 | /* No broadcast on UP ! */ |
9d09951d TG |
1028 | if (num_possible_cpus() > 1) { |
1029 | lapic_clockevent.mult = 1; | |
0e078e2f | 1030 | setup_APIC_timer(); |
9d09951d | 1031 | } |
0e078e2f TG |
1032 | return; |
1033 | } | |
1034 | ||
89b3b1f4 | 1035 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
1036 | /* No broadcast on UP ! */ |
1037 | if (num_possible_cpus() > 1) | |
1038 | setup_APIC_timer(); | |
1039 | return; | |
1040 | } | |
1041 | ||
0e078e2f TG |
1042 | /* |
1043 | * If nmi_watchdog is set to IO_APIC, we need the | |
1044 | * PIT/HPET going. Otherwise register lapic as a dummy | |
1045 | * device. | |
1046 | */ | |
072b198a | 1047 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 1048 | |
274cfe59 | 1049 | /* Setup the lapic or request the broadcast */ |
0e078e2f | 1050 | setup_APIC_timer(); |
07c94a38 | 1051 | amd_e400_c1e_apic_setup(); |
0e078e2f TG |
1052 | } |
1053 | ||
148f9bb8 | 1054 | void setup_secondary_APIC_clock(void) |
0e078e2f | 1055 | { |
0e078e2f | 1056 | setup_APIC_timer(); |
07c94a38 | 1057 | amd_e400_c1e_apic_setup(); |
0e078e2f TG |
1058 | } |
1059 | ||
1060 | /* | |
1061 | * The guts of the apic timer interrupt | |
1062 | */ | |
1063 | static void local_apic_timer_interrupt(void) | |
1064 | { | |
3bec6def | 1065 | struct clock_event_device *evt = this_cpu_ptr(&lapic_events); |
0e078e2f TG |
1066 | |
1067 | /* | |
1068 | * Normally we should not be here till LAPIC has been initialized but | |
1069 | * in some cases like kdump, its possible that there is a pending LAPIC | |
1070 | * timer interrupt from previous kernel's context and is delivered in | |
1071 | * new kernel the moment interrupts are enabled. | |
1072 | * | |
1073 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
1074 | * its possible that when we get here evt->event_handler is NULL. | |
1075 | * Check for event_handler being NULL and discard the interrupt as | |
1076 | * spurious. | |
1077 | */ | |
1078 | if (!evt->event_handler) { | |
8d3bcc44 KW |
1079 | pr_warn("Spurious LAPIC timer interrupt on cpu %d\n", |
1080 | smp_processor_id()); | |
0e078e2f | 1081 | /* Switch it off */ |
b23d8e52 | 1082 | lapic_timer_shutdown(evt); |
0e078e2f TG |
1083 | return; |
1084 | } | |
1085 | ||
1086 | /* | |
1087 | * the NMI deadlock-detector uses this. | |
1088 | */ | |
915b0d01 | 1089 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
1090 | |
1091 | evt->event_handler(evt); | |
1092 | } | |
1093 | ||
1094 | /* | |
1095 | * Local APIC timer interrupt. This is the most natural way for doing | |
1096 | * local interrupts, but local timer interrupts can be emulated by | |
1097 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
1098 | * | |
1099 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
1100 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
1101 | */ | |
db0338ee | 1102 | DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt) |
0e078e2f TG |
1103 | { |
1104 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1105 | ||
db0338ee | 1106 | ack_APIC_irq(); |
cf910e83 | 1107 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); |
0e078e2f | 1108 | local_apic_timer_interrupt(); |
cf910e83 | 1109 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
274cfe59 | 1110 | |
0e078e2f TG |
1111 | set_irq_regs(old_regs); |
1112 | } | |
1113 | ||
0e078e2f TG |
1114 | /* |
1115 | * Local APIC start and shutdown | |
1116 | */ | |
1117 | ||
1118 | /** | |
1119 | * clear_local_APIC - shutdown the local APIC | |
1120 | * | |
1121 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
1122 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
1123 | * leftovers during boot. | |
1124 | */ | |
1125 | void clear_local_APIC(void) | |
1126 | { | |
2584a82d | 1127 | int maxlvt; |
0e078e2f TG |
1128 | u32 v; |
1129 | ||
d3432896 | 1130 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 1131 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
1132 | return; |
1133 | ||
1134 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
1135 | /* |
1136 | * Masking an LVT entry can trigger a local APIC error | |
1137 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1138 | */ | |
1139 | if (maxlvt >= 3) { | |
1140 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
1141 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
1142 | } | |
1143 | /* | |
1144 | * Careful: we have to set masks only first to deassert | |
1145 | * any level-triggered sources. | |
1146 | */ | |
1147 | v = apic_read(APIC_LVTT); | |
1148 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
1149 | v = apic_read(APIC_LVT0); | |
1150 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
1151 | v = apic_read(APIC_LVT1); | |
1152 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
1153 | if (maxlvt >= 4) { | |
1154 | v = apic_read(APIC_LVTPC); | |
1155 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1156 | } | |
1157 | ||
6764014b | 1158 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 1159 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
1160 | if (maxlvt >= 5) { |
1161 | v = apic_read(APIC_LVTTHMR); | |
1162 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
1163 | } | |
1164 | #endif | |
5ca8681c AK |
1165 | #ifdef CONFIG_X86_MCE_INTEL |
1166 | if (maxlvt >= 6) { | |
1167 | v = apic_read(APIC_LVTCMCI); | |
1168 | if (!(v & APIC_LVT_MASKED)) | |
1169 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
1170 | } | |
1171 | #endif | |
1172 | ||
0e078e2f TG |
1173 | /* |
1174 | * Clean APIC state for other OSs: | |
1175 | */ | |
1176 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
1177 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1178 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1179 | if (maxlvt >= 3) | |
1180 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
1181 | if (maxlvt >= 4) | |
1182 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
1183 | |
1184 | /* Integrated APIC (!82489DX) ? */ | |
1185 | if (lapic_is_integrated()) { | |
1186 | if (maxlvt > 3) | |
1187 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
1188 | apic_write(APIC_ESR, 0); | |
1189 | apic_read(APIC_ESR); | |
1190 | } | |
0e078e2f TG |
1191 | } |
1192 | ||
1193 | /** | |
60dcaad5 TG |
1194 | * apic_soft_disable - Clears and software disables the local APIC on hotplug |
1195 | * | |
1196 | * Contrary to disable_local_APIC() this does not touch the enable bit in | |
1197 | * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC | |
1198 | * bus would require a hardware reset as the APIC would lose track of bus | |
1199 | * arbitration. On systems with FSB delivery APICBASE could be disabled, | |
1200 | * but it has to be guaranteed that no interrupt is sent to the APIC while | |
1201 | * in that state and it's not clear from the SDM whether it still responds | |
1202 | * to INIT/SIPI messages. Stay on the safe side and use software disable. | |
0e078e2f | 1203 | */ |
60dcaad5 | 1204 | void apic_soft_disable(void) |
0e078e2f | 1205 | { |
60dcaad5 | 1206 | u32 value; |
4a13ad0b | 1207 | |
0e078e2f TG |
1208 | clear_local_APIC(); |
1209 | ||
60dcaad5 | 1210 | /* Soft disable APIC (implies clearing of registers for 82489DX!). */ |
0e078e2f TG |
1211 | value = apic_read(APIC_SPIV); |
1212 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1213 | apic_write(APIC_SPIV, value); | |
60dcaad5 TG |
1214 | } |
1215 | ||
1216 | /** | |
1217 | * disable_local_APIC - clear and disable the local APIC | |
1218 | */ | |
1219 | void disable_local_APIC(void) | |
1220 | { | |
1221 | /* APIC hasn't been mapped yet */ | |
1222 | if (!x2apic_mode && !apic_phys) | |
1223 | return; | |
1224 | ||
1225 | apic_soft_disable(); | |
990b183e CG |
1226 | |
1227 | #ifdef CONFIG_X86_32 | |
1228 | /* | |
1229 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
1230 | * restore the disabled state. | |
1231 | */ | |
1232 | if (enabled_via_apicbase) { | |
1233 | unsigned int l, h; | |
1234 | ||
1235 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1236 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1237 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1238 | } | |
1239 | #endif | |
0e078e2f TG |
1240 | } |
1241 | ||
fe4024dc CG |
1242 | /* |
1243 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1244 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1245 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1246 | * for the case where Linux didn't enable the LAPIC. | |
1247 | */ | |
0e078e2f TG |
1248 | void lapic_shutdown(void) |
1249 | { | |
1250 | unsigned long flags; | |
1251 | ||
93984fbd | 1252 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
0e078e2f TG |
1253 | return; |
1254 | ||
1255 | local_irq_save(flags); | |
1256 | ||
fe4024dc CG |
1257 | #ifdef CONFIG_X86_32 |
1258 | if (!enabled_via_apicbase) | |
1259 | clear_local_APIC(); | |
1260 | else | |
1261 | #endif | |
1262 | disable_local_APIC(); | |
1263 | ||
0e078e2f TG |
1264 | |
1265 | local_irq_restore(flags); | |
1266 | } | |
1267 | ||
0e078e2f TG |
1268 | /** |
1269 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1270 | */ | |
1da177e4 LT |
1271 | void __init sync_Arb_IDs(void) |
1272 | { | |
296cb951 CG |
1273 | /* |
1274 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1275 | * needed on AMD. | |
1276 | */ | |
1277 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1278 | return; |
1279 | ||
1280 | /* | |
1281 | * Wait for idle. | |
1282 | */ | |
1283 | apic_wait_icr_idle(); | |
1284 | ||
1285 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1286 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1287 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1288 | } |
1289 | ||
6444b40e | 1290 | enum apic_intr_mode_id apic_intr_mode __ro_after_init; |
0114a8e8 | 1291 | |
97992387 | 1292 | static int __init __apic_intr_mode_select(void) |
1da177e4 | 1293 | { |
0114a8e8 | 1294 | /* Check kernel option */ |
49062454 | 1295 | if (apic_is_disabled) { |
0114a8e8 DL |
1296 | pr_info("APIC disabled via kernel command line\n"); |
1297 | return APIC_PIC; | |
1298 | } | |
1da177e4 | 1299 | |
0114a8e8 DL |
1300 | /* Check BIOS */ |
1301 | #ifdef CONFIG_X86_64 | |
1302 | /* On 64-bit, the APIC must be integrated, Check local APIC only */ | |
1303 | if (!boot_cpu_has(X86_FEATURE_APIC)) { | |
49062454 | 1304 | apic_is_disabled = true; |
0114a8e8 DL |
1305 | pr_info("APIC disabled by BIOS\n"); |
1306 | return APIC_PIC; | |
1307 | } | |
1308 | #else | |
1309 | /* On 32-bit, the APIC may be integrated APIC or 82489DX */ | |
1da177e4 | 1310 | |
0114a8e8 DL |
1311 | /* Neither 82489DX nor integrated APIC ? */ |
1312 | if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { | |
49062454 | 1313 | apic_is_disabled = true; |
0114a8e8 DL |
1314 | return APIC_PIC; |
1315 | } | |
1da177e4 | 1316 | |
0114a8e8 DL |
1317 | /* If the BIOS pretends there is an integrated APIC ? */ |
1318 | if (!boot_cpu_has(X86_FEATURE_APIC) && | |
1319 | APIC_INTEGRATED(boot_cpu_apic_version)) { | |
49062454 | 1320 | apic_is_disabled = true; |
d10a9044 | 1321 | pr_err(FW_BUG "Local APIC not detected, force emulation\n"); |
0114a8e8 DL |
1322 | return APIC_PIC; |
1323 | } | |
1324 | #endif | |
638c0411 | 1325 | |
0114a8e8 DL |
1326 | /* Check MP table or ACPI MADT configuration */ |
1327 | if (!smp_found_config) { | |
1328 | disable_ioapic_support(); | |
3e730dad | 1329 | if (!acpi_lapic) { |
0114a8e8 | 1330 | pr_info("APIC: ACPI MADT or MP tables are not detected\n"); |
3e730dad DL |
1331 | return APIC_VIRTUAL_WIRE_NO_CONFIG; |
1332 | } | |
0114a8e8 DL |
1333 | return APIC_VIRTUAL_WIRE; |
1334 | } | |
1335 | ||
3e730dad DL |
1336 | #ifdef CONFIG_SMP |
1337 | /* If SMP should be disabled, then really disable it! */ | |
1338 | if (!setup_max_cpus) { | |
1339 | pr_info("APIC: SMP mode deactivated\n"); | |
1340 | return APIC_SYMMETRIC_IO_NO_ROUTING; | |
1341 | } | |
638c0411 | 1342 | #endif |
1da177e4 | 1343 | |
0114a8e8 DL |
1344 | return APIC_SYMMETRIC_IO; |
1345 | } | |
1346 | ||
97992387 TG |
1347 | /* Select the interrupt delivery mode for the BSP */ |
1348 | void __init apic_intr_mode_select(void) | |
1349 | { | |
1350 | apic_intr_mode = __apic_intr_mode_select(); | |
1351 | } | |
1352 | ||
fc90ccfd VS |
1353 | /* |
1354 | * An initial setup of the virtual wire mode. | |
1355 | */ | |
1356 | void __init init_bsp_APIC(void) | |
1357 | { | |
1358 | unsigned int value; | |
1359 | ||
1360 | /* | |
1361 | * Don't do the setup now if we have a SMP BIOS as the | |
1362 | * through-I/O-APIC virtual wire mode might be active. | |
1363 | */ | |
1364 | if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) | |
1365 | return; | |
1366 | ||
1367 | /* | |
1368 | * Do not trust the local APIC being empty at bootup. | |
1369 | */ | |
1370 | clear_local_APIC(); | |
1371 | ||
1372 | /* | |
1373 | * Enable APIC. | |
1374 | */ | |
1375 | value = apic_read(APIC_SPIV); | |
1376 | value &= ~APIC_VECTOR_MASK; | |
1377 | value |= APIC_SPIV_APIC_ENABLED; | |
1378 | ||
1379 | #ifdef CONFIG_X86_32 | |
1380 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1381 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1382 | (boot_cpu_data.x86 == 15)) | |
1383 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1384 | else | |
1385 | #endif | |
1386 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1387 | value |= SPURIOUS_APIC_VECTOR; | |
1388 | apic_write(APIC_SPIV, value); | |
1389 | ||
1390 | /* | |
1391 | * Set up the virtual wire mode. | |
1392 | */ | |
1393 | apic_write(APIC_LVT0, APIC_DM_EXTINT); | |
1394 | value = APIC_DM_NMI; | |
1395 | if (!lapic_is_integrated()) /* 82489DX */ | |
1396 | value |= APIC_LVT_LEVEL_TRIGGER; | |
1397 | if (apic_extnmi == APIC_EXTNMI_NONE) | |
1398 | value |= APIC_LVT_MASKED; | |
1399 | apic_write(APIC_LVT1, value); | |
1400 | } | |
1401 | ||
748b170c TG |
1402 | static void __init apic_bsp_setup(bool upmode); |
1403 | ||
4b1669e8 DL |
1404 | /* Init the interrupt delivery mode for the BSP */ |
1405 | void __init apic_intr_mode_init(void) | |
1406 | { | |
0c759131 | 1407 | bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); |
3e730dad | 1408 | |
4f45ed9f | 1409 | switch (apic_intr_mode) { |
4b1669e8 DL |
1410 | case APIC_PIC: |
1411 | pr_info("APIC: Keep in PIC mode(8259)\n"); | |
1412 | return; | |
1413 | case APIC_VIRTUAL_WIRE: | |
1414 | pr_info("APIC: Switch to virtual wire mode setup\n"); | |
3e730dad DL |
1415 | break; |
1416 | case APIC_VIRTUAL_WIRE_NO_CONFIG: | |
1417 | pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); | |
1418 | upmode = true; | |
3e730dad | 1419 | break; |
4b1669e8 | 1420 | case APIC_SYMMETRIC_IO: |
79761ce8 | 1421 | pr_info("APIC: Switch to symmetric I/O mode setup\n"); |
3e730dad DL |
1422 | break; |
1423 | case APIC_SYMMETRIC_IO_NO_ROUTING: | |
79761ce8 | 1424 | pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); |
3e730dad | 1425 | break; |
4b1669e8 | 1426 | } |
3e730dad | 1427 | |
7a116a2d KS |
1428 | default_setup_apic_routing(); |
1429 | ||
bb733e43 TG |
1430 | if (x86_platform.apic_post_init) |
1431 | x86_platform.apic_post_init(); | |
1432 | ||
3e730dad | 1433 | apic_bsp_setup(upmode); |
1da177e4 LT |
1434 | } |
1435 | ||
148f9bb8 | 1436 | static void lapic_setup_esr(void) |
c43da2f5 | 1437 | { |
9df08f10 CG |
1438 | unsigned int oldvalue, value, maxlvt; |
1439 | ||
1440 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1441 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1442 | return; |
1443 | } | |
c43da2f5 | 1444 | |
08125d3e | 1445 | if (apic->disable_esr) { |
c43da2f5 | 1446 | /* |
9df08f10 CG |
1447 | * Something untraceable is creating bad interrupts on |
1448 | * secondary quads ... for the moment, just leave the | |
1449 | * ESR disabled - we can't do anything useful with the | |
1450 | * errors anyway - mbligh | |
c43da2f5 | 1451 | */ |
ba21ebb6 | 1452 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1453 | return; |
c43da2f5 | 1454 | } |
9df08f10 CG |
1455 | |
1456 | maxlvt = lapic_get_maxlvt(); | |
1457 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1458 | apic_write(APIC_ESR, 0); | |
1459 | oldvalue = apic_read(APIC_ESR); | |
1460 | ||
1461 | /* enables sending errors */ | |
1462 | value = ERROR_APIC_VECTOR; | |
1463 | apic_write(APIC_LVTERR, value); | |
1464 | ||
1465 | /* | |
1466 | * spec says clear errors after enabling vector. | |
1467 | */ | |
1468 | if (maxlvt > 3) | |
1469 | apic_write(APIC_ESR, 0); | |
1470 | value = apic_read(APIC_ESR); | |
1471 | if (value != oldvalue) | |
1472 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1473 | "vector: 0x%08x after: 0x%08x\n", | |
1474 | oldvalue, value); | |
c43da2f5 CG |
1475 | } |
1476 | ||
cc8bf191 TG |
1477 | #define APIC_IR_REGS APIC_ISR_NR |
1478 | #define APIC_IR_BITS (APIC_IR_REGS * 32) | |
1479 | #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG) | |
1480 | ||
1481 | union apic_ir { | |
1482 | unsigned long map[APIC_IR_MAPSIZE]; | |
1483 | u32 regs[APIC_IR_REGS]; | |
1484 | }; | |
1485 | ||
1486 | static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr) | |
9b217f33 | 1487 | { |
cc8bf191 TG |
1488 | int i, bit; |
1489 | ||
1490 | /* Read the IRRs */ | |
1491 | for (i = 0; i < APIC_IR_REGS; i++) | |
1492 | irr->regs[i] = apic_read(APIC_IRR + i * 0x10); | |
1493 | ||
1494 | /* Read the ISRs */ | |
1495 | for (i = 0; i < APIC_IR_REGS; i++) | |
1496 | isr->regs[i] = apic_read(APIC_ISR + i * 0x10); | |
9b217f33 | 1497 | |
9b217f33 | 1498 | /* |
cc8bf191 TG |
1499 | * If the ISR map is not empty. ACK the APIC and run another round |
1500 | * to verify whether a pending IRR has been unblocked and turned | |
1501 | * into a ISR. | |
9b217f33 | 1502 | */ |
cc8bf191 TG |
1503 | if (!bitmap_empty(isr->map, APIC_IR_BITS)) { |
1504 | /* | |
1505 | * There can be multiple ISR bits set when a high priority | |
1506 | * interrupt preempted a lower priority one. Issue an ACK | |
1507 | * per set bit. | |
1508 | */ | |
1509 | for_each_set_bit(bit, isr->map, APIC_IR_BITS) | |
1510 | ack_APIC_irq(); | |
1511 | return true; | |
1512 | } | |
1513 | ||
1514 | return !bitmap_empty(irr->map, APIC_IR_BITS); | |
1515 | } | |
1516 | ||
1517 | /* | |
1518 | * After a crash, we no longer service the interrupts and a pending | |
1519 | * interrupt from previous kernel might still have ISR bit set. | |
1520 | * | |
1521 | * Most probably by now the CPU has serviced that pending interrupt and it | |
1522 | * might not have done the ack_APIC_irq() because it thought, interrupt | |
1523 | * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear | |
d9f6e12f | 1524 | * the ISR bit and cpu thinks it has already serviced the interrupt. Hence |
cc8bf191 TG |
1525 | * a vector might get locked. It was noticed for timer irq (vector |
1526 | * 0x31). Issue an extra EOI to clear ISR. | |
1527 | * | |
1528 | * If there are pending IRR bits they turn into ISR bits after a higher | |
1529 | * priority ISR bit has been acked. | |
1530 | */ | |
1531 | static void apic_pending_intr_clear(void) | |
1532 | { | |
1533 | union apic_ir irr, isr; | |
1534 | unsigned int i; | |
1535 | ||
1536 | /* 512 loops are way oversized and give the APIC a chance to obey. */ | |
1537 | for (i = 0; i < 512; i++) { | |
1538 | if (!apic_check_and_ack(&irr, &isr)) | |
1539 | return; | |
1540 | } | |
1541 | /* Dump the IRR/ISR content if that failed */ | |
1542 | pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map); | |
9b217f33 DL |
1543 | } |
1544 | ||
0e078e2f TG |
1545 | /** |
1546 | * setup_local_APIC - setup the local APIC | |
0aa002fe | 1547 | * |
543113d2 | 1548 | * Used to setup local APIC while initializing BSP or bringing up APs. |
0aa002fe | 1549 | * Always called with preemption disabled. |
0e078e2f | 1550 | */ |
b753a2b7 | 1551 | static void setup_local_APIC(void) |
1da177e4 | 1552 | { |
0aa002fe | 1553 | int cpu = smp_processor_id(); |
9b217f33 | 1554 | unsigned int value; |
8c3ba8d0 | 1555 | |
49062454 | 1556 | if (apic_is_disabled) { |
7167d08e | 1557 | disable_ioapic_support(); |
f1182638 JB |
1558 | return; |
1559 | } | |
1560 | ||
2640da4c TG |
1561 | /* |
1562 | * If this comes from kexec/kcrash the APIC might be enabled in | |
1563 | * SPIV. Soft disable it before doing further initialization. | |
1564 | */ | |
1565 | value = apic_read(APIC_SPIV); | |
1566 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1567 | apic_write(APIC_SPIV, value); | |
1568 | ||
89c38c28 CG |
1569 | #ifdef CONFIG_X86_32 |
1570 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1571 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1572 | apic_write(APIC_ESR, 0); |
1573 | apic_write(APIC_ESR, 0); | |
1574 | apic_write(APIC_ESR, 0); | |
1575 | apic_write(APIC_ESR, 0); | |
1576 | } | |
1577 | #endif | |
1da177e4 LT |
1578 | /* |
1579 | * Double-check whether this APIC is really registered. | |
1580 | * This is meaningless in clustered apic mode, so we skip it. | |
1581 | */ | |
c2777f98 | 1582 | BUG_ON(!apic->apic_id_registered()); |
1da177e4 LT |
1583 | |
1584 | /* | |
1585 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1586 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1587 | * document number 292116). So here it goes... | |
1588 | */ | |
a5c43296 | 1589 | apic->init_apic_ldr(); |
1da177e4 | 1590 | |
6f802c4b | 1591 | #ifdef CONFIG_X86_32 |
8c44963b | 1592 | if (apic->dest_mode_logical) { |
fe6f85ca JB |
1593 | int logical_apicid, ldr_apicid; |
1594 | ||
1595 | /* | |
1596 | * APIC LDR is initialized. If logical_apicid mapping was | |
1597 | * initialized during get_smp_config(), make sure it matches | |
1598 | * the actual value. | |
1599 | */ | |
1600 | logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); | |
1601 | ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
1602 | if (logical_apicid != BAD_APICID) | |
1603 | WARN_ON(logical_apicid != ldr_apicid); | |
1604 | /* Always use the value from LDR. */ | |
1605 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; | |
1606 | } | |
6f802c4b TH |
1607 | #endif |
1608 | ||
1da177e4 | 1609 | /* |
229b969b AL |
1610 | * Set Task Priority to 'accept all except vectors 0-31'. An APIC |
1611 | * vector in the 16-31 range could be delivered if TPR == 0, but we | |
1612 | * would think it's an exception and terrible things will happen. We | |
1613 | * never change this later on. | |
1da177e4 LT |
1614 | */ |
1615 | value = apic_read(APIC_TASKPRI); | |
1616 | value &= ~APIC_TPRI_MASK; | |
229b969b | 1617 | value |= 0x10; |
11a8e778 | 1618 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1619 | |
cc8bf191 | 1620 | /* Clear eventually stale ISR/IRR bits */ |
9b217f33 | 1621 | apic_pending_intr_clear(); |
da7ed9f9 | 1622 | |
1da177e4 LT |
1623 | /* |
1624 | * Now that we are all set up, enable the APIC | |
1625 | */ | |
1626 | value = apic_read(APIC_SPIV); | |
1627 | value &= ~APIC_VECTOR_MASK; | |
1628 | /* | |
1629 | * Enable APIC | |
1630 | */ | |
1631 | value |= APIC_SPIV_APIC_ENABLED; | |
1632 | ||
89c38c28 CG |
1633 | #ifdef CONFIG_X86_32 |
1634 | /* | |
1635 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1636 | * certain networking cards. If high frequency interrupts are | |
1637 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1638 | * entry is masked/unmasked at a high rate as well then sooner or | |
1639 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1640 | * from the device. If focus CPU is disabled then the hang goes | |
1641 | * away, oh well :-( | |
1642 | * | |
1643 | * [ This bug can be reproduced easily with a level-triggered | |
1644 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1645 | * BX chipset. ] | |
1646 | */ | |
1647 | /* | |
1648 | * Actually disabling the focus CPU check just makes the hang less | |
d9f6e12f | 1649 | * frequent as it makes the interrupt distribution model be more |
89c38c28 | 1650 | * like LRU than MRU (the short-term load is more even across CPUs). |
89c38c28 CG |
1651 | */ |
1652 | ||
1653 | /* | |
1654 | * - enable focus processor (bit==0) | |
1655 | * - 64bit mode always use processor focus | |
1656 | * so no need to set it | |
1657 | */ | |
1658 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1659 | #endif | |
3f14c746 | 1660 | |
1da177e4 LT |
1661 | /* |
1662 | * Set spurious IRQ vector | |
1663 | */ | |
1664 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1665 | apic_write(APIC_SPIV, value); |
1da177e4 | 1666 | |
39c89dff TG |
1667 | perf_events_lapic_init(); |
1668 | ||
1da177e4 LT |
1669 | /* |
1670 | * Set up LVT0, LVT1: | |
1671 | * | |
a1652bb8 | 1672 | * set up through-local-APIC on the boot CPU's LINT0. This is not |
1da177e4 LT |
1673 | * strictly necessary in pure symmetric-IO mode, but sometimes |
1674 | * we delegate interrupts to the 8259A. | |
1675 | */ | |
1676 | /* | |
1677 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1678 | */ | |
1679 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
ecf600f8 | 1680 | if (!cpu && (pic_mode || !value || ioapic_is_disabled)) { |
1da177e4 | 1681 | value = APIC_DM_EXTINT; |
0aa002fe | 1682 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1683 | } else { |
1684 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
0aa002fe | 1685 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1686 | } |
11a8e778 | 1687 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1688 | |
1689 | /* | |
b7c4948e HK |
1690 | * Only the BSP sees the LINT1 NMI signal by default. This can be |
1691 | * modified by apic_extnmi= boot option. | |
1da177e4 | 1692 | */ |
b7c4948e HK |
1693 | if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || |
1694 | apic_extnmi == APIC_EXTNMI_ALL) | |
1da177e4 LT |
1695 | value = APIC_DM_NMI; |
1696 | else | |
1697 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
ae41a2a4 DL |
1698 | |
1699 | /* Is 82489DX ? */ | |
1700 | if (!lapic_is_integrated()) | |
89c38c28 | 1701 | value |= APIC_LVT_LEVEL_TRIGGER; |
11a8e778 | 1702 | apic_write(APIC_LVT1, value); |
89c38c28 | 1703 | |
be71b855 AK |
1704 | #ifdef CONFIG_X86_MCE_INTEL |
1705 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1706 | if (!cpu) |
be71b855 AK |
1707 | cmci_recheck(); |
1708 | #endif | |
739f33b3 | 1709 | } |
1da177e4 | 1710 | |
05f7e46d | 1711 | static void end_local_APIC_setup(void) |
739f33b3 AK |
1712 | { |
1713 | lapic_setup_esr(); | |
fa6b95fc CG |
1714 | |
1715 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1716 | { |
1717 | unsigned int value; | |
1718 | /* Disable the local apic timer */ | |
1719 | value = apic_read(APIC_LVTT); | |
1720 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1721 | apic_write(APIC_LVTT, value); | |
1722 | } | |
fa6b95fc CG |
1723 | #endif |
1724 | ||
0e078e2f | 1725 | apic_pm_activate(); |
2fb270f3 JB |
1726 | } |
1727 | ||
05f7e46d TG |
1728 | /* |
1729 | * APIC setup function for application processors. Called from smpboot.c | |
1730 | */ | |
1731 | void apic_ap_setup(void) | |
2fb270f3 | 1732 | { |
05f7e46d | 1733 | setup_local_APIC(); |
2fb270f3 | 1734 | end_local_APIC_setup(); |
1da177e4 | 1735 | } |
1da177e4 | 1736 | |
d63107fa TG |
1737 | static __init void cpu_set_boot_apic(void); |
1738 | ||
d10a9044 TG |
1739 | static __init void apic_read_boot_cpu_id(bool x2apic) |
1740 | { | |
1741 | /* | |
1742 | * This can be invoked from check_x2apic() before the APIC has been | |
1743 | * selected. But that code knows for sure that the BIOS enabled | |
1744 | * X2APIC. | |
1745 | */ | |
1746 | if (x2apic) { | |
1747 | boot_cpu_physical_apicid = native_apic_msr_read(APIC_ID); | |
1748 | boot_cpu_apic_version = GET_APIC_VERSION(native_apic_msr_read(APIC_LVR)); | |
1749 | } else { | |
1750 | boot_cpu_physical_apicid = read_apic_id(); | |
1751 | boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
1752 | } | |
d63107fa | 1753 | cpu_set_boot_apic(); |
d10a9044 TG |
1754 | } |
1755 | ||
06cd9a7d | 1756 | #ifdef CONFIG_X86_X2APIC |
bfb05070 | 1757 | int x2apic_mode; |
db7d8e47 | 1758 | EXPORT_SYMBOL_GPL(x2apic_mode); |
12e189d3 TG |
1759 | |
1760 | enum { | |
1761 | X2APIC_OFF, | |
12e189d3 | 1762 | X2APIC_DISABLED, |
b8d1d163 DS |
1763 | /* All states below here have X2APIC enabled */ |
1764 | X2APIC_ON, | |
1765 | X2APIC_ON_LOCKED | |
12e189d3 TG |
1766 | }; |
1767 | static int x2apic_state; | |
1768 | ||
b8d1d163 DS |
1769 | static bool x2apic_hw_locked(void) |
1770 | { | |
1771 | u64 ia32_cap; | |
1772 | u64 msr; | |
1773 | ||
1774 | ia32_cap = x86_read_arch_cap_msr(); | |
1775 | if (ia32_cap & ARCH_CAP_XAPIC_DISABLE) { | |
1776 | rdmsrl(MSR_IA32_XAPIC_DISABLE_STATUS, msr); | |
1777 | return (msr & LEGACY_XAPIC_DISABLED); | |
1778 | } | |
1779 | return false; | |
1780 | } | |
1781 | ||
d786ad32 | 1782 | static void __x2apic_disable(void) |
44e25ff9 TG |
1783 | { |
1784 | u64 msr; | |
1785 | ||
93984fbd | 1786 | if (!boot_cpu_has(X86_FEATURE_APIC)) |
659006bf TG |
1787 | return; |
1788 | ||
44e25ff9 TG |
1789 | rdmsrl(MSR_IA32_APICBASE, msr); |
1790 | if (!(msr & X2APIC_ENABLE)) | |
1791 | return; | |
1792 | /* Disable xapic and x2apic first and then reenable xapic mode */ | |
1793 | wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1794 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1795 | printk_once(KERN_INFO "x2apic disabled\n"); | |
1796 | } | |
1797 | ||
d786ad32 | 1798 | static void __x2apic_enable(void) |
659006bf TG |
1799 | { |
1800 | u64 msr; | |
1801 | ||
1802 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1803 | if (msr & X2APIC_ENABLE) | |
1804 | return; | |
1805 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); | |
1806 | printk_once(KERN_INFO "x2apic enabled\n"); | |
1807 | } | |
1808 | ||
bfb05070 TG |
1809 | static int __init setup_nox2apic(char *str) |
1810 | { | |
1811 | if (x2apic_enabled()) { | |
1812 | int apicid = native_apic_msr_read(APIC_ID); | |
1813 | ||
1814 | if (apicid >= 255) { | |
8d3bcc44 KW |
1815 | pr_warn("Apicid: %08x, cannot enforce nox2apic\n", |
1816 | apicid); | |
bfb05070 TG |
1817 | return 0; |
1818 | } | |
b8d1d163 DS |
1819 | if (x2apic_hw_locked()) { |
1820 | pr_warn("APIC locked in x2apic mode, can't disable\n"); | |
1821 | return 0; | |
1822 | } | |
8d3bcc44 | 1823 | pr_warn("x2apic already enabled.\n"); |
44e25ff9 TG |
1824 | __x2apic_disable(); |
1825 | } | |
1826 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
12e189d3 | 1827 | x2apic_state = X2APIC_DISABLED; |
44e25ff9 | 1828 | x2apic_mode = 0; |
bfb05070 TG |
1829 | return 0; |
1830 | } | |
1831 | early_param("nox2apic", setup_nox2apic); | |
1832 | ||
659006bf TG |
1833 | /* Called from cpu_init() to enable x2apic on (secondary) cpus */ |
1834 | void x2apic_setup(void) | |
1835 | { | |
1836 | /* | |
b8d1d163 DS |
1837 | * Try to make the AP's APIC state match that of the BSP, but if the |
1838 | * BSP is unlocked and the AP is locked then there is a state mismatch. | |
1839 | * Warn about the mismatch in case a GP fault occurs due to a locked AP | |
1840 | * trying to be turned off. | |
1841 | */ | |
1842 | if (x2apic_state != X2APIC_ON_LOCKED && x2apic_hw_locked()) | |
1843 | pr_warn("x2apic lock mismatch between BSP and AP.\n"); | |
1844 | /* | |
1845 | * If x2apic is not in ON or LOCKED state, disable it if already enabled | |
659006bf TG |
1846 | * from BIOS. |
1847 | */ | |
b8d1d163 | 1848 | if (x2apic_state < X2APIC_ON) { |
659006bf TG |
1849 | __x2apic_disable(); |
1850 | return; | |
1851 | } | |
1852 | __x2apic_enable(); | |
1853 | } | |
1854 | ||
5a88f354 TG |
1855 | static __init void apic_set_fixmap(void); |
1856 | ||
44e25ff9 | 1857 | static __init void x2apic_disable(void) |
fb209bd8 | 1858 | { |
a57e456a | 1859 | u32 x2apic_id, state = x2apic_state; |
fb209bd8 | 1860 | |
a57e456a TG |
1861 | x2apic_mode = 0; |
1862 | x2apic_state = X2APIC_DISABLED; | |
1863 | ||
1864 | if (state != X2APIC_ON) | |
1865 | return; | |
fb209bd8 | 1866 | |
6d2d49d2 TG |
1867 | x2apic_id = read_apic_id(); |
1868 | if (x2apic_id >= 255) | |
1869 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
9aa16365 | 1870 | |
b8d1d163 DS |
1871 | if (x2apic_hw_locked()) { |
1872 | pr_warn("Cannot disable locked x2apic, id: %08x\n", x2apic_id); | |
1873 | return; | |
1874 | } | |
1875 | ||
6d2d49d2 | 1876 | __x2apic_disable(); |
5a88f354 | 1877 | apic_set_fixmap(); |
fb209bd8 YL |
1878 | } |
1879 | ||
659006bf | 1880 | static __init void x2apic_enable(void) |
6e1cb38a | 1881 | { |
659006bf | 1882 | if (x2apic_state != X2APIC_OFF) |
06cd9a7d YL |
1883 | return; |
1884 | ||
659006bf | 1885 | x2apic_mode = 1; |
12e189d3 | 1886 | x2apic_state = X2APIC_ON; |
659006bf | 1887 | __x2apic_enable(); |
6e1cb38a | 1888 | } |
d524165c | 1889 | |
62e61633 | 1890 | static __init void try_to_enable_x2apic(int remap_mode) |
07806c50 | 1891 | { |
659006bf | 1892 | if (x2apic_state == X2APIC_DISABLED) |
07806c50 JL |
1893 | return; |
1894 | ||
62e61633 | 1895 | if (remap_mode != IRQ_REMAP_X2APIC_MODE) { |
ab0f59c6 DW |
1896 | u32 apic_limit = 255; |
1897 | ||
26573a97 DW |
1898 | /* |
1899 | * Using X2APIC without IR is not architecturally supported | |
1900 | * on bare metal but may be supported in guests. | |
07806c50 | 1901 | */ |
26573a97 | 1902 | if (!x86_init.hyper.x2apic_available()) { |
62e61633 | 1903 | pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); |
44e25ff9 | 1904 | x2apic_disable(); |
07806c50 JL |
1905 | return; |
1906 | } | |
1907 | ||
ab0f59c6 DW |
1908 | /* |
1909 | * If the hypervisor supports extended destination ID in | |
1910 | * MSI, that increases the maximum APIC ID that can be | |
1911 | * used for non-remapped IRQ domains. | |
1912 | */ | |
1913 | if (x86_init.hyper.msi_ext_dest_id()) { | |
1914 | virt_ext_dest_id = 1; | |
1915 | apic_limit = 32767; | |
1916 | } | |
1917 | ||
07806c50 | 1918 | /* |
26573a97 | 1919 | * Without IR, all CPUs can be addressed by IOAPIC/MSI only |
d9f6e12f | 1920 | * in physical mode, and CPUs with an APIC ID that cannot |
26573a97 | 1921 | * be addressed must not be brought online. |
07806c50 | 1922 | */ |
ab0f59c6 | 1923 | x2apic_set_max_apicid(apic_limit); |
55eae7de | 1924 | x2apic_phys = 1; |
07806c50 | 1925 | } |
659006bf | 1926 | x2apic_enable(); |
55eae7de TG |
1927 | } |
1928 | ||
1929 | void __init check_x2apic(void) | |
1930 | { | |
1931 | if (x2apic_enabled()) { | |
1932 | pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); | |
1933 | x2apic_mode = 1; | |
b8d1d163 DS |
1934 | if (x2apic_hw_locked()) |
1935 | x2apic_state = X2APIC_ON_LOCKED; | |
1936 | else | |
1937 | x2apic_state = X2APIC_ON; | |
d10a9044 | 1938 | apic_read_boot_cpu_id(true); |
62436a4d | 1939 | } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { |
12e189d3 | 1940 | x2apic_state = X2APIC_DISABLED; |
55eae7de TG |
1941 | } |
1942 | } | |
1943 | #else /* CONFIG_X86_X2APIC */ | |
e3998434 | 1944 | void __init check_x2apic(void) |
55eae7de TG |
1945 | { |
1946 | if (!apic_is_x2apic_enabled()) | |
e3998434 | 1947 | return; |
55eae7de | 1948 | /* |
e3998434 | 1949 | * Checkme: Can we simply turn off x2APIC here instead of disabling the APIC? |
55eae7de | 1950 | */ |
e3998434 MJ |
1951 | pr_err("Kernel does not support x2APIC, please recompile with CONFIG_X86_X2APIC.\n"); |
1952 | pr_err("Disabling APIC, expect reduced performance and functionality.\n"); | |
1953 | ||
49062454 | 1954 | apic_is_disabled = true; |
e3998434 | 1955 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
55eae7de | 1956 | } |
55eae7de | 1957 | |
62e61633 | 1958 | static inline void try_to_enable_x2apic(int remap_mode) { } |
659006bf | 1959 | static inline void __x2apic_enable(void) { } |
55eae7de TG |
1960 | #endif /* !CONFIG_X86_X2APIC */ |
1961 | ||
ce69a784 GN |
1962 | void __init enable_IR_x2apic(void) |
1963 | { | |
1964 | unsigned long flags; | |
07806c50 | 1965 | int ret, ir_stat; |
b7f42ab2 | 1966 | |
ecf600f8 | 1967 | if (ioapic_is_disabled) { |
11277aab | 1968 | pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); |
2e63ad4b | 1969 | return; |
11277aab | 1970 | } |
2e63ad4b | 1971 | |
07806c50 JL |
1972 | ir_stat = irq_remapping_prepare(); |
1973 | if (ir_stat < 0 && !x2apic_supported()) | |
e670761f | 1974 | return; |
ce69a784 | 1975 | |
31dce14a | 1976 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1977 | if (ret) { |
ba21ebb6 | 1978 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1979 | return; |
5ffa4eb2 | 1980 | } |
6e1cb38a | 1981 | |
05c3dc2c | 1982 | local_irq_save(flags); |
b81bb373 | 1983 | legacy_pic->mask_all(); |
31dce14a | 1984 | mask_ioapic_entries(); |
05c3dc2c | 1985 | |
6a6256f9 | 1986 | /* If irq_remapping_prepare() succeeded, try to enable it */ |
07806c50 | 1987 | if (ir_stat >= 0) |
11277aab | 1988 | ir_stat = irq_remapping_enable(); |
07806c50 JL |
1989 | /* ir_stat contains the remap mode or an error code */ |
1990 | try_to_enable_x2apic(ir_stat); | |
a31bc327 | 1991 | |
07806c50 | 1992 | if (ir_stat < 0) |
31dce14a | 1993 | restore_ioapic_entries(); |
b81bb373 | 1994 | legacy_pic->restore_mask(); |
6e1cb38a | 1995 | local_irq_restore(flags); |
6e1cb38a | 1996 | } |
93758238 | 1997 | |
be7a656f | 1998 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1999 | /* |
2000 | * Detect and enable local APICs on non-SMP boards. | |
2001 | * Original code written by Keir Fraser. | |
2002 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 2003 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 2004 | */ |
1751aded | 2005 | static bool __init detect_init_APIC(void) |
1da177e4 | 2006 | { |
93984fbd | 2007 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
ba21ebb6 | 2008 | pr_info("No local APIC present\n"); |
1751aded | 2009 | return false; |
1da177e4 LT |
2010 | } |
2011 | ||
2012 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1751aded | 2013 | return true; |
1da177e4 | 2014 | } |
be7a656f | 2015 | #else |
5a7ae78f | 2016 | |
1751aded | 2017 | static bool __init apic_verify(void) |
5a7ae78f TG |
2018 | { |
2019 | u32 features, h, l; | |
2020 | ||
2021 | /* | |
2022 | * The APIC feature bit should now be enabled | |
2023 | * in `cpuid' | |
2024 | */ | |
2025 | features = cpuid_edx(1); | |
2026 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
8d3bcc44 | 2027 | pr_warn("Could not enable APIC!\n"); |
1751aded | 2028 | return false; |
5a7ae78f TG |
2029 | } |
2030 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
2031 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
2032 | ||
2033 | /* The BIOS may have set up the APIC at some other address */ | |
cbf2829b BD |
2034 | if (boot_cpu_data.x86 >= 6) { |
2035 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2036 | if (l & MSR_IA32_APICBASE_ENABLE) | |
2037 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
2038 | } | |
5a7ae78f TG |
2039 | |
2040 | pr_info("Found and enabled local APIC!\n"); | |
1751aded | 2041 | return true; |
5a7ae78f TG |
2042 | } |
2043 | ||
1751aded | 2044 | bool __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
2045 | { |
2046 | u32 h, l; | |
2047 | ||
49062454 | 2048 | if (apic_is_disabled) |
1751aded | 2049 | return false; |
5a7ae78f TG |
2050 | |
2051 | /* | |
2052 | * Some BIOSes disable the local APIC in the APIC_BASE | |
2053 | * MSR. This can only be done in software for Intel P6 or later | |
2054 | * and AMD K7 (Model > 1) or later. | |
2055 | */ | |
cbf2829b BD |
2056 | if (boot_cpu_data.x86 >= 6) { |
2057 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2058 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
2059 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
2060 | l &= ~MSR_IA32_APICBASE_BASE; | |
2061 | l |= MSR_IA32_APICBASE_ENABLE | addr; | |
2062 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2063 | enabled_via_apicbase = 1; | |
2064 | } | |
5a7ae78f TG |
2065 | } |
2066 | return apic_verify(); | |
2067 | } | |
2068 | ||
be7a656f YL |
2069 | /* |
2070 | * Detect and initialize APIC | |
2071 | */ | |
1751aded | 2072 | static bool __init detect_init_APIC(void) |
be7a656f | 2073 | { |
be7a656f | 2074 | /* Disabled by kernel option? */ |
49062454 | 2075 | if (apic_is_disabled) |
1751aded | 2076 | return false; |
be7a656f YL |
2077 | |
2078 | switch (boot_cpu_data.x86_vendor) { | |
2079 | case X86_VENDOR_AMD: | |
2080 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 2081 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
2082 | break; |
2083 | goto no_apic; | |
da33dfef PW |
2084 | case X86_VENDOR_HYGON: |
2085 | break; | |
be7a656f YL |
2086 | case X86_VENDOR_INTEL: |
2087 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
93984fbd | 2088 | (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) |
be7a656f YL |
2089 | break; |
2090 | goto no_apic; | |
2091 | default: | |
2092 | goto no_apic; | |
2093 | } | |
2094 | ||
93984fbd | 2095 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
be7a656f YL |
2096 | /* |
2097 | * Over-ride BIOS and try to enable the local APIC only if | |
2098 | * "lapic" specified. | |
2099 | */ | |
2100 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
2101 | pr_info("Local APIC disabled by BIOS -- " |
2102 | "you can enable it with \"lapic\"\n"); | |
1751aded | 2103 | return false; |
be7a656f | 2104 | } |
1751aded TG |
2105 | if (!apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
2106 | return false; | |
5a7ae78f | 2107 | } else { |
1751aded TG |
2108 | if (!apic_verify()) |
2109 | return false; | |
be7a656f | 2110 | } |
be7a656f YL |
2111 | |
2112 | apic_pm_activate(); | |
2113 | ||
1751aded | 2114 | return true; |
be7a656f YL |
2115 | |
2116 | no_apic: | |
ba21ebb6 | 2117 | pr_info("No local APIC present or hardware disabled\n"); |
1751aded | 2118 | return false; |
be7a656f YL |
2119 | } |
2120 | #endif | |
1da177e4 | 2121 | |
0e078e2f TG |
2122 | /** |
2123 | * init_apic_mappings - initialize APIC mappings | |
2124 | */ | |
1da177e4 LT |
2125 | void __init init_apic_mappings(void) |
2126 | { | |
c84cb373 | 2127 | if (apic_validate_deadline_timer()) |
de308d18 | 2128 | pr_info("TSC deadline timer available\n"); |
bd9240a1 | 2129 | |
d10a9044 | 2130 | if (x2apic_mode) |
6e1cb38a | 2131 | return; |
6e1cb38a | 2132 | |
4797f6b0 | 2133 | /* If no local APIC can be found return early */ |
1751aded | 2134 | if (!smp_found_config && !detect_init_APIC()) { |
4797f6b0 YL |
2135 | /* lets NOP'ify apic operations */ |
2136 | pr_info("APIC: disable apic facility\n"); | |
2137 | apic_disable(); | |
2138 | } else { | |
1da177e4 LT |
2139 | apic_phys = mp_lapic_addr; |
2140 | ||
4797f6b0 | 2141 | /* |
5ba039a5 DL |
2142 | * If the system has ACPI MADT tables or MP info, the LAPIC |
2143 | * address is already registered. | |
4797f6b0 | 2144 | */ |
5989cd6a | 2145 | if (!acpi_lapic && !smp_found_config) |
326a2e6b | 2146 | register_lapic_address(apic_phys); |
cec6be6d | 2147 | } |
1da177e4 LT |
2148 | } |
2149 | ||
5a88f354 TG |
2150 | static __init void apic_set_fixmap(void) |
2151 | { | |
2152 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); | |
2153 | apic_mmio_base = APIC_BASE; | |
2154 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
2155 | apic_mmio_base, mp_lapic_addr); | |
2156 | apic_read_boot_cpu_id(false); | |
2157 | } | |
2158 | ||
c0104d38 YL |
2159 | void __init register_lapic_address(unsigned long address) |
2160 | { | |
2161 | mp_lapic_addr = address; | |
2162 | ||
5a88f354 TG |
2163 | if (!x2apic_mode) |
2164 | apic_set_fixmap(); | |
c0104d38 YL |
2165 | } |
2166 | ||
1da177e4 | 2167 | /* |
0e078e2f | 2168 | * Local APIC interrupts |
1da177e4 LT |
2169 | */ |
2170 | ||
3c5e0267 TG |
2171 | /* |
2172 | * Common handling code for spurious_interrupt and spurious_vector entry | |
2173 | * points below. No point in allowing the compiler to inline it twice. | |
0e078e2f | 2174 | */ |
3c5e0267 | 2175 | static noinline void handle_spurious_interrupt(u8 vector) |
1da177e4 | 2176 | { |
dc1528dd YL |
2177 | u32 v; |
2178 | ||
61069de7 TG |
2179 | trace_spurious_apic_entry(vector); |
2180 | ||
f8a8fe61 TG |
2181 | inc_irq_stat(irq_spurious_count); |
2182 | ||
2183 | /* | |
2184 | * If this is a spurious interrupt then do not acknowledge | |
2185 | */ | |
2186 | if (vector == SPURIOUS_APIC_VECTOR) { | |
2187 | /* See SDM vol 3 */ | |
2188 | pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", | |
2189 | smp_processor_id()); | |
2190 | goto out; | |
2191 | } | |
2192 | ||
1da177e4 | 2193 | /* |
f8a8fe61 TG |
2194 | * If it is a vectored one, verify it's set in the ISR. If set, |
2195 | * acknowledge it. | |
1da177e4 | 2196 | */ |
2414e021 | 2197 | v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); |
f8a8fe61 TG |
2198 | if (v & (1 << (vector & 0x1f))) { |
2199 | pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", | |
2200 | vector, smp_processor_id()); | |
0e078e2f | 2201 | ack_APIC_irq(); |
f8a8fe61 TG |
2202 | } else { |
2203 | pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", | |
2204 | vector, smp_processor_id()); | |
2205 | } | |
2206 | out: | |
2414e021 | 2207 | trace_spurious_apic_exit(vector); |
0e078e2f | 2208 | } |
1da177e4 | 2209 | |
3c5e0267 TG |
2210 | /** |
2211 | * spurious_interrupt - Catch all for interrupts raised on unused vectors | |
2212 | * @regs: Pointer to pt_regs on stack | |
2213 | * @vector: The vector number | |
2214 | * | |
2215 | * This is invoked from ASM entry code to catch all interrupts which | |
2216 | * trigger on an entry which is routed to the common_spurious idtentry | |
2217 | * point. | |
2218 | */ | |
2219 | DEFINE_IDTENTRY_IRQ(spurious_interrupt) | |
2220 | { | |
2221 | handle_spurious_interrupt(vector); | |
2222 | } | |
2223 | ||
db0338ee | 2224 | DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt) |
633260fa | 2225 | { |
3c5e0267 | 2226 | handle_spurious_interrupt(SPURIOUS_APIC_VECTOR); |
0e078e2f | 2227 | } |
1da177e4 | 2228 | |
0e078e2f TG |
2229 | /* |
2230 | * This interrupt should never happen with our APIC/SMP architecture | |
2231 | */ | |
db0338ee | 2232 | DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt) |
0e078e2f | 2233 | { |
2b398bd9 YS |
2234 | static const char * const error_interrupt_reason[] = { |
2235 | "Send CS error", /* APIC Error Bit 0 */ | |
2236 | "Receive CS error", /* APIC Error Bit 1 */ | |
2237 | "Send accept error", /* APIC Error Bit 2 */ | |
2238 | "Receive accept error", /* APIC Error Bit 3 */ | |
2239 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
2240 | "Send illegal vector", /* APIC Error Bit 5 */ | |
2241 | "Received illegal vector", /* APIC Error Bit 6 */ | |
2242 | "Illegal register address", /* APIC Error Bit 7 */ | |
2243 | }; | |
61069de7 TG |
2244 | u32 v, i = 0; |
2245 | ||
61069de7 | 2246 | trace_error_apic_entry(ERROR_APIC_VECTOR); |
1da177e4 | 2247 | |
0e078e2f | 2248 | /* First tickle the hardware, only then report what went on. -- REW */ |
023de4a0 MR |
2249 | if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ |
2250 | apic_write(APIC_ESR, 0); | |
60283df7 | 2251 | v = apic_read(APIC_ESR); |
0e078e2f TG |
2252 | ack_APIC_irq(); |
2253 | atomic_inc(&irq_err_count); | |
ba7eda4c | 2254 | |
60283df7 RW |
2255 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", |
2256 | smp_processor_id(), v); | |
2b398bd9 | 2257 | |
60283df7 RW |
2258 | v &= 0xff; |
2259 | while (v) { | |
2260 | if (v & 0x1) | |
2b398bd9 YS |
2261 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); |
2262 | i++; | |
60283df7 | 2263 | v >>= 1; |
4b8073e4 | 2264 | } |
2b398bd9 YS |
2265 | |
2266 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); | |
2267 | ||
cf910e83 | 2268 | trace_error_apic_exit(ERROR_APIC_VECTOR); |
1da177e4 LT |
2269 | } |
2270 | ||
b5841765 | 2271 | /** |
36c9d674 CG |
2272 | * connect_bsp_APIC - attach the APIC to the interrupt system |
2273 | */ | |
05f7e46d | 2274 | static void __init connect_bsp_APIC(void) |
b5841765 | 2275 | { |
36c9d674 CG |
2276 | #ifdef CONFIG_X86_32 |
2277 | if (pic_mode) { | |
2278 | /* | |
2279 | * Do not trust the local APIC being empty at bootup. | |
2280 | */ | |
2281 | clear_local_APIC(); | |
2282 | /* | |
2283 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
2284 | * local APIC to INT and NMI lines. | |
2285 | */ | |
2286 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
2287 | "enabling APIC mode.\n"); | |
c0eaa453 | 2288 | imcr_pic_to_apic(); |
36c9d674 CG |
2289 | } |
2290 | #endif | |
b5841765 GC |
2291 | } |
2292 | ||
274cfe59 CG |
2293 | /** |
2294 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
2295 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
2296 | * | |
2297 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
2298 | * APIC is disabled. | |
2299 | */ | |
0e078e2f | 2300 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 2301 | { |
1b4ee4e4 CG |
2302 | unsigned int value; |
2303 | ||
c177b0bc CG |
2304 | #ifdef CONFIG_X86_32 |
2305 | if (pic_mode) { | |
2306 | /* | |
2307 | * Put the board back into PIC mode (has an effect only on | |
2308 | * certain older boards). Note that APIC interrupts, including | |
2309 | * IPIs, won't work beyond this point! The only exception are | |
2310 | * INIT IPIs. | |
2311 | */ | |
2312 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
2313 | "entering PIC mode.\n"); | |
c0eaa453 | 2314 | imcr_apic_to_pic(); |
c177b0bc CG |
2315 | return; |
2316 | } | |
2317 | #endif | |
2318 | ||
0e078e2f | 2319 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 2320 | |
0e078e2f TG |
2321 | /* For the spurious interrupt use vector F, and enable it */ |
2322 | value = apic_read(APIC_SPIV); | |
2323 | value &= ~APIC_VECTOR_MASK; | |
2324 | value |= APIC_SPIV_APIC_ENABLED; | |
2325 | value |= 0xf; | |
2326 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 2327 | |
0e078e2f TG |
2328 | if (!virt_wire_setup) { |
2329 | /* | |
2330 | * For LVT0 make it edge triggered, active high, | |
2331 | * external and enabled | |
2332 | */ | |
2333 | value = apic_read(APIC_LVT0); | |
2334 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2335 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2336 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2337 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2338 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
2339 | apic_write(APIC_LVT0, value); | |
2340 | } else { | |
2341 | /* Disable LVT0 */ | |
2342 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
2343 | } | |
b8ce3359 | 2344 | |
c177b0bc CG |
2345 | /* |
2346 | * For LVT1 make it edge triggered, active high, | |
2347 | * nmi and enabled | |
2348 | */ | |
0e078e2f TG |
2349 | value = apic_read(APIC_LVT1); |
2350 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2351 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2352 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2353 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2354 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
2355 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
2356 | } |
2357 | ||
8f54969d GZ |
2358 | /* |
2359 | * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated | |
2360 | * contiguously, it equals to current allocated max logical CPU ID plus 1. | |
12bf98b9 DL |
2361 | * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, |
2362 | * so the maximum of nr_logical_cpuids is nr_cpu_ids. | |
8f54969d GZ |
2363 | * |
2364 | * NOTE: Reserve 0 for BSP. | |
2365 | */ | |
2366 | static int nr_logical_cpuids = 1; | |
2367 | ||
2368 | /* | |
2369 | * Used to store mapping between logical CPU IDs and APIC IDs. | |
2370 | */ | |
7e75178a | 2371 | int cpuid_to_apicid[] = { |
8f54969d GZ |
2372 | [0 ... NR_CPUS - 1] = -1, |
2373 | }; | |
2374 | ||
dd926880 JH |
2375 | bool arch_match_cpu_phys_id(int cpu, u64 phys_id) |
2376 | { | |
2377 | return phys_id == cpuid_to_apicid[cpu]; | |
2378 | } | |
2379 | ||
d0055f35 | 2380 | #ifdef CONFIG_SMP |
f54d4434 | 2381 | static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) |
6a4d2657 | 2382 | { |
6a4d2657 | 2383 | /* Isolate the SMT bit(s) in the APICID and check for 0 */ |
f54d4434 TG |
2384 | u32 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; |
2385 | ||
2386 | if (smp_num_siblings == 1 || !(apicid & mask)) | |
2387 | cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); | |
6a4d2657 | 2388 | } |
5da80b28 TG |
2389 | |
2390 | /* | |
2391 | * Due to the utter mess of CPUID evaluation smp_num_siblings is not valid | |
2392 | * during early boot. Initialize the primary thread mask before SMP | |
2393 | * bringup. | |
2394 | */ | |
2395 | static int __init smp_init_primary_thread_mask(void) | |
2396 | { | |
2397 | unsigned int cpu; | |
2398 | ||
2399 | for (cpu = 0; cpu < nr_logical_cpuids; cpu++) | |
2400 | cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); | |
2401 | return 0; | |
2402 | } | |
2403 | early_initcall(smp_init_primary_thread_mask); | |
f54d4434 TG |
2404 | #else |
2405 | static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) { } | |
d0055f35 | 2406 | #endif |
6a4d2657 | 2407 | |
8f54969d GZ |
2408 | /* |
2409 | * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids | |
2410 | * and cpuid_to_apicid[] synchronized. | |
2411 | */ | |
2412 | static int allocate_logical_cpuid(int apicid) | |
2413 | { | |
2414 | int i; | |
2415 | ||
2416 | /* | |
2417 | * cpuid <-> apicid mapping is persistent, so when a cpu is up, | |
2418 | * check if the kernel has allocated a cpuid for it. | |
2419 | */ | |
2420 | for (i = 0; i < nr_logical_cpuids; i++) { | |
2421 | if (cpuid_to_apicid[i] == apicid) | |
2422 | return i; | |
2423 | } | |
2424 | ||
2425 | /* Allocate a new cpuid. */ | |
2426 | if (nr_logical_cpuids >= nr_cpu_ids) { | |
9b130ad5 | 2427 | WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " |
8f54969d | 2428 | "Processor %d/0x%x and the rest are ignored.\n", |
bb3f0a52 DL |
2429 | nr_cpu_ids, nr_logical_cpuids, apicid); |
2430 | return -EINVAL; | |
8f54969d GZ |
2431 | } |
2432 | ||
2433 | cpuid_to_apicid[nr_logical_cpuids] = apicid; | |
2434 | return nr_logical_cpuids++; | |
2435 | } | |
2436 | ||
249ada2c | 2437 | static void cpu_update_apic(int cpu, int apicid) |
be8a5685 | 2438 | { |
3e5095d1 | 2439 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 | 2440 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
1b313f4a | 2441 | #endif |
acb8bc09 TH |
2442 | #ifdef CONFIG_X86_32 |
2443 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = | |
2444 | apic->x86_32_early_logical_apicid(cpu); | |
2445 | #endif | |
1de88cd4 | 2446 | set_cpu_possible(cpu, true); |
2b85b3d2 DL |
2447 | physid_set(apicid, phys_cpu_present_map); |
2448 | set_cpu_present(cpu, true); | |
2449 | num_processors++; | |
7e1f85f9 | 2450 | |
5da80b28 TG |
2451 | if (system_state != SYSTEM_BOOTING) |
2452 | cpu_mark_primary_thread(cpu, apicid); | |
d63107fa TG |
2453 | } |
2454 | ||
2455 | static __init void cpu_set_boot_apic(void) | |
2456 | { | |
2457 | cpuid_to_apicid[0] = boot_cpu_physical_apicid; | |
249ada2c | 2458 | cpu_update_apic(0, boot_cpu_physical_apicid); |
d63107fa TG |
2459 | } |
2460 | ||
249ada2c | 2461 | int generic_processor_info(int apicid) |
d63107fa TG |
2462 | { |
2463 | int cpu, max = nr_cpu_ids; | |
2464 | ||
2465 | /* The boot CPU must be set before MADT/MPTABLE parsing happens */ | |
2466 | if (cpuid_to_apicid[0] == BAD_APICID) | |
2467 | panic("Boot CPU APIC not registered yet\n"); | |
2468 | ||
2469 | if (apicid == boot_cpu_physical_apicid) | |
2470 | return 0; | |
2471 | ||
2472 | if (disabled_cpu_apicid == apicid) { | |
2473 | int thiscpu = num_processors + disabled_cpus; | |
2474 | ||
2475 | pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", | |
2476 | thiscpu, apicid); | |
f54d4434 | 2477 | |
d63107fa TG |
2478 | disabled_cpus++; |
2479 | return -ENODEV; | |
2480 | } | |
2481 | ||
2482 | if (num_processors >= nr_cpu_ids) { | |
2483 | int thiscpu = max + disabled_cpus; | |
2484 | ||
2485 | pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " | |
2486 | "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2487 | ||
2488 | disabled_cpus++; | |
2489 | return -EINVAL; | |
2490 | } | |
2491 | ||
2492 | cpu = allocate_logical_cpuid(apicid); | |
2493 | if (cpu < 0) { | |
2494 | disabled_cpus++; | |
2495 | return -EINVAL; | |
2496 | } | |
2497 | ||
249ada2c | 2498 | cpu_update_apic(cpu, apicid); |
7e1f85f9 | 2499 | return cpu; |
be8a5685 AS |
2500 | } |
2501 | ||
d63107fa | 2502 | |
f598181a DW |
2503 | void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, |
2504 | bool dmar) | |
2505 | { | |
6285aa50 | 2506 | memset(msg, 0, sizeof(*msg)); |
f598181a | 2507 | |
6285aa50 TG |
2508 | msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; |
2509 | msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical; | |
2510 | msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF; | |
f598181a | 2511 | |
6285aa50 TG |
2512 | msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED; |
2513 | msg->arch_data.vector = cfg->vector; | |
f598181a | 2514 | |
6285aa50 | 2515 | msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; |
f598181a DW |
2516 | /* |
2517 | * Only the IOMMU itself can use the trick of putting destination | |
2518 | * APIC ID into the high bits of the address. Anything else would | |
2519 | * just be writing to memory if it tried that, and needs IR to | |
ab0f59c6 DW |
2520 | * address APICs which can't be addressed in the normal 32-bit |
2521 | * address range at 0xFFExxxxx. That is typically just 8 bits, but | |
2522 | * some hypervisors allow the extended destination ID field in bits | |
2523 | * 5-11 to be used, giving support for 15 bits of APIC IDs in total. | |
f598181a DW |
2524 | */ |
2525 | if (dmar) | |
6285aa50 | 2526 | msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8; |
ab0f59c6 DW |
2527 | else if (virt_ext_dest_id && cfg->dest_apicid < 0x8000) |
2528 | msg->arch_addr_lo.virt_destid_8_14 = cfg->dest_apicid >> 8; | |
f598181a | 2529 | else |
6285aa50 | 2530 | WARN_ON_ONCE(cfg->dest_apicid > 0xFF); |
f598181a DW |
2531 | } |
2532 | ||
6285aa50 TG |
2533 | u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid) |
2534 | { | |
2535 | u32 dest = msg->arch_addr_lo.destid_0_7; | |
2536 | ||
2537 | if (extid) | |
2538 | dest |= msg->arch_addr_hi.destid_8_31 << 8; | |
2539 | return dest; | |
2540 | } | |
2541 | EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid); | |
2542 | ||
f39642d0 KS |
2543 | #ifdef CONFIG_X86_64 |
2544 | void __init acpi_wake_cpu_handler_update(wakeup_cpu_handler handler) | |
2545 | { | |
2546 | struct apic **drv; | |
2547 | ||
2548 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) | |
2549 | (*drv)->wakeup_secondary_cpu_64 = handler; | |
2550 | } | |
2551 | #endif | |
2552 | ||
1551df64 MT |
2553 | /* |
2554 | * Override the generic EOI implementation with an optimized version. | |
2555 | * Only called during early boot when only one CPU is active and with | |
2556 | * interrupts disabled, so we know this does not race with actual APIC driver | |
2557 | * use. | |
2558 | */ | |
2559 | void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) | |
2560 | { | |
2561 | struct apic **drv; | |
2562 | ||
2563 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { | |
2564 | /* Should happen once for each apic */ | |
2565 | WARN_ON((*drv)->eoi_write == eoi_write); | |
8ca22552 | 2566 | (*drv)->native_eoi_write = (*drv)->eoi_write; |
1551df64 MT |
2567 | (*drv)->eoi_write = eoi_write; |
2568 | } | |
2569 | } | |
2570 | ||
374aab33 | 2571 | static void __init apic_bsp_up_setup(void) |
05f7e46d | 2572 | { |
374aab33 | 2573 | #ifdef CONFIG_X86_64 |
5d64d209 | 2574 | apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); |
374aab33 TG |
2575 | #endif |
2576 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
05f7e46d TG |
2577 | } |
2578 | ||
2579 | /** | |
2580 | * apic_bsp_setup - Setup function for local apic and io-apic | |
374aab33 | 2581 | * @upmode: Force UP mode (for APIC_init_uniprocessor) |
05f7e46d | 2582 | */ |
748b170c | 2583 | static void __init apic_bsp_setup(bool upmode) |
05f7e46d | 2584 | { |
05f7e46d | 2585 | connect_bsp_APIC(); |
374aab33 TG |
2586 | if (upmode) |
2587 | apic_bsp_up_setup(); | |
05f7e46d TG |
2588 | setup_local_APIC(); |
2589 | ||
05f7e46d | 2590 | enable_IO_APIC(); |
374aab33 TG |
2591 | end_local_APIC_setup(); |
2592 | irq_remap_enable_fault_handling(); | |
05f7e46d | 2593 | setup_IO_APIC(); |
7d65f9e8 | 2594 | lapic_update_legacy_vectors(); |
e714a91f TG |
2595 | } |
2596 | ||
30b8b006 TG |
2597 | #ifdef CONFIG_UP_LATE_INIT |
2598 | void __init up_late_init(void) | |
2599 | { | |
0c759131 DL |
2600 | if (apic_intr_mode == APIC_PIC) |
2601 | return; | |
e714a91f | 2602 | |
a2510d15 DL |
2603 | /* Setup local timer */ |
2604 | x86_init.timers.setup_percpu_clockev(); | |
30b8b006 TG |
2605 | } |
2606 | #endif | |
2607 | ||
89039b37 | 2608 | /* |
0e078e2f | 2609 | * Power management |
89039b37 | 2610 | */ |
0e078e2f TG |
2611 | #ifdef CONFIG_PM |
2612 | ||
2613 | static struct { | |
274cfe59 CG |
2614 | /* |
2615 | * 'active' is true if the local APIC was enabled by us and | |
2616 | * not the BIOS; this signifies that we are also responsible | |
2617 | * for disabling it before entering apm/acpi suspend | |
2618 | */ | |
0e078e2f TG |
2619 | int active; |
2620 | /* r/w apic fields */ | |
2621 | unsigned int apic_id; | |
2622 | unsigned int apic_taskpri; | |
2623 | unsigned int apic_ldr; | |
2624 | unsigned int apic_dfr; | |
2625 | unsigned int apic_spiv; | |
2626 | unsigned int apic_lvtt; | |
2627 | unsigned int apic_lvtpc; | |
2628 | unsigned int apic_lvt0; | |
2629 | unsigned int apic_lvt1; | |
2630 | unsigned int apic_lvterr; | |
2631 | unsigned int apic_tmict; | |
2632 | unsigned int apic_tdcr; | |
2633 | unsigned int apic_thmr; | |
42baa258 | 2634 | unsigned int apic_cmci; |
0e078e2f TG |
2635 | } apic_pm_state; |
2636 | ||
f3c6ea1b | 2637 | static int lapic_suspend(void) |
0e078e2f TG |
2638 | { |
2639 | unsigned long flags; | |
2640 | int maxlvt; | |
89039b37 | 2641 | |
0e078e2f TG |
2642 | if (!apic_pm_state.active) |
2643 | return 0; | |
89039b37 | 2644 | |
0e078e2f | 2645 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2646 | |
2d7a66d0 | 2647 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2648 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2649 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2650 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2651 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2652 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2653 | if (maxlvt >= 4) | |
2654 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2655 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2656 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2657 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2658 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2659 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2660 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2661 | if (maxlvt >= 5) |
2662 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2663 | #endif | |
42baa258 JG |
2664 | #ifdef CONFIG_X86_MCE_INTEL |
2665 | if (maxlvt >= 6) | |
2666 | apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); | |
2667 | #endif | |
24968cfd | 2668 | |
0e078e2f | 2669 | local_irq_save(flags); |
0f378d73 TW |
2670 | |
2671 | /* | |
2672 | * Mask IOAPIC before disabling the local APIC to prevent stale IRR | |
2673 | * entries on some implementations. | |
2674 | */ | |
2675 | mask_ioapic_entries(); | |
2676 | ||
0e078e2f | 2677 | disable_local_APIC(); |
fc1edaf9 | 2678 | |
70733e0c | 2679 | irq_remapping_disable(); |
fc1edaf9 | 2680 | |
0e078e2f TG |
2681 | local_irq_restore(flags); |
2682 | return 0; | |
1da177e4 LT |
2683 | } |
2684 | ||
f3c6ea1b | 2685 | static void lapic_resume(void) |
1da177e4 | 2686 | { |
0e078e2f TG |
2687 | unsigned int l, h; |
2688 | unsigned long flags; | |
31dce14a | 2689 | int maxlvt; |
b24696bc | 2690 | |
0e078e2f | 2691 | if (!apic_pm_state.active) |
f3c6ea1b | 2692 | return; |
89b831ef | 2693 | |
0e078e2f | 2694 | local_irq_save(flags); |
336224ba JR |
2695 | |
2696 | /* | |
2697 | * IO-APIC and PIC have their own resume routines. | |
2698 | * We just mask them here to make sure the interrupt | |
2699 | * subsystem is completely quiet while we enable x2apic | |
2700 | * and interrupt-remapping. | |
2701 | */ | |
2702 | mask_ioapic_entries(); | |
2703 | legacy_pic->mask_all(); | |
92206c90 | 2704 | |
659006bf TG |
2705 | if (x2apic_mode) { |
2706 | __x2apic_enable(); | |
2707 | } else { | |
92206c90 CG |
2708 | /* |
2709 | * Make sure the APICBASE points to the right address | |
2710 | * | |
2711 | * FIXME! This will be wrong if we ever support suspend on | |
2712 | * SMP! We'll need to do this as part of the CPU restore! | |
2713 | */ | |
cbf2829b BD |
2714 | if (boot_cpu_data.x86 >= 6) { |
2715 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2716 | l &= ~MSR_IA32_APICBASE_BASE; | |
2717 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2718 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2719 | } | |
d5e629a6 | 2720 | } |
6e1cb38a | 2721 | |
b24696bc | 2722 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2723 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2724 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2725 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2726 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2727 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2728 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2729 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2730 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
42baa258 | 2731 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2732 | if (maxlvt >= 5) |
2733 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
42baa258 JG |
2734 | #endif |
2735 | #ifdef CONFIG_X86_MCE_INTEL | |
2736 | if (maxlvt >= 6) | |
2737 | apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); | |
0e078e2f TG |
2738 | #endif |
2739 | if (maxlvt >= 4) | |
2740 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2741 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2742 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2743 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2744 | apic_write(APIC_ESR, 0); | |
2745 | apic_read(APIC_ESR); | |
2746 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2747 | apic_write(APIC_ESR, 0); | |
2748 | apic_read(APIC_ESR); | |
92206c90 | 2749 | |
70733e0c | 2750 | irq_remapping_reenable(x2apic_mode); |
31dce14a | 2751 | |
0e078e2f | 2752 | local_irq_restore(flags); |
0e078e2f | 2753 | } |
b8ce3359 | 2754 | |
274cfe59 CG |
2755 | /* |
2756 | * This device has no shutdown method - fully functioning local APICs | |
2757 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2758 | */ | |
2759 | ||
f3c6ea1b | 2760 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2761 | .resume = lapic_resume, |
2762 | .suspend = lapic_suspend, | |
2763 | }; | |
b8ce3359 | 2764 | |
148f9bb8 | 2765 | static void apic_pm_activate(void) |
0e078e2f TG |
2766 | { |
2767 | apic_pm_state.active = 1; | |
1da177e4 LT |
2768 | } |
2769 | ||
0e078e2f | 2770 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2771 | { |
0e078e2f | 2772 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
93984fbd | 2773 | if (boot_cpu_has(X86_FEATURE_APIC)) |
f3c6ea1b | 2774 | register_syscore_ops(&lapic_syscore_ops); |
e83a5fdc | 2775 | |
f3c6ea1b | 2776 | return 0; |
1da177e4 | 2777 | } |
b24696bc FY |
2778 | |
2779 | /* local apic needs to resume before other devices access its registers. */ | |
2780 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2781 | |
2782 | #else /* CONFIG_PM */ | |
2783 | ||
2784 | static void apic_pm_activate(void) { } | |
2785 | ||
2786 | #endif /* CONFIG_PM */ | |
1da177e4 | 2787 | |
f28c0ae2 | 2788 | #ifdef CONFIG_X86_64 |
e0e42142 | 2789 | |
148f9bb8 PG |
2790 | static int multi_checked; |
2791 | static int multi; | |
e0e42142 | 2792 | |
148f9bb8 | 2793 | static int set_multi(const struct dmi_system_id *d) |
e0e42142 YL |
2794 | { |
2795 | if (multi) | |
2796 | return 0; | |
6f0aced6 | 2797 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2798 | multi = 1; |
2799 | return 0; | |
2800 | } | |
2801 | ||
148f9bb8 | 2802 | static const struct dmi_system_id multi_dmi_table[] = { |
e0e42142 YL |
2803 | { |
2804 | .callback = set_multi, | |
2805 | .ident = "IBM System Summit2", | |
2806 | .matches = { | |
2807 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2808 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2809 | }, | |
2810 | }, | |
2811 | {} | |
2812 | }; | |
2813 | ||
148f9bb8 | 2814 | static void dmi_check_multi(void) |
e0e42142 YL |
2815 | { |
2816 | if (multi_checked) | |
2817 | return; | |
2818 | ||
2819 | dmi_check_system(multi_dmi_table); | |
2820 | multi_checked = 1; | |
2821 | } | |
2822 | ||
2823 | /* | |
2824 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2825 | * | |
2826 | * Thus far, the major user of this is IBM's Summit2 series: | |
2827 | * Clustered boxes may have unsynced TSC problems if they are | |
2828 | * multi-chassis. | |
2829 | * Use DMI to check them | |
2830 | */ | |
148f9bb8 | 2831 | int apic_is_clustered_box(void) |
e0e42142 YL |
2832 | { |
2833 | dmi_check_multi(); | |
411cf9ee | 2834 | return multi; |
1da177e4 | 2835 | } |
f28c0ae2 | 2836 | #endif |
1da177e4 LT |
2837 | |
2838 | /* | |
0e078e2f | 2839 | * APIC command line parameters |
1da177e4 | 2840 | */ |
789fa735 | 2841 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2842 | { |
49062454 | 2843 | apic_is_disabled = true; |
9175fc06 | 2844 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2845 | return 0; |
2846 | } | |
2847 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2848 | |
2c8c0e6b | 2849 | /* same as disableapic, for compatibility */ |
789fa735 | 2850 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2851 | { |
789fa735 | 2852 | return setup_disableapic(arg); |
6935d1f9 | 2853 | } |
2c8c0e6b | 2854 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2855 | |
2e7c2838 LT |
2856 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2857 | { | |
2858 | local_apic_timer_c2_ok = 1; | |
2859 | return 0; | |
2860 | } | |
2861 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2862 | ||
36fef094 | 2863 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2864 | { |
1da177e4 | 2865 | disable_apic_timer = 1; |
36fef094 | 2866 | return 0; |
6935d1f9 | 2867 | } |
36fef094 CG |
2868 | early_param("noapictimer", parse_disable_apic_timer); |
2869 | ||
2870 | static int __init parse_nolapic_timer(char *arg) | |
2871 | { | |
2872 | disable_apic_timer = 1; | |
2873 | return 0; | |
6935d1f9 | 2874 | } |
36fef094 | 2875 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2876 | |
79af9bec CG |
2877 | static int __init apic_set_verbosity(char *arg) |
2878 | { | |
2879 | if (!arg) { | |
ecf600f8 TG |
2880 | if (IS_ENABLED(CONFIG_X86_32)) |
2881 | return -EINVAL; | |
2882 | ||
2883 | ioapic_is_disabled = false; | |
79af9bec | 2884 | return 0; |
79af9bec CG |
2885 | } |
2886 | ||
2887 | if (strcmp("debug", arg) == 0) | |
2888 | apic_verbosity = APIC_DEBUG; | |
2889 | else if (strcmp("verbose", arg) == 0) | |
2890 | apic_verbosity = APIC_VERBOSE; | |
4fcab669 | 2891 | #ifdef CONFIG_X86_64 |
79af9bec | 2892 | else { |
8d3bcc44 | 2893 | pr_warn("APIC Verbosity level %s not recognised" |
79af9bec CG |
2894 | " use apic=verbose or apic=debug\n", arg); |
2895 | return -EINVAL; | |
2896 | } | |
4fcab669 | 2897 | #endif |
79af9bec CG |
2898 | |
2899 | return 0; | |
2900 | } | |
2901 | early_param("apic", apic_set_verbosity); | |
2902 | ||
1e934dda YL |
2903 | static int __init lapic_insert_resource(void) |
2904 | { | |
2905 | if (!apic_phys) | |
2906 | return -1; | |
2907 | ||
2908 | /* Put local APIC into the resource map. */ | |
2909 | lapic_resource.start = apic_phys; | |
2910 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2911 | insert_resource(&iomem_resource, &lapic_resource); | |
2912 | ||
2913 | return 0; | |
2914 | } | |
2915 | ||
2916 | /* | |
1506c8dc | 2917 | * need call insert after e820__reserve_resources() |
1e934dda YL |
2918 | * that is using request_resource |
2919 | */ | |
2920 | late_initcall(lapic_insert_resource); | |
151e0c7d HD |
2921 | |
2922 | static int __init apic_set_disabled_cpu_apicid(char *arg) | |
2923 | { | |
2924 | if (!arg || !get_option(&arg, &disabled_cpu_apicid)) | |
2925 | return -EINVAL; | |
2926 | ||
2927 | return 0; | |
2928 | } | |
2929 | early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); | |
b7c4948e HK |
2930 | |
2931 | static int __init apic_set_extnmi(char *arg) | |
2932 | { | |
2933 | if (!arg) | |
2934 | return -EINVAL; | |
2935 | ||
2936 | if (!strncmp("all", arg, 3)) | |
2937 | apic_extnmi = APIC_EXTNMI_ALL; | |
2938 | else if (!strncmp("none", arg, 4)) | |
2939 | apic_extnmi = APIC_EXTNMI_NONE; | |
2940 | else if (!strncmp("bsp", arg, 3)) | |
2941 | apic_extnmi = APIC_EXTNMI_BSP; | |
2942 | else { | |
2943 | pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); | |
2944 | return -EINVAL; | |
2945 | } | |
2946 | ||
2947 | return 0; | |
2948 | } | |
2949 | early_param("apic_extnmi", apic_set_extnmi); |