Commit | Line | Data |
---|---|---|
457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Local APIC handling, local APIC timers | |
4 | * | |
8f47e163 | 5 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
6 | * |
7 | * Fixes | |
8 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
9 | * thanks to Eric Gilmore | |
10 | * and Rolf G. Tews | |
11 | * for testing these extensively. | |
12 | * Maciej W. Rozycki : Various updates and fixes. | |
13 | * Mikael Pettersson : Power Management for UP-APIC. | |
14 | * Pavel Machek and | |
15 | * Mikael Pettersson : PM converted to driver model. | |
16 | */ | |
17 | ||
cdd6c482 | 18 | #include <linux/perf_event.h> |
1da177e4 | 19 | #include <linux/kernel_stat.h> |
d1de36f5 | 20 | #include <linux/mc146818rtc.h> |
70a20025 | 21 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
22 | #include <linux/clockchips.h> |
23 | #include <linux/interrupt.h> | |
57c8a661 | 24 | #include <linux/memblock.h> |
d1de36f5 IM |
25 | #include <linux/ftrace.h> |
26 | #include <linux/ioport.h> | |
186f4360 | 27 | #include <linux/export.h> |
f3c6ea1b | 28 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
29 | #include <linux/delay.h> |
30 | #include <linux/timex.h> | |
334955ef | 31 | #include <linux/i8253.h> |
6e1cb38a | 32 | #include <linux/dmar.h> |
d1de36f5 IM |
33 | #include <linux/init.h> |
34 | #include <linux/cpu.h> | |
35 | #include <linux/dmi.h> | |
d1de36f5 IM |
36 | #include <linux/smp.h> |
37 | #include <linux/mm.h> | |
1da177e4 | 38 | |
965e05ff TG |
39 | #include <xen/xen.h> |
40 | ||
83ab8514 | 41 | #include <asm/trace/irq_vectors.h> |
8a8f422d | 42 | #include <asm/irq_remapping.h> |
fb6a0408 | 43 | #include <asm/pc-conf-reg.h> |
cdd6c482 | 44 | #include <asm/perf_event.h> |
736decac | 45 | #include <asm/x86_init.h> |
60063497 | 46 | #include <linux/atomic.h> |
25a068b8 | 47 | #include <asm/barrier.h> |
1da177e4 | 48 | #include <asm/mpspec.h> |
d1de36f5 | 49 | #include <asm/i8259.h> |
73dea47f | 50 | #include <asm/proto.h> |
ad3bc25a | 51 | #include <asm/traps.h> |
2c8c0e6b | 52 | #include <asm/apic.h> |
13c01139 | 53 | #include <asm/acpi.h> |
7167d08e | 54 | #include <asm/io_apic.h> |
d1de36f5 IM |
55 | #include <asm/desc.h> |
56 | #include <asm/hpet.h> | |
d1de36f5 | 57 | #include <asm/mtrr.h> |
16f871bc | 58 | #include <asm/time.h> |
2bc13797 | 59 | #include <asm/smp.h> |
be71b855 | 60 | #include <asm/mce.h> |
8c3ba8d0 | 61 | #include <asm/tsc.h> |
2904ed8d | 62 | #include <asm/hypervisor.h> |
bd9240a1 PZ |
63 | #include <asm/cpu_device_id.h> |
64 | #include <asm/intel-family.h> | |
447ae316 | 65 | #include <asm/irq_regs.h> |
b8d1d163 | 66 | #include <asm/cpu.h> |
1da177e4 | 67 | |
79c9a17c TG |
68 | #include "local.h" |
69 | ||
ec70de8b | 70 | unsigned int num_processors; |
fdbecd9f | 71 | |
148f9bb8 | 72 | unsigned disabled_cpus; |
fdbecd9f | 73 | |
ec70de8b | 74 | /* Processor that is doing the boot up */ |
4705243d | 75 | u32 boot_cpu_physical_apicid __ro_after_init = BAD_APICID; |
cc08e04c | 76 | EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); |
5af5573e | 77 | |
6444b40e | 78 | u8 boot_cpu_apic_version __ro_after_init; |
cff9ab2b | 79 | |
80e5609c | 80 | /* |
fdbecd9f | 81 | * Bitmask of physically existing CPUs: |
80e5609c | 82 | */ |
ec70de8b BG |
83 | physid_mask_t phys_cpu_present_map; |
84 | ||
151e0c7d HD |
85 | /* |
86 | * Processor to be disabled specified by kernel parameter | |
87 | * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to | |
88 | * avoid undefined behaviour caused by sending INIT from AP to BSP. | |
89 | */ | |
4705243d | 90 | static u32 disabled_cpu_apicid __ro_after_init = BAD_APICID; |
151e0c7d | 91 | |
b7c4948e HK |
92 | /* |
93 | * This variable controls which CPUs receive external NMIs. By default, | |
94 | * external NMIs are delivered only to the BSP. | |
95 | */ | |
6444b40e | 96 | static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP; |
b7c4948e | 97 | |
ab0f59c6 DW |
98 | /* |
99 | * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID | |
100 | */ | |
101 | static bool virt_ext_dest_id __ro_after_init; | |
102 | ||
bea629d5 TG |
103 | /* For parallel bootup. */ |
104 | unsigned long apic_mmio_base __ro_after_init; | |
105 | ||
78c32000 TG |
106 | static inline bool apic_accessible(void) |
107 | { | |
108 | return x2apic_mode || apic_mmio_base; | |
109 | } | |
110 | ||
ec70de8b BG |
111 | /* |
112 | * Map cpu index to physical APIC ID | |
113 | */ | |
4705243d | 114 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_apicid, BAD_APICID); |
3e9e57fa | 115 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); |
ec70de8b | 116 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
3e9e57fa | 117 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); |
80e5609c | 118 | |
b3c51170 | 119 | #ifdef CONFIG_X86_32 |
f28c0ae2 | 120 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
6444b40e | 121 | static int enabled_via_apicbase __ro_after_init; |
f28c0ae2 | 122 | |
c0eaa453 CG |
123 | /* |
124 | * Handle interrupt mode configuration register (IMCR). | |
125 | * This register controls whether the interrupt signals | |
126 | * that reach the BSP come from the master PIC or from the | |
127 | * local APIC. Before entering Symmetric I/O Mode, either | |
128 | * the BIOS or the operating system must switch out of | |
129 | * PIC Mode by changing the IMCR. | |
130 | */ | |
5cda395f | 131 | static inline void imcr_pic_to_apic(void) |
c0eaa453 | 132 | { |
c0eaa453 | 133 | /* NMI and 8259 INTR go through APIC */ |
fb6a0408 | 134 | pc_conf_set(PC_CONF_MPS_IMCR, 0x01); |
c0eaa453 CG |
135 | } |
136 | ||
5cda395f | 137 | static inline void imcr_apic_to_pic(void) |
c0eaa453 | 138 | { |
c0eaa453 | 139 | /* NMI and 8259 INTR go directly to BSP */ |
fb6a0408 | 140 | pc_conf_set(PC_CONF_MPS_IMCR, 0x00); |
c0eaa453 | 141 | } |
b3c51170 YL |
142 | #endif |
143 | ||
279f1461 SS |
144 | /* |
145 | * Knob to control our willingness to enable the local APIC. | |
146 | * | |
147 | * +1=force-enable | |
148 | */ | |
149 | static int force_enable_local_apic __initdata; | |
dc9788f4 | 150 | |
279f1461 SS |
151 | /* |
152 | * APIC command line parameters | |
153 | */ | |
154 | static int __init parse_lapic(char *arg) | |
155 | { | |
97f2645f | 156 | if (IS_ENABLED(CONFIG_X86_32) && !arg) |
279f1461 | 157 | force_enable_local_apic = 1; |
27cf9298 | 158 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
279f1461 SS |
159 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
160 | return 0; | |
161 | } | |
162 | early_param("lapic", parse_lapic); | |
163 | ||
b3c51170 | 164 | #ifdef CONFIG_X86_64 |
bc1d99c1 | 165 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
166 | static __init int setup_apicpmtimer(char *s) |
167 | { | |
168 | apic_calibrate_pmtmr = 1; | |
169 | notsc_setup(NULL); | |
12441ccd | 170 | return 1; |
b3c51170 YL |
171 | } |
172 | __setup("apicpmtimer", setup_apicpmtimer); | |
173 | #endif | |
174 | ||
81287ad6 | 175 | static unsigned long mp_lapic_addr __ro_after_init; |
49062454 | 176 | bool apic_is_disabled __ro_after_init; |
b3c51170 | 177 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
25874a29 | 178 | static int disable_apic_timer __initdata; |
e83a5fdc | 179 | /* Local APIC timer works in C2 */ |
6444b40e | 180 | int local_apic_timer_c2_ok __ro_after_init; |
2e7c2838 LT |
181 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); |
182 | ||
e83a5fdc HS |
183 | /* |
184 | * Debug level, exported for io_apic.c | |
185 | */ | |
6444b40e | 186 | int apic_verbosity __ro_after_init; |
e83a5fdc | 187 | |
6444b40e | 188 | int pic_mode __ro_after_init; |
89c38c28 | 189 | |
bab4b27c | 190 | /* Have we found an MP table */ |
6444b40e | 191 | int smp_found_config __ro_after_init; |
bab4b27c | 192 | |
39928722 AD |
193 | static struct resource lapic_resource = { |
194 | .name = "Local APIC", | |
195 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
196 | }; | |
197 | ||
52ae346b | 198 | unsigned int lapic_timer_period = 0; |
d03030e9 | 199 | |
0e078e2f | 200 | static void apic_pm_activate(void); |
ba7eda4c | 201 | |
0e078e2f TG |
202 | /* |
203 | * Get the LAPIC version | |
204 | */ | |
205 | static inline int lapic_get_version(void) | |
ba7eda4c | 206 | { |
0e078e2f | 207 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
208 | } |
209 | ||
0e078e2f | 210 | /* |
9c803869 | 211 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
212 | */ |
213 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 214 | { |
9c803869 | 215 | return APIC_INTEGRATED(lapic_get_version()); |
ba7eda4c TG |
216 | } |
217 | ||
218 | /* | |
0e078e2f | 219 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 220 | */ |
0e078e2f | 221 | static int modern_apic(void) |
ba7eda4c | 222 | { |
0e078e2f TG |
223 | /* AMD systems use old APIC versions, so check the CPU */ |
224 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
225 | boot_cpu_data.x86 >= 0xf) | |
226 | return 1; | |
da33dfef PW |
227 | |
228 | /* Hygon systems use modern APIC */ | |
229 | if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) | |
230 | return 1; | |
231 | ||
0e078e2f | 232 | return lapic_get_version() >= 0x14; |
ba7eda4c TG |
233 | } |
234 | ||
08306ce6 | 235 | /* |
a933c618 CG |
236 | * right after this call apic become NOOP driven |
237 | * so apic->write/read doesn't do anything | |
08306ce6 | 238 | */ |
25874a29 | 239 | static void __init apic_disable(void) |
08306ce6 | 240 | { |
3af1e415 | 241 | apic_install_driver(&apic_noop); |
08306ce6 CG |
242 | } |
243 | ||
c1eeb2de | 244 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 245 | { |
ea7bdc65 JK |
246 | unsigned long flags; |
247 | ||
248 | local_irq_save(flags); | |
bf348f66 | 249 | apic_write(APIC_ICR2, SET_XAPIC_DEST_FIELD(id)); |
1b374e4d | 250 | apic_write(APIC_ICR, low); |
ea7bdc65 | 251 | local_irq_restore(flags); |
1b374e4d SS |
252 | } |
253 | ||
c1eeb2de | 254 | u64 native_apic_icr_read(void) |
1b374e4d SS |
255 | { |
256 | u32 icr1, icr2; | |
257 | ||
258 | icr2 = apic_read(APIC_ICR2); | |
259 | icr1 = apic_read(APIC_ICR); | |
260 | ||
cf9768d7 | 261 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
262 | } |
263 | ||
7c37e48b CG |
264 | #ifdef CONFIG_X86_32 |
265 | /** | |
266 | * get_physical_broadcast - Get number of physical broadcast IDs | |
267 | */ | |
268 | int get_physical_broadcast(void) | |
269 | { | |
270 | return modern_apic() ? 0xff : 0xf; | |
271 | } | |
272 | #endif | |
273 | ||
0e078e2f TG |
274 | /** |
275 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
276 | */ | |
37e650c7 | 277 | int lapic_get_maxlvt(void) |
1da177e4 | 278 | { |
36a028de CG |
279 | /* |
280 | * - we always have APIC integrated on 64bit mode | |
281 | * - 82489DXs do not report # of LVT entries | |
282 | */ | |
ae41a2a4 | 283 | return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; |
1da177e4 LT |
284 | } |
285 | ||
274cfe59 CG |
286 | /* |
287 | * Local APIC timer | |
288 | */ | |
289 | ||
c40aaec6 | 290 | /* Clock divisor */ |
c40aaec6 | 291 | #define APIC_DIVISOR 16 |
1a9e4c56 | 292 | #define TSC_DIVISOR 8 |
f07f4f90 | 293 | |
daf3af47 TG |
294 | /* i82489DX specific */ |
295 | #define I82489DX_BASE_DIVIDER (((0x2) << 18)) | |
296 | ||
0e078e2f TG |
297 | /* |
298 | * This function sets up the local APIC timer, with a timeout of | |
299 | * 'clocks' APIC bus clock. During calibration we actually call | |
300 | * this function twice on the boot CPU, once with a bogus timeout | |
301 | * value, second time for real. The other (noncalibrating) CPUs | |
302 | * call this function only once, with the real, calibrated value. | |
303 | * | |
304 | * We do reads before writes even if unnecessary, to get around the | |
305 | * P5 APIC double write bug. | |
306 | */ | |
0e078e2f | 307 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 308 | { |
0e078e2f | 309 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 310 | |
0e078e2f TG |
311 | lvtt_value = LOCAL_TIMER_VECTOR; |
312 | if (!oneshot) | |
313 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
279f1461 SS |
314 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
315 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; | |
316 | ||
daf3af47 TG |
317 | /* |
318 | * The i82489DX APIC uses bit 18 and 19 for the base divider. This | |
319 | * overlaps with bit 18 on integrated APICs, but is not documented | |
320 | * in the SDM. No problem though. i82489DX equipped systems do not | |
321 | * have TSC deadline timer. | |
322 | */ | |
f07f4f90 | 323 | if (!lapic_is_integrated()) |
daf3af47 | 324 | lvtt_value |= I82489DX_BASE_DIVIDER; |
f07f4f90 | 325 | |
0e078e2f TG |
326 | if (!irqen) |
327 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 328 | |
0e078e2f | 329 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 | 330 | |
279f1461 | 331 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
5d7c631d SL |
332 | /* |
333 | * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, | |
334 | * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. | |
335 | * According to Intel, MFENCE can do the serialization here. | |
336 | */ | |
337 | asm volatile("mfence" : : : "memory"); | |
279f1461 SS |
338 | return; |
339 | } | |
340 | ||
1da177e4 | 341 | /* |
0e078e2f | 342 | * Divide PICLK by 16 |
1da177e4 | 343 | */ |
0e078e2f | 344 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
345 | apic_write(APIC_TDCR, |
346 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
347 | APIC_TDR_DIV_16); | |
0e078e2f TG |
348 | |
349 | if (!oneshot) | |
f07f4f90 | 350 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
351 | } |
352 | ||
0e078e2f | 353 | /* |
a68c439b | 354 | * Setup extended LVT, AMD specific |
7b83dae7 | 355 | * |
a68c439b RR |
356 | * Software should use the LVT offsets the BIOS provides. The offsets |
357 | * are determined by the subsystems using it like those for MCE | |
358 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
359 | * are supported. Beginning with family 10h at least 4 offsets are | |
360 | * available. | |
286f5718 | 361 | * |
a68c439b RR |
362 | * Since the offsets must be consistent for all cores, we keep track |
363 | * of the LVT offsets in software and reserve the offset for the same | |
364 | * vector also to be used on other cores. An offset is freed by | |
365 | * setting the entry to APIC_EILVT_MASKED. | |
366 | * | |
367 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
368 | * "[Firmware Bug]: ..." error message is generated. However, if | |
369 | * software does not properly determines the offsets, it is not | |
370 | * necessarily a BIOS bug. | |
0e078e2f | 371 | */ |
7b83dae7 | 372 | |
a68c439b RR |
373 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
374 | ||
375 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
376 | { | |
377 | return (old & APIC_EILVT_MASKED) | |
378 | || (new == APIC_EILVT_MASKED) | |
379 | || ((new & ~APIC_EILVT_MASKED) == old); | |
380 | } | |
381 | ||
382 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
383 | { | |
8abc3122 | 384 | unsigned int rsvd, vector; |
a68c439b RR |
385 | |
386 | if (offset >= APIC_EILVT_NR_MAX) | |
387 | return ~0; | |
388 | ||
8abc3122 | 389 | rsvd = atomic_read(&eilvt_offsets[offset]); |
a68c439b | 390 | do { |
8abc3122 RR |
391 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
392 | if (vector && !eilvt_entry_is_changeable(vector, new)) | |
a68c439b RR |
393 | /* may not change if vectors are different */ |
394 | return rsvd; | |
f96fb2df | 395 | } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new)); |
a68c439b | 396 | |
f96fb2df | 397 | rsvd = new & ~APIC_EILVT_MASKED; |
8abc3122 RR |
398 | if (rsvd && rsvd != vector) |
399 | pr_info("LVT offset %d assigned for vector 0x%02x\n", | |
400 | offset, rsvd); | |
401 | ||
a68c439b RR |
402 | return new; |
403 | } | |
404 | ||
405 | /* | |
406 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
407 | * enables the vector. See also the BKDGs. Must be called with |
408 | * preemption disabled. | |
a68c439b RR |
409 | */ |
410 | ||
27afdf20 | 411 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 412 | { |
a68c439b RR |
413 | unsigned long reg = APIC_EILVTn(offset); |
414 | unsigned int new, old, reserved; | |
415 | ||
416 | new = (mask << 16) | (msg_type << 8) | vector; | |
417 | old = apic_read(reg); | |
418 | reserved = reserve_eilvt_offset(offset, new); | |
419 | ||
420 | if (reserved != new) { | |
eb48c9cb RR |
421 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
422 | "vector 0x%x, but the register is already in use for " | |
423 | "vector 0x%x on another cpu\n", | |
424 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
425 | return -EINVAL; |
426 | } | |
427 | ||
428 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
429 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
430 | "vector 0x%x, but the register is already in use for " | |
431 | "vector 0x%x on this cpu\n", | |
432 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
433 | return -EBUSY; |
434 | } | |
435 | ||
436 | apic_write(reg, new); | |
a8fcf1a2 | 437 | |
a68c439b | 438 | return 0; |
1da177e4 | 439 | } |
27afdf20 | 440 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 441 | |
0e078e2f TG |
442 | /* |
443 | * Program the next event, relative to now | |
444 | */ | |
445 | static int lapic_next_event(unsigned long delta, | |
446 | struct clock_event_device *evt) | |
1da177e4 | 447 | { |
0e078e2f TG |
448 | apic_write(APIC_TMICT, delta); |
449 | return 0; | |
1da177e4 LT |
450 | } |
451 | ||
279f1461 SS |
452 | static int lapic_next_deadline(unsigned long delta, |
453 | struct clock_event_device *evt) | |
454 | { | |
455 | u64 tsc; | |
456 | ||
25a068b8 DH |
457 | /* This MSR is special and need a special fence: */ |
458 | weak_wrmsr_fence(); | |
459 | ||
4ea1636b | 460 | tsc = rdtsc(); |
279f1461 SS |
461 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); |
462 | return 0; | |
463 | } | |
464 | ||
b23d8e52 | 465 | static int lapic_timer_shutdown(struct clock_event_device *evt) |
9b7711f0 | 466 | { |
0e078e2f | 467 | unsigned int v; |
9b7711f0 | 468 | |
0e078e2f TG |
469 | /* Lapic used as dummy for broadcast ? */ |
470 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
b23d8e52 | 471 | return 0; |
9b7711f0 | 472 | |
b23d8e52 VK |
473 | v = apic_read(APIC_LVTT); |
474 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
475 | apic_write(APIC_LVTT, v); | |
476 | apic_write(APIC_TMICT, 0); | |
b23d8e52 VK |
477 | return 0; |
478 | } | |
9b7711f0 | 479 | |
b23d8e52 VK |
480 | static inline int |
481 | lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) | |
482 | { | |
b23d8e52 VK |
483 | /* Lapic used as dummy for broadcast ? */ |
484 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
485 | return 0; | |
9b7711f0 | 486 | |
52ae346b | 487 | __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); |
b23d8e52 VK |
488 | return 0; |
489 | } | |
490 | ||
491 | static int lapic_timer_set_periodic(struct clock_event_device *evt) | |
492 | { | |
493 | return lapic_timer_set_periodic_oneshot(evt, false); | |
494 | } | |
495 | ||
496 | static int lapic_timer_set_oneshot(struct clock_event_device *evt) | |
497 | { | |
498 | return lapic_timer_set_periodic_oneshot(evt, true); | |
9b7711f0 HS |
499 | } |
500 | ||
1da177e4 | 501 | /* |
0e078e2f | 502 | * Local APIC timer broadcast function |
1da177e4 | 503 | */ |
9628937d | 504 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 505 | { |
0e078e2f | 506 | #ifdef CONFIG_SMP |
28b82352 | 507 | __apic_send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
508 | #endif |
509 | } | |
1da177e4 | 510 | |
25874a29 HK |
511 | |
512 | /* | |
513 | * The local apic timer can be used for any function which is CPU local. | |
514 | */ | |
515 | static struct clock_event_device lapic_clockevent = { | |
914122c3 FW |
516 | .name = "lapic", |
517 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
518 | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP | |
519 | | CLOCK_EVT_FEAT_DUMMY, | |
520 | .shift = 32, | |
521 | .set_state_shutdown = lapic_timer_shutdown, | |
522 | .set_state_periodic = lapic_timer_set_periodic, | |
523 | .set_state_oneshot = lapic_timer_set_oneshot, | |
524 | .set_state_oneshot_stopped = lapic_timer_shutdown, | |
525 | .set_next_event = lapic_next_event, | |
526 | .broadcast = lapic_timer_broadcast, | |
527 | .rating = 100, | |
528 | .irq = -1, | |
25874a29 HK |
529 | }; |
530 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
531 | ||
66abf238 BP |
532 | static const struct x86_cpu_id deadline_match[] __initconst = { |
533 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */ | |
534 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */ | |
616dd587 | 535 | |
66abf238 | 536 | X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020), |
d9e6dbcf | 537 | |
66abf238 BP |
538 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011), |
539 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e), | |
540 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c), | |
541 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003), | |
616dd587 | 542 | |
66abf238 BP |
543 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136), |
544 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014), | |
545 | X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0), | |
bd9240a1 | 546 | |
adefe55e TG |
547 | X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22), |
548 | X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20), | |
549 | X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17), | |
bd9240a1 | 550 | |
adefe55e TG |
551 | X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25), |
552 | X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17), | |
bd9240a1 | 553 | |
adefe55e TG |
554 | X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2), |
555 | X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2), | |
bd9240a1 | 556 | |
adefe55e TG |
557 | X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52), |
558 | X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52), | |
bd9240a1 PZ |
559 | |
560 | {}, | |
561 | }; | |
562 | ||
c84cb373 | 563 | static __init bool apic_validate_deadline_timer(void) |
bd9240a1 | 564 | { |
594a30fb | 565 | const struct x86_cpu_id *m; |
bd9240a1 PZ |
566 | u32 rev; |
567 | ||
c84cb373 TG |
568 | if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
569 | return false; | |
570 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) | |
571 | return true; | |
594a30fb HG |
572 | |
573 | m = x86_match_cpu(deadline_match); | |
bd9240a1 | 574 | if (!m) |
c84cb373 | 575 | return true; |
bd9240a1 | 576 | |
66abf238 | 577 | rev = (u32)m->driver_data; |
bd9240a1 PZ |
578 | |
579 | if (boot_cpu_data.microcode >= rev) | |
c84cb373 | 580 | return true; |
bd9240a1 PZ |
581 | |
582 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); | |
583 | pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " | |
584 | "please update microcode to version: 0x%x (or later)\n", rev); | |
c84cb373 | 585 | return false; |
bd9240a1 PZ |
586 | } |
587 | ||
0e078e2f | 588 | /* |
421f91d2 | 589 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
590 | * of the boot CPU and register the clock event in the framework. |
591 | */ | |
148f9bb8 | 592 | static void setup_APIC_timer(void) |
0e078e2f | 593 | { |
89cbc767 | 594 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
1da177e4 | 595 | |
349c004e | 596 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 | 597 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
d9f6e12f | 598 | /* Make LAPIC timer preferable over percpu HPET */ |
db954b58 VP |
599 | lapic_clockevent.rating = 150; |
600 | } | |
601 | ||
0e078e2f | 602 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 603 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 604 | |
279f1461 | 605 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
c6e9f42b | 606 | levt->name = "lapic-deadline"; |
279f1461 SS |
607 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | |
608 | CLOCK_EVT_FEAT_DUMMY); | |
609 | levt->set_next_event = lapic_next_deadline; | |
610 | clockevents_config_and_register(levt, | |
1a9e4c56 | 611 | tsc_khz * (1000 / TSC_DIVISOR), |
279f1461 SS |
612 | 0xF, ~0UL); |
613 | } else | |
614 | clockevents_register_device(levt); | |
0e078e2f | 615 | } |
1da177e4 | 616 | |
6731b0d6 NS |
617 | /* |
618 | * Install the updated TSC frequency from recalibration at the TSC | |
619 | * deadline clockevent devices. | |
620 | */ | |
621 | static void __lapic_update_tsc_freq(void *info) | |
622 | { | |
623 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); | |
624 | ||
625 | if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) | |
626 | return; | |
627 | ||
628 | clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); | |
629 | } | |
630 | ||
631 | void lapic_update_tsc_freq(void) | |
632 | { | |
633 | /* | |
634 | * The clockevent device's ->mult and ->shift can both be | |
635 | * changed. In order to avoid races, schedule the frequency | |
636 | * update code on each CPU. | |
637 | */ | |
638 | on_each_cpu(__lapic_update_tsc_freq, NULL, 0); | |
639 | } | |
640 | ||
2f04fa88 YL |
641 | /* |
642 | * In this functions we calibrate APIC bus clocks to the external timer. | |
643 | * | |
644 | * We want to do the calibration only once since we want to have local timer | |
d9f6e12f | 645 | * irqs synchronous. CPUs connected by the same APIC bus have the very same bus |
2f04fa88 YL |
646 | * frequency. |
647 | * | |
648 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
649 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
650 | * readout is broken, so it never gets out of the wait loop again. This was | |
651 | * also reported by others. | |
652 | * | |
653 | * Monitoring the jiffies value is inaccurate and the clockevents | |
654 | * infrastructure allows us to do a simple substitution of the interrupt | |
655 | * handler. | |
656 | * | |
657 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
658 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
659 | * back to normal later in the boot process). | |
660 | */ | |
661 | ||
662 | #define LAPIC_CAL_LOOPS (HZ/10) | |
663 | ||
664 | static __initdata int lapic_cal_loops = -1; | |
665 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
666 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
667 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
668 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
669 | ||
670 | /* | |
f897e60a | 671 | * Temporary interrupt handler and polled calibration function. |
2f04fa88 YL |
672 | */ |
673 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
674 | { | |
675 | unsigned long long tsc = 0; | |
676 | long tapic = apic_read(APIC_TMCCT); | |
677 | unsigned long pm = acpi_pm_read_early(); | |
678 | ||
59e21e3d | 679 | if (boot_cpu_has(X86_FEATURE_TSC)) |
4ea1636b | 680 | tsc = rdtsc(); |
2f04fa88 YL |
681 | |
682 | switch (lapic_cal_loops++) { | |
683 | case 0: | |
684 | lapic_cal_t1 = tapic; | |
685 | lapic_cal_tsc1 = tsc; | |
686 | lapic_cal_pm1 = pm; | |
687 | lapic_cal_j1 = jiffies; | |
688 | break; | |
689 | ||
690 | case LAPIC_CAL_LOOPS: | |
691 | lapic_cal_t2 = tapic; | |
692 | lapic_cal_tsc2 = tsc; | |
693 | if (pm < lapic_cal_pm1) | |
694 | pm += ACPI_PM_OVRRUN; | |
695 | lapic_cal_pm2 = pm; | |
696 | lapic_cal_j2 = jiffies; | |
697 | break; | |
698 | } | |
699 | } | |
700 | ||
754ef0cd YI |
701 | static int __init |
702 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
703 | { |
704 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
705 | const long pm_thresh = pm_100ms / 100; | |
706 | unsigned long mult; | |
707 | u64 res; | |
708 | ||
709 | #ifndef CONFIG_X86_PM_TIMER | |
710 | return -1; | |
711 | #endif | |
712 | ||
39ba5d43 | 713 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
714 | |
715 | /* Check, if the PM timer is available */ | |
716 | if (!deltapm) | |
717 | return -1; | |
718 | ||
719 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
720 | ||
721 | if (deltapm > (pm_100ms - pm_thresh) && | |
722 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 723 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
724 | return 0; |
725 | } | |
726 | ||
727 | res = (((u64)deltapm) * mult) >> 22; | |
728 | do_div(res, 1000000); | |
8d3bcc44 KW |
729 | pr_warn("APIC calibration not consistent " |
730 | "with PM-Timer: %ldms instead of 100ms\n", (long)res); | |
754ef0cd YI |
731 | |
732 | /* Correct the lapic counter value */ | |
733 | res = (((u64)(*delta)) * pm_100ms); | |
734 | do_div(res, deltapm); | |
735 | pr_info("APIC delta adjusted to PM-Timer: " | |
736 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
737 | *delta = (long)res; | |
738 | ||
739 | /* Correct the tsc counter value */ | |
59e21e3d | 740 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
754ef0cd | 741 | res = (((u64)(*deltatsc)) * pm_100ms); |
b189892d | 742 | do_div(res, deltapm); |
754ef0cd | 743 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 744 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
745 | (unsigned long)res, *deltatsc); |
746 | *deltatsc = (long)res; | |
b189892d CG |
747 | } |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
6eb4f082 JP |
752 | static int __init lapic_init_clockevent(void) |
753 | { | |
52ae346b | 754 | if (!lapic_timer_period) |
6eb4f082 JP |
755 | return -1; |
756 | ||
757 | /* Calculate the scaled math multiplication factor */ | |
52ae346b | 758 | lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, |
6eb4f082 JP |
759 | TICK_NSEC, lapic_clockevent.shift); |
760 | lapic_clockevent.max_delta_ns = | |
761 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); | |
762 | lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; | |
763 | lapic_clockevent.min_delta_ns = | |
764 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
765 | lapic_clockevent.min_delta_ticks = 0xF; | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
c8c40767 TG |
770 | bool __init apic_needs_pit(void) |
771 | { | |
772 | /* | |
773 | * If the frequencies are not known, PIT is required for both TSC | |
774 | * and apic timer calibration. | |
775 | */ | |
776 | if (!tsc_khz || !cpu_khz) | |
777 | return true; | |
778 | ||
97992387 | 779 | /* Is there an APIC at all or is it disabled? */ |
49062454 | 780 | if (!boot_cpu_has(X86_FEATURE_APIC) || apic_is_disabled) |
97992387 TG |
781 | return true; |
782 | ||
783 | /* | |
784 | * If interrupt delivery mode is legacy PIC or virtual wire without | |
54aa699e | 785 | * configuration, the local APIC timer won't be set up. Make sure |
97992387 TG |
786 | * that the PIT is initialized. |
787 | */ | |
788 | if (apic_intr_mode == APIC_PIC || | |
789 | apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG) | |
c8c40767 TG |
790 | return true; |
791 | ||
afa8b475 JS |
792 | /* Virt guests may lack ARAT, but still have DEADLINE */ |
793 | if (!boot_cpu_has(X86_FEATURE_ARAT)) | |
794 | return true; | |
795 | ||
c8c40767 TG |
796 | /* Deadline timer is based on TSC so no further PIT action required */ |
797 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) | |
798 | return false; | |
799 | ||
800 | /* APIC timer disabled? */ | |
801 | if (disable_apic_timer) | |
802 | return true; | |
803 | /* | |
804 | * The APIC timer frequency is known already, no PIT calibration | |
805 | * required. If unknown, let the PIT be initialized. | |
806 | */ | |
807 | return lapic_timer_period == 0; | |
808 | } | |
809 | ||
2f04fa88 YL |
810 | static int __init calibrate_APIC_clock(void) |
811 | { | |
89cbc767 | 812 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
f897e60a TG |
813 | u64 tsc_perj = 0, tsc_start = 0; |
814 | unsigned long jif_start; | |
2f04fa88 | 815 | unsigned long deltaj; |
754ef0cd | 816 | long delta, deltatsc; |
2f04fa88 YL |
817 | int pm_referenced = 0; |
818 | ||
6eb4f082 JP |
819 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
820 | return 0; | |
821 | ||
822 | /* | |
823 | * Check if lapic timer has already been calibrated by platform | |
824 | * specific routine, such as tsc calibration code. If so just fill | |
1ade93ef JP |
825 | * in the clockevent structure and return. |
826 | */ | |
6eb4f082 | 827 | if (!lapic_init_clockevent()) { |
1ade93ef | 828 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
52ae346b | 829 | lapic_timer_period); |
6eb4f082 JP |
830 | /* |
831 | * Direct calibration methods must have an always running | |
832 | * local APIC timer, no need for broadcast timer. | |
833 | */ | |
1ade93ef JP |
834 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
835 | return 0; | |
836 | } | |
837 | ||
279f1461 SS |
838 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
839 | "calibrating APIC timer ...\n"); | |
840 | ||
f897e60a TG |
841 | /* |
842 | * There are platforms w/o global clockevent devices. Instead of | |
843 | * making the calibration conditional on that, use a polling based | |
844 | * approach everywhere. | |
845 | */ | |
2f04fa88 YL |
846 | local_irq_disable(); |
847 | ||
2f04fa88 | 848 | /* |
81608f3c | 849 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
850 | * can underflow in the 100ms detection time frame |
851 | */ | |
81608f3c | 852 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 | 853 | |
f897e60a TG |
854 | /* |
855 | * Methods to terminate the calibration loop: | |
856 | * 1) Global clockevent if available (jiffies) | |
857 | * 2) TSC if available and frequency is known | |
858 | */ | |
859 | jif_start = READ_ONCE(jiffies); | |
860 | ||
861 | if (tsc_khz) { | |
862 | tsc_start = rdtsc(); | |
863 | tsc_perj = div_u64((u64)tsc_khz * 1000, HZ); | |
864 | } | |
865 | ||
866 | /* | |
867 | * Enable interrupts so the tick can fire, if a global | |
868 | * clockevent device is available | |
869 | */ | |
2f04fa88 YL |
870 | local_irq_enable(); |
871 | ||
f897e60a TG |
872 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) { |
873 | /* Wait for a tick to elapse */ | |
874 | while (1) { | |
875 | if (tsc_khz) { | |
876 | u64 tsc_now = rdtsc(); | |
877 | if ((tsc_now - tsc_start) >= tsc_perj) { | |
878 | tsc_start += tsc_perj; | |
879 | break; | |
880 | } | |
881 | } else { | |
882 | unsigned long jif_now = READ_ONCE(jiffies); | |
883 | ||
884 | if (time_after(jif_now, jif_start)) { | |
885 | jif_start = jif_now; | |
886 | break; | |
887 | } | |
888 | } | |
889 | cpu_relax(); | |
890 | } | |
2f04fa88 | 891 | |
f897e60a TG |
892 | /* Invoke the calibration routine */ |
893 | local_irq_disable(); | |
894 | lapic_cal_handler(NULL); | |
895 | local_irq_enable(); | |
896 | } | |
2f04fa88 | 897 | |
f897e60a | 898 | local_irq_disable(); |
2f04fa88 YL |
899 | |
900 | /* Build delta t1-t2 as apic timer counts down */ | |
901 | delta = lapic_cal_t1 - lapic_cal_t2; | |
902 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
903 | ||
754ef0cd YI |
904 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
905 | ||
b189892d CG |
906 | /* we trust the PM based calibration if possible */ |
907 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 908 | &delta, &deltatsc); |
2f04fa88 | 909 | |
52ae346b | 910 | lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
6eb4f082 | 911 | lapic_init_clockevent(); |
2f04fa88 YL |
912 | |
913 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 914 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 | 915 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
52ae346b | 916 | lapic_timer_period); |
2f04fa88 | 917 | |
59e21e3d | 918 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
2f04fa88 YL |
919 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
920 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
921 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
922 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
923 | } |
924 | ||
925 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
926 | "%u.%04u MHz.\n", | |
52ae346b DD |
927 | lapic_timer_period / (1000000 / HZ), |
928 | lapic_timer_period % (1000000 / HZ)); | |
2f04fa88 YL |
929 | |
930 | /* | |
931 | * Do a sanity check on the APIC calibration result | |
932 | */ | |
52ae346b | 933 | if (lapic_timer_period < (1000000 / HZ)) { |
2f04fa88 | 934 | local_irq_enable(); |
8d3bcc44 | 935 | pr_warn("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
936 | return -1; |
937 | } | |
938 | ||
939 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
940 | ||
b189892d | 941 | /* |
f897e60a TG |
942 | * PM timer calibration failed or not turned on so lets try APIC |
943 | * timer based calibration, if a global clockevent device is | |
944 | * available. | |
b189892d | 945 | */ |
f897e60a | 946 | if (!pm_referenced && global_clock_event) { |
2f04fa88 YL |
947 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); |
948 | ||
949 | /* | |
950 | * Setup the apic timer manually | |
951 | */ | |
952 | levt->event_handler = lapic_cal_handler; | |
b23d8e52 | 953 | lapic_timer_set_periodic(levt); |
2f04fa88 YL |
954 | lapic_cal_loops = -1; |
955 | ||
956 | /* Let the interrupts run */ | |
957 | local_irq_enable(); | |
958 | ||
959 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
960 | cpu_relax(); | |
961 | ||
2f04fa88 | 962 | /* Stop the lapic timer */ |
c948c260 | 963 | local_irq_disable(); |
b23d8e52 | 964 | lapic_timer_shutdown(levt); |
2f04fa88 | 965 | |
2f04fa88 YL |
966 | /* Jiffies delta */ |
967 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
968 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
969 | ||
970 | /* Check, if the jiffies result is consistent */ | |
971 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
972 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
973 | else | |
974 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
c948c260 TG |
975 | } |
976 | local_irq_enable(); | |
2f04fa88 YL |
977 | |
978 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
8d3bcc44 | 979 | pr_warn("APIC timer disabled due to verification failure\n"); |
843c4089 | 980 | return -1; |
2f04fa88 YL |
981 | } |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
e83a5fdc HS |
986 | /* |
987 | * Setup the boot APIC | |
988 | * | |
989 | * Calibrate and verify the result. | |
990 | */ | |
0e078e2f TG |
991 | void __init setup_boot_APIC_clock(void) |
992 | { | |
993 | /* | |
274cfe59 CG |
994 | * The local apic timer can be disabled via the kernel |
995 | * commandline or from the CPU detection code. Register the lapic | |
996 | * timer as a dummy clock event source on SMP systems, so the | |
997 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
998 | */ |
999 | if (disable_apic_timer) { | |
ba21ebb6 | 1000 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 1001 | /* No broadcast on UP ! */ |
9d09951d TG |
1002 | if (num_possible_cpus() > 1) { |
1003 | lapic_clockevent.mult = 1; | |
0e078e2f | 1004 | setup_APIC_timer(); |
9d09951d | 1005 | } |
0e078e2f TG |
1006 | return; |
1007 | } | |
1008 | ||
89b3b1f4 | 1009 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
1010 | /* No broadcast on UP ! */ |
1011 | if (num_possible_cpus() > 1) | |
1012 | setup_APIC_timer(); | |
1013 | return; | |
1014 | } | |
1015 | ||
0e078e2f TG |
1016 | /* |
1017 | * If nmi_watchdog is set to IO_APIC, we need the | |
1018 | * PIT/HPET going. Otherwise register lapic as a dummy | |
1019 | * device. | |
1020 | */ | |
072b198a | 1021 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 1022 | |
274cfe59 | 1023 | /* Setup the lapic or request the broadcast */ |
0e078e2f | 1024 | setup_APIC_timer(); |
07c94a38 | 1025 | amd_e400_c1e_apic_setup(); |
0e078e2f TG |
1026 | } |
1027 | ||
148f9bb8 | 1028 | void setup_secondary_APIC_clock(void) |
0e078e2f | 1029 | { |
0e078e2f | 1030 | setup_APIC_timer(); |
07c94a38 | 1031 | amd_e400_c1e_apic_setup(); |
0e078e2f TG |
1032 | } |
1033 | ||
1034 | /* | |
1035 | * The guts of the apic timer interrupt | |
1036 | */ | |
1037 | static void local_apic_timer_interrupt(void) | |
1038 | { | |
3bec6def | 1039 | struct clock_event_device *evt = this_cpu_ptr(&lapic_events); |
0e078e2f TG |
1040 | |
1041 | /* | |
1042 | * Normally we should not be here till LAPIC has been initialized but | |
1043 | * in some cases like kdump, its possible that there is a pending LAPIC | |
1044 | * timer interrupt from previous kernel's context and is delivered in | |
1045 | * new kernel the moment interrupts are enabled. | |
1046 | * | |
1047 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
1048 | * its possible that when we get here evt->event_handler is NULL. | |
1049 | * Check for event_handler being NULL and discard the interrupt as | |
1050 | * spurious. | |
1051 | */ | |
1052 | if (!evt->event_handler) { | |
8d3bcc44 KW |
1053 | pr_warn("Spurious LAPIC timer interrupt on cpu %d\n", |
1054 | smp_processor_id()); | |
0e078e2f | 1055 | /* Switch it off */ |
b23d8e52 | 1056 | lapic_timer_shutdown(evt); |
0e078e2f TG |
1057 | return; |
1058 | } | |
1059 | ||
1060 | /* | |
1061 | * the NMI deadlock-detector uses this. | |
1062 | */ | |
915b0d01 | 1063 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
1064 | |
1065 | evt->event_handler(evt); | |
1066 | } | |
1067 | ||
1068 | /* | |
1069 | * Local APIC timer interrupt. This is the most natural way for doing | |
1070 | * local interrupts, but local timer interrupts can be emulated by | |
1071 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
1072 | * | |
1073 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
1074 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
1075 | */ | |
db0338ee | 1076 | DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt) |
0e078e2f TG |
1077 | { |
1078 | struct pt_regs *old_regs = set_irq_regs(regs); | |
1079 | ||
670c04ad | 1080 | apic_eoi(); |
cf910e83 | 1081 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); |
0e078e2f | 1082 | local_apic_timer_interrupt(); |
cf910e83 | 1083 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
274cfe59 | 1084 | |
0e078e2f TG |
1085 | set_irq_regs(old_regs); |
1086 | } | |
1087 | ||
0e078e2f TG |
1088 | /* |
1089 | * Local APIC start and shutdown | |
1090 | */ | |
1091 | ||
1092 | /** | |
1093 | * clear_local_APIC - shutdown the local APIC | |
1094 | * | |
1095 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
1096 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
1097 | * leftovers during boot. | |
1098 | */ | |
1099 | void clear_local_APIC(void) | |
1100 | { | |
2584a82d | 1101 | int maxlvt; |
0e078e2f TG |
1102 | u32 v; |
1103 | ||
78c32000 | 1104 | if (!apic_accessible()) |
d3432896 AK |
1105 | return; |
1106 | ||
1107 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
1108 | /* |
1109 | * Masking an LVT entry can trigger a local APIC error | |
1110 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1111 | */ | |
1112 | if (maxlvt >= 3) { | |
1113 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
1114 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
1115 | } | |
1116 | /* | |
1117 | * Careful: we have to set masks only first to deassert | |
1118 | * any level-triggered sources. | |
1119 | */ | |
1120 | v = apic_read(APIC_LVTT); | |
1121 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
1122 | v = apic_read(APIC_LVT0); | |
1123 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
1124 | v = apic_read(APIC_LVT1); | |
1125 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
1126 | if (maxlvt >= 4) { | |
1127 | v = apic_read(APIC_LVTPC); | |
1128 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1129 | } | |
1130 | ||
6764014b | 1131 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 1132 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
1133 | if (maxlvt >= 5) { |
1134 | v = apic_read(APIC_LVTTHMR); | |
1135 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
1136 | } | |
1137 | #endif | |
5ca8681c AK |
1138 | #ifdef CONFIG_X86_MCE_INTEL |
1139 | if (maxlvt >= 6) { | |
1140 | v = apic_read(APIC_LVTCMCI); | |
1141 | if (!(v & APIC_LVT_MASKED)) | |
1142 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
1143 | } | |
1144 | #endif | |
1145 | ||
0e078e2f TG |
1146 | /* |
1147 | * Clean APIC state for other OSs: | |
1148 | */ | |
1149 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
1150 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1151 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1152 | if (maxlvt >= 3) | |
1153 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
1154 | if (maxlvt >= 4) | |
1155 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
1156 | |
1157 | /* Integrated APIC (!82489DX) ? */ | |
1158 | if (lapic_is_integrated()) { | |
1159 | if (maxlvt > 3) | |
1160 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
1161 | apic_write(APIC_ESR, 0); | |
1162 | apic_read(APIC_ESR); | |
1163 | } | |
0e078e2f TG |
1164 | } |
1165 | ||
1166 | /** | |
60dcaad5 TG |
1167 | * apic_soft_disable - Clears and software disables the local APIC on hotplug |
1168 | * | |
1169 | * Contrary to disable_local_APIC() this does not touch the enable bit in | |
1170 | * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC | |
1171 | * bus would require a hardware reset as the APIC would lose track of bus | |
1172 | * arbitration. On systems with FSB delivery APICBASE could be disabled, | |
1173 | * but it has to be guaranteed that no interrupt is sent to the APIC while | |
1174 | * in that state and it's not clear from the SDM whether it still responds | |
1175 | * to INIT/SIPI messages. Stay on the safe side and use software disable. | |
0e078e2f | 1176 | */ |
60dcaad5 | 1177 | void apic_soft_disable(void) |
0e078e2f | 1178 | { |
60dcaad5 | 1179 | u32 value; |
4a13ad0b | 1180 | |
0e078e2f TG |
1181 | clear_local_APIC(); |
1182 | ||
60dcaad5 | 1183 | /* Soft disable APIC (implies clearing of registers for 82489DX!). */ |
0e078e2f TG |
1184 | value = apic_read(APIC_SPIV); |
1185 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1186 | apic_write(APIC_SPIV, value); | |
60dcaad5 TG |
1187 | } |
1188 | ||
1189 | /** | |
1190 | * disable_local_APIC - clear and disable the local APIC | |
1191 | */ | |
1192 | void disable_local_APIC(void) | |
1193 | { | |
78c32000 | 1194 | if (!apic_accessible()) |
60dcaad5 TG |
1195 | return; |
1196 | ||
1197 | apic_soft_disable(); | |
990b183e CG |
1198 | |
1199 | #ifdef CONFIG_X86_32 | |
1200 | /* | |
1201 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
1202 | * restore the disabled state. | |
1203 | */ | |
1204 | if (enabled_via_apicbase) { | |
1205 | unsigned int l, h; | |
1206 | ||
1207 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1208 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1209 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1210 | } | |
1211 | #endif | |
0e078e2f TG |
1212 | } |
1213 | ||
fe4024dc CG |
1214 | /* |
1215 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1216 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1217 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1218 | * for the case where Linux didn't enable the LAPIC. | |
1219 | */ | |
0e078e2f TG |
1220 | void lapic_shutdown(void) |
1221 | { | |
1222 | unsigned long flags; | |
1223 | ||
93984fbd | 1224 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
0e078e2f TG |
1225 | return; |
1226 | ||
1227 | local_irq_save(flags); | |
1228 | ||
fe4024dc CG |
1229 | #ifdef CONFIG_X86_32 |
1230 | if (!enabled_via_apicbase) | |
1231 | clear_local_APIC(); | |
1232 | else | |
1233 | #endif | |
1234 | disable_local_APIC(); | |
1235 | ||
0e078e2f TG |
1236 | |
1237 | local_irq_restore(flags); | |
1238 | } | |
1239 | ||
0e078e2f TG |
1240 | /** |
1241 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1242 | */ | |
1da177e4 LT |
1243 | void __init sync_Arb_IDs(void) |
1244 | { | |
296cb951 CG |
1245 | /* |
1246 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1247 | * needed on AMD. | |
1248 | */ | |
1249 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1250 | return; |
1251 | ||
1252 | /* | |
1253 | * Wait for idle. | |
1254 | */ | |
1255 | apic_wait_icr_idle(); | |
1256 | ||
1257 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1258 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1259 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1260 | } |
1261 | ||
6444b40e | 1262 | enum apic_intr_mode_id apic_intr_mode __ro_after_init; |
0114a8e8 | 1263 | |
97992387 | 1264 | static int __init __apic_intr_mode_select(void) |
1da177e4 | 1265 | { |
0114a8e8 | 1266 | /* Check kernel option */ |
49062454 | 1267 | if (apic_is_disabled) { |
0114a8e8 DL |
1268 | pr_info("APIC disabled via kernel command line\n"); |
1269 | return APIC_PIC; | |
1270 | } | |
1da177e4 | 1271 | |
0114a8e8 DL |
1272 | /* Check BIOS */ |
1273 | #ifdef CONFIG_X86_64 | |
1274 | /* On 64-bit, the APIC must be integrated, Check local APIC only */ | |
1275 | if (!boot_cpu_has(X86_FEATURE_APIC)) { | |
49062454 | 1276 | apic_is_disabled = true; |
0114a8e8 DL |
1277 | pr_info("APIC disabled by BIOS\n"); |
1278 | return APIC_PIC; | |
1279 | } | |
1280 | #else | |
1281 | /* On 32-bit, the APIC may be integrated APIC or 82489DX */ | |
1da177e4 | 1282 | |
0114a8e8 DL |
1283 | /* Neither 82489DX nor integrated APIC ? */ |
1284 | if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { | |
49062454 | 1285 | apic_is_disabled = true; |
0114a8e8 DL |
1286 | return APIC_PIC; |
1287 | } | |
1da177e4 | 1288 | |
0114a8e8 DL |
1289 | /* If the BIOS pretends there is an integrated APIC ? */ |
1290 | if (!boot_cpu_has(X86_FEATURE_APIC) && | |
1291 | APIC_INTEGRATED(boot_cpu_apic_version)) { | |
49062454 | 1292 | apic_is_disabled = true; |
d10a9044 | 1293 | pr_err(FW_BUG "Local APIC not detected, force emulation\n"); |
0114a8e8 DL |
1294 | return APIC_PIC; |
1295 | } | |
1296 | #endif | |
638c0411 | 1297 | |
0114a8e8 DL |
1298 | /* Check MP table or ACPI MADT configuration */ |
1299 | if (!smp_found_config) { | |
1300 | disable_ioapic_support(); | |
3e730dad | 1301 | if (!acpi_lapic) { |
0114a8e8 | 1302 | pr_info("APIC: ACPI MADT or MP tables are not detected\n"); |
3e730dad DL |
1303 | return APIC_VIRTUAL_WIRE_NO_CONFIG; |
1304 | } | |
0114a8e8 DL |
1305 | return APIC_VIRTUAL_WIRE; |
1306 | } | |
1307 | ||
3e730dad DL |
1308 | #ifdef CONFIG_SMP |
1309 | /* If SMP should be disabled, then really disable it! */ | |
1310 | if (!setup_max_cpus) { | |
1311 | pr_info("APIC: SMP mode deactivated\n"); | |
1312 | return APIC_SYMMETRIC_IO_NO_ROUTING; | |
1313 | } | |
638c0411 | 1314 | #endif |
1da177e4 | 1315 | |
0114a8e8 DL |
1316 | return APIC_SYMMETRIC_IO; |
1317 | } | |
1318 | ||
97992387 TG |
1319 | /* Select the interrupt delivery mode for the BSP */ |
1320 | void __init apic_intr_mode_select(void) | |
1321 | { | |
1322 | apic_intr_mode = __apic_intr_mode_select(); | |
1323 | } | |
1324 | ||
fc90ccfd VS |
1325 | /* |
1326 | * An initial setup of the virtual wire mode. | |
1327 | */ | |
1328 | void __init init_bsp_APIC(void) | |
1329 | { | |
1330 | unsigned int value; | |
1331 | ||
1332 | /* | |
1333 | * Don't do the setup now if we have a SMP BIOS as the | |
1334 | * through-I/O-APIC virtual wire mode might be active. | |
1335 | */ | |
1336 | if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) | |
1337 | return; | |
1338 | ||
1339 | /* | |
1340 | * Do not trust the local APIC being empty at bootup. | |
1341 | */ | |
1342 | clear_local_APIC(); | |
1343 | ||
1344 | /* | |
1345 | * Enable APIC. | |
1346 | */ | |
1347 | value = apic_read(APIC_SPIV); | |
1348 | value &= ~APIC_VECTOR_MASK; | |
1349 | value |= APIC_SPIV_APIC_ENABLED; | |
1350 | ||
1351 | #ifdef CONFIG_X86_32 | |
1352 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1353 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1354 | (boot_cpu_data.x86 == 15)) | |
1355 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1356 | else | |
1357 | #endif | |
1358 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1359 | value |= SPURIOUS_APIC_VECTOR; | |
1360 | apic_write(APIC_SPIV, value); | |
1361 | ||
1362 | /* | |
1363 | * Set up the virtual wire mode. | |
1364 | */ | |
1365 | apic_write(APIC_LVT0, APIC_DM_EXTINT); | |
1366 | value = APIC_DM_NMI; | |
1367 | if (!lapic_is_integrated()) /* 82489DX */ | |
1368 | value |= APIC_LVT_LEVEL_TRIGGER; | |
1369 | if (apic_extnmi == APIC_EXTNMI_NONE) | |
1370 | value |= APIC_LVT_MASKED; | |
1371 | apic_write(APIC_LVT1, value); | |
1372 | } | |
1373 | ||
748b170c TG |
1374 | static void __init apic_bsp_setup(bool upmode); |
1375 | ||
4b1669e8 DL |
1376 | /* Init the interrupt delivery mode for the BSP */ |
1377 | void __init apic_intr_mode_init(void) | |
1378 | { | |
0c759131 | 1379 | bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); |
3e730dad | 1380 | |
4f45ed9f | 1381 | switch (apic_intr_mode) { |
4b1669e8 DL |
1382 | case APIC_PIC: |
1383 | pr_info("APIC: Keep in PIC mode(8259)\n"); | |
1384 | return; | |
1385 | case APIC_VIRTUAL_WIRE: | |
1386 | pr_info("APIC: Switch to virtual wire mode setup\n"); | |
3e730dad DL |
1387 | break; |
1388 | case APIC_VIRTUAL_WIRE_NO_CONFIG: | |
1389 | pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); | |
1390 | upmode = true; | |
3e730dad | 1391 | break; |
4b1669e8 | 1392 | case APIC_SYMMETRIC_IO: |
79761ce8 | 1393 | pr_info("APIC: Switch to symmetric I/O mode setup\n"); |
3e730dad DL |
1394 | break; |
1395 | case APIC_SYMMETRIC_IO_NO_ROUTING: | |
79761ce8 | 1396 | pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); |
3e730dad | 1397 | break; |
4b1669e8 | 1398 | } |
3e730dad | 1399 | |
9d87f5b6 TG |
1400 | x86_64_probe_apic(); |
1401 | ||
1402 | x86_32_install_bigsmp(); | |
7a116a2d | 1403 | |
bb733e43 TG |
1404 | if (x86_platform.apic_post_init) |
1405 | x86_platform.apic_post_init(); | |
1406 | ||
3e730dad | 1407 | apic_bsp_setup(upmode); |
1da177e4 LT |
1408 | } |
1409 | ||
148f9bb8 | 1410 | static void lapic_setup_esr(void) |
c43da2f5 | 1411 | { |
9df08f10 CG |
1412 | unsigned int oldvalue, value, maxlvt; |
1413 | ||
1414 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1415 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1416 | return; |
1417 | } | |
c43da2f5 | 1418 | |
08125d3e | 1419 | if (apic->disable_esr) { |
c43da2f5 | 1420 | /* |
9df08f10 CG |
1421 | * Something untraceable is creating bad interrupts on |
1422 | * secondary quads ... for the moment, just leave the | |
1423 | * ESR disabled - we can't do anything useful with the | |
1424 | * errors anyway - mbligh | |
c43da2f5 | 1425 | */ |
ba21ebb6 | 1426 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1427 | return; |
c43da2f5 | 1428 | } |
9df08f10 CG |
1429 | |
1430 | maxlvt = lapic_get_maxlvt(); | |
1431 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1432 | apic_write(APIC_ESR, 0); | |
1433 | oldvalue = apic_read(APIC_ESR); | |
1434 | ||
1435 | /* enables sending errors */ | |
1436 | value = ERROR_APIC_VECTOR; | |
1437 | apic_write(APIC_LVTERR, value); | |
1438 | ||
1439 | /* | |
1440 | * spec says clear errors after enabling vector. | |
1441 | */ | |
1442 | if (maxlvt > 3) | |
1443 | apic_write(APIC_ESR, 0); | |
1444 | value = apic_read(APIC_ESR); | |
1445 | if (value != oldvalue) | |
1446 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1447 | "vector: 0x%08x after: 0x%08x\n", | |
1448 | oldvalue, value); | |
c43da2f5 CG |
1449 | } |
1450 | ||
cc8bf191 TG |
1451 | #define APIC_IR_REGS APIC_ISR_NR |
1452 | #define APIC_IR_BITS (APIC_IR_REGS * 32) | |
1453 | #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG) | |
1454 | ||
1455 | union apic_ir { | |
1456 | unsigned long map[APIC_IR_MAPSIZE]; | |
1457 | u32 regs[APIC_IR_REGS]; | |
1458 | }; | |
1459 | ||
1460 | static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr) | |
9b217f33 | 1461 | { |
cc8bf191 TG |
1462 | int i, bit; |
1463 | ||
1464 | /* Read the IRRs */ | |
1465 | for (i = 0; i < APIC_IR_REGS; i++) | |
1466 | irr->regs[i] = apic_read(APIC_IRR + i * 0x10); | |
1467 | ||
1468 | /* Read the ISRs */ | |
1469 | for (i = 0; i < APIC_IR_REGS; i++) | |
1470 | isr->regs[i] = apic_read(APIC_ISR + i * 0x10); | |
9b217f33 | 1471 | |
9b217f33 | 1472 | /* |
cc8bf191 TG |
1473 | * If the ISR map is not empty. ACK the APIC and run another round |
1474 | * to verify whether a pending IRR has been unblocked and turned | |
1475 | * into a ISR. | |
9b217f33 | 1476 | */ |
cc8bf191 TG |
1477 | if (!bitmap_empty(isr->map, APIC_IR_BITS)) { |
1478 | /* | |
1479 | * There can be multiple ISR bits set when a high priority | |
1480 | * interrupt preempted a lower priority one. Issue an ACK | |
1481 | * per set bit. | |
1482 | */ | |
1483 | for_each_set_bit(bit, isr->map, APIC_IR_BITS) | |
670c04ad | 1484 | apic_eoi(); |
cc8bf191 TG |
1485 | return true; |
1486 | } | |
1487 | ||
1488 | return !bitmap_empty(irr->map, APIC_IR_BITS); | |
1489 | } | |
1490 | ||
1491 | /* | |
1492 | * After a crash, we no longer service the interrupts and a pending | |
1493 | * interrupt from previous kernel might still have ISR bit set. | |
1494 | * | |
1495 | * Most probably by now the CPU has serviced that pending interrupt and it | |
670c04ad | 1496 | * might not have done the apic_eoi() because it thought, interrupt |
cc8bf191 | 1497 | * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear |
d9f6e12f | 1498 | * the ISR bit and cpu thinks it has already serviced the interrupt. Hence |
cc8bf191 TG |
1499 | * a vector might get locked. It was noticed for timer irq (vector |
1500 | * 0x31). Issue an extra EOI to clear ISR. | |
1501 | * | |
1502 | * If there are pending IRR bits they turn into ISR bits after a higher | |
1503 | * priority ISR bit has been acked. | |
1504 | */ | |
1505 | static void apic_pending_intr_clear(void) | |
1506 | { | |
1507 | union apic_ir irr, isr; | |
1508 | unsigned int i; | |
1509 | ||
1510 | /* 512 loops are way oversized and give the APIC a chance to obey. */ | |
1511 | for (i = 0; i < 512; i++) { | |
1512 | if (!apic_check_and_ack(&irr, &isr)) | |
1513 | return; | |
1514 | } | |
1515 | /* Dump the IRR/ISR content if that failed */ | |
1516 | pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map); | |
9b217f33 DL |
1517 | } |
1518 | ||
0e078e2f TG |
1519 | /** |
1520 | * setup_local_APIC - setup the local APIC | |
0aa002fe | 1521 | * |
543113d2 | 1522 | * Used to setup local APIC while initializing BSP or bringing up APs. |
0aa002fe | 1523 | * Always called with preemption disabled. |
0e078e2f | 1524 | */ |
b753a2b7 | 1525 | static void setup_local_APIC(void) |
1da177e4 | 1526 | { |
0aa002fe | 1527 | int cpu = smp_processor_id(); |
9b217f33 | 1528 | unsigned int value; |
8c3ba8d0 | 1529 | |
49062454 | 1530 | if (apic_is_disabled) { |
7167d08e | 1531 | disable_ioapic_support(); |
f1182638 JB |
1532 | return; |
1533 | } | |
1534 | ||
2640da4c TG |
1535 | /* |
1536 | * If this comes from kexec/kcrash the APIC might be enabled in | |
1537 | * SPIV. Soft disable it before doing further initialization. | |
1538 | */ | |
1539 | value = apic_read(APIC_SPIV); | |
1540 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1541 | apic_write(APIC_SPIV, value); | |
1542 | ||
89c38c28 CG |
1543 | #ifdef CONFIG_X86_32 |
1544 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1545 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1546 | apic_write(APIC_ESR, 0); |
1547 | apic_write(APIC_ESR, 0); | |
1548 | apic_write(APIC_ESR, 0); | |
1549 | apic_write(APIC_ESR, 0); | |
1550 | } | |
1551 | #endif | |
5a3a46bd TG |
1552 | /* Validate that the APIC is registered if required */ |
1553 | BUG_ON(apic->apic_id_registered && !apic->apic_id_registered()); | |
1da177e4 LT |
1554 | |
1555 | /* | |
1556 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1557 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
2f6df03f TG |
1558 | * document number 292116). |
1559 | * | |
1560 | * Except for APICs which operate in physical destination mode. | |
1da177e4 | 1561 | */ |
2f6df03f TG |
1562 | if (apic->init_apic_ldr) |
1563 | apic->init_apic_ldr(); | |
1da177e4 LT |
1564 | |
1565 | /* | |
229b969b AL |
1566 | * Set Task Priority to 'accept all except vectors 0-31'. An APIC |
1567 | * vector in the 16-31 range could be delivered if TPR == 0, but we | |
1568 | * would think it's an exception and terrible things will happen. We | |
1569 | * never change this later on. | |
1da177e4 LT |
1570 | */ |
1571 | value = apic_read(APIC_TASKPRI); | |
1572 | value &= ~APIC_TPRI_MASK; | |
229b969b | 1573 | value |= 0x10; |
11a8e778 | 1574 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1575 | |
cc8bf191 | 1576 | /* Clear eventually stale ISR/IRR bits */ |
9b217f33 | 1577 | apic_pending_intr_clear(); |
da7ed9f9 | 1578 | |
1da177e4 LT |
1579 | /* |
1580 | * Now that we are all set up, enable the APIC | |
1581 | */ | |
1582 | value = apic_read(APIC_SPIV); | |
1583 | value &= ~APIC_VECTOR_MASK; | |
1584 | /* | |
1585 | * Enable APIC | |
1586 | */ | |
1587 | value |= APIC_SPIV_APIC_ENABLED; | |
1588 | ||
89c38c28 CG |
1589 | #ifdef CONFIG_X86_32 |
1590 | /* | |
1591 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1592 | * certain networking cards. If high frequency interrupts are | |
1593 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1594 | * entry is masked/unmasked at a high rate as well then sooner or | |
1595 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1596 | * from the device. If focus CPU is disabled then the hang goes | |
1597 | * away, oh well :-( | |
1598 | * | |
1599 | * [ This bug can be reproduced easily with a level-triggered | |
1600 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1601 | * BX chipset. ] | |
1602 | */ | |
1603 | /* | |
1604 | * Actually disabling the focus CPU check just makes the hang less | |
d9f6e12f | 1605 | * frequent as it makes the interrupt distribution model be more |
89c38c28 | 1606 | * like LRU than MRU (the short-term load is more even across CPUs). |
89c38c28 CG |
1607 | */ |
1608 | ||
1609 | /* | |
1610 | * - enable focus processor (bit==0) | |
1611 | * - 64bit mode always use processor focus | |
1612 | * so no need to set it | |
1613 | */ | |
1614 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1615 | #endif | |
3f14c746 | 1616 | |
1da177e4 LT |
1617 | /* |
1618 | * Set spurious IRQ vector | |
1619 | */ | |
1620 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1621 | apic_write(APIC_SPIV, value); |
1da177e4 | 1622 | |
39c89dff TG |
1623 | perf_events_lapic_init(); |
1624 | ||
1da177e4 LT |
1625 | /* |
1626 | * Set up LVT0, LVT1: | |
1627 | * | |
a1652bb8 | 1628 | * set up through-local-APIC on the boot CPU's LINT0. This is not |
1da177e4 LT |
1629 | * strictly necessary in pure symmetric-IO mode, but sometimes |
1630 | * we delegate interrupts to the 8259A. | |
1631 | */ | |
1632 | /* | |
1633 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1634 | */ | |
1635 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
ecf600f8 | 1636 | if (!cpu && (pic_mode || !value || ioapic_is_disabled)) { |
1da177e4 | 1637 | value = APIC_DM_EXTINT; |
0aa002fe | 1638 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1639 | } else { |
1640 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
0aa002fe | 1641 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1642 | } |
11a8e778 | 1643 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1644 | |
1645 | /* | |
b7c4948e HK |
1646 | * Only the BSP sees the LINT1 NMI signal by default. This can be |
1647 | * modified by apic_extnmi= boot option. | |
1da177e4 | 1648 | */ |
b7c4948e HK |
1649 | if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || |
1650 | apic_extnmi == APIC_EXTNMI_ALL) | |
1da177e4 LT |
1651 | value = APIC_DM_NMI; |
1652 | else | |
1653 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
ae41a2a4 DL |
1654 | |
1655 | /* Is 82489DX ? */ | |
1656 | if (!lapic_is_integrated()) | |
89c38c28 | 1657 | value |= APIC_LVT_LEVEL_TRIGGER; |
11a8e778 | 1658 | apic_write(APIC_LVT1, value); |
89c38c28 | 1659 | |
be71b855 AK |
1660 | #ifdef CONFIG_X86_MCE_INTEL |
1661 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1662 | if (!cpu) |
be71b855 AK |
1663 | cmci_recheck(); |
1664 | #endif | |
739f33b3 | 1665 | } |
1da177e4 | 1666 | |
05f7e46d | 1667 | static void end_local_APIC_setup(void) |
739f33b3 AK |
1668 | { |
1669 | lapic_setup_esr(); | |
fa6b95fc CG |
1670 | |
1671 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1672 | { |
1673 | unsigned int value; | |
1674 | /* Disable the local apic timer */ | |
1675 | value = apic_read(APIC_LVTT); | |
1676 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1677 | apic_write(APIC_LVTT, value); | |
1678 | } | |
fa6b95fc CG |
1679 | #endif |
1680 | ||
0e078e2f | 1681 | apic_pm_activate(); |
2fb270f3 JB |
1682 | } |
1683 | ||
05f7e46d TG |
1684 | /* |
1685 | * APIC setup function for application processors. Called from smpboot.c | |
1686 | */ | |
1687 | void apic_ap_setup(void) | |
2fb270f3 | 1688 | { |
05f7e46d | 1689 | setup_local_APIC(); |
2fb270f3 | 1690 | end_local_APIC_setup(); |
1da177e4 | 1691 | } |
1da177e4 | 1692 | |
d63107fa TG |
1693 | static __init void cpu_set_boot_apic(void); |
1694 | ||
d10a9044 TG |
1695 | static __init void apic_read_boot_cpu_id(bool x2apic) |
1696 | { | |
1697 | /* | |
1698 | * This can be invoked from check_x2apic() before the APIC has been | |
1699 | * selected. But that code knows for sure that the BIOS enabled | |
1700 | * X2APIC. | |
1701 | */ | |
1702 | if (x2apic) { | |
1703 | boot_cpu_physical_apicid = native_apic_msr_read(APIC_ID); | |
1704 | boot_cpu_apic_version = GET_APIC_VERSION(native_apic_msr_read(APIC_LVR)); | |
1705 | } else { | |
1706 | boot_cpu_physical_apicid = read_apic_id(); | |
1707 | boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
1708 | } | |
d63107fa | 1709 | cpu_set_boot_apic(); |
d10a9044 TG |
1710 | } |
1711 | ||
06cd9a7d | 1712 | #ifdef CONFIG_X86_X2APIC |
bfb05070 | 1713 | int x2apic_mode; |
db7d8e47 | 1714 | EXPORT_SYMBOL_GPL(x2apic_mode); |
12e189d3 TG |
1715 | |
1716 | enum { | |
1717 | X2APIC_OFF, | |
12e189d3 | 1718 | X2APIC_DISABLED, |
b8d1d163 DS |
1719 | /* All states below here have X2APIC enabled */ |
1720 | X2APIC_ON, | |
1721 | X2APIC_ON_LOCKED | |
12e189d3 TG |
1722 | }; |
1723 | static int x2apic_state; | |
1724 | ||
b8d1d163 DS |
1725 | static bool x2apic_hw_locked(void) |
1726 | { | |
1727 | u64 ia32_cap; | |
1728 | u64 msr; | |
1729 | ||
1730 | ia32_cap = x86_read_arch_cap_msr(); | |
1731 | if (ia32_cap & ARCH_CAP_XAPIC_DISABLE) { | |
1732 | rdmsrl(MSR_IA32_XAPIC_DISABLE_STATUS, msr); | |
1733 | return (msr & LEGACY_XAPIC_DISABLED); | |
1734 | } | |
1735 | return false; | |
1736 | } | |
1737 | ||
d786ad32 | 1738 | static void __x2apic_disable(void) |
44e25ff9 TG |
1739 | { |
1740 | u64 msr; | |
1741 | ||
93984fbd | 1742 | if (!boot_cpu_has(X86_FEATURE_APIC)) |
659006bf TG |
1743 | return; |
1744 | ||
44e25ff9 TG |
1745 | rdmsrl(MSR_IA32_APICBASE, msr); |
1746 | if (!(msr & X2APIC_ENABLE)) | |
1747 | return; | |
1748 | /* Disable xapic and x2apic first and then reenable xapic mode */ | |
1749 | wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1750 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1751 | printk_once(KERN_INFO "x2apic disabled\n"); | |
1752 | } | |
1753 | ||
d786ad32 | 1754 | static void __x2apic_enable(void) |
659006bf TG |
1755 | { |
1756 | u64 msr; | |
1757 | ||
1758 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1759 | if (msr & X2APIC_ENABLE) | |
1760 | return; | |
1761 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); | |
1762 | printk_once(KERN_INFO "x2apic enabled\n"); | |
1763 | } | |
1764 | ||
bfb05070 TG |
1765 | static int __init setup_nox2apic(char *str) |
1766 | { | |
1767 | if (x2apic_enabled()) { | |
4705243d | 1768 | u32 apicid = native_apic_msr_read(APIC_ID); |
bfb05070 TG |
1769 | |
1770 | if (apicid >= 255) { | |
8d3bcc44 KW |
1771 | pr_warn("Apicid: %08x, cannot enforce nox2apic\n", |
1772 | apicid); | |
bfb05070 TG |
1773 | return 0; |
1774 | } | |
b8d1d163 DS |
1775 | if (x2apic_hw_locked()) { |
1776 | pr_warn("APIC locked in x2apic mode, can't disable\n"); | |
1777 | return 0; | |
1778 | } | |
8d3bcc44 | 1779 | pr_warn("x2apic already enabled.\n"); |
44e25ff9 TG |
1780 | __x2apic_disable(); |
1781 | } | |
1782 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
12e189d3 | 1783 | x2apic_state = X2APIC_DISABLED; |
44e25ff9 | 1784 | x2apic_mode = 0; |
bfb05070 TG |
1785 | return 0; |
1786 | } | |
1787 | early_param("nox2apic", setup_nox2apic); | |
1788 | ||
659006bf TG |
1789 | /* Called from cpu_init() to enable x2apic on (secondary) cpus */ |
1790 | void x2apic_setup(void) | |
1791 | { | |
1792 | /* | |
b8d1d163 DS |
1793 | * Try to make the AP's APIC state match that of the BSP, but if the |
1794 | * BSP is unlocked and the AP is locked then there is a state mismatch. | |
1795 | * Warn about the mismatch in case a GP fault occurs due to a locked AP | |
1796 | * trying to be turned off. | |
1797 | */ | |
1798 | if (x2apic_state != X2APIC_ON_LOCKED && x2apic_hw_locked()) | |
1799 | pr_warn("x2apic lock mismatch between BSP and AP.\n"); | |
1800 | /* | |
1801 | * If x2apic is not in ON or LOCKED state, disable it if already enabled | |
659006bf TG |
1802 | * from BIOS. |
1803 | */ | |
b8d1d163 | 1804 | if (x2apic_state < X2APIC_ON) { |
659006bf TG |
1805 | __x2apic_disable(); |
1806 | return; | |
1807 | } | |
1808 | __x2apic_enable(); | |
1809 | } | |
1810 | ||
5a88f354 TG |
1811 | static __init void apic_set_fixmap(void); |
1812 | ||
44e25ff9 | 1813 | static __init void x2apic_disable(void) |
fb209bd8 | 1814 | { |
a57e456a | 1815 | u32 x2apic_id, state = x2apic_state; |
fb209bd8 | 1816 | |
a57e456a TG |
1817 | x2apic_mode = 0; |
1818 | x2apic_state = X2APIC_DISABLED; | |
1819 | ||
1820 | if (state != X2APIC_ON) | |
1821 | return; | |
fb209bd8 | 1822 | |
6d2d49d2 TG |
1823 | x2apic_id = read_apic_id(); |
1824 | if (x2apic_id >= 255) | |
1825 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
9aa16365 | 1826 | |
b8d1d163 DS |
1827 | if (x2apic_hw_locked()) { |
1828 | pr_warn("Cannot disable locked x2apic, id: %08x\n", x2apic_id); | |
1829 | return; | |
1830 | } | |
1831 | ||
6d2d49d2 | 1832 | __x2apic_disable(); |
5a88f354 | 1833 | apic_set_fixmap(); |
fb209bd8 YL |
1834 | } |
1835 | ||
659006bf | 1836 | static __init void x2apic_enable(void) |
6e1cb38a | 1837 | { |
659006bf | 1838 | if (x2apic_state != X2APIC_OFF) |
06cd9a7d YL |
1839 | return; |
1840 | ||
659006bf | 1841 | x2apic_mode = 1; |
12e189d3 | 1842 | x2apic_state = X2APIC_ON; |
659006bf | 1843 | __x2apic_enable(); |
6e1cb38a | 1844 | } |
d524165c | 1845 | |
62e61633 | 1846 | static __init void try_to_enable_x2apic(int remap_mode) |
07806c50 | 1847 | { |
659006bf | 1848 | if (x2apic_state == X2APIC_DISABLED) |
07806c50 JL |
1849 | return; |
1850 | ||
62e61633 | 1851 | if (remap_mode != IRQ_REMAP_X2APIC_MODE) { |
ab0f59c6 DW |
1852 | u32 apic_limit = 255; |
1853 | ||
26573a97 DW |
1854 | /* |
1855 | * Using X2APIC without IR is not architecturally supported | |
1856 | * on bare metal but may be supported in guests. | |
07806c50 | 1857 | */ |
26573a97 | 1858 | if (!x86_init.hyper.x2apic_available()) { |
62e61633 | 1859 | pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); |
44e25ff9 | 1860 | x2apic_disable(); |
07806c50 JL |
1861 | return; |
1862 | } | |
1863 | ||
ab0f59c6 DW |
1864 | /* |
1865 | * If the hypervisor supports extended destination ID in | |
1866 | * MSI, that increases the maximum APIC ID that can be | |
1867 | * used for non-remapped IRQ domains. | |
1868 | */ | |
1869 | if (x86_init.hyper.msi_ext_dest_id()) { | |
1870 | virt_ext_dest_id = 1; | |
1871 | apic_limit = 32767; | |
1872 | } | |
1873 | ||
07806c50 | 1874 | /* |
26573a97 | 1875 | * Without IR, all CPUs can be addressed by IOAPIC/MSI only |
d9f6e12f | 1876 | * in physical mode, and CPUs with an APIC ID that cannot |
26573a97 | 1877 | * be addressed must not be brought online. |
07806c50 | 1878 | */ |
ab0f59c6 | 1879 | x2apic_set_max_apicid(apic_limit); |
55eae7de | 1880 | x2apic_phys = 1; |
07806c50 | 1881 | } |
659006bf | 1882 | x2apic_enable(); |
55eae7de TG |
1883 | } |
1884 | ||
1885 | void __init check_x2apic(void) | |
1886 | { | |
1887 | if (x2apic_enabled()) { | |
1888 | pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); | |
1889 | x2apic_mode = 1; | |
b8d1d163 DS |
1890 | if (x2apic_hw_locked()) |
1891 | x2apic_state = X2APIC_ON_LOCKED; | |
1892 | else | |
1893 | x2apic_state = X2APIC_ON; | |
d10a9044 | 1894 | apic_read_boot_cpu_id(true); |
62436a4d | 1895 | } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { |
12e189d3 | 1896 | x2apic_state = X2APIC_DISABLED; |
55eae7de TG |
1897 | } |
1898 | } | |
1899 | #else /* CONFIG_X86_X2APIC */ | |
e3998434 | 1900 | void __init check_x2apic(void) |
55eae7de TG |
1901 | { |
1902 | if (!apic_is_x2apic_enabled()) | |
e3998434 | 1903 | return; |
55eae7de | 1904 | /* |
e3998434 | 1905 | * Checkme: Can we simply turn off x2APIC here instead of disabling the APIC? |
55eae7de | 1906 | */ |
e3998434 MJ |
1907 | pr_err("Kernel does not support x2APIC, please recompile with CONFIG_X86_X2APIC.\n"); |
1908 | pr_err("Disabling APIC, expect reduced performance and functionality.\n"); | |
1909 | ||
49062454 | 1910 | apic_is_disabled = true; |
e3998434 | 1911 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
55eae7de | 1912 | } |
55eae7de | 1913 | |
62e61633 | 1914 | static inline void try_to_enable_x2apic(int remap_mode) { } |
659006bf | 1915 | static inline void __x2apic_enable(void) { } |
55eae7de TG |
1916 | #endif /* !CONFIG_X86_X2APIC */ |
1917 | ||
ce69a784 GN |
1918 | void __init enable_IR_x2apic(void) |
1919 | { | |
1920 | unsigned long flags; | |
07806c50 | 1921 | int ret, ir_stat; |
b7f42ab2 | 1922 | |
ecf600f8 | 1923 | if (ioapic_is_disabled) { |
11277aab | 1924 | pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); |
2e63ad4b | 1925 | return; |
11277aab | 1926 | } |
2e63ad4b | 1927 | |
07806c50 JL |
1928 | ir_stat = irq_remapping_prepare(); |
1929 | if (ir_stat < 0 && !x2apic_supported()) | |
e670761f | 1930 | return; |
ce69a784 | 1931 | |
31dce14a | 1932 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1933 | if (ret) { |
ba21ebb6 | 1934 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1935 | return; |
5ffa4eb2 | 1936 | } |
6e1cb38a | 1937 | |
05c3dc2c | 1938 | local_irq_save(flags); |
b81bb373 | 1939 | legacy_pic->mask_all(); |
31dce14a | 1940 | mask_ioapic_entries(); |
05c3dc2c | 1941 | |
6a6256f9 | 1942 | /* If irq_remapping_prepare() succeeded, try to enable it */ |
07806c50 | 1943 | if (ir_stat >= 0) |
11277aab | 1944 | ir_stat = irq_remapping_enable(); |
07806c50 JL |
1945 | /* ir_stat contains the remap mode or an error code */ |
1946 | try_to_enable_x2apic(ir_stat); | |
a31bc327 | 1947 | |
07806c50 | 1948 | if (ir_stat < 0) |
31dce14a | 1949 | restore_ioapic_entries(); |
b81bb373 | 1950 | legacy_pic->restore_mask(); |
6e1cb38a | 1951 | local_irq_restore(flags); |
6e1cb38a | 1952 | } |
93758238 | 1953 | |
be7a656f | 1954 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1955 | /* |
1956 | * Detect and enable local APICs on non-SMP boards. | |
1957 | * Original code written by Keir Fraser. | |
1958 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1959 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1960 | */ |
1751aded | 1961 | static bool __init detect_init_APIC(void) |
1da177e4 | 1962 | { |
93984fbd | 1963 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
ba21ebb6 | 1964 | pr_info("No local APIC present\n"); |
1751aded | 1965 | return false; |
1da177e4 LT |
1966 | } |
1967 | ||
81287ad6 | 1968 | register_lapic_address(APIC_DEFAULT_PHYS_BASE); |
1751aded | 1969 | return true; |
1da177e4 | 1970 | } |
be7a656f | 1971 | #else |
5a7ae78f | 1972 | |
81287ad6 | 1973 | static bool __init apic_verify(unsigned long addr) |
5a7ae78f TG |
1974 | { |
1975 | u32 features, h, l; | |
1976 | ||
1977 | /* | |
1978 | * The APIC feature bit should now be enabled | |
1979 | * in `cpuid' | |
1980 | */ | |
1981 | features = cpuid_edx(1); | |
1982 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
8d3bcc44 | 1983 | pr_warn("Could not enable APIC!\n"); |
1751aded | 1984 | return false; |
5a7ae78f TG |
1985 | } |
1986 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
5a7ae78f TG |
1987 | |
1988 | /* The BIOS may have set up the APIC at some other address */ | |
cbf2829b BD |
1989 | if (boot_cpu_data.x86 >= 6) { |
1990 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1991 | if (l & MSR_IA32_APICBASE_ENABLE) | |
81287ad6 | 1992 | addr = l & MSR_IA32_APICBASE_BASE; |
cbf2829b | 1993 | } |
5a7ae78f | 1994 | |
81287ad6 | 1995 | register_lapic_address(addr); |
5a7ae78f | 1996 | pr_info("Found and enabled local APIC!\n"); |
1751aded | 1997 | return true; |
5a7ae78f TG |
1998 | } |
1999 | ||
1751aded | 2000 | bool __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
2001 | { |
2002 | u32 h, l; | |
2003 | ||
49062454 | 2004 | if (apic_is_disabled) |
1751aded | 2005 | return false; |
5a7ae78f TG |
2006 | |
2007 | /* | |
2008 | * Some BIOSes disable the local APIC in the APIC_BASE | |
2009 | * MSR. This can only be done in software for Intel P6 or later | |
2010 | * and AMD K7 (Model > 1) or later. | |
2011 | */ | |
cbf2829b BD |
2012 | if (boot_cpu_data.x86 >= 6) { |
2013 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2014 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
2015 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
2016 | l &= ~MSR_IA32_APICBASE_BASE; | |
2017 | l |= MSR_IA32_APICBASE_ENABLE | addr; | |
2018 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2019 | enabled_via_apicbase = 1; | |
2020 | } | |
5a7ae78f | 2021 | } |
81287ad6 | 2022 | return apic_verify(addr); |
5a7ae78f TG |
2023 | } |
2024 | ||
be7a656f YL |
2025 | /* |
2026 | * Detect and initialize APIC | |
2027 | */ | |
1751aded | 2028 | static bool __init detect_init_APIC(void) |
be7a656f | 2029 | { |
be7a656f | 2030 | /* Disabled by kernel option? */ |
49062454 | 2031 | if (apic_is_disabled) |
1751aded | 2032 | return false; |
be7a656f YL |
2033 | |
2034 | switch (boot_cpu_data.x86_vendor) { | |
2035 | case X86_VENDOR_AMD: | |
2036 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 2037 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
2038 | break; |
2039 | goto no_apic; | |
da33dfef PW |
2040 | case X86_VENDOR_HYGON: |
2041 | break; | |
be7a656f YL |
2042 | case X86_VENDOR_INTEL: |
2043 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
93984fbd | 2044 | (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) |
be7a656f YL |
2045 | break; |
2046 | goto no_apic; | |
2047 | default: | |
2048 | goto no_apic; | |
2049 | } | |
2050 | ||
93984fbd | 2051 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
be7a656f YL |
2052 | /* |
2053 | * Over-ride BIOS and try to enable the local APIC only if | |
2054 | * "lapic" specified. | |
2055 | */ | |
2056 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
2057 | pr_info("Local APIC disabled by BIOS -- " |
2058 | "you can enable it with \"lapic\"\n"); | |
1751aded | 2059 | return false; |
be7a656f | 2060 | } |
1751aded TG |
2061 | if (!apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
2062 | return false; | |
5a7ae78f | 2063 | } else { |
81287ad6 | 2064 | if (!apic_verify(APIC_DEFAULT_PHYS_BASE)) |
1751aded | 2065 | return false; |
be7a656f | 2066 | } |
be7a656f YL |
2067 | |
2068 | apic_pm_activate(); | |
2069 | ||
1751aded | 2070 | return true; |
be7a656f YL |
2071 | |
2072 | no_apic: | |
ba21ebb6 | 2073 | pr_info("No local APIC present or hardware disabled\n"); |
1751aded | 2074 | return false; |
be7a656f YL |
2075 | } |
2076 | #endif | |
1da177e4 | 2077 | |
0e078e2f TG |
2078 | /** |
2079 | * init_apic_mappings - initialize APIC mappings | |
2080 | */ | |
1da177e4 LT |
2081 | void __init init_apic_mappings(void) |
2082 | { | |
c84cb373 | 2083 | if (apic_validate_deadline_timer()) |
de308d18 | 2084 | pr_info("TSC deadline timer available\n"); |
bd9240a1 | 2085 | |
d10a9044 | 2086 | if (x2apic_mode) |
6e1cb38a | 2087 | return; |
6e1cb38a | 2088 | |
e8122513 TG |
2089 | if (!smp_found_config) { |
2090 | if (!detect_init_APIC()) { | |
2091 | pr_info("APIC: disable apic facility\n"); | |
2092 | apic_disable(); | |
2093 | } | |
2094 | num_processors = 1; | |
cec6be6d | 2095 | } |
1da177e4 LT |
2096 | } |
2097 | ||
5a88f354 TG |
2098 | static __init void apic_set_fixmap(void) |
2099 | { | |
2100 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); | |
78c32000 | 2101 | apic_mmio_base = APIC_BASE; |
5a88f354 TG |
2102 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
2103 | apic_mmio_base, mp_lapic_addr); | |
2104 | apic_read_boot_cpu_id(false); | |
2105 | } | |
2106 | ||
c0104d38 YL |
2107 | void __init register_lapic_address(unsigned long address) |
2108 | { | |
81287ad6 TG |
2109 | /* This should only happen once */ |
2110 | WARN_ON_ONCE(mp_lapic_addr); | |
c0104d38 YL |
2111 | mp_lapic_addr = address; |
2112 | ||
5a88f354 TG |
2113 | if (!x2apic_mode) |
2114 | apic_set_fixmap(); | |
c0104d38 YL |
2115 | } |
2116 | ||
1da177e4 | 2117 | /* |
0e078e2f | 2118 | * Local APIC interrupts |
1da177e4 LT |
2119 | */ |
2120 | ||
3c5e0267 TG |
2121 | /* |
2122 | * Common handling code for spurious_interrupt and spurious_vector entry | |
2123 | * points below. No point in allowing the compiler to inline it twice. | |
0e078e2f | 2124 | */ |
3c5e0267 | 2125 | static noinline void handle_spurious_interrupt(u8 vector) |
1da177e4 | 2126 | { |
dc1528dd YL |
2127 | u32 v; |
2128 | ||
61069de7 TG |
2129 | trace_spurious_apic_entry(vector); |
2130 | ||
f8a8fe61 TG |
2131 | inc_irq_stat(irq_spurious_count); |
2132 | ||
2133 | /* | |
2134 | * If this is a spurious interrupt then do not acknowledge | |
2135 | */ | |
2136 | if (vector == SPURIOUS_APIC_VECTOR) { | |
2137 | /* See SDM vol 3 */ | |
2138 | pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", | |
2139 | smp_processor_id()); | |
2140 | goto out; | |
2141 | } | |
2142 | ||
1da177e4 | 2143 | /* |
f8a8fe61 TG |
2144 | * If it is a vectored one, verify it's set in the ISR. If set, |
2145 | * acknowledge it. | |
1da177e4 | 2146 | */ |
2414e021 | 2147 | v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); |
f8a8fe61 TG |
2148 | if (v & (1 << (vector & 0x1f))) { |
2149 | pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", | |
2150 | vector, smp_processor_id()); | |
670c04ad | 2151 | apic_eoi(); |
f8a8fe61 TG |
2152 | } else { |
2153 | pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", | |
2154 | vector, smp_processor_id()); | |
2155 | } | |
2156 | out: | |
2414e021 | 2157 | trace_spurious_apic_exit(vector); |
0e078e2f | 2158 | } |
1da177e4 | 2159 | |
3c5e0267 TG |
2160 | /** |
2161 | * spurious_interrupt - Catch all for interrupts raised on unused vectors | |
2162 | * @regs: Pointer to pt_regs on stack | |
2163 | * @vector: The vector number | |
2164 | * | |
2165 | * This is invoked from ASM entry code to catch all interrupts which | |
2166 | * trigger on an entry which is routed to the common_spurious idtentry | |
2167 | * point. | |
2168 | */ | |
2169 | DEFINE_IDTENTRY_IRQ(spurious_interrupt) | |
2170 | { | |
2171 | handle_spurious_interrupt(vector); | |
2172 | } | |
2173 | ||
db0338ee | 2174 | DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt) |
633260fa | 2175 | { |
3c5e0267 | 2176 | handle_spurious_interrupt(SPURIOUS_APIC_VECTOR); |
0e078e2f | 2177 | } |
1da177e4 | 2178 | |
0e078e2f TG |
2179 | /* |
2180 | * This interrupt should never happen with our APIC/SMP architecture | |
2181 | */ | |
db0338ee | 2182 | DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt) |
0e078e2f | 2183 | { |
2b398bd9 YS |
2184 | static const char * const error_interrupt_reason[] = { |
2185 | "Send CS error", /* APIC Error Bit 0 */ | |
2186 | "Receive CS error", /* APIC Error Bit 1 */ | |
2187 | "Send accept error", /* APIC Error Bit 2 */ | |
2188 | "Receive accept error", /* APIC Error Bit 3 */ | |
2189 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
2190 | "Send illegal vector", /* APIC Error Bit 5 */ | |
2191 | "Received illegal vector", /* APIC Error Bit 6 */ | |
2192 | "Illegal register address", /* APIC Error Bit 7 */ | |
2193 | }; | |
61069de7 TG |
2194 | u32 v, i = 0; |
2195 | ||
61069de7 | 2196 | trace_error_apic_entry(ERROR_APIC_VECTOR); |
1da177e4 | 2197 | |
0e078e2f | 2198 | /* First tickle the hardware, only then report what went on. -- REW */ |
023de4a0 MR |
2199 | if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ |
2200 | apic_write(APIC_ESR, 0); | |
60283df7 | 2201 | v = apic_read(APIC_ESR); |
670c04ad | 2202 | apic_eoi(); |
0e078e2f | 2203 | atomic_inc(&irq_err_count); |
ba7eda4c | 2204 | |
60283df7 RW |
2205 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", |
2206 | smp_processor_id(), v); | |
2b398bd9 | 2207 | |
60283df7 RW |
2208 | v &= 0xff; |
2209 | while (v) { | |
2210 | if (v & 0x1) | |
2b398bd9 YS |
2211 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); |
2212 | i++; | |
60283df7 | 2213 | v >>= 1; |
4b8073e4 | 2214 | } |
2b398bd9 YS |
2215 | |
2216 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); | |
2217 | ||
cf910e83 | 2218 | trace_error_apic_exit(ERROR_APIC_VECTOR); |
1da177e4 LT |
2219 | } |
2220 | ||
b5841765 | 2221 | /** |
36c9d674 CG |
2222 | * connect_bsp_APIC - attach the APIC to the interrupt system |
2223 | */ | |
05f7e46d | 2224 | static void __init connect_bsp_APIC(void) |
b5841765 | 2225 | { |
36c9d674 CG |
2226 | #ifdef CONFIG_X86_32 |
2227 | if (pic_mode) { | |
2228 | /* | |
2229 | * Do not trust the local APIC being empty at bootup. | |
2230 | */ | |
2231 | clear_local_APIC(); | |
2232 | /* | |
2233 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
2234 | * local APIC to INT and NMI lines. | |
2235 | */ | |
2236 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
2237 | "enabling APIC mode.\n"); | |
c0eaa453 | 2238 | imcr_pic_to_apic(); |
36c9d674 CG |
2239 | } |
2240 | #endif | |
b5841765 GC |
2241 | } |
2242 | ||
274cfe59 CG |
2243 | /** |
2244 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
2245 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
2246 | * | |
2247 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
2248 | * APIC is disabled. | |
2249 | */ | |
0e078e2f | 2250 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 2251 | { |
1b4ee4e4 CG |
2252 | unsigned int value; |
2253 | ||
c177b0bc CG |
2254 | #ifdef CONFIG_X86_32 |
2255 | if (pic_mode) { | |
2256 | /* | |
2257 | * Put the board back into PIC mode (has an effect only on | |
2258 | * certain older boards). Note that APIC interrupts, including | |
2259 | * IPIs, won't work beyond this point! The only exception are | |
2260 | * INIT IPIs. | |
2261 | */ | |
2262 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
2263 | "entering PIC mode.\n"); | |
c0eaa453 | 2264 | imcr_apic_to_pic(); |
c177b0bc CG |
2265 | return; |
2266 | } | |
2267 | #endif | |
2268 | ||
0e078e2f | 2269 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 2270 | |
0e078e2f TG |
2271 | /* For the spurious interrupt use vector F, and enable it */ |
2272 | value = apic_read(APIC_SPIV); | |
2273 | value &= ~APIC_VECTOR_MASK; | |
2274 | value |= APIC_SPIV_APIC_ENABLED; | |
2275 | value |= 0xf; | |
2276 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 2277 | |
0e078e2f TG |
2278 | if (!virt_wire_setup) { |
2279 | /* | |
2280 | * For LVT0 make it edge triggered, active high, | |
2281 | * external and enabled | |
2282 | */ | |
2283 | value = apic_read(APIC_LVT0); | |
2284 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2285 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2286 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2287 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2288 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
2289 | apic_write(APIC_LVT0, value); | |
2290 | } else { | |
2291 | /* Disable LVT0 */ | |
2292 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
2293 | } | |
b8ce3359 | 2294 | |
c177b0bc CG |
2295 | /* |
2296 | * For LVT1 make it edge triggered, active high, | |
2297 | * nmi and enabled | |
2298 | */ | |
0e078e2f TG |
2299 | value = apic_read(APIC_LVT1); |
2300 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2301 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2302 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2303 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2304 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
2305 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
2306 | } |
2307 | ||
8f54969d GZ |
2308 | /* |
2309 | * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated | |
2310 | * contiguously, it equals to current allocated max logical CPU ID plus 1. | |
12bf98b9 DL |
2311 | * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, |
2312 | * so the maximum of nr_logical_cpuids is nr_cpu_ids. | |
8f54969d GZ |
2313 | * |
2314 | * NOTE: Reserve 0 for BSP. | |
2315 | */ | |
2316 | static int nr_logical_cpuids = 1; | |
2317 | ||
2318 | /* | |
2319 | * Used to store mapping between logical CPU IDs and APIC IDs. | |
2320 | */ | |
4705243d | 2321 | u32 cpuid_to_apicid[] = { [0 ... NR_CPUS - 1] = BAD_APICID, }; |
8f54969d | 2322 | |
dd926880 JH |
2323 | bool arch_match_cpu_phys_id(int cpu, u64 phys_id) |
2324 | { | |
4705243d | 2325 | return phys_id == (u64)cpuid_to_apicid[cpu]; |
dd926880 JH |
2326 | } |
2327 | ||
d0055f35 | 2328 | #ifdef CONFIG_SMP |
f54d4434 | 2329 | static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) |
6a4d2657 | 2330 | { |
6a4d2657 | 2331 | /* Isolate the SMT bit(s) in the APICID and check for 0 */ |
f54d4434 TG |
2332 | u32 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; |
2333 | ||
2334 | if (smp_num_siblings == 1 || !(apicid & mask)) | |
2335 | cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); | |
6a4d2657 | 2336 | } |
5da80b28 TG |
2337 | |
2338 | /* | |
2339 | * Due to the utter mess of CPUID evaluation smp_num_siblings is not valid | |
2340 | * during early boot. Initialize the primary thread mask before SMP | |
2341 | * bringup. | |
2342 | */ | |
2343 | static int __init smp_init_primary_thread_mask(void) | |
2344 | { | |
2345 | unsigned int cpu; | |
2346 | ||
965e05ff TG |
2347 | /* |
2348 | * XEN/PV provides either none or useless topology information. | |
2349 | * Pretend that all vCPUs are primary threads. | |
2350 | */ | |
2351 | if (xen_pv_domain()) { | |
2352 | cpumask_copy(&__cpu_primary_thread_mask, cpu_possible_mask); | |
2353 | return 0; | |
2354 | } | |
2355 | ||
5da80b28 TG |
2356 | for (cpu = 0; cpu < nr_logical_cpuids; cpu++) |
2357 | cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); | |
2358 | return 0; | |
2359 | } | |
2360 | early_initcall(smp_init_primary_thread_mask); | |
f54d4434 TG |
2361 | #else |
2362 | static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) { } | |
d0055f35 | 2363 | #endif |
6a4d2657 | 2364 | |
8f54969d GZ |
2365 | /* |
2366 | * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids | |
2367 | * and cpuid_to_apicid[] synchronized. | |
2368 | */ | |
2369 | static int allocate_logical_cpuid(int apicid) | |
2370 | { | |
2371 | int i; | |
2372 | ||
2373 | /* | |
2374 | * cpuid <-> apicid mapping is persistent, so when a cpu is up, | |
2375 | * check if the kernel has allocated a cpuid for it. | |
2376 | */ | |
2377 | for (i = 0; i < nr_logical_cpuids; i++) { | |
2378 | if (cpuid_to_apicid[i] == apicid) | |
2379 | return i; | |
2380 | } | |
2381 | ||
2382 | /* Allocate a new cpuid. */ | |
2383 | if (nr_logical_cpuids >= nr_cpu_ids) { | |
9b130ad5 | 2384 | WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " |
8f54969d | 2385 | "Processor %d/0x%x and the rest are ignored.\n", |
bb3f0a52 DL |
2386 | nr_cpu_ids, nr_logical_cpuids, apicid); |
2387 | return -EINVAL; | |
8f54969d GZ |
2388 | } |
2389 | ||
2390 | cpuid_to_apicid[nr_logical_cpuids] = apicid; | |
2391 | return nr_logical_cpuids++; | |
2392 | } | |
2393 | ||
4705243d | 2394 | static void cpu_update_apic(int cpu, u32 apicid) |
be8a5685 | 2395 | { |
3e5095d1 | 2396 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 | 2397 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
acb8bc09 | 2398 | #endif |
1de88cd4 | 2399 | set_cpu_possible(cpu, true); |
2b85b3d2 DL |
2400 | physid_set(apicid, phys_cpu_present_map); |
2401 | set_cpu_present(cpu, true); | |
2402 | num_processors++; | |
7e1f85f9 | 2403 | |
5da80b28 TG |
2404 | if (system_state != SYSTEM_BOOTING) |
2405 | cpu_mark_primary_thread(cpu, apicid); | |
d63107fa TG |
2406 | } |
2407 | ||
2408 | static __init void cpu_set_boot_apic(void) | |
2409 | { | |
2410 | cpuid_to_apicid[0] = boot_cpu_physical_apicid; | |
249ada2c | 2411 | cpu_update_apic(0, boot_cpu_physical_apicid); |
79c9a17c | 2412 | x86_32_probe_bigsmp_early(); |
d63107fa TG |
2413 | } |
2414 | ||
249ada2c | 2415 | int generic_processor_info(int apicid) |
d63107fa TG |
2416 | { |
2417 | int cpu, max = nr_cpu_ids; | |
2418 | ||
2419 | /* The boot CPU must be set before MADT/MPTABLE parsing happens */ | |
2420 | if (cpuid_to_apicid[0] == BAD_APICID) | |
2421 | panic("Boot CPU APIC not registered yet\n"); | |
2422 | ||
2423 | if (apicid == boot_cpu_physical_apicid) | |
2424 | return 0; | |
2425 | ||
2426 | if (disabled_cpu_apicid == apicid) { | |
2427 | int thiscpu = num_processors + disabled_cpus; | |
2428 | ||
2429 | pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", | |
2430 | thiscpu, apicid); | |
f54d4434 | 2431 | |
d63107fa TG |
2432 | disabled_cpus++; |
2433 | return -ENODEV; | |
2434 | } | |
2435 | ||
2436 | if (num_processors >= nr_cpu_ids) { | |
2437 | int thiscpu = max + disabled_cpus; | |
2438 | ||
2439 | pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " | |
2440 | "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2441 | ||
2442 | disabled_cpus++; | |
2443 | return -EINVAL; | |
2444 | } | |
2445 | ||
2446 | cpu = allocate_logical_cpuid(apicid); | |
2447 | if (cpu < 0) { | |
2448 | disabled_cpus++; | |
2449 | return -EINVAL; | |
2450 | } | |
2451 | ||
249ada2c | 2452 | cpu_update_apic(cpu, apicid); |
7e1f85f9 | 2453 | return cpu; |
be8a5685 AS |
2454 | } |
2455 | ||
d63107fa | 2456 | |
f598181a DW |
2457 | void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, |
2458 | bool dmar) | |
2459 | { | |
6285aa50 | 2460 | memset(msg, 0, sizeof(*msg)); |
f598181a | 2461 | |
6285aa50 TG |
2462 | msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; |
2463 | msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical; | |
2464 | msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF; | |
f598181a | 2465 | |
6285aa50 TG |
2466 | msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED; |
2467 | msg->arch_data.vector = cfg->vector; | |
f598181a | 2468 | |
6285aa50 | 2469 | msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; |
f598181a DW |
2470 | /* |
2471 | * Only the IOMMU itself can use the trick of putting destination | |
2472 | * APIC ID into the high bits of the address. Anything else would | |
2473 | * just be writing to memory if it tried that, and needs IR to | |
ab0f59c6 DW |
2474 | * address APICs which can't be addressed in the normal 32-bit |
2475 | * address range at 0xFFExxxxx. That is typically just 8 bits, but | |
2476 | * some hypervisors allow the extended destination ID field in bits | |
2477 | * 5-11 to be used, giving support for 15 bits of APIC IDs in total. | |
f598181a DW |
2478 | */ |
2479 | if (dmar) | |
6285aa50 | 2480 | msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8; |
ab0f59c6 DW |
2481 | else if (virt_ext_dest_id && cfg->dest_apicid < 0x8000) |
2482 | msg->arch_addr_lo.virt_destid_8_14 = cfg->dest_apicid >> 8; | |
f598181a | 2483 | else |
6285aa50 | 2484 | WARN_ON_ONCE(cfg->dest_apicid > 0xFF); |
f598181a DW |
2485 | } |
2486 | ||
6285aa50 TG |
2487 | u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid) |
2488 | { | |
2489 | u32 dest = msg->arch_addr_lo.destid_0_7; | |
2490 | ||
2491 | if (extid) | |
2492 | dest |= msg->arch_addr_hi.destid_8_31 << 8; | |
2493 | return dest; | |
2494 | } | |
2495 | EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid); | |
2496 | ||
374aab33 | 2497 | static void __init apic_bsp_up_setup(void) |
05f7e46d | 2498 | { |
374aab33 | 2499 | #ifdef CONFIG_X86_64 |
5d64d209 | 2500 | apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); |
374aab33 TG |
2501 | #endif |
2502 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
05f7e46d TG |
2503 | } |
2504 | ||
2505 | /** | |
2506 | * apic_bsp_setup - Setup function for local apic and io-apic | |
374aab33 | 2507 | * @upmode: Force UP mode (for APIC_init_uniprocessor) |
05f7e46d | 2508 | */ |
748b170c | 2509 | static void __init apic_bsp_setup(bool upmode) |
05f7e46d | 2510 | { |
05f7e46d | 2511 | connect_bsp_APIC(); |
374aab33 TG |
2512 | if (upmode) |
2513 | apic_bsp_up_setup(); | |
05f7e46d TG |
2514 | setup_local_APIC(); |
2515 | ||
05f7e46d | 2516 | enable_IO_APIC(); |
374aab33 TG |
2517 | end_local_APIC_setup(); |
2518 | irq_remap_enable_fault_handling(); | |
05f7e46d | 2519 | setup_IO_APIC(); |
7d65f9e8 | 2520 | lapic_update_legacy_vectors(); |
e714a91f TG |
2521 | } |
2522 | ||
30b8b006 TG |
2523 | #ifdef CONFIG_UP_LATE_INIT |
2524 | void __init up_late_init(void) | |
2525 | { | |
0c759131 DL |
2526 | if (apic_intr_mode == APIC_PIC) |
2527 | return; | |
e714a91f | 2528 | |
a2510d15 DL |
2529 | /* Setup local timer */ |
2530 | x86_init.timers.setup_percpu_clockev(); | |
30b8b006 TG |
2531 | } |
2532 | #endif | |
2533 | ||
89039b37 | 2534 | /* |
0e078e2f | 2535 | * Power management |
89039b37 | 2536 | */ |
0e078e2f TG |
2537 | #ifdef CONFIG_PM |
2538 | ||
2539 | static struct { | |
274cfe59 CG |
2540 | /* |
2541 | * 'active' is true if the local APIC was enabled by us and | |
2542 | * not the BIOS; this signifies that we are also responsible | |
2543 | * for disabling it before entering apm/acpi suspend | |
2544 | */ | |
0e078e2f TG |
2545 | int active; |
2546 | /* r/w apic fields */ | |
4705243d | 2547 | u32 apic_id; |
0e078e2f TG |
2548 | unsigned int apic_taskpri; |
2549 | unsigned int apic_ldr; | |
2550 | unsigned int apic_dfr; | |
2551 | unsigned int apic_spiv; | |
2552 | unsigned int apic_lvtt; | |
2553 | unsigned int apic_lvtpc; | |
2554 | unsigned int apic_lvt0; | |
2555 | unsigned int apic_lvt1; | |
2556 | unsigned int apic_lvterr; | |
2557 | unsigned int apic_tmict; | |
2558 | unsigned int apic_tdcr; | |
2559 | unsigned int apic_thmr; | |
42baa258 | 2560 | unsigned int apic_cmci; |
0e078e2f TG |
2561 | } apic_pm_state; |
2562 | ||
f3c6ea1b | 2563 | static int lapic_suspend(void) |
0e078e2f TG |
2564 | { |
2565 | unsigned long flags; | |
2566 | int maxlvt; | |
89039b37 | 2567 | |
0e078e2f TG |
2568 | if (!apic_pm_state.active) |
2569 | return 0; | |
89039b37 | 2570 | |
0e078e2f | 2571 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2572 | |
2d7a66d0 | 2573 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2574 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2575 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2576 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2577 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2578 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2579 | if (maxlvt >= 4) | |
2580 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2581 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2582 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2583 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2584 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2585 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2586 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2587 | if (maxlvt >= 5) |
2588 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2589 | #endif | |
42baa258 JG |
2590 | #ifdef CONFIG_X86_MCE_INTEL |
2591 | if (maxlvt >= 6) | |
2592 | apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); | |
2593 | #endif | |
24968cfd | 2594 | |
0e078e2f | 2595 | local_irq_save(flags); |
0f378d73 TW |
2596 | |
2597 | /* | |
2598 | * Mask IOAPIC before disabling the local APIC to prevent stale IRR | |
2599 | * entries on some implementations. | |
2600 | */ | |
2601 | mask_ioapic_entries(); | |
2602 | ||
0e078e2f | 2603 | disable_local_APIC(); |
fc1edaf9 | 2604 | |
70733e0c | 2605 | irq_remapping_disable(); |
fc1edaf9 | 2606 | |
0e078e2f TG |
2607 | local_irq_restore(flags); |
2608 | return 0; | |
1da177e4 LT |
2609 | } |
2610 | ||
f3c6ea1b | 2611 | static void lapic_resume(void) |
1da177e4 | 2612 | { |
0e078e2f TG |
2613 | unsigned int l, h; |
2614 | unsigned long flags; | |
31dce14a | 2615 | int maxlvt; |
b24696bc | 2616 | |
0e078e2f | 2617 | if (!apic_pm_state.active) |
f3c6ea1b | 2618 | return; |
89b831ef | 2619 | |
0e078e2f | 2620 | local_irq_save(flags); |
336224ba JR |
2621 | |
2622 | /* | |
2623 | * IO-APIC and PIC have their own resume routines. | |
2624 | * We just mask them here to make sure the interrupt | |
2625 | * subsystem is completely quiet while we enable x2apic | |
2626 | * and interrupt-remapping. | |
2627 | */ | |
2628 | mask_ioapic_entries(); | |
2629 | legacy_pic->mask_all(); | |
92206c90 | 2630 | |
659006bf TG |
2631 | if (x2apic_mode) { |
2632 | __x2apic_enable(); | |
2633 | } else { | |
92206c90 CG |
2634 | /* |
2635 | * Make sure the APICBASE points to the right address | |
2636 | * | |
2637 | * FIXME! This will be wrong if we ever support suspend on | |
2638 | * SMP! We'll need to do this as part of the CPU restore! | |
2639 | */ | |
cbf2829b BD |
2640 | if (boot_cpu_data.x86 >= 6) { |
2641 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2642 | l &= ~MSR_IA32_APICBASE_BASE; | |
2643 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2644 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2645 | } | |
d5e629a6 | 2646 | } |
6e1cb38a | 2647 | |
b24696bc | 2648 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2649 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2650 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2651 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2652 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2653 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2654 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2655 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2656 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
42baa258 | 2657 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2658 | if (maxlvt >= 5) |
2659 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
42baa258 JG |
2660 | #endif |
2661 | #ifdef CONFIG_X86_MCE_INTEL | |
2662 | if (maxlvt >= 6) | |
2663 | apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); | |
0e078e2f TG |
2664 | #endif |
2665 | if (maxlvt >= 4) | |
2666 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2667 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2668 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2669 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2670 | apic_write(APIC_ESR, 0); | |
2671 | apic_read(APIC_ESR); | |
2672 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2673 | apic_write(APIC_ESR, 0); | |
2674 | apic_read(APIC_ESR); | |
92206c90 | 2675 | |
70733e0c | 2676 | irq_remapping_reenable(x2apic_mode); |
31dce14a | 2677 | |
0e078e2f | 2678 | local_irq_restore(flags); |
0e078e2f | 2679 | } |
b8ce3359 | 2680 | |
274cfe59 CG |
2681 | /* |
2682 | * This device has no shutdown method - fully functioning local APICs | |
2683 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2684 | */ | |
2685 | ||
f3c6ea1b | 2686 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2687 | .resume = lapic_resume, |
2688 | .suspend = lapic_suspend, | |
2689 | }; | |
b8ce3359 | 2690 | |
148f9bb8 | 2691 | static void apic_pm_activate(void) |
0e078e2f TG |
2692 | { |
2693 | apic_pm_state.active = 1; | |
1da177e4 LT |
2694 | } |
2695 | ||
0e078e2f | 2696 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2697 | { |
0e078e2f | 2698 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
93984fbd | 2699 | if (boot_cpu_has(X86_FEATURE_APIC)) |
f3c6ea1b | 2700 | register_syscore_ops(&lapic_syscore_ops); |
e83a5fdc | 2701 | |
f3c6ea1b | 2702 | return 0; |
1da177e4 | 2703 | } |
b24696bc FY |
2704 | |
2705 | /* local apic needs to resume before other devices access its registers. */ | |
2706 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2707 | |
2708 | #else /* CONFIG_PM */ | |
2709 | ||
2710 | static void apic_pm_activate(void) { } | |
2711 | ||
2712 | #endif /* CONFIG_PM */ | |
1da177e4 | 2713 | |
f28c0ae2 | 2714 | #ifdef CONFIG_X86_64 |
e0e42142 | 2715 | |
148f9bb8 PG |
2716 | static int multi_checked; |
2717 | static int multi; | |
e0e42142 | 2718 | |
148f9bb8 | 2719 | static int set_multi(const struct dmi_system_id *d) |
e0e42142 YL |
2720 | { |
2721 | if (multi) | |
2722 | return 0; | |
6f0aced6 | 2723 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2724 | multi = 1; |
2725 | return 0; | |
2726 | } | |
2727 | ||
148f9bb8 | 2728 | static const struct dmi_system_id multi_dmi_table[] = { |
e0e42142 YL |
2729 | { |
2730 | .callback = set_multi, | |
2731 | .ident = "IBM System Summit2", | |
2732 | .matches = { | |
2733 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2734 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2735 | }, | |
2736 | }, | |
2737 | {} | |
2738 | }; | |
2739 | ||
148f9bb8 | 2740 | static void dmi_check_multi(void) |
e0e42142 YL |
2741 | { |
2742 | if (multi_checked) | |
2743 | return; | |
2744 | ||
2745 | dmi_check_system(multi_dmi_table); | |
2746 | multi_checked = 1; | |
2747 | } | |
2748 | ||
2749 | /* | |
2750 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2751 | * | |
2752 | * Thus far, the major user of this is IBM's Summit2 series: | |
2753 | * Clustered boxes may have unsynced TSC problems if they are | |
2754 | * multi-chassis. | |
2755 | * Use DMI to check them | |
2756 | */ | |
148f9bb8 | 2757 | int apic_is_clustered_box(void) |
e0e42142 YL |
2758 | { |
2759 | dmi_check_multi(); | |
411cf9ee | 2760 | return multi; |
1da177e4 | 2761 | } |
f28c0ae2 | 2762 | #endif |
1da177e4 LT |
2763 | |
2764 | /* | |
0e078e2f | 2765 | * APIC command line parameters |
1da177e4 | 2766 | */ |
789fa735 | 2767 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2768 | { |
49062454 | 2769 | apic_is_disabled = true; |
9175fc06 | 2770 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2771 | return 0; |
2772 | } | |
2773 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2774 | |
2c8c0e6b | 2775 | /* same as disableapic, for compatibility */ |
789fa735 | 2776 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2777 | { |
789fa735 | 2778 | return setup_disableapic(arg); |
6935d1f9 | 2779 | } |
2c8c0e6b | 2780 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2781 | |
2e7c2838 LT |
2782 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2783 | { | |
2784 | local_apic_timer_c2_ok = 1; | |
2785 | return 0; | |
2786 | } | |
2787 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2788 | ||
36fef094 | 2789 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2790 | { |
1da177e4 | 2791 | disable_apic_timer = 1; |
36fef094 | 2792 | return 0; |
6935d1f9 | 2793 | } |
36fef094 CG |
2794 | early_param("noapictimer", parse_disable_apic_timer); |
2795 | ||
2796 | static int __init parse_nolapic_timer(char *arg) | |
2797 | { | |
2798 | disable_apic_timer = 1; | |
2799 | return 0; | |
6935d1f9 | 2800 | } |
36fef094 | 2801 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2802 | |
79af9bec CG |
2803 | static int __init apic_set_verbosity(char *arg) |
2804 | { | |
2805 | if (!arg) { | |
ecf600f8 TG |
2806 | if (IS_ENABLED(CONFIG_X86_32)) |
2807 | return -EINVAL; | |
2808 | ||
2809 | ioapic_is_disabled = false; | |
79af9bec | 2810 | return 0; |
79af9bec CG |
2811 | } |
2812 | ||
2813 | if (strcmp("debug", arg) == 0) | |
2814 | apic_verbosity = APIC_DEBUG; | |
2815 | else if (strcmp("verbose", arg) == 0) | |
2816 | apic_verbosity = APIC_VERBOSE; | |
4fcab669 | 2817 | #ifdef CONFIG_X86_64 |
79af9bec | 2818 | else { |
8d3bcc44 | 2819 | pr_warn("APIC Verbosity level %s not recognised" |
79af9bec CG |
2820 | " use apic=verbose or apic=debug\n", arg); |
2821 | return -EINVAL; | |
2822 | } | |
4fcab669 | 2823 | #endif |
79af9bec CG |
2824 | |
2825 | return 0; | |
2826 | } | |
2827 | early_param("apic", apic_set_verbosity); | |
2828 | ||
1e934dda YL |
2829 | static int __init lapic_insert_resource(void) |
2830 | { | |
78c32000 | 2831 | if (!apic_mmio_base) |
1e934dda YL |
2832 | return -1; |
2833 | ||
2834 | /* Put local APIC into the resource map. */ | |
78c32000 | 2835 | lapic_resource.start = apic_mmio_base; |
1e934dda YL |
2836 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; |
2837 | insert_resource(&iomem_resource, &lapic_resource); | |
2838 | ||
2839 | return 0; | |
2840 | } | |
2841 | ||
2842 | /* | |
1506c8dc | 2843 | * need call insert after e820__reserve_resources() |
1e934dda YL |
2844 | * that is using request_resource |
2845 | */ | |
2846 | late_initcall(lapic_insert_resource); | |
151e0c7d HD |
2847 | |
2848 | static int __init apic_set_disabled_cpu_apicid(char *arg) | |
2849 | { | |
2850 | if (!arg || !get_option(&arg, &disabled_cpu_apicid)) | |
2851 | return -EINVAL; | |
2852 | ||
2853 | return 0; | |
2854 | } | |
2855 | early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); | |
b7c4948e HK |
2856 | |
2857 | static int __init apic_set_extnmi(char *arg) | |
2858 | { | |
2859 | if (!arg) | |
2860 | return -EINVAL; | |
2861 | ||
2862 | if (!strncmp("all", arg, 3)) | |
2863 | apic_extnmi = APIC_EXTNMI_ALL; | |
2864 | else if (!strncmp("none", arg, 4)) | |
2865 | apic_extnmi = APIC_EXTNMI_NONE; | |
2866 | else if (!strncmp("bsp", arg, 3)) | |
2867 | apic_extnmi = APIC_EXTNMI_BSP; | |
2868 | else { | |
2869 | pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); | |
2870 | return -EINVAL; | |
2871 | } | |
2872 | ||
2873 | return 0; | |
2874 | } | |
2875 | early_param("apic_extnmi", apic_set_extnmi); |