Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
cdd6c482 | 17 | #include <linux/perf_event.h> |
1da177e4 | 18 | #include <linux/kernel_stat.h> |
d1de36f5 | 19 | #include <linux/mc146818rtc.h> |
70a20025 | 20 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
21 | #include <linux/clockchips.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/ftrace.h> | |
25 | #include <linux/ioport.h> | |
e83a5fdc | 26 | #include <linux/module.h> |
f3c6ea1b | 27 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
28 | #include <linux/delay.h> |
29 | #include <linux/timex.h> | |
334955ef | 30 | #include <linux/i8253.h> |
6e1cb38a | 31 | #include <linux/dmar.h> |
d1de36f5 IM |
32 | #include <linux/init.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/dmi.h> | |
d1de36f5 IM |
35 | #include <linux/smp.h> |
36 | #include <linux/mm.h> | |
1da177e4 | 37 | |
cdd6c482 | 38 | #include <asm/perf_event.h> |
736decac | 39 | #include <asm/x86_init.h> |
1da177e4 | 40 | #include <asm/pgalloc.h> |
60063497 | 41 | #include <linux/atomic.h> |
1da177e4 | 42 | #include <asm/mpspec.h> |
d1de36f5 | 43 | #include <asm/i8259.h> |
73dea47f | 44 | #include <asm/proto.h> |
2c8c0e6b | 45 | #include <asm/apic.h> |
7167d08e | 46 | #include <asm/io_apic.h> |
d1de36f5 IM |
47 | #include <asm/desc.h> |
48 | #include <asm/hpet.h> | |
49 | #include <asm/idle.h> | |
50 | #include <asm/mtrr.h> | |
16f871bc | 51 | #include <asm/time.h> |
2bc13797 | 52 | #include <asm/smp.h> |
be71b855 | 53 | #include <asm/mce.h> |
8c3ba8d0 | 54 | #include <asm/tsc.h> |
2904ed8d | 55 | #include <asm/hypervisor.h> |
1da177e4 | 56 | |
ec70de8b | 57 | unsigned int num_processors; |
fdbecd9f | 58 | |
ec70de8b | 59 | unsigned disabled_cpus __cpuinitdata; |
fdbecd9f | 60 | |
ec70de8b BG |
61 | /* Processor that is doing the boot up */ |
62 | unsigned int boot_cpu_physical_apicid = -1U; | |
5af5573e | 63 | |
80e5609c | 64 | /* |
fdbecd9f | 65 | * The highest APIC ID seen during enumeration. |
80e5609c | 66 | */ |
ec70de8b | 67 | unsigned int max_physical_apicid; |
5af5573e | 68 | |
80e5609c | 69 | /* |
fdbecd9f | 70 | * Bitmask of physically existing CPUs: |
80e5609c | 71 | */ |
ec70de8b BG |
72 | physid_mask_t phys_cpu_present_map; |
73 | ||
74 | /* | |
75 | * Map cpu index to physical APIC ID | |
76 | */ | |
77 | DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); | |
78 | DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); | |
79 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
80 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
80e5609c | 81 | |
b3c51170 | 82 | #ifdef CONFIG_X86_32 |
4c321ff8 | 83 | |
4c321ff8 TH |
84 | /* |
85 | * On x86_32, the mapping between cpu and logical apicid may vary | |
86 | * depending on apic in use. The following early percpu variable is | |
87 | * used for the mapping. This is where the behaviors of x86_64 and 32 | |
88 | * actually diverge. Let's keep it ugly for now. | |
89 | */ | |
90 | DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID); | |
4c321ff8 | 91 | |
b3c51170 YL |
92 | /* |
93 | * Knob to control our willingness to enable the local APIC. | |
94 | * | |
95 | * +1=force-enable | |
96 | */ | |
25874a29 | 97 | static int force_enable_local_apic __initdata; |
b3c51170 YL |
98 | /* |
99 | * APIC command line parameters | |
100 | */ | |
101 | static int __init parse_lapic(char *arg) | |
102 | { | |
103 | force_enable_local_apic = 1; | |
104 | return 0; | |
105 | } | |
106 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
107 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
108 | static int enabled_via_apicbase; | |
109 | ||
c0eaa453 CG |
110 | /* |
111 | * Handle interrupt mode configuration register (IMCR). | |
112 | * This register controls whether the interrupt signals | |
113 | * that reach the BSP come from the master PIC or from the | |
114 | * local APIC. Before entering Symmetric I/O Mode, either | |
115 | * the BIOS or the operating system must switch out of | |
116 | * PIC Mode by changing the IMCR. | |
117 | */ | |
5cda395f | 118 | static inline void imcr_pic_to_apic(void) |
c0eaa453 CG |
119 | { |
120 | /* select IMCR register */ | |
121 | outb(0x70, 0x22); | |
122 | /* NMI and 8259 INTR go through APIC */ | |
123 | outb(0x01, 0x23); | |
124 | } | |
125 | ||
5cda395f | 126 | static inline void imcr_apic_to_pic(void) |
c0eaa453 CG |
127 | { |
128 | /* select IMCR register */ | |
129 | outb(0x70, 0x22); | |
130 | /* NMI and 8259 INTR go directly to BSP */ | |
131 | outb(0x00, 0x23); | |
132 | } | |
b3c51170 YL |
133 | #endif |
134 | ||
135 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 136 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
137 | static __init int setup_apicpmtimer(char *s) |
138 | { | |
139 | apic_calibrate_pmtmr = 1; | |
140 | notsc_setup(NULL); | |
141 | return 0; | |
142 | } | |
143 | __setup("apicpmtimer", setup_apicpmtimer); | |
144 | #endif | |
145 | ||
fc1edaf9 | 146 | int x2apic_mode; |
06cd9a7d | 147 | #ifdef CONFIG_X86_X2APIC |
6e1cb38a | 148 | /* x2apic enabled before OS handover */ |
fb209bd8 YL |
149 | int x2apic_preenabled; |
150 | static int x2apic_disabled; | |
a31bc327 | 151 | static int nox2apic; |
49899eac YL |
152 | static __init int setup_nox2apic(char *str) |
153 | { | |
39d83a5d | 154 | if (x2apic_enabled()) { |
a31bc327 YL |
155 | int apicid = native_apic_msr_read(APIC_ID); |
156 | ||
157 | if (apicid >= 255) { | |
158 | pr_warning("Apicid: %08x, cannot enforce nox2apic\n", | |
159 | apicid); | |
160 | return 0; | |
161 | } | |
162 | ||
163 | pr_warning("x2apic already enabled. will disable it\n"); | |
164 | } else | |
165 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
166 | ||
167 | nox2apic = 1; | |
39d83a5d | 168 | |
49899eac YL |
169 | return 0; |
170 | } | |
171 | early_param("nox2apic", setup_nox2apic); | |
172 | #endif | |
1da177e4 | 173 | |
b3c51170 YL |
174 | unsigned long mp_lapic_addr; |
175 | int disable_apic; | |
176 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
25874a29 | 177 | static int disable_apic_timer __initdata; |
e83a5fdc | 178 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
179 | int local_apic_timer_c2_ok; |
180 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
181 | ||
efa2559f YL |
182 | int first_system_vector = 0xfe; |
183 | ||
e83a5fdc HS |
184 | /* |
185 | * Debug level, exported for io_apic.c | |
186 | */ | |
baa13188 | 187 | unsigned int apic_verbosity; |
e83a5fdc | 188 | |
89c38c28 CG |
189 | int pic_mode; |
190 | ||
bab4b27c AS |
191 | /* Have we found an MP table */ |
192 | int smp_found_config; | |
193 | ||
39928722 AD |
194 | static struct resource lapic_resource = { |
195 | .name = "Local APIC", | |
196 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
197 | }; | |
198 | ||
1ade93ef | 199 | unsigned int lapic_timer_frequency = 0; |
d03030e9 | 200 | |
0e078e2f | 201 | static void apic_pm_activate(void); |
ba7eda4c | 202 | |
d3432896 AK |
203 | static unsigned long apic_phys; |
204 | ||
0e078e2f TG |
205 | /* |
206 | * Get the LAPIC version | |
207 | */ | |
208 | static inline int lapic_get_version(void) | |
ba7eda4c | 209 | { |
0e078e2f | 210 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
211 | } |
212 | ||
0e078e2f | 213 | /* |
9c803869 | 214 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
215 | */ |
216 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 217 | { |
9c803869 | 218 | #ifdef CONFIG_X86_64 |
0e078e2f | 219 | return 1; |
9c803869 CG |
220 | #else |
221 | return APIC_INTEGRATED(lapic_get_version()); | |
222 | #endif | |
ba7eda4c TG |
223 | } |
224 | ||
225 | /* | |
0e078e2f | 226 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 227 | */ |
0e078e2f | 228 | static int modern_apic(void) |
ba7eda4c | 229 | { |
0e078e2f TG |
230 | /* AMD systems use old APIC versions, so check the CPU */ |
231 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
232 | boot_cpu_data.x86 >= 0xf) | |
233 | return 1; | |
234 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
235 | } |
236 | ||
08306ce6 | 237 | /* |
a933c618 CG |
238 | * right after this call apic become NOOP driven |
239 | * so apic->write/read doesn't do anything | |
08306ce6 | 240 | */ |
25874a29 | 241 | static void __init apic_disable(void) |
08306ce6 | 242 | { |
f88f2b4f | 243 | pr_info("APIC: switched to apic NOOP\n"); |
a933c618 | 244 | apic = &apic_noop; |
08306ce6 CG |
245 | } |
246 | ||
c1eeb2de | 247 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
248 | { |
249 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
250 | cpu_relax(); | |
251 | } | |
252 | ||
c1eeb2de | 253 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 254 | { |
3c6bb07a | 255 | u32 send_status; |
8339e9fb FLV |
256 | int timeout; |
257 | ||
258 | timeout = 0; | |
259 | do { | |
260 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
261 | if (!send_status) | |
262 | break; | |
b49d7d87 | 263 | inc_irq_stat(icr_read_retry_count); |
8339e9fb FLV |
264 | udelay(100); |
265 | } while (timeout++ < 1000); | |
266 | ||
267 | return send_status; | |
268 | } | |
269 | ||
c1eeb2de | 270 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 271 | { |
ed4e5ec1 | 272 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
273 | apic_write(APIC_ICR, low); |
274 | } | |
275 | ||
c1eeb2de | 276 | u64 native_apic_icr_read(void) |
1b374e4d SS |
277 | { |
278 | u32 icr1, icr2; | |
279 | ||
280 | icr2 = apic_read(APIC_ICR2); | |
281 | icr1 = apic_read(APIC_ICR); | |
282 | ||
cf9768d7 | 283 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
284 | } |
285 | ||
7c37e48b CG |
286 | #ifdef CONFIG_X86_32 |
287 | /** | |
288 | * get_physical_broadcast - Get number of physical broadcast IDs | |
289 | */ | |
290 | int get_physical_broadcast(void) | |
291 | { | |
292 | return modern_apic() ? 0xff : 0xf; | |
293 | } | |
294 | #endif | |
295 | ||
0e078e2f TG |
296 | /** |
297 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
298 | */ | |
37e650c7 | 299 | int lapic_get_maxlvt(void) |
1da177e4 | 300 | { |
36a028de | 301 | unsigned int v; |
1da177e4 LT |
302 | |
303 | v = apic_read(APIC_LVR); | |
36a028de CG |
304 | /* |
305 | * - we always have APIC integrated on 64bit mode | |
306 | * - 82489DXs do not report # of LVT entries | |
307 | */ | |
308 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
309 | } |
310 | ||
274cfe59 CG |
311 | /* |
312 | * Local APIC timer | |
313 | */ | |
314 | ||
c40aaec6 | 315 | /* Clock divisor */ |
c40aaec6 | 316 | #define APIC_DIVISOR 16 |
f07f4f90 | 317 | |
0e078e2f TG |
318 | /* |
319 | * This function sets up the local APIC timer, with a timeout of | |
320 | * 'clocks' APIC bus clock. During calibration we actually call | |
321 | * this function twice on the boot CPU, once with a bogus timeout | |
322 | * value, second time for real. The other (noncalibrating) CPUs | |
323 | * call this function only once, with the real, calibrated value. | |
324 | * | |
325 | * We do reads before writes even if unnecessary, to get around the | |
326 | * P5 APIC double write bug. | |
327 | */ | |
0e078e2f | 328 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 329 | { |
0e078e2f | 330 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 331 | |
0e078e2f TG |
332 | lvtt_value = LOCAL_TIMER_VECTOR; |
333 | if (!oneshot) | |
334 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
335 | if (!lapic_is_integrated()) |
336 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
337 | ||
0e078e2f TG |
338 | if (!irqen) |
339 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 340 | |
0e078e2f | 341 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
342 | |
343 | /* | |
0e078e2f | 344 | * Divide PICLK by 16 |
1da177e4 | 345 | */ |
0e078e2f | 346 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
347 | apic_write(APIC_TDCR, |
348 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
349 | APIC_TDR_DIV_16); | |
0e078e2f TG |
350 | |
351 | if (!oneshot) | |
f07f4f90 | 352 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
353 | } |
354 | ||
0e078e2f | 355 | /* |
a68c439b | 356 | * Setup extended LVT, AMD specific |
7b83dae7 | 357 | * |
a68c439b RR |
358 | * Software should use the LVT offsets the BIOS provides. The offsets |
359 | * are determined by the subsystems using it like those for MCE | |
360 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
361 | * are supported. Beginning with family 10h at least 4 offsets are | |
362 | * available. | |
286f5718 | 363 | * |
a68c439b RR |
364 | * Since the offsets must be consistent for all cores, we keep track |
365 | * of the LVT offsets in software and reserve the offset for the same | |
366 | * vector also to be used on other cores. An offset is freed by | |
367 | * setting the entry to APIC_EILVT_MASKED. | |
368 | * | |
369 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
370 | * "[Firmware Bug]: ..." error message is generated. However, if | |
371 | * software does not properly determines the offsets, it is not | |
372 | * necessarily a BIOS bug. | |
0e078e2f | 373 | */ |
7b83dae7 | 374 | |
a68c439b RR |
375 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
376 | ||
377 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
378 | { | |
379 | return (old & APIC_EILVT_MASKED) | |
380 | || (new == APIC_EILVT_MASKED) | |
381 | || ((new & ~APIC_EILVT_MASKED) == old); | |
382 | } | |
383 | ||
384 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
385 | { | |
8abc3122 | 386 | unsigned int rsvd, vector; |
a68c439b RR |
387 | |
388 | if (offset >= APIC_EILVT_NR_MAX) | |
389 | return ~0; | |
390 | ||
8abc3122 | 391 | rsvd = atomic_read(&eilvt_offsets[offset]); |
a68c439b | 392 | do { |
8abc3122 RR |
393 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
394 | if (vector && !eilvt_entry_is_changeable(vector, new)) | |
a68c439b RR |
395 | /* may not change if vectors are different */ |
396 | return rsvd; | |
397 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); | |
398 | } while (rsvd != new); | |
399 | ||
8abc3122 RR |
400 | rsvd &= ~APIC_EILVT_MASKED; |
401 | if (rsvd && rsvd != vector) | |
402 | pr_info("LVT offset %d assigned for vector 0x%02x\n", | |
403 | offset, rsvd); | |
404 | ||
a68c439b RR |
405 | return new; |
406 | } | |
407 | ||
408 | /* | |
409 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
410 | * enables the vector. See also the BKDGs. Must be called with |
411 | * preemption disabled. | |
a68c439b RR |
412 | */ |
413 | ||
27afdf20 | 414 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 415 | { |
a68c439b RR |
416 | unsigned long reg = APIC_EILVTn(offset); |
417 | unsigned int new, old, reserved; | |
418 | ||
419 | new = (mask << 16) | (msg_type << 8) | vector; | |
420 | old = apic_read(reg); | |
421 | reserved = reserve_eilvt_offset(offset, new); | |
422 | ||
423 | if (reserved != new) { | |
eb48c9cb RR |
424 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
425 | "vector 0x%x, but the register is already in use for " | |
426 | "vector 0x%x on another cpu\n", | |
427 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
428 | return -EINVAL; |
429 | } | |
430 | ||
431 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
432 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
433 | "vector 0x%x, but the register is already in use for " | |
434 | "vector 0x%x on this cpu\n", | |
435 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
436 | return -EBUSY; |
437 | } | |
438 | ||
439 | apic_write(reg, new); | |
a8fcf1a2 | 440 | |
a68c439b | 441 | return 0; |
1da177e4 | 442 | } |
27afdf20 | 443 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 444 | |
0e078e2f TG |
445 | /* |
446 | * Program the next event, relative to now | |
447 | */ | |
448 | static int lapic_next_event(unsigned long delta, | |
449 | struct clock_event_device *evt) | |
1da177e4 | 450 | { |
0e078e2f TG |
451 | apic_write(APIC_TMICT, delta); |
452 | return 0; | |
1da177e4 LT |
453 | } |
454 | ||
0e078e2f TG |
455 | /* |
456 | * Setup the lapic timer in periodic or oneshot mode | |
457 | */ | |
458 | static void lapic_timer_setup(enum clock_event_mode mode, | |
459 | struct clock_event_device *evt) | |
9b7711f0 HS |
460 | { |
461 | unsigned long flags; | |
0e078e2f | 462 | unsigned int v; |
9b7711f0 | 463 | |
0e078e2f TG |
464 | /* Lapic used as dummy for broadcast ? */ |
465 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
466 | return; |
467 | ||
468 | local_irq_save(flags); | |
469 | ||
0e078e2f TG |
470 | switch (mode) { |
471 | case CLOCK_EVT_MODE_PERIODIC: | |
472 | case CLOCK_EVT_MODE_ONESHOT: | |
1ade93ef | 473 | __setup_APIC_LVTT(lapic_timer_frequency, |
0e078e2f TG |
474 | mode != CLOCK_EVT_MODE_PERIODIC, 1); |
475 | break; | |
476 | case CLOCK_EVT_MODE_UNUSED: | |
477 | case CLOCK_EVT_MODE_SHUTDOWN: | |
478 | v = apic_read(APIC_LVTT); | |
479 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
480 | apic_write(APIC_LVTT, v); | |
6f9b4100 | 481 | apic_write(APIC_TMICT, 0); |
0e078e2f TG |
482 | break; |
483 | case CLOCK_EVT_MODE_RESUME: | |
484 | /* Nothing to do here */ | |
485 | break; | |
486 | } | |
9b7711f0 HS |
487 | |
488 | local_irq_restore(flags); | |
489 | } | |
490 | ||
1da177e4 | 491 | /* |
0e078e2f | 492 | * Local APIC timer broadcast function |
1da177e4 | 493 | */ |
9628937d | 494 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 495 | { |
0e078e2f | 496 | #ifdef CONFIG_SMP |
dac5f412 | 497 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
498 | #endif |
499 | } | |
1da177e4 | 500 | |
25874a29 HK |
501 | |
502 | /* | |
503 | * The local apic timer can be used for any function which is CPU local. | |
504 | */ | |
505 | static struct clock_event_device lapic_clockevent = { | |
506 | .name = "lapic", | |
507 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
508 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
509 | .shift = 32, | |
510 | .set_mode = lapic_timer_setup, | |
511 | .set_next_event = lapic_next_event, | |
512 | .broadcast = lapic_timer_broadcast, | |
513 | .rating = 100, | |
514 | .irq = -1, | |
515 | }; | |
516 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
517 | ||
0e078e2f | 518 | /* |
421f91d2 | 519 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
520 | * of the boot CPU and register the clock event in the framework. |
521 | */ | |
db4b5525 | 522 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
523 | { |
524 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 525 | |
349c004e | 526 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 VP |
527 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
528 | /* Make LAPIC timer preferrable over percpu HPET */ | |
529 | lapic_clockevent.rating = 150; | |
530 | } | |
531 | ||
0e078e2f | 532 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 533 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 534 | |
0e078e2f TG |
535 | clockevents_register_device(levt); |
536 | } | |
1da177e4 | 537 | |
2f04fa88 YL |
538 | /* |
539 | * In this functions we calibrate APIC bus clocks to the external timer. | |
540 | * | |
541 | * We want to do the calibration only once since we want to have local timer | |
542 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
543 | * frequency. | |
544 | * | |
545 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
546 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
547 | * readout is broken, so it never gets out of the wait loop again. This was | |
548 | * also reported by others. | |
549 | * | |
550 | * Monitoring the jiffies value is inaccurate and the clockevents | |
551 | * infrastructure allows us to do a simple substitution of the interrupt | |
552 | * handler. | |
553 | * | |
554 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
555 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
556 | * back to normal later in the boot process). | |
557 | */ | |
558 | ||
559 | #define LAPIC_CAL_LOOPS (HZ/10) | |
560 | ||
561 | static __initdata int lapic_cal_loops = -1; | |
562 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
563 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
564 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
565 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
566 | ||
567 | /* | |
568 | * Temporary interrupt handler. | |
569 | */ | |
570 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
571 | { | |
572 | unsigned long long tsc = 0; | |
573 | long tapic = apic_read(APIC_TMCCT); | |
574 | unsigned long pm = acpi_pm_read_early(); | |
575 | ||
576 | if (cpu_has_tsc) | |
577 | rdtscll(tsc); | |
578 | ||
579 | switch (lapic_cal_loops++) { | |
580 | case 0: | |
581 | lapic_cal_t1 = tapic; | |
582 | lapic_cal_tsc1 = tsc; | |
583 | lapic_cal_pm1 = pm; | |
584 | lapic_cal_j1 = jiffies; | |
585 | break; | |
586 | ||
587 | case LAPIC_CAL_LOOPS: | |
588 | lapic_cal_t2 = tapic; | |
589 | lapic_cal_tsc2 = tsc; | |
590 | if (pm < lapic_cal_pm1) | |
591 | pm += ACPI_PM_OVRRUN; | |
592 | lapic_cal_pm2 = pm; | |
593 | lapic_cal_j2 = jiffies; | |
594 | break; | |
595 | } | |
596 | } | |
597 | ||
754ef0cd YI |
598 | static int __init |
599 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
600 | { |
601 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
602 | const long pm_thresh = pm_100ms / 100; | |
603 | unsigned long mult; | |
604 | u64 res; | |
605 | ||
606 | #ifndef CONFIG_X86_PM_TIMER | |
607 | return -1; | |
608 | #endif | |
609 | ||
39ba5d43 | 610 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
611 | |
612 | /* Check, if the PM timer is available */ | |
613 | if (!deltapm) | |
614 | return -1; | |
615 | ||
616 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
617 | ||
618 | if (deltapm > (pm_100ms - pm_thresh) && | |
619 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 620 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
621 | return 0; |
622 | } | |
623 | ||
624 | res = (((u64)deltapm) * mult) >> 22; | |
625 | do_div(res, 1000000); | |
626 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 627 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
628 | |
629 | /* Correct the lapic counter value */ | |
630 | res = (((u64)(*delta)) * pm_100ms); | |
631 | do_div(res, deltapm); | |
632 | pr_info("APIC delta adjusted to PM-Timer: " | |
633 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
634 | *delta = (long)res; | |
635 | ||
636 | /* Correct the tsc counter value */ | |
637 | if (cpu_has_tsc) { | |
638 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 639 | do_div(res, deltapm); |
754ef0cd | 640 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 641 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
642 | (unsigned long)res, *deltatsc); |
643 | *deltatsc = (long)res; | |
b189892d CG |
644 | } |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
2f04fa88 YL |
649 | static int __init calibrate_APIC_clock(void) |
650 | { | |
651 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
652 | void (*real_handler)(struct clock_event_device *dev); |
653 | unsigned long deltaj; | |
754ef0cd | 654 | long delta, deltatsc; |
2f04fa88 YL |
655 | int pm_referenced = 0; |
656 | ||
1ade93ef JP |
657 | /** |
658 | * check if lapic timer has already been calibrated by platform | |
659 | * specific routine, such as tsc calibration code. if so, we just fill | |
660 | * in the clockevent structure and return. | |
661 | */ | |
662 | ||
663 | if (lapic_timer_frequency) { | |
664 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", | |
665 | lapic_timer_frequency); | |
666 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, | |
667 | TICK_NSEC, lapic_clockevent.shift); | |
668 | lapic_clockevent.max_delta_ns = | |
669 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
670 | lapic_clockevent.min_delta_ns = | |
671 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
672 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
673 | return 0; | |
674 | } | |
675 | ||
2f04fa88 YL |
676 | local_irq_disable(); |
677 | ||
678 | /* Replace the global interrupt handler */ | |
679 | real_handler = global_clock_event->event_handler; | |
680 | global_clock_event->event_handler = lapic_cal_handler; | |
681 | ||
682 | /* | |
81608f3c | 683 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
684 | * can underflow in the 100ms detection time frame |
685 | */ | |
81608f3c | 686 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
687 | |
688 | /* Let the interrupts run */ | |
689 | local_irq_enable(); | |
690 | ||
691 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
692 | cpu_relax(); | |
693 | ||
694 | local_irq_disable(); | |
695 | ||
696 | /* Restore the real event handler */ | |
697 | global_clock_event->event_handler = real_handler; | |
698 | ||
699 | /* Build delta t1-t2 as apic timer counts down */ | |
700 | delta = lapic_cal_t1 - lapic_cal_t2; | |
701 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
702 | ||
754ef0cd YI |
703 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
704 | ||
b189892d CG |
705 | /* we trust the PM based calibration if possible */ |
706 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 707 | &delta, &deltatsc); |
2f04fa88 YL |
708 | |
709 | /* Calculate the scaled math multiplication factor */ | |
710 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
711 | lapic_clockevent.shift); | |
712 | lapic_clockevent.max_delta_ns = | |
4aed89d6 | 713 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
2f04fa88 YL |
714 | lapic_clockevent.min_delta_ns = |
715 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
716 | ||
1ade93ef | 717 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
2f04fa88 YL |
718 | |
719 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 720 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 | 721 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
1ade93ef | 722 | lapic_timer_frequency); |
2f04fa88 YL |
723 | |
724 | if (cpu_has_tsc) { | |
2f04fa88 YL |
725 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
726 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
727 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
728 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
729 | } |
730 | ||
731 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
732 | "%u.%04u MHz.\n", | |
1ade93ef JP |
733 | lapic_timer_frequency / (1000000 / HZ), |
734 | lapic_timer_frequency % (1000000 / HZ)); | |
2f04fa88 YL |
735 | |
736 | /* | |
737 | * Do a sanity check on the APIC calibration result | |
738 | */ | |
1ade93ef | 739 | if (lapic_timer_frequency < (1000000 / HZ)) { |
2f04fa88 | 740 | local_irq_enable(); |
ba21ebb6 | 741 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
742 | return -1; |
743 | } | |
744 | ||
745 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
746 | ||
b189892d CG |
747 | /* |
748 | * PM timer calibration failed or not turned on | |
749 | * so lets try APIC timer based calibration | |
750 | */ | |
2f04fa88 YL |
751 | if (!pm_referenced) { |
752 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
753 | ||
754 | /* | |
755 | * Setup the apic timer manually | |
756 | */ | |
757 | levt->event_handler = lapic_cal_handler; | |
758 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
759 | lapic_cal_loops = -1; | |
760 | ||
761 | /* Let the interrupts run */ | |
762 | local_irq_enable(); | |
763 | ||
764 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
765 | cpu_relax(); | |
766 | ||
2f04fa88 YL |
767 | /* Stop the lapic timer */ |
768 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
769 | ||
2f04fa88 YL |
770 | /* Jiffies delta */ |
771 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
772 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
773 | ||
774 | /* Check, if the jiffies result is consistent */ | |
775 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
776 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
777 | else | |
778 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
779 | } else | |
780 | local_irq_enable(); | |
781 | ||
782 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 783 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
784 | return -1; |
785 | } | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
e83a5fdc HS |
790 | /* |
791 | * Setup the boot APIC | |
792 | * | |
793 | * Calibrate and verify the result. | |
794 | */ | |
0e078e2f TG |
795 | void __init setup_boot_APIC_clock(void) |
796 | { | |
797 | /* | |
274cfe59 CG |
798 | * The local apic timer can be disabled via the kernel |
799 | * commandline or from the CPU detection code. Register the lapic | |
800 | * timer as a dummy clock event source on SMP systems, so the | |
801 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
802 | */ |
803 | if (disable_apic_timer) { | |
ba21ebb6 | 804 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 805 | /* No broadcast on UP ! */ |
9d09951d TG |
806 | if (num_possible_cpus() > 1) { |
807 | lapic_clockevent.mult = 1; | |
0e078e2f | 808 | setup_APIC_timer(); |
9d09951d | 809 | } |
0e078e2f TG |
810 | return; |
811 | } | |
812 | ||
274cfe59 CG |
813 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
814 | "calibrating APIC timer ...\n"); | |
815 | ||
89b3b1f4 | 816 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
817 | /* No broadcast on UP ! */ |
818 | if (num_possible_cpus() > 1) | |
819 | setup_APIC_timer(); | |
820 | return; | |
821 | } | |
822 | ||
0e078e2f TG |
823 | /* |
824 | * If nmi_watchdog is set to IO_APIC, we need the | |
825 | * PIT/HPET going. Otherwise register lapic as a dummy | |
826 | * device. | |
827 | */ | |
072b198a | 828 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 829 | |
274cfe59 | 830 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
831 | setup_APIC_timer(); |
832 | } | |
833 | ||
0e078e2f TG |
834 | void __cpuinit setup_secondary_APIC_clock(void) |
835 | { | |
0e078e2f TG |
836 | setup_APIC_timer(); |
837 | } | |
838 | ||
839 | /* | |
840 | * The guts of the apic timer interrupt | |
841 | */ | |
842 | static void local_apic_timer_interrupt(void) | |
843 | { | |
844 | int cpu = smp_processor_id(); | |
845 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
846 | ||
847 | /* | |
848 | * Normally we should not be here till LAPIC has been initialized but | |
849 | * in some cases like kdump, its possible that there is a pending LAPIC | |
850 | * timer interrupt from previous kernel's context and is delivered in | |
851 | * new kernel the moment interrupts are enabled. | |
852 | * | |
853 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
854 | * its possible that when we get here evt->event_handler is NULL. | |
855 | * Check for event_handler being NULL and discard the interrupt as | |
856 | * spurious. | |
857 | */ | |
858 | if (!evt->event_handler) { | |
ba21ebb6 | 859 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
860 | /* Switch it off */ |
861 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
862 | return; | |
863 | } | |
864 | ||
865 | /* | |
866 | * the NMI deadlock-detector uses this. | |
867 | */ | |
915b0d01 | 868 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
869 | |
870 | evt->event_handler(evt); | |
871 | } | |
872 | ||
873 | /* | |
874 | * Local APIC timer interrupt. This is the most natural way for doing | |
875 | * local interrupts, but local timer interrupts can be emulated by | |
876 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
877 | * | |
878 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
879 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
880 | */ | |
bcbc4f20 | 881 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
882 | { |
883 | struct pt_regs *old_regs = set_irq_regs(regs); | |
884 | ||
885 | /* | |
886 | * NOTE! We'd better ACK the irq immediately, | |
887 | * because timer handling can be slow. | |
888 | */ | |
889 | ack_APIC_irq(); | |
890 | /* | |
891 | * update_process_times() expects us to have done irq_enter(). | |
892 | * Besides, if we don't timer interrupts ignore the global | |
893 | * interrupt lock, which is the WrongThing (tm) to do. | |
894 | */ | |
0e078e2f | 895 | irq_enter(); |
98ad1cc1 | 896 | exit_idle(); |
0e078e2f TG |
897 | local_apic_timer_interrupt(); |
898 | irq_exit(); | |
274cfe59 | 899 | |
0e078e2f TG |
900 | set_irq_regs(old_regs); |
901 | } | |
902 | ||
903 | int setup_profiling_timer(unsigned int multiplier) | |
904 | { | |
905 | return -EINVAL; | |
906 | } | |
907 | ||
0e078e2f TG |
908 | /* |
909 | * Local APIC start and shutdown | |
910 | */ | |
911 | ||
912 | /** | |
913 | * clear_local_APIC - shutdown the local APIC | |
914 | * | |
915 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
916 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
917 | * leftovers during boot. | |
918 | */ | |
919 | void clear_local_APIC(void) | |
920 | { | |
2584a82d | 921 | int maxlvt; |
0e078e2f TG |
922 | u32 v; |
923 | ||
d3432896 | 924 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 925 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
926 | return; |
927 | ||
928 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
929 | /* |
930 | * Masking an LVT entry can trigger a local APIC error | |
931 | * if the vector is zero. Mask LVTERR first to prevent this. | |
932 | */ | |
933 | if (maxlvt >= 3) { | |
934 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
935 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
936 | } | |
937 | /* | |
938 | * Careful: we have to set masks only first to deassert | |
939 | * any level-triggered sources. | |
940 | */ | |
941 | v = apic_read(APIC_LVTT); | |
942 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
943 | v = apic_read(APIC_LVT0); | |
944 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
945 | v = apic_read(APIC_LVT1); | |
946 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
947 | if (maxlvt >= 4) { | |
948 | v = apic_read(APIC_LVTPC); | |
949 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
950 | } | |
951 | ||
6764014b | 952 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 953 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
954 | if (maxlvt >= 5) { |
955 | v = apic_read(APIC_LVTTHMR); | |
956 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
957 | } | |
958 | #endif | |
5ca8681c AK |
959 | #ifdef CONFIG_X86_MCE_INTEL |
960 | if (maxlvt >= 6) { | |
961 | v = apic_read(APIC_LVTCMCI); | |
962 | if (!(v & APIC_LVT_MASKED)) | |
963 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
964 | } | |
965 | #endif | |
966 | ||
0e078e2f TG |
967 | /* |
968 | * Clean APIC state for other OSs: | |
969 | */ | |
970 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
971 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
972 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
973 | if (maxlvt >= 3) | |
974 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
975 | if (maxlvt >= 4) | |
976 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
977 | |
978 | /* Integrated APIC (!82489DX) ? */ | |
979 | if (lapic_is_integrated()) { | |
980 | if (maxlvt > 3) | |
981 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
982 | apic_write(APIC_ESR, 0); | |
983 | apic_read(APIC_ESR); | |
984 | } | |
0e078e2f TG |
985 | } |
986 | ||
987 | /** | |
988 | * disable_local_APIC - clear and disable the local APIC | |
989 | */ | |
990 | void disable_local_APIC(void) | |
991 | { | |
992 | unsigned int value; | |
993 | ||
4a13ad0b | 994 | /* APIC hasn't been mapped yet */ |
fd19dce7 | 995 | if (!x2apic_mode && !apic_phys) |
4a13ad0b JB |
996 | return; |
997 | ||
0e078e2f TG |
998 | clear_local_APIC(); |
999 | ||
1000 | /* | |
1001 | * Disable APIC (implies clearing of registers | |
1002 | * for 82489DX!). | |
1003 | */ | |
1004 | value = apic_read(APIC_SPIV); | |
1005 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1006 | apic_write(APIC_SPIV, value); | |
990b183e CG |
1007 | |
1008 | #ifdef CONFIG_X86_32 | |
1009 | /* | |
1010 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
1011 | * restore the disabled state. | |
1012 | */ | |
1013 | if (enabled_via_apicbase) { | |
1014 | unsigned int l, h; | |
1015 | ||
1016 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1017 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1018 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1019 | } | |
1020 | #endif | |
0e078e2f TG |
1021 | } |
1022 | ||
fe4024dc CG |
1023 | /* |
1024 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1025 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1026 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1027 | * for the case where Linux didn't enable the LAPIC. | |
1028 | */ | |
0e078e2f TG |
1029 | void lapic_shutdown(void) |
1030 | { | |
1031 | unsigned long flags; | |
1032 | ||
8312136f | 1033 | if (!cpu_has_apic && !apic_from_smp_config()) |
0e078e2f TG |
1034 | return; |
1035 | ||
1036 | local_irq_save(flags); | |
1037 | ||
fe4024dc CG |
1038 | #ifdef CONFIG_X86_32 |
1039 | if (!enabled_via_apicbase) | |
1040 | clear_local_APIC(); | |
1041 | else | |
1042 | #endif | |
1043 | disable_local_APIC(); | |
1044 | ||
0e078e2f TG |
1045 | |
1046 | local_irq_restore(flags); | |
1047 | } | |
1048 | ||
1049 | /* | |
1050 | * This is to verify that we're looking at a real local APIC. | |
1051 | * Check these against your board if the CPUs aren't getting | |
1052 | * started for no apparent reason. | |
1053 | */ | |
1054 | int __init verify_local_APIC(void) | |
1055 | { | |
1056 | unsigned int reg0, reg1; | |
1057 | ||
1058 | /* | |
1059 | * The version register is read-only in a real APIC. | |
1060 | */ | |
1061 | reg0 = apic_read(APIC_LVR); | |
1062 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
1063 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
1064 | reg1 = apic_read(APIC_LVR); | |
1065 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
1066 | ||
1067 | /* | |
1068 | * The two version reads above should print the same | |
1069 | * numbers. If the second one is different, then we | |
1070 | * poke at a non-APIC. | |
1071 | */ | |
1072 | if (reg1 != reg0) | |
1073 | return 0; | |
1074 | ||
1075 | /* | |
1076 | * Check if the version looks reasonably. | |
1077 | */ | |
1078 | reg1 = GET_APIC_VERSION(reg0); | |
1079 | if (reg1 == 0x00 || reg1 == 0xff) | |
1080 | return 0; | |
1081 | reg1 = lapic_get_maxlvt(); | |
1082 | if (reg1 < 0x02 || reg1 == 0xff) | |
1083 | return 0; | |
1084 | ||
1085 | /* | |
1086 | * The ID register is read/write in a real APIC. | |
1087 | */ | |
2d7a66d0 | 1088 | reg0 = apic_read(APIC_ID); |
0e078e2f | 1089 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
5b812727 | 1090 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
2d7a66d0 | 1091 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1092 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1093 | apic_write(APIC_ID, reg0); | |
5b812727 | 1094 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
0e078e2f TG |
1095 | return 0; |
1096 | ||
1097 | /* | |
1da177e4 LT |
1098 | * The next two are just to see if we have sane values. |
1099 | * They're only really relevant if we're in Virtual Wire | |
1100 | * compatibility mode, but most boxes are anymore. | |
1101 | */ | |
1102 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1103 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1104 | reg1 = apic_read(APIC_LVT1); |
1105 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1106 | ||
1107 | return 1; | |
1108 | } | |
1109 | ||
0e078e2f TG |
1110 | /** |
1111 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1112 | */ | |
1da177e4 LT |
1113 | void __init sync_Arb_IDs(void) |
1114 | { | |
296cb951 CG |
1115 | /* |
1116 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1117 | * needed on AMD. | |
1118 | */ | |
1119 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1120 | return; |
1121 | ||
1122 | /* | |
1123 | * Wait for idle. | |
1124 | */ | |
1125 | apic_wait_icr_idle(); | |
1126 | ||
1127 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1128 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1129 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1130 | } |
1131 | ||
1da177e4 LT |
1132 | /* |
1133 | * An initial setup of the virtual wire mode. | |
1134 | */ | |
1135 | void __init init_bsp_APIC(void) | |
1136 | { | |
11a8e778 | 1137 | unsigned int value; |
1da177e4 LT |
1138 | |
1139 | /* | |
1140 | * Don't do the setup now if we have a SMP BIOS as the | |
1141 | * through-I/O-APIC virtual wire mode might be active. | |
1142 | */ | |
1143 | if (smp_found_config || !cpu_has_apic) | |
1144 | return; | |
1145 | ||
1da177e4 LT |
1146 | /* |
1147 | * Do not trust the local APIC being empty at bootup. | |
1148 | */ | |
1149 | clear_local_APIC(); | |
1150 | ||
1151 | /* | |
1152 | * Enable APIC. | |
1153 | */ | |
1154 | value = apic_read(APIC_SPIV); | |
1155 | value &= ~APIC_VECTOR_MASK; | |
1156 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1157 | |
1158 | #ifdef CONFIG_X86_32 | |
1159 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1160 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1161 | (boot_cpu_data.x86 == 15)) | |
1162 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1163 | else | |
1164 | #endif | |
1165 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1166 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1167 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1168 | |
1169 | /* | |
1170 | * Set up the virtual wire mode. | |
1171 | */ | |
11a8e778 | 1172 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1173 | value = APIC_DM_NMI; |
638c0411 CG |
1174 | if (!lapic_is_integrated()) /* 82489DX */ |
1175 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1176 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1177 | } |
1178 | ||
c43da2f5 CG |
1179 | static void __cpuinit lapic_setup_esr(void) |
1180 | { | |
9df08f10 CG |
1181 | unsigned int oldvalue, value, maxlvt; |
1182 | ||
1183 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1184 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1185 | return; |
1186 | } | |
c43da2f5 | 1187 | |
08125d3e | 1188 | if (apic->disable_esr) { |
c43da2f5 | 1189 | /* |
9df08f10 CG |
1190 | * Something untraceable is creating bad interrupts on |
1191 | * secondary quads ... for the moment, just leave the | |
1192 | * ESR disabled - we can't do anything useful with the | |
1193 | * errors anyway - mbligh | |
c43da2f5 | 1194 | */ |
ba21ebb6 | 1195 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1196 | return; |
c43da2f5 | 1197 | } |
9df08f10 CG |
1198 | |
1199 | maxlvt = lapic_get_maxlvt(); | |
1200 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1201 | apic_write(APIC_ESR, 0); | |
1202 | oldvalue = apic_read(APIC_ESR); | |
1203 | ||
1204 | /* enables sending errors */ | |
1205 | value = ERROR_APIC_VECTOR; | |
1206 | apic_write(APIC_LVTERR, value); | |
1207 | ||
1208 | /* | |
1209 | * spec says clear errors after enabling vector. | |
1210 | */ | |
1211 | if (maxlvt > 3) | |
1212 | apic_write(APIC_ESR, 0); | |
1213 | value = apic_read(APIC_ESR); | |
1214 | if (value != oldvalue) | |
1215 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1216 | "vector: 0x%08x after: 0x%08x\n", | |
1217 | oldvalue, value); | |
c43da2f5 CG |
1218 | } |
1219 | ||
0e078e2f TG |
1220 | /** |
1221 | * setup_local_APIC - setup the local APIC | |
0aa002fe TH |
1222 | * |
1223 | * Used to setup local APIC while initializing BSP or bringin up APs. | |
1224 | * Always called with preemption disabled. | |
0e078e2f TG |
1225 | */ |
1226 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1227 | { |
0aa002fe | 1228 | int cpu = smp_processor_id(); |
8c3ba8d0 KJ |
1229 | unsigned int value, queued; |
1230 | int i, j, acked = 0; | |
1231 | unsigned long long tsc = 0, ntsc; | |
1232 | long long max_loops = cpu_khz; | |
1233 | ||
1234 | if (cpu_has_tsc) | |
1235 | rdtscll(tsc); | |
1da177e4 | 1236 | |
f1182638 | 1237 | if (disable_apic) { |
7167d08e | 1238 | disable_ioapic_support(); |
f1182638 JB |
1239 | return; |
1240 | } | |
1241 | ||
89c38c28 CG |
1242 | #ifdef CONFIG_X86_32 |
1243 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1244 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1245 | apic_write(APIC_ESR, 0); |
1246 | apic_write(APIC_ESR, 0); | |
1247 | apic_write(APIC_ESR, 0); | |
1248 | apic_write(APIC_ESR, 0); | |
1249 | } | |
1250 | #endif | |
cdd6c482 | 1251 | perf_events_lapic_init(); |
89c38c28 | 1252 | |
1da177e4 LT |
1253 | /* |
1254 | * Double-check whether this APIC is really registered. | |
1255 | * This is meaningless in clustered apic mode, so we skip it. | |
1256 | */ | |
c2777f98 | 1257 | BUG_ON(!apic->apic_id_registered()); |
1da177e4 LT |
1258 | |
1259 | /* | |
1260 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1261 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1262 | * document number 292116). So here it goes... | |
1263 | */ | |
a5c43296 | 1264 | apic->init_apic_ldr(); |
1da177e4 | 1265 | |
6f802c4b TH |
1266 | #ifdef CONFIG_X86_32 |
1267 | /* | |
acb8bc09 TH |
1268 | * APIC LDR is initialized. If logical_apicid mapping was |
1269 | * initialized during get_smp_config(), make sure it matches the | |
1270 | * actual value. | |
6f802c4b | 1271 | */ |
acb8bc09 TH |
1272 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
1273 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); | |
1274 | /* always use the value from LDR */ | |
6f802c4b TH |
1275 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
1276 | logical_smp_processor_id(); | |
c4b90c11 TH |
1277 | |
1278 | /* | |
1279 | * Some NUMA implementations (NUMAQ) don't initialize apicid to | |
1280 | * node mapping during NUMA init. Now that logical apicid is | |
1281 | * guaranteed to be known, give it another chance. This is already | |
1282 | * a bit too late - percpu allocation has already happened without | |
1283 | * proper NUMA affinity. | |
1284 | */ | |
84914ed0 TH |
1285 | if (apic->x86_32_numa_cpu_node) |
1286 | set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu), | |
1287 | apic->x86_32_numa_cpu_node(cpu)); | |
6f802c4b TH |
1288 | #endif |
1289 | ||
1da177e4 LT |
1290 | /* |
1291 | * Set Task Priority to 'accept all'. We never change this | |
1292 | * later on. | |
1293 | */ | |
1294 | value = apic_read(APIC_TASKPRI); | |
1295 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1296 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1297 | |
da7ed9f9 VG |
1298 | /* |
1299 | * After a crash, we no longer service the interrupts and a pending | |
1300 | * interrupt from previous kernel might still have ISR bit set. | |
1301 | * | |
1302 | * Most probably by now CPU has serviced that pending interrupt and | |
1303 | * it might not have done the ack_APIC_irq() because it thought, | |
1304 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1305 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1306 | * the interrupt. Hence a vector might get locked. It was noticed | |
1307 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1308 | */ | |
8c3ba8d0 KJ |
1309 | do { |
1310 | queued = 0; | |
1311 | for (i = APIC_ISR_NR - 1; i >= 0; i--) | |
1312 | queued |= apic_read(APIC_IRR + i*0x10); | |
1313 | ||
1314 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1315 | value = apic_read(APIC_ISR + i*0x10); | |
1316 | for (j = 31; j >= 0; j--) { | |
1317 | if (value & (1<<j)) { | |
1318 | ack_APIC_irq(); | |
1319 | acked++; | |
1320 | } | |
1321 | } | |
da7ed9f9 | 1322 | } |
8c3ba8d0 KJ |
1323 | if (acked > 256) { |
1324 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", | |
1325 | acked); | |
1326 | break; | |
1327 | } | |
1328 | if (cpu_has_tsc) { | |
1329 | rdtscll(ntsc); | |
1330 | max_loops = (cpu_khz << 10) - (ntsc - tsc); | |
1331 | } else | |
1332 | max_loops--; | |
1333 | } while (queued && max_loops > 0); | |
1334 | WARN_ON(max_loops <= 0); | |
da7ed9f9 | 1335 | |
1da177e4 LT |
1336 | /* |
1337 | * Now that we are all set up, enable the APIC | |
1338 | */ | |
1339 | value = apic_read(APIC_SPIV); | |
1340 | value &= ~APIC_VECTOR_MASK; | |
1341 | /* | |
1342 | * Enable APIC | |
1343 | */ | |
1344 | value |= APIC_SPIV_APIC_ENABLED; | |
1345 | ||
89c38c28 CG |
1346 | #ifdef CONFIG_X86_32 |
1347 | /* | |
1348 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1349 | * certain networking cards. If high frequency interrupts are | |
1350 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1351 | * entry is masked/unmasked at a high rate as well then sooner or | |
1352 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1353 | * from the device. If focus CPU is disabled then the hang goes | |
1354 | * away, oh well :-( | |
1355 | * | |
1356 | * [ This bug can be reproduced easily with a level-triggered | |
1357 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1358 | * BX chipset. ] | |
1359 | */ | |
1360 | /* | |
1361 | * Actually disabling the focus CPU check just makes the hang less | |
1362 | * frequent as it makes the interrupt distributon model be more | |
1363 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1364 | * See also the comment in end_level_ioapic_irq(). --macro | |
1365 | */ | |
1366 | ||
1367 | /* | |
1368 | * - enable focus processor (bit==0) | |
1369 | * - 64bit mode always use processor focus | |
1370 | * so no need to set it | |
1371 | */ | |
1372 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1373 | #endif | |
3f14c746 | 1374 | |
1da177e4 LT |
1375 | /* |
1376 | * Set spurious IRQ vector | |
1377 | */ | |
1378 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1379 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1380 | |
1381 | /* | |
1382 | * Set up LVT0, LVT1: | |
1383 | * | |
1384 | * set up through-local-APIC on the BP's LINT0. This is not | |
1385 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1386 | * we delegate interrupts to the 8259A. | |
1387 | */ | |
1388 | /* | |
1389 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1390 | */ | |
1391 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
0aa002fe | 1392 | if (!cpu && (pic_mode || !value)) { |
1da177e4 | 1393 | value = APIC_DM_EXTINT; |
0aa002fe | 1394 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1395 | } else { |
1396 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
0aa002fe | 1397 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1398 | } |
11a8e778 | 1399 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1400 | |
1401 | /* | |
1402 | * only the BP should see the LINT1 NMI signal, obviously. | |
1403 | */ | |
0aa002fe | 1404 | if (!cpu) |
1da177e4 LT |
1405 | value = APIC_DM_NMI; |
1406 | else | |
1407 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1408 | if (!lapic_is_integrated()) /* 82489DX */ |
1409 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1410 | apic_write(APIC_LVT1, value); |
89c38c28 | 1411 | |
be71b855 AK |
1412 | #ifdef CONFIG_X86_MCE_INTEL |
1413 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1414 | if (!cpu) |
be71b855 AK |
1415 | cmci_recheck(); |
1416 | #endif | |
739f33b3 | 1417 | } |
1da177e4 | 1418 | |
739f33b3 AK |
1419 | void __cpuinit end_local_APIC_setup(void) |
1420 | { | |
1421 | lapic_setup_esr(); | |
fa6b95fc CG |
1422 | |
1423 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1424 | { |
1425 | unsigned int value; | |
1426 | /* Disable the local apic timer */ | |
1427 | value = apic_read(APIC_LVTT); | |
1428 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1429 | apic_write(APIC_LVTT, value); | |
1430 | } | |
fa6b95fc CG |
1431 | #endif |
1432 | ||
0e078e2f | 1433 | apic_pm_activate(); |
2fb270f3 JB |
1434 | } |
1435 | ||
1436 | void __init bsp_end_local_APIC_setup(void) | |
1437 | { | |
1438 | end_local_APIC_setup(); | |
7f7fbf45 KK |
1439 | |
1440 | /* | |
1441 | * Now that local APIC setup is completed for BP, configure the fault | |
1442 | * handling for interrupt remapping. | |
1443 | */ | |
2fb270f3 | 1444 | if (intr_remapping_enabled) |
7f7fbf45 KK |
1445 | enable_drhd_fault_handling(); |
1446 | ||
1da177e4 | 1447 | } |
1da177e4 | 1448 | |
06cd9a7d | 1449 | #ifdef CONFIG_X86_X2APIC |
fb209bd8 YL |
1450 | /* |
1451 | * Need to disable xapic and x2apic at the same time and then enable xapic mode | |
1452 | */ | |
1453 | static inline void __disable_x2apic(u64 msr) | |
1454 | { | |
1455 | wrmsrl(MSR_IA32_APICBASE, | |
1456 | msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1457 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1458 | } | |
1459 | ||
a31bc327 | 1460 | static __init void disable_x2apic(void) |
fb209bd8 YL |
1461 | { |
1462 | u64 msr; | |
1463 | ||
1464 | if (!cpu_has_x2apic) | |
1465 | return; | |
1466 | ||
1467 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1468 | if (msr & X2APIC_ENABLE) { | |
1469 | u32 x2apic_id = read_apic_id(); | |
1470 | ||
1471 | if (x2apic_id >= 255) | |
1472 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
1473 | ||
1474 | pr_info("Disabling x2apic\n"); | |
1475 | __disable_x2apic(msr); | |
1476 | ||
a31bc327 YL |
1477 | if (nox2apic) { |
1478 | clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC); | |
1479 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
1480 | } | |
1481 | ||
fb209bd8 YL |
1482 | x2apic_disabled = 1; |
1483 | x2apic_mode = 0; | |
1484 | ||
1485 | register_lapic_address(mp_lapic_addr); | |
1486 | } | |
1487 | } | |
1488 | ||
6e1cb38a SS |
1489 | void check_x2apic(void) |
1490 | { | |
ef1f87aa | 1491 | if (x2apic_enabled()) { |
ba21ebb6 | 1492 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
fc1edaf9 | 1493 | x2apic_preenabled = x2apic_mode = 1; |
6e1cb38a SS |
1494 | } |
1495 | } | |
1496 | ||
1497 | void enable_x2apic(void) | |
1498 | { | |
fb209bd8 YL |
1499 | u64 msr; |
1500 | ||
1501 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1502 | if (x2apic_disabled) { | |
1503 | __disable_x2apic(msr); | |
1504 | return; | |
1505 | } | |
6e1cb38a | 1506 | |
fc1edaf9 | 1507 | if (!x2apic_mode) |
06cd9a7d YL |
1508 | return; |
1509 | ||
6e1cb38a | 1510 | if (!(msr & X2APIC_ENABLE)) { |
450b1e8d | 1511 | printk_once(KERN_INFO "Enabling x2apic\n"); |
fb209bd8 | 1512 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); |
6e1cb38a SS |
1513 | } |
1514 | } | |
93758238 | 1515 | #endif /* CONFIG_X86_X2APIC */ |
6e1cb38a | 1516 | |
ce69a784 | 1517 | int __init enable_IR(void) |
6e1cb38a | 1518 | { |
d3f13810 | 1519 | #ifdef CONFIG_IRQ_REMAP |
93758238 WH |
1520 | if (!intr_remapping_supported()) { |
1521 | pr_debug("intr-remapping not supported\n"); | |
41750d31 | 1522 | return -1; |
6e1cb38a SS |
1523 | } |
1524 | ||
93758238 WH |
1525 | if (!x2apic_preenabled && skip_ioapic_setup) { |
1526 | pr_info("Skipped enabling intr-remap because of skipping " | |
1527 | "io-apic setup\n"); | |
41750d31 | 1528 | return -1; |
6e1cb38a SS |
1529 | } |
1530 | ||
41750d31 | 1531 | return enable_intr_remapping(); |
ce69a784 | 1532 | #endif |
41750d31 | 1533 | return -1; |
ce69a784 GN |
1534 | } |
1535 | ||
1536 | void __init enable_IR_x2apic(void) | |
1537 | { | |
1538 | unsigned long flags; | |
ce69a784 | 1539 | int ret, x2apic_enabled = 0; |
e670761f | 1540 | int dmar_table_init_ret; |
b7f42ab2 | 1541 | |
b7f42ab2 | 1542 | dmar_table_init_ret = dmar_table_init(); |
e670761f YL |
1543 | if (dmar_table_init_ret && !x2apic_supported()) |
1544 | return; | |
ce69a784 | 1545 | |
31dce14a | 1546 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1547 | if (ret) { |
ba21ebb6 | 1548 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1549 | return; |
5ffa4eb2 | 1550 | } |
6e1cb38a | 1551 | |
05c3dc2c | 1552 | local_irq_save(flags); |
b81bb373 | 1553 | legacy_pic->mask_all(); |
31dce14a | 1554 | mask_ioapic_entries(); |
05c3dc2c | 1555 | |
a31bc327 YL |
1556 | if (x2apic_preenabled && nox2apic) |
1557 | disable_x2apic(); | |
1558 | ||
b7f42ab2 | 1559 | if (dmar_table_init_ret) |
41750d31 | 1560 | ret = -1; |
b7f42ab2 YL |
1561 | else |
1562 | ret = enable_IR(); | |
1563 | ||
fb209bd8 | 1564 | if (!x2apic_supported()) |
a31bc327 | 1565 | goto skip_x2apic; |
fb209bd8 | 1566 | |
41750d31 | 1567 | if (ret < 0) { |
ce69a784 GN |
1568 | /* IR is required if there is APIC ID > 255 even when running |
1569 | * under KVM | |
1570 | */ | |
2904ed8d | 1571 | if (max_physical_apicid > 255 || |
fb209bd8 YL |
1572 | !hypervisor_x2apic_available()) { |
1573 | if (x2apic_preenabled) | |
1574 | disable_x2apic(); | |
a31bc327 | 1575 | goto skip_x2apic; |
fb209bd8 | 1576 | } |
ce69a784 GN |
1577 | /* |
1578 | * without IR all CPUs can be addressed by IOAPIC/MSI | |
1579 | * only in physical mode | |
1580 | */ | |
1581 | x2apic_force_phys(); | |
1582 | } | |
6e1cb38a | 1583 | |
fb209bd8 YL |
1584 | if (ret == IRQ_REMAP_XAPIC_MODE) { |
1585 | pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n"); | |
a31bc327 | 1586 | goto skip_x2apic; |
fb209bd8 | 1587 | } |
41750d31 | 1588 | |
ce69a784 | 1589 | x2apic_enabled = 1; |
93758238 | 1590 | |
fc1edaf9 SS |
1591 | if (x2apic_supported() && !x2apic_mode) { |
1592 | x2apic_mode = 1; | |
6e1cb38a | 1593 | enable_x2apic(); |
93758238 | 1594 | pr_info("Enabled x2apic\n"); |
6e1cb38a | 1595 | } |
5ffa4eb2 | 1596 | |
a31bc327 | 1597 | skip_x2apic: |
41750d31 | 1598 | if (ret < 0) /* IR enabling failed */ |
31dce14a | 1599 | restore_ioapic_entries(); |
b81bb373 | 1600 | legacy_pic->restore_mask(); |
6e1cb38a | 1601 | local_irq_restore(flags); |
6e1cb38a | 1602 | } |
93758238 | 1603 | |
be7a656f | 1604 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1605 | /* |
1606 | * Detect and enable local APICs on non-SMP boards. | |
1607 | * Original code written by Keir Fraser. | |
1608 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1609 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1610 | */ |
0e078e2f | 1611 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1612 | { |
1613 | if (!cpu_has_apic) { | |
ba21ebb6 | 1614 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1615 | return -1; |
1616 | } | |
1617 | ||
1618 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
1619 | return 0; |
1620 | } | |
be7a656f | 1621 | #else |
5a7ae78f | 1622 | |
25874a29 | 1623 | static int __init apic_verify(void) |
5a7ae78f TG |
1624 | { |
1625 | u32 features, h, l; | |
1626 | ||
1627 | /* | |
1628 | * The APIC feature bit should now be enabled | |
1629 | * in `cpuid' | |
1630 | */ | |
1631 | features = cpuid_edx(1); | |
1632 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
1633 | pr_warning("Could not enable APIC!\n"); | |
1634 | return -1; | |
1635 | } | |
1636 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1637 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1638 | ||
1639 | /* The BIOS may have set up the APIC at some other address */ | |
cbf2829b BD |
1640 | if (boot_cpu_data.x86 >= 6) { |
1641 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1642 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1643 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1644 | } | |
5a7ae78f TG |
1645 | |
1646 | pr_info("Found and enabled local APIC!\n"); | |
1647 | return 0; | |
1648 | } | |
1649 | ||
25874a29 | 1650 | int __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
1651 | { |
1652 | u32 h, l; | |
1653 | ||
1654 | if (disable_apic) | |
1655 | return -1; | |
1656 | ||
1657 | /* | |
1658 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1659 | * MSR. This can only be done in software for Intel P6 or later | |
1660 | * and AMD K7 (Model > 1) or later. | |
1661 | */ | |
cbf2829b BD |
1662 | if (boot_cpu_data.x86 >= 6) { |
1663 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1664 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1665 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
1666 | l &= ~MSR_IA32_APICBASE_BASE; | |
1667 | l |= MSR_IA32_APICBASE_ENABLE | addr; | |
1668 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1669 | enabled_via_apicbase = 1; | |
1670 | } | |
5a7ae78f TG |
1671 | } |
1672 | return apic_verify(); | |
1673 | } | |
1674 | ||
be7a656f YL |
1675 | /* |
1676 | * Detect and initialize APIC | |
1677 | */ | |
1678 | static int __init detect_init_APIC(void) | |
1679 | { | |
be7a656f YL |
1680 | /* Disabled by kernel option? */ |
1681 | if (disable_apic) | |
1682 | return -1; | |
1683 | ||
1684 | switch (boot_cpu_data.x86_vendor) { | |
1685 | case X86_VENDOR_AMD: | |
1686 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1687 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1688 | break; |
1689 | goto no_apic; | |
1690 | case X86_VENDOR_INTEL: | |
1691 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1692 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1693 | break; | |
1694 | goto no_apic; | |
1695 | default: | |
1696 | goto no_apic; | |
1697 | } | |
1698 | ||
1699 | if (!cpu_has_apic) { | |
1700 | /* | |
1701 | * Over-ride BIOS and try to enable the local APIC only if | |
1702 | * "lapic" specified. | |
1703 | */ | |
1704 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1705 | pr_info("Local APIC disabled by BIOS -- " |
1706 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1707 | return -1; |
1708 | } | |
a906fdaa | 1709 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
5a7ae78f TG |
1710 | return -1; |
1711 | } else { | |
1712 | if (apic_verify()) | |
1713 | return -1; | |
be7a656f | 1714 | } |
be7a656f YL |
1715 | |
1716 | apic_pm_activate(); | |
1717 | ||
1718 | return 0; | |
1719 | ||
1720 | no_apic: | |
ba21ebb6 | 1721 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1722 | return -1; |
1723 | } | |
1724 | #endif | |
1da177e4 | 1725 | |
0e078e2f TG |
1726 | /** |
1727 | * init_apic_mappings - initialize APIC mappings | |
1728 | */ | |
1da177e4 LT |
1729 | void __init init_apic_mappings(void) |
1730 | { | |
4401da61 YL |
1731 | unsigned int new_apicid; |
1732 | ||
fc1edaf9 | 1733 | if (x2apic_mode) { |
4c9961d5 | 1734 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1735 | return; |
1736 | } | |
1737 | ||
4797f6b0 | 1738 | /* If no local APIC can be found return early */ |
1da177e4 | 1739 | if (!smp_found_config && detect_init_APIC()) { |
4797f6b0 YL |
1740 | /* lets NOP'ify apic operations */ |
1741 | pr_info("APIC: disable apic facility\n"); | |
1742 | apic_disable(); | |
1743 | } else { | |
1da177e4 LT |
1744 | apic_phys = mp_lapic_addr; |
1745 | ||
4797f6b0 YL |
1746 | /* |
1747 | * acpi lapic path already maps that address in | |
1748 | * acpi_register_lapic_address() | |
1749 | */ | |
5989cd6a | 1750 | if (!acpi_lapic && !smp_found_config) |
326a2e6b | 1751 | register_lapic_address(apic_phys); |
cec6be6d | 1752 | } |
1da177e4 LT |
1753 | |
1754 | /* | |
1755 | * Fetch the APIC ID of the BSP in case we have a | |
1756 | * default configuration (or the MP table is broken). | |
1757 | */ | |
4401da61 YL |
1758 | new_apicid = read_apic_id(); |
1759 | if (boot_cpu_physical_apicid != new_apicid) { | |
1760 | boot_cpu_physical_apicid = new_apicid; | |
103428e5 CG |
1761 | /* |
1762 | * yeah -- we lie about apic_version | |
1763 | * in case if apic was disabled via boot option | |
1764 | * but it's not a problem for SMP compiled kernel | |
1765 | * since smp_sanity_check is prepared for such a case | |
1766 | * and disable smp mode | |
1767 | */ | |
4401da61 YL |
1768 | apic_version[new_apicid] = |
1769 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
08306ce6 | 1770 | } |
1da177e4 LT |
1771 | } |
1772 | ||
c0104d38 YL |
1773 | void __init register_lapic_address(unsigned long address) |
1774 | { | |
1775 | mp_lapic_addr = address; | |
1776 | ||
0450193b YL |
1777 | if (!x2apic_mode) { |
1778 | set_fixmap_nocache(FIX_APIC_BASE, address); | |
1779 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
1780 | APIC_BASE, mp_lapic_addr); | |
1781 | } | |
c0104d38 YL |
1782 | if (boot_cpu_physical_apicid == -1U) { |
1783 | boot_cpu_physical_apicid = read_apic_id(); | |
1784 | apic_version[boot_cpu_physical_apicid] = | |
1785 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
1786 | } | |
1787 | } | |
1788 | ||
1da177e4 | 1789 | /* |
0e078e2f TG |
1790 | * This initializes the IO-APIC and APIC hardware if this is |
1791 | * a UP kernel. | |
1da177e4 | 1792 | */ |
56d91f13 | 1793 | int apic_version[MAX_LOCAL_APIC]; |
1b313f4a | 1794 | |
0e078e2f | 1795 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1796 | { |
0e078e2f | 1797 | if (disable_apic) { |
ba21ebb6 | 1798 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1799 | return -1; |
1800 | } | |
f1182638 | 1801 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1802 | if (!cpu_has_apic) { |
1803 | disable_apic = 1; | |
ba21ebb6 | 1804 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1805 | return -1; |
1806 | } | |
fa2bd35a YL |
1807 | #else |
1808 | if (!smp_found_config && !cpu_has_apic) | |
1809 | return -1; | |
1810 | ||
1811 | /* | |
1812 | * Complain if the BIOS pretends there is one. | |
1813 | */ | |
1814 | if (!cpu_has_apic && | |
1815 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1816 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1817 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1818 | return -1; |
1819 | } | |
1820 | #endif | |
1821 | ||
72ce0165 | 1822 | default_setup_apic_routing(); |
6e1cb38a | 1823 | |
0e078e2f | 1824 | verify_local_APIC(); |
b5841765 GC |
1825 | connect_bsp_APIC(); |
1826 | ||
fa2bd35a | 1827 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1828 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1829 | #else |
1830 | /* | |
1831 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1832 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1833 | * might be zero if read from MP tables. Get it from LAPIC. | |
1834 | */ | |
1835 | # ifdef CONFIG_CRASH_DUMP | |
1836 | boot_cpu_physical_apicid = read_apic_id(); | |
1837 | # endif | |
1838 | #endif | |
1839 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1840 | setup_local_APIC(); |
1da177e4 | 1841 | |
88d0f550 | 1842 | #ifdef CONFIG_X86_IO_APIC |
739f33b3 AK |
1843 | /* |
1844 | * Now enable IO-APICs, actually call clear_IO_APIC | |
98c061b6 | 1845 | * We need clear_IO_APIC before enabling error vector |
739f33b3 AK |
1846 | */ |
1847 | if (!skip_ioapic_setup && nr_ioapics) | |
1848 | enable_IO_APIC(); | |
fa2bd35a | 1849 | #endif |
739f33b3 | 1850 | |
2fb270f3 | 1851 | bsp_end_local_APIC_setup(); |
739f33b3 | 1852 | |
fa2bd35a | 1853 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1854 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1855 | setup_IO_APIC(); | |
98c061b6 | 1856 | else { |
0e078e2f | 1857 | nr_ioapics = 0; |
98c061b6 | 1858 | } |
fa2bd35a YL |
1859 | #endif |
1860 | ||
736decac | 1861 | x86_init.timers.setup_percpu_clockev(); |
0e078e2f | 1862 | return 0; |
1da177e4 LT |
1863 | } |
1864 | ||
1865 | /* | |
0e078e2f | 1866 | * Local APIC interrupts |
1da177e4 LT |
1867 | */ |
1868 | ||
0e078e2f TG |
1869 | /* |
1870 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1871 | */ | |
dc1528dd | 1872 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1873 | { |
dc1528dd YL |
1874 | u32 v; |
1875 | ||
0e078e2f | 1876 | irq_enter(); |
98ad1cc1 | 1877 | exit_idle(); |
1da177e4 | 1878 | /* |
0e078e2f TG |
1879 | * Check if this really is a spurious interrupt and ACK it |
1880 | * if it is a vectored one. Just in case... | |
1881 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1882 | */ |
0e078e2f TG |
1883 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1884 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1885 | ack_APIC_irq(); | |
c4d58cbd | 1886 | |
915b0d01 HS |
1887 | inc_irq_stat(irq_spurious_count); |
1888 | ||
dc1528dd | 1889 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1890 | pr_info("spurious APIC interrupt on CPU#%d, " |
1891 | "should never happen.\n", smp_processor_id()); | |
0e078e2f TG |
1892 | irq_exit(); |
1893 | } | |
1da177e4 | 1894 | |
0e078e2f TG |
1895 | /* |
1896 | * This interrupt should never happen with our APIC/SMP architecture | |
1897 | */ | |
dc1528dd | 1898 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1899 | { |
2b398bd9 YS |
1900 | u32 v0, v1; |
1901 | u32 i = 0; | |
1902 | static const char * const error_interrupt_reason[] = { | |
1903 | "Send CS error", /* APIC Error Bit 0 */ | |
1904 | "Receive CS error", /* APIC Error Bit 1 */ | |
1905 | "Send accept error", /* APIC Error Bit 2 */ | |
1906 | "Receive accept error", /* APIC Error Bit 3 */ | |
1907 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
1908 | "Send illegal vector", /* APIC Error Bit 5 */ | |
1909 | "Received illegal vector", /* APIC Error Bit 6 */ | |
1910 | "Illegal register address", /* APIC Error Bit 7 */ | |
1911 | }; | |
1da177e4 | 1912 | |
0e078e2f | 1913 | irq_enter(); |
98ad1cc1 | 1914 | exit_idle(); |
0e078e2f | 1915 | /* First tickle the hardware, only then report what went on. -- REW */ |
2b398bd9 | 1916 | v0 = apic_read(APIC_ESR); |
0e078e2f TG |
1917 | apic_write(APIC_ESR, 0); |
1918 | v1 = apic_read(APIC_ESR); | |
1919 | ack_APIC_irq(); | |
1920 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1921 | |
2b398bd9 YS |
1922 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)", |
1923 | smp_processor_id(), v0 , v1); | |
1924 | ||
1925 | v1 = v1 & 0xff; | |
1926 | while (v1) { | |
1927 | if (v1 & 0x1) | |
1928 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); | |
1929 | i++; | |
1930 | v1 >>= 1; | |
1931 | }; | |
1932 | ||
1933 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); | |
1934 | ||
0e078e2f | 1935 | irq_exit(); |
1da177e4 LT |
1936 | } |
1937 | ||
b5841765 | 1938 | /** |
36c9d674 CG |
1939 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1940 | */ | |
b5841765 GC |
1941 | void __init connect_bsp_APIC(void) |
1942 | { | |
36c9d674 CG |
1943 | #ifdef CONFIG_X86_32 |
1944 | if (pic_mode) { | |
1945 | /* | |
1946 | * Do not trust the local APIC being empty at bootup. | |
1947 | */ | |
1948 | clear_local_APIC(); | |
1949 | /* | |
1950 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1951 | * local APIC to INT and NMI lines. | |
1952 | */ | |
1953 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1954 | "enabling APIC mode.\n"); | |
c0eaa453 | 1955 | imcr_pic_to_apic(); |
36c9d674 CG |
1956 | } |
1957 | #endif | |
49040333 IM |
1958 | if (apic->enable_apic_mode) |
1959 | apic->enable_apic_mode(); | |
b5841765 GC |
1960 | } |
1961 | ||
274cfe59 CG |
1962 | /** |
1963 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1964 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1965 | * | |
1966 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1967 | * APIC is disabled. | |
1968 | */ | |
0e078e2f | 1969 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1970 | { |
1b4ee4e4 CG |
1971 | unsigned int value; |
1972 | ||
c177b0bc CG |
1973 | #ifdef CONFIG_X86_32 |
1974 | if (pic_mode) { | |
1975 | /* | |
1976 | * Put the board back into PIC mode (has an effect only on | |
1977 | * certain older boards). Note that APIC interrupts, including | |
1978 | * IPIs, won't work beyond this point! The only exception are | |
1979 | * INIT IPIs. | |
1980 | */ | |
1981 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1982 | "entering PIC mode.\n"); | |
c0eaa453 | 1983 | imcr_apic_to_pic(); |
c177b0bc CG |
1984 | return; |
1985 | } | |
1986 | #endif | |
1987 | ||
0e078e2f | 1988 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1989 | |
0e078e2f TG |
1990 | /* For the spurious interrupt use vector F, and enable it */ |
1991 | value = apic_read(APIC_SPIV); | |
1992 | value &= ~APIC_VECTOR_MASK; | |
1993 | value |= APIC_SPIV_APIC_ENABLED; | |
1994 | value |= 0xf; | |
1995 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1996 | |
0e078e2f TG |
1997 | if (!virt_wire_setup) { |
1998 | /* | |
1999 | * For LVT0 make it edge triggered, active high, | |
2000 | * external and enabled | |
2001 | */ | |
2002 | value = apic_read(APIC_LVT0); | |
2003 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2004 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2005 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2006 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2007 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
2008 | apic_write(APIC_LVT0, value); | |
2009 | } else { | |
2010 | /* Disable LVT0 */ | |
2011 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
2012 | } | |
b8ce3359 | 2013 | |
c177b0bc CG |
2014 | /* |
2015 | * For LVT1 make it edge triggered, active high, | |
2016 | * nmi and enabled | |
2017 | */ | |
0e078e2f TG |
2018 | value = apic_read(APIC_LVT1); |
2019 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
2020 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
2021 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
2022 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
2023 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
2024 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
2025 | } |
2026 | ||
be8a5685 AS |
2027 | void __cpuinit generic_processor_info(int apicid, int version) |
2028 | { | |
14cb6dcf VG |
2029 | int cpu, max = nr_cpu_ids; |
2030 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, | |
2031 | phys_cpu_present_map); | |
2032 | ||
2033 | /* | |
2034 | * If boot cpu has not been detected yet, then only allow upto | |
2035 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu | |
2036 | */ | |
2037 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && | |
2038 | apicid != boot_cpu_physical_apicid) { | |
2039 | int thiscpu = max + disabled_cpus - 1; | |
2040 | ||
2041 | pr_warning( | |
2042 | "ACPI: NR_CPUS/possible_cpus limit of %i almost" | |
2043 | " reached. Keeping one slot for boot cpu." | |
2044 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2045 | ||
2046 | disabled_cpus++; | |
2047 | return; | |
2048 | } | |
be8a5685 | 2049 | |
3b11ce7f | 2050 | if (num_processors >= nr_cpu_ids) { |
3b11ce7f MT |
2051 | int thiscpu = max + disabled_cpus; |
2052 | ||
2053 | pr_warning( | |
2054 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
2055 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2056 | ||
2057 | disabled_cpus++; | |
be8a5685 AS |
2058 | return; |
2059 | } | |
2060 | ||
2061 | num_processors++; | |
be8a5685 AS |
2062 | if (apicid == boot_cpu_physical_apicid) { |
2063 | /* | |
2064 | * x86_bios_cpu_apicid is required to have processors listed | |
2065 | * in same order as logical cpu numbers. Hence the first | |
2066 | * entry is BSP, and so on. | |
e5fea868 YL |
2067 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
2068 | * for BSP. | |
be8a5685 AS |
2069 | */ |
2070 | cpu = 0; | |
e5fea868 YL |
2071 | } else |
2072 | cpu = cpumask_next_zero(-1, cpu_present_mask); | |
2073 | ||
2074 | /* | |
2075 | * Validate version | |
2076 | */ | |
2077 | if (version == 0x0) { | |
2078 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", | |
2079 | cpu, apicid); | |
2080 | version = 0x10; | |
be8a5685 | 2081 | } |
e5fea868 YL |
2082 | apic_version[apicid] = version; |
2083 | ||
2084 | if (version != apic_version[boot_cpu_physical_apicid]) { | |
2085 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", | |
2086 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
2087 | } | |
2088 | ||
2089 | physid_set(apicid, phys_cpu_present_map); | |
e0da3364 YL |
2090 | if (apicid > max_physical_apicid) |
2091 | max_physical_apicid = apicid; | |
2092 | ||
3e5095d1 | 2093 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
2094 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
2095 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 2096 | #endif |
acb8bc09 TH |
2097 | #ifdef CONFIG_X86_32 |
2098 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = | |
2099 | apic->x86_32_early_logical_apicid(cpu); | |
2100 | #endif | |
1de88cd4 MT |
2101 | set_cpu_possible(cpu, true); |
2102 | set_cpu_present(cpu, true); | |
be8a5685 AS |
2103 | } |
2104 | ||
0c81c746 SS |
2105 | int hard_smp_processor_id(void) |
2106 | { | |
2107 | return read_apic_id(); | |
2108 | } | |
1dcdd3d1 IM |
2109 | |
2110 | void default_init_apic_ldr(void) | |
2111 | { | |
2112 | unsigned long val; | |
2113 | ||
2114 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
2115 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
2116 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
2117 | apic_write(APIC_LDR, val); | |
2118 | } | |
2119 | ||
89039b37 | 2120 | /* |
0e078e2f | 2121 | * Power management |
89039b37 | 2122 | */ |
0e078e2f TG |
2123 | #ifdef CONFIG_PM |
2124 | ||
2125 | static struct { | |
274cfe59 CG |
2126 | /* |
2127 | * 'active' is true if the local APIC was enabled by us and | |
2128 | * not the BIOS; this signifies that we are also responsible | |
2129 | * for disabling it before entering apm/acpi suspend | |
2130 | */ | |
0e078e2f TG |
2131 | int active; |
2132 | /* r/w apic fields */ | |
2133 | unsigned int apic_id; | |
2134 | unsigned int apic_taskpri; | |
2135 | unsigned int apic_ldr; | |
2136 | unsigned int apic_dfr; | |
2137 | unsigned int apic_spiv; | |
2138 | unsigned int apic_lvtt; | |
2139 | unsigned int apic_lvtpc; | |
2140 | unsigned int apic_lvt0; | |
2141 | unsigned int apic_lvt1; | |
2142 | unsigned int apic_lvterr; | |
2143 | unsigned int apic_tmict; | |
2144 | unsigned int apic_tdcr; | |
2145 | unsigned int apic_thmr; | |
2146 | } apic_pm_state; | |
2147 | ||
f3c6ea1b | 2148 | static int lapic_suspend(void) |
0e078e2f TG |
2149 | { |
2150 | unsigned long flags; | |
2151 | int maxlvt; | |
89039b37 | 2152 | |
0e078e2f TG |
2153 | if (!apic_pm_state.active) |
2154 | return 0; | |
89039b37 | 2155 | |
0e078e2f | 2156 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2157 | |
2d7a66d0 | 2158 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2159 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2160 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2161 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2162 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2163 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2164 | if (maxlvt >= 4) | |
2165 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2166 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2167 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2168 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2169 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2170 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2171 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2172 | if (maxlvt >= 5) |
2173 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2174 | #endif | |
24968cfd | 2175 | |
0e078e2f TG |
2176 | local_irq_save(flags); |
2177 | disable_local_APIC(); | |
fc1edaf9 | 2178 | |
b24696bc FY |
2179 | if (intr_remapping_enabled) |
2180 | disable_intr_remapping(); | |
fc1edaf9 | 2181 | |
0e078e2f TG |
2182 | local_irq_restore(flags); |
2183 | return 0; | |
1da177e4 LT |
2184 | } |
2185 | ||
f3c6ea1b | 2186 | static void lapic_resume(void) |
1da177e4 | 2187 | { |
0e078e2f TG |
2188 | unsigned int l, h; |
2189 | unsigned long flags; | |
31dce14a | 2190 | int maxlvt; |
b24696bc | 2191 | |
0e078e2f | 2192 | if (!apic_pm_state.active) |
f3c6ea1b | 2193 | return; |
89b831ef | 2194 | |
0e078e2f | 2195 | local_irq_save(flags); |
9a2755c3 | 2196 | if (intr_remapping_enabled) { |
31dce14a SS |
2197 | /* |
2198 | * IO-APIC and PIC have their own resume routines. | |
2199 | * We just mask them here to make sure the interrupt | |
2200 | * subsystem is completely quiet while we enable x2apic | |
2201 | * and interrupt-remapping. | |
2202 | */ | |
2203 | mask_ioapic_entries(); | |
b81bb373 | 2204 | legacy_pic->mask_all(); |
b24696bc | 2205 | } |
92206c90 | 2206 | |
fc1edaf9 | 2207 | if (x2apic_mode) |
92206c90 | 2208 | enable_x2apic(); |
cf6567fe | 2209 | else { |
92206c90 CG |
2210 | /* |
2211 | * Make sure the APICBASE points to the right address | |
2212 | * | |
2213 | * FIXME! This will be wrong if we ever support suspend on | |
2214 | * SMP! We'll need to do this as part of the CPU restore! | |
2215 | */ | |
cbf2829b BD |
2216 | if (boot_cpu_data.x86 >= 6) { |
2217 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2218 | l &= ~MSR_IA32_APICBASE_BASE; | |
2219 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2220 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2221 | } | |
d5e629a6 | 2222 | } |
6e1cb38a | 2223 | |
b24696bc | 2224 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2225 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2226 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2227 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2228 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2229 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2230 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2231 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2232 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2233 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2234 | if (maxlvt >= 5) |
2235 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2236 | #endif | |
2237 | if (maxlvt >= 4) | |
2238 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2239 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2240 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2241 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2242 | apic_write(APIC_ESR, 0); | |
2243 | apic_read(APIC_ESR); | |
2244 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2245 | apic_write(APIC_ESR, 0); | |
2246 | apic_read(APIC_ESR); | |
92206c90 | 2247 | |
31dce14a | 2248 | if (intr_remapping_enabled) |
fc1edaf9 | 2249 | reenable_intr_remapping(x2apic_mode); |
31dce14a | 2250 | |
0e078e2f | 2251 | local_irq_restore(flags); |
0e078e2f | 2252 | } |
b8ce3359 | 2253 | |
274cfe59 CG |
2254 | /* |
2255 | * This device has no shutdown method - fully functioning local APICs | |
2256 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2257 | */ | |
2258 | ||
f3c6ea1b | 2259 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2260 | .resume = lapic_resume, |
2261 | .suspend = lapic_suspend, | |
2262 | }; | |
b8ce3359 | 2263 | |
0e078e2f TG |
2264 | static void __cpuinit apic_pm_activate(void) |
2265 | { | |
2266 | apic_pm_state.active = 1; | |
1da177e4 LT |
2267 | } |
2268 | ||
0e078e2f | 2269 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2270 | { |
0e078e2f | 2271 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
f3c6ea1b RW |
2272 | if (cpu_has_apic) |
2273 | register_syscore_ops(&lapic_syscore_ops); | |
e83a5fdc | 2274 | |
f3c6ea1b | 2275 | return 0; |
1da177e4 | 2276 | } |
b24696bc FY |
2277 | |
2278 | /* local apic needs to resume before other devices access its registers. */ | |
2279 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2280 | |
2281 | #else /* CONFIG_PM */ | |
2282 | ||
2283 | static void apic_pm_activate(void) { } | |
2284 | ||
2285 | #endif /* CONFIG_PM */ | |
1da177e4 | 2286 | |
f28c0ae2 | 2287 | #ifdef CONFIG_X86_64 |
e0e42142 YL |
2288 | |
2289 | static int __cpuinit apic_cluster_num(void) | |
1da177e4 LT |
2290 | { |
2291 | int i, clusters, zeros; | |
2292 | unsigned id; | |
322850af | 2293 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2294 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2295 | ||
23ca4bba | 2296 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2297 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2298 | |
168ef543 | 2299 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2300 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2301 | if (bios_cpu_apicid) { |
2302 | id = bios_cpu_apicid[i]; | |
e423e33e | 2303 | } else if (i < nr_cpu_ids) { |
e8c10ef9 | 2304 | if (cpu_present(i)) |
2305 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2306 | else | |
2307 | continue; | |
e423e33e | 2308 | } else |
e8c10ef9 | 2309 | break; |
2310 | ||
1da177e4 LT |
2311 | if (id != BAD_APICID) |
2312 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2313 | } | |
2314 | ||
2315 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2316 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2317 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2318 | * Since clusters are allocated sequentially, count zeros only if | |
2319 | * they are bounded by ones. | |
1da177e4 LT |
2320 | */ |
2321 | clusters = 0; | |
2322 | zeros = 0; | |
2323 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2324 | if (test_bit(i, clustermap)) { | |
2325 | clusters += 1 + zeros; | |
2326 | zeros = 0; | |
2327 | } else | |
2328 | ++zeros; | |
2329 | } | |
2330 | ||
e0e42142 YL |
2331 | return clusters; |
2332 | } | |
2333 | ||
2334 | static int __cpuinitdata multi_checked; | |
2335 | static int __cpuinitdata multi; | |
2336 | ||
2337 | static int __cpuinit set_multi(const struct dmi_system_id *d) | |
2338 | { | |
2339 | if (multi) | |
2340 | return 0; | |
6f0aced6 | 2341 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2342 | multi = 1; |
2343 | return 0; | |
2344 | } | |
2345 | ||
2346 | static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { | |
2347 | { | |
2348 | .callback = set_multi, | |
2349 | .ident = "IBM System Summit2", | |
2350 | .matches = { | |
2351 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2352 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2353 | }, | |
2354 | }, | |
2355 | {} | |
2356 | }; | |
2357 | ||
2358 | static void __cpuinit dmi_check_multi(void) | |
2359 | { | |
2360 | if (multi_checked) | |
2361 | return; | |
2362 | ||
2363 | dmi_check_system(multi_dmi_table); | |
2364 | multi_checked = 1; | |
2365 | } | |
2366 | ||
2367 | /* | |
2368 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2369 | * | |
2370 | * Thus far, the major user of this is IBM's Summit2 series: | |
2371 | * Clustered boxes may have unsynced TSC problems if they are | |
2372 | * multi-chassis. | |
2373 | * Use DMI to check them | |
2374 | */ | |
2375 | __cpuinit int apic_is_clustered_box(void) | |
2376 | { | |
2377 | dmi_check_multi(); | |
2378 | if (multi) | |
1cb68487 RT |
2379 | return 1; |
2380 | ||
e0e42142 YL |
2381 | if (!is_vsmp_box()) |
2382 | return 0; | |
2383 | ||
1da177e4 | 2384 | /* |
e0e42142 YL |
2385 | * ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2386 | * not guaranteed to be synced between boards | |
1da177e4 | 2387 | */ |
e0e42142 YL |
2388 | if (apic_cluster_num() > 1) |
2389 | return 1; | |
2390 | ||
2391 | return 0; | |
1da177e4 | 2392 | } |
f28c0ae2 | 2393 | #endif |
1da177e4 LT |
2394 | |
2395 | /* | |
0e078e2f | 2396 | * APIC command line parameters |
1da177e4 | 2397 | */ |
789fa735 | 2398 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2399 | { |
1da177e4 | 2400 | disable_apic = 1; |
9175fc06 | 2401 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2402 | return 0; |
2403 | } | |
2404 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2405 | |
2c8c0e6b | 2406 | /* same as disableapic, for compatibility */ |
789fa735 | 2407 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2408 | { |
789fa735 | 2409 | return setup_disableapic(arg); |
6935d1f9 | 2410 | } |
2c8c0e6b | 2411 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2412 | |
2e7c2838 LT |
2413 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2414 | { | |
2415 | local_apic_timer_c2_ok = 1; | |
2416 | return 0; | |
2417 | } | |
2418 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2419 | ||
36fef094 | 2420 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2421 | { |
1da177e4 | 2422 | disable_apic_timer = 1; |
36fef094 | 2423 | return 0; |
6935d1f9 | 2424 | } |
36fef094 CG |
2425 | early_param("noapictimer", parse_disable_apic_timer); |
2426 | ||
2427 | static int __init parse_nolapic_timer(char *arg) | |
2428 | { | |
2429 | disable_apic_timer = 1; | |
2430 | return 0; | |
6935d1f9 | 2431 | } |
36fef094 | 2432 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2433 | |
79af9bec CG |
2434 | static int __init apic_set_verbosity(char *arg) |
2435 | { | |
2436 | if (!arg) { | |
2437 | #ifdef CONFIG_X86_64 | |
2438 | skip_ioapic_setup = 0; | |
79af9bec CG |
2439 | return 0; |
2440 | #endif | |
2441 | return -EINVAL; | |
2442 | } | |
2443 | ||
2444 | if (strcmp("debug", arg) == 0) | |
2445 | apic_verbosity = APIC_DEBUG; | |
2446 | else if (strcmp("verbose", arg) == 0) | |
2447 | apic_verbosity = APIC_VERBOSE; | |
2448 | else { | |
ba21ebb6 | 2449 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2450 | " use apic=verbose or apic=debug\n", arg); |
2451 | return -EINVAL; | |
2452 | } | |
2453 | ||
2454 | return 0; | |
2455 | } | |
2456 | early_param("apic", apic_set_verbosity); | |
2457 | ||
1e934dda YL |
2458 | static int __init lapic_insert_resource(void) |
2459 | { | |
2460 | if (!apic_phys) | |
2461 | return -1; | |
2462 | ||
2463 | /* Put local APIC into the resource map. */ | |
2464 | lapic_resource.start = apic_phys; | |
2465 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2466 | insert_resource(&iomem_resource, &lapic_resource); | |
2467 | ||
2468 | return 0; | |
2469 | } | |
2470 | ||
2471 | /* | |
2472 | * need call insert after e820_reserve_resources() | |
2473 | * that is using request_resource | |
2474 | */ | |
2475 | late_initcall(lapic_insert_resource); |