Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
cdd6c482 | 17 | #include <linux/perf_event.h> |
1da177e4 | 18 | #include <linux/kernel_stat.h> |
d1de36f5 | 19 | #include <linux/mc146818rtc.h> |
70a20025 | 20 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
21 | #include <linux/clockchips.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/ftrace.h> | |
25 | #include <linux/ioport.h> | |
186f4360 | 26 | #include <linux/export.h> |
f3c6ea1b | 27 | #include <linux/syscore_ops.h> |
d1de36f5 IM |
28 | #include <linux/delay.h> |
29 | #include <linux/timex.h> | |
334955ef | 30 | #include <linux/i8253.h> |
6e1cb38a | 31 | #include <linux/dmar.h> |
d1de36f5 IM |
32 | #include <linux/init.h> |
33 | #include <linux/cpu.h> | |
34 | #include <linux/dmi.h> | |
d1de36f5 IM |
35 | #include <linux/smp.h> |
36 | #include <linux/mm.h> | |
1da177e4 | 37 | |
83ab8514 | 38 | #include <asm/trace/irq_vectors.h> |
8a8f422d | 39 | #include <asm/irq_remapping.h> |
cdd6c482 | 40 | #include <asm/perf_event.h> |
736decac | 41 | #include <asm/x86_init.h> |
1da177e4 | 42 | #include <asm/pgalloc.h> |
60063497 | 43 | #include <linux/atomic.h> |
1da177e4 | 44 | #include <asm/mpspec.h> |
d1de36f5 | 45 | #include <asm/i8259.h> |
73dea47f | 46 | #include <asm/proto.h> |
2c8c0e6b | 47 | #include <asm/apic.h> |
7167d08e | 48 | #include <asm/io_apic.h> |
d1de36f5 IM |
49 | #include <asm/desc.h> |
50 | #include <asm/hpet.h> | |
51 | #include <asm/idle.h> | |
52 | #include <asm/mtrr.h> | |
16f871bc | 53 | #include <asm/time.h> |
2bc13797 | 54 | #include <asm/smp.h> |
be71b855 | 55 | #include <asm/mce.h> |
8c3ba8d0 | 56 | #include <asm/tsc.h> |
2904ed8d | 57 | #include <asm/hypervisor.h> |
1da177e4 | 58 | |
ec70de8b | 59 | unsigned int num_processors; |
fdbecd9f | 60 | |
148f9bb8 | 61 | unsigned disabled_cpus; |
fdbecd9f | 62 | |
ec70de8b BG |
63 | /* Processor that is doing the boot up */ |
64 | unsigned int boot_cpu_physical_apicid = -1U; | |
cc08e04c | 65 | EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); |
5af5573e | 66 | |
80e5609c | 67 | /* |
fdbecd9f | 68 | * The highest APIC ID seen during enumeration. |
80e5609c | 69 | */ |
a491cc90 | 70 | static unsigned int max_physical_apicid; |
5af5573e | 71 | |
80e5609c | 72 | /* |
fdbecd9f | 73 | * Bitmask of physically existing CPUs: |
80e5609c | 74 | */ |
ec70de8b BG |
75 | physid_mask_t phys_cpu_present_map; |
76 | ||
151e0c7d HD |
77 | /* |
78 | * Processor to be disabled specified by kernel parameter | |
79 | * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to | |
80 | * avoid undefined behaviour caused by sending INIT from AP to BSP. | |
81 | */ | |
5b4d1dbc | 82 | static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; |
151e0c7d | 83 | |
b7c4948e HK |
84 | /* |
85 | * This variable controls which CPUs receive external NMIs. By default, | |
86 | * external NMIs are delivered only to the BSP. | |
87 | */ | |
88 | static int apic_extnmi = APIC_EXTNMI_BSP; | |
89 | ||
ec70de8b BG |
90 | /* |
91 | * Map cpu index to physical APIC ID | |
92 | */ | |
0816b0f0 VZ |
93 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); |
94 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); | |
3e9e57fa | 95 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); |
ec70de8b BG |
96 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
97 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
3e9e57fa | 98 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); |
80e5609c | 99 | |
b3c51170 | 100 | #ifdef CONFIG_X86_32 |
4c321ff8 | 101 | |
4c321ff8 TH |
102 | /* |
103 | * On x86_32, the mapping between cpu and logical apicid may vary | |
104 | * depending on apic in use. The following early percpu variable is | |
105 | * used for the mapping. This is where the behaviors of x86_64 and 32 | |
106 | * actually diverge. Let's keep it ugly for now. | |
107 | */ | |
0816b0f0 | 108 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); |
4c321ff8 | 109 | |
f28c0ae2 YL |
110 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
111 | static int enabled_via_apicbase; | |
112 | ||
c0eaa453 CG |
113 | /* |
114 | * Handle interrupt mode configuration register (IMCR). | |
115 | * This register controls whether the interrupt signals | |
116 | * that reach the BSP come from the master PIC or from the | |
117 | * local APIC. Before entering Symmetric I/O Mode, either | |
118 | * the BIOS or the operating system must switch out of | |
119 | * PIC Mode by changing the IMCR. | |
120 | */ | |
5cda395f | 121 | static inline void imcr_pic_to_apic(void) |
c0eaa453 CG |
122 | { |
123 | /* select IMCR register */ | |
124 | outb(0x70, 0x22); | |
125 | /* NMI and 8259 INTR go through APIC */ | |
126 | outb(0x01, 0x23); | |
127 | } | |
128 | ||
5cda395f | 129 | static inline void imcr_apic_to_pic(void) |
c0eaa453 CG |
130 | { |
131 | /* select IMCR register */ | |
132 | outb(0x70, 0x22); | |
133 | /* NMI and 8259 INTR go directly to BSP */ | |
134 | outb(0x00, 0x23); | |
135 | } | |
b3c51170 YL |
136 | #endif |
137 | ||
279f1461 SS |
138 | /* |
139 | * Knob to control our willingness to enable the local APIC. | |
140 | * | |
141 | * +1=force-enable | |
142 | */ | |
143 | static int force_enable_local_apic __initdata; | |
dc9788f4 | 144 | |
279f1461 SS |
145 | /* |
146 | * APIC command line parameters | |
147 | */ | |
148 | static int __init parse_lapic(char *arg) | |
149 | { | |
150 | if (config_enabled(CONFIG_X86_32) && !arg) | |
151 | force_enable_local_apic = 1; | |
27cf9298 | 152 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
279f1461 SS |
153 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
154 | return 0; | |
155 | } | |
156 | early_param("lapic", parse_lapic); | |
157 | ||
b3c51170 | 158 | #ifdef CONFIG_X86_64 |
bc1d99c1 | 159 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
160 | static __init int setup_apicpmtimer(char *s) |
161 | { | |
162 | apic_calibrate_pmtmr = 1; | |
163 | notsc_setup(NULL); | |
164 | return 0; | |
165 | } | |
166 | __setup("apicpmtimer", setup_apicpmtimer); | |
167 | #endif | |
168 | ||
b3c51170 YL |
169 | unsigned long mp_lapic_addr; |
170 | int disable_apic; | |
171 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
25874a29 | 172 | static int disable_apic_timer __initdata; |
e83a5fdc | 173 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
174 | int local_apic_timer_c2_ok; |
175 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
176 | ||
2414e021 | 177 | int first_system_vector = FIRST_SYSTEM_VECTOR; |
efa2559f | 178 | |
e83a5fdc HS |
179 | /* |
180 | * Debug level, exported for io_apic.c | |
181 | */ | |
baa13188 | 182 | unsigned int apic_verbosity; |
e83a5fdc | 183 | |
89c38c28 CG |
184 | int pic_mode; |
185 | ||
bab4b27c AS |
186 | /* Have we found an MP table */ |
187 | int smp_found_config; | |
188 | ||
39928722 AD |
189 | static struct resource lapic_resource = { |
190 | .name = "Local APIC", | |
191 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
192 | }; | |
193 | ||
1ade93ef | 194 | unsigned int lapic_timer_frequency = 0; |
d03030e9 | 195 | |
0e078e2f | 196 | static void apic_pm_activate(void); |
ba7eda4c | 197 | |
d3432896 AK |
198 | static unsigned long apic_phys; |
199 | ||
0e078e2f TG |
200 | /* |
201 | * Get the LAPIC version | |
202 | */ | |
203 | static inline int lapic_get_version(void) | |
ba7eda4c | 204 | { |
0e078e2f | 205 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
206 | } |
207 | ||
0e078e2f | 208 | /* |
9c803869 | 209 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
210 | */ |
211 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 212 | { |
9c803869 | 213 | #ifdef CONFIG_X86_64 |
0e078e2f | 214 | return 1; |
9c803869 CG |
215 | #else |
216 | return APIC_INTEGRATED(lapic_get_version()); | |
217 | #endif | |
ba7eda4c TG |
218 | } |
219 | ||
220 | /* | |
0e078e2f | 221 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 222 | */ |
0e078e2f | 223 | static int modern_apic(void) |
ba7eda4c | 224 | { |
0e078e2f TG |
225 | /* AMD systems use old APIC versions, so check the CPU */ |
226 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
227 | boot_cpu_data.x86 >= 0xf) | |
228 | return 1; | |
229 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
230 | } |
231 | ||
08306ce6 | 232 | /* |
a933c618 CG |
233 | * right after this call apic become NOOP driven |
234 | * so apic->write/read doesn't do anything | |
08306ce6 | 235 | */ |
25874a29 | 236 | static void __init apic_disable(void) |
08306ce6 | 237 | { |
f88f2b4f | 238 | pr_info("APIC: switched to apic NOOP\n"); |
a933c618 | 239 | apic = &apic_noop; |
08306ce6 CG |
240 | } |
241 | ||
c1eeb2de | 242 | void native_apic_wait_icr_idle(void) |
8339e9fb FLV |
243 | { |
244 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
245 | cpu_relax(); | |
246 | } | |
247 | ||
c1eeb2de | 248 | u32 native_safe_apic_wait_icr_idle(void) |
8339e9fb | 249 | { |
3c6bb07a | 250 | u32 send_status; |
8339e9fb FLV |
251 | int timeout; |
252 | ||
253 | timeout = 0; | |
254 | do { | |
255 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
256 | if (!send_status) | |
257 | break; | |
b49d7d87 | 258 | inc_irq_stat(icr_read_retry_count); |
8339e9fb FLV |
259 | udelay(100); |
260 | } while (timeout++ < 1000); | |
261 | ||
262 | return send_status; | |
263 | } | |
264 | ||
c1eeb2de | 265 | void native_apic_icr_write(u32 low, u32 id) |
1b374e4d | 266 | { |
ea7bdc65 JK |
267 | unsigned long flags; |
268 | ||
269 | local_irq_save(flags); | |
ed4e5ec1 | 270 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d | 271 | apic_write(APIC_ICR, low); |
ea7bdc65 | 272 | local_irq_restore(flags); |
1b374e4d SS |
273 | } |
274 | ||
c1eeb2de | 275 | u64 native_apic_icr_read(void) |
1b374e4d SS |
276 | { |
277 | u32 icr1, icr2; | |
278 | ||
279 | icr2 = apic_read(APIC_ICR2); | |
280 | icr1 = apic_read(APIC_ICR); | |
281 | ||
cf9768d7 | 282 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
283 | } |
284 | ||
7c37e48b CG |
285 | #ifdef CONFIG_X86_32 |
286 | /** | |
287 | * get_physical_broadcast - Get number of physical broadcast IDs | |
288 | */ | |
289 | int get_physical_broadcast(void) | |
290 | { | |
291 | return modern_apic() ? 0xff : 0xf; | |
292 | } | |
293 | #endif | |
294 | ||
0e078e2f TG |
295 | /** |
296 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
297 | */ | |
37e650c7 | 298 | int lapic_get_maxlvt(void) |
1da177e4 | 299 | { |
36a028de | 300 | unsigned int v; |
1da177e4 LT |
301 | |
302 | v = apic_read(APIC_LVR); | |
36a028de CG |
303 | /* |
304 | * - we always have APIC integrated on 64bit mode | |
305 | * - 82489DXs do not report # of LVT entries | |
306 | */ | |
307 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
308 | } |
309 | ||
274cfe59 CG |
310 | /* |
311 | * Local APIC timer | |
312 | */ | |
313 | ||
c40aaec6 | 314 | /* Clock divisor */ |
c40aaec6 | 315 | #define APIC_DIVISOR 16 |
279f1461 | 316 | #define TSC_DIVISOR 32 |
f07f4f90 | 317 | |
0e078e2f TG |
318 | /* |
319 | * This function sets up the local APIC timer, with a timeout of | |
320 | * 'clocks' APIC bus clock. During calibration we actually call | |
321 | * this function twice on the boot CPU, once with a bogus timeout | |
322 | * value, second time for real. The other (noncalibrating) CPUs | |
323 | * call this function only once, with the real, calibrated value. | |
324 | * | |
325 | * We do reads before writes even if unnecessary, to get around the | |
326 | * P5 APIC double write bug. | |
327 | */ | |
0e078e2f | 328 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 329 | { |
0e078e2f | 330 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 331 | |
0e078e2f TG |
332 | lvtt_value = LOCAL_TIMER_VECTOR; |
333 | if (!oneshot) | |
334 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
279f1461 SS |
335 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
336 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; | |
337 | ||
f07f4f90 CG |
338 | if (!lapic_is_integrated()) |
339 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
340 | ||
0e078e2f TG |
341 | if (!irqen) |
342 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 343 | |
0e078e2f | 344 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 | 345 | |
279f1461 | 346 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
5d7c631d SL |
347 | /* |
348 | * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, | |
349 | * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. | |
350 | * According to Intel, MFENCE can do the serialization here. | |
351 | */ | |
352 | asm volatile("mfence" : : : "memory"); | |
353 | ||
279f1461 SS |
354 | printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); |
355 | return; | |
356 | } | |
357 | ||
1da177e4 | 358 | /* |
0e078e2f | 359 | * Divide PICLK by 16 |
1da177e4 | 360 | */ |
0e078e2f | 361 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
362 | apic_write(APIC_TDCR, |
363 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
364 | APIC_TDR_DIV_16); | |
0e078e2f TG |
365 | |
366 | if (!oneshot) | |
f07f4f90 | 367 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
368 | } |
369 | ||
0e078e2f | 370 | /* |
a68c439b | 371 | * Setup extended LVT, AMD specific |
7b83dae7 | 372 | * |
a68c439b RR |
373 | * Software should use the LVT offsets the BIOS provides. The offsets |
374 | * are determined by the subsystems using it like those for MCE | |
375 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts | |
376 | * are supported. Beginning with family 10h at least 4 offsets are | |
377 | * available. | |
286f5718 | 378 | * |
a68c439b RR |
379 | * Since the offsets must be consistent for all cores, we keep track |
380 | * of the LVT offsets in software and reserve the offset for the same | |
381 | * vector also to be used on other cores. An offset is freed by | |
382 | * setting the entry to APIC_EILVT_MASKED. | |
383 | * | |
384 | * If the BIOS is right, there should be no conflicts. Otherwise a | |
385 | * "[Firmware Bug]: ..." error message is generated. However, if | |
386 | * software does not properly determines the offsets, it is not | |
387 | * necessarily a BIOS bug. | |
0e078e2f | 388 | */ |
7b83dae7 | 389 | |
a68c439b RR |
390 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
391 | ||
392 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) | |
393 | { | |
394 | return (old & APIC_EILVT_MASKED) | |
395 | || (new == APIC_EILVT_MASKED) | |
396 | || ((new & ~APIC_EILVT_MASKED) == old); | |
397 | } | |
398 | ||
399 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |
400 | { | |
8abc3122 | 401 | unsigned int rsvd, vector; |
a68c439b RR |
402 | |
403 | if (offset >= APIC_EILVT_NR_MAX) | |
404 | return ~0; | |
405 | ||
8abc3122 | 406 | rsvd = atomic_read(&eilvt_offsets[offset]); |
a68c439b | 407 | do { |
8abc3122 RR |
408 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
409 | if (vector && !eilvt_entry_is_changeable(vector, new)) | |
a68c439b RR |
410 | /* may not change if vectors are different */ |
411 | return rsvd; | |
412 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); | |
413 | } while (rsvd != new); | |
414 | ||
8abc3122 RR |
415 | rsvd &= ~APIC_EILVT_MASKED; |
416 | if (rsvd && rsvd != vector) | |
417 | pr_info("LVT offset %d assigned for vector 0x%02x\n", | |
418 | offset, rsvd); | |
419 | ||
a68c439b RR |
420 | return new; |
421 | } | |
422 | ||
423 | /* | |
424 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
cbf74cea RR |
425 | * enables the vector. See also the BKDGs. Must be called with |
426 | * preemption disabled. | |
a68c439b RR |
427 | */ |
428 | ||
27afdf20 | 429 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
1da177e4 | 430 | { |
a68c439b RR |
431 | unsigned long reg = APIC_EILVTn(offset); |
432 | unsigned int new, old, reserved; | |
433 | ||
434 | new = (mask << 16) | (msg_type << 8) | vector; | |
435 | old = apic_read(reg); | |
436 | reserved = reserve_eilvt_offset(offset, new); | |
437 | ||
438 | if (reserved != new) { | |
eb48c9cb RR |
439 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
440 | "vector 0x%x, but the register is already in use for " | |
441 | "vector 0x%x on another cpu\n", | |
442 | smp_processor_id(), reg, offset, new, reserved); | |
a68c439b RR |
443 | return -EINVAL; |
444 | } | |
445 | ||
446 | if (!eilvt_entry_is_changeable(old, new)) { | |
eb48c9cb RR |
447 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
448 | "vector 0x%x, but the register is already in use for " | |
449 | "vector 0x%x on this cpu\n", | |
450 | smp_processor_id(), reg, offset, new, old); | |
a68c439b RR |
451 | return -EBUSY; |
452 | } | |
453 | ||
454 | apic_write(reg, new); | |
a8fcf1a2 | 455 | |
a68c439b | 456 | return 0; |
1da177e4 | 457 | } |
27afdf20 | 458 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
7b83dae7 | 459 | |
0e078e2f TG |
460 | /* |
461 | * Program the next event, relative to now | |
462 | */ | |
463 | static int lapic_next_event(unsigned long delta, | |
464 | struct clock_event_device *evt) | |
1da177e4 | 465 | { |
0e078e2f TG |
466 | apic_write(APIC_TMICT, delta); |
467 | return 0; | |
1da177e4 LT |
468 | } |
469 | ||
279f1461 SS |
470 | static int lapic_next_deadline(unsigned long delta, |
471 | struct clock_event_device *evt) | |
472 | { | |
473 | u64 tsc; | |
474 | ||
4ea1636b | 475 | tsc = rdtsc(); |
279f1461 SS |
476 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); |
477 | return 0; | |
478 | } | |
479 | ||
b23d8e52 | 480 | static int lapic_timer_shutdown(struct clock_event_device *evt) |
9b7711f0 | 481 | { |
0e078e2f | 482 | unsigned int v; |
9b7711f0 | 483 | |
0e078e2f TG |
484 | /* Lapic used as dummy for broadcast ? */ |
485 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
b23d8e52 | 486 | return 0; |
9b7711f0 | 487 | |
b23d8e52 VK |
488 | v = apic_read(APIC_LVTT); |
489 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
490 | apic_write(APIC_LVTT, v); | |
491 | apic_write(APIC_TMICT, 0); | |
b23d8e52 VK |
492 | return 0; |
493 | } | |
9b7711f0 | 494 | |
b23d8e52 VK |
495 | static inline int |
496 | lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) | |
497 | { | |
b23d8e52 VK |
498 | /* Lapic used as dummy for broadcast ? */ |
499 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
500 | return 0; | |
9b7711f0 | 501 | |
b23d8e52 | 502 | __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); |
b23d8e52 VK |
503 | return 0; |
504 | } | |
505 | ||
506 | static int lapic_timer_set_periodic(struct clock_event_device *evt) | |
507 | { | |
508 | return lapic_timer_set_periodic_oneshot(evt, false); | |
509 | } | |
510 | ||
511 | static int lapic_timer_set_oneshot(struct clock_event_device *evt) | |
512 | { | |
513 | return lapic_timer_set_periodic_oneshot(evt, true); | |
9b7711f0 HS |
514 | } |
515 | ||
1da177e4 | 516 | /* |
0e078e2f | 517 | * Local APIC timer broadcast function |
1da177e4 | 518 | */ |
9628937d | 519 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 520 | { |
0e078e2f | 521 | #ifdef CONFIG_SMP |
dac5f412 | 522 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
523 | #endif |
524 | } | |
1da177e4 | 525 | |
25874a29 HK |
526 | |
527 | /* | |
528 | * The local apic timer can be used for any function which is CPU local. | |
529 | */ | |
530 | static struct clock_event_device lapic_clockevent = { | |
b23d8e52 VK |
531 | .name = "lapic", |
532 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
533 | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP | |
534 | | CLOCK_EVT_FEAT_DUMMY, | |
535 | .shift = 32, | |
536 | .set_state_shutdown = lapic_timer_shutdown, | |
537 | .set_state_periodic = lapic_timer_set_periodic, | |
538 | .set_state_oneshot = lapic_timer_set_oneshot, | |
539 | .set_next_event = lapic_next_event, | |
540 | .broadcast = lapic_timer_broadcast, | |
541 | .rating = 100, | |
542 | .irq = -1, | |
25874a29 HK |
543 | }; |
544 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
545 | ||
0e078e2f | 546 | /* |
421f91d2 | 547 | * Setup the local APIC timer for this CPU. Copy the initialized values |
0e078e2f TG |
548 | * of the boot CPU and register the clock event in the framework. |
549 | */ | |
148f9bb8 | 550 | static void setup_APIC_timer(void) |
0e078e2f | 551 | { |
89cbc767 | 552 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
1da177e4 | 553 | |
349c004e | 554 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
db954b58 VP |
555 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
556 | /* Make LAPIC timer preferrable over percpu HPET */ | |
557 | lapic_clockevent.rating = 150; | |
558 | } | |
559 | ||
0e078e2f | 560 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 561 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 562 | |
279f1461 SS |
563 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
564 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | | |
565 | CLOCK_EVT_FEAT_DUMMY); | |
566 | levt->set_next_event = lapic_next_deadline; | |
567 | clockevents_config_and_register(levt, | |
568 | (tsc_khz / TSC_DIVISOR) * 1000, | |
569 | 0xF, ~0UL); | |
570 | } else | |
571 | clockevents_register_device(levt); | |
0e078e2f | 572 | } |
1da177e4 | 573 | |
2f04fa88 YL |
574 | /* |
575 | * In this functions we calibrate APIC bus clocks to the external timer. | |
576 | * | |
577 | * We want to do the calibration only once since we want to have local timer | |
578 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
579 | * frequency. | |
580 | * | |
581 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
582 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
583 | * readout is broken, so it never gets out of the wait loop again. This was | |
584 | * also reported by others. | |
585 | * | |
586 | * Monitoring the jiffies value is inaccurate and the clockevents | |
587 | * infrastructure allows us to do a simple substitution of the interrupt | |
588 | * handler. | |
589 | * | |
590 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
591 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
592 | * back to normal later in the boot process). | |
593 | */ | |
594 | ||
595 | #define LAPIC_CAL_LOOPS (HZ/10) | |
596 | ||
597 | static __initdata int lapic_cal_loops = -1; | |
598 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
599 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
600 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
601 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
602 | ||
603 | /* | |
604 | * Temporary interrupt handler. | |
605 | */ | |
606 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
607 | { | |
608 | unsigned long long tsc = 0; | |
609 | long tapic = apic_read(APIC_TMCCT); | |
610 | unsigned long pm = acpi_pm_read_early(); | |
611 | ||
59e21e3d | 612 | if (boot_cpu_has(X86_FEATURE_TSC)) |
4ea1636b | 613 | tsc = rdtsc(); |
2f04fa88 YL |
614 | |
615 | switch (lapic_cal_loops++) { | |
616 | case 0: | |
617 | lapic_cal_t1 = tapic; | |
618 | lapic_cal_tsc1 = tsc; | |
619 | lapic_cal_pm1 = pm; | |
620 | lapic_cal_j1 = jiffies; | |
621 | break; | |
622 | ||
623 | case LAPIC_CAL_LOOPS: | |
624 | lapic_cal_t2 = tapic; | |
625 | lapic_cal_tsc2 = tsc; | |
626 | if (pm < lapic_cal_pm1) | |
627 | pm += ACPI_PM_OVRRUN; | |
628 | lapic_cal_pm2 = pm; | |
629 | lapic_cal_j2 = jiffies; | |
630 | break; | |
631 | } | |
632 | } | |
633 | ||
754ef0cd YI |
634 | static int __init |
635 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
636 | { |
637 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
638 | const long pm_thresh = pm_100ms / 100; | |
639 | unsigned long mult; | |
640 | u64 res; | |
641 | ||
642 | #ifndef CONFIG_X86_PM_TIMER | |
643 | return -1; | |
644 | #endif | |
645 | ||
39ba5d43 | 646 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
647 | |
648 | /* Check, if the PM timer is available */ | |
649 | if (!deltapm) | |
650 | return -1; | |
651 | ||
652 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
653 | ||
654 | if (deltapm > (pm_100ms - pm_thresh) && | |
655 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 656 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
657 | return 0; |
658 | } | |
659 | ||
660 | res = (((u64)deltapm) * mult) >> 22; | |
661 | do_div(res, 1000000); | |
662 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 663 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
664 | |
665 | /* Correct the lapic counter value */ | |
666 | res = (((u64)(*delta)) * pm_100ms); | |
667 | do_div(res, deltapm); | |
668 | pr_info("APIC delta adjusted to PM-Timer: " | |
669 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
670 | *delta = (long)res; | |
671 | ||
672 | /* Correct the tsc counter value */ | |
59e21e3d | 673 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
754ef0cd | 674 | res = (((u64)(*deltatsc)) * pm_100ms); |
b189892d | 675 | do_div(res, deltapm); |
754ef0cd | 676 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
3235dc3f | 677 | "PM-Timer: %lu (%ld)\n", |
754ef0cd YI |
678 | (unsigned long)res, *deltatsc); |
679 | *deltatsc = (long)res; | |
b189892d CG |
680 | } |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
2f04fa88 YL |
685 | static int __init calibrate_APIC_clock(void) |
686 | { | |
89cbc767 | 687 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
2f04fa88 YL |
688 | void (*real_handler)(struct clock_event_device *dev); |
689 | unsigned long deltaj; | |
754ef0cd | 690 | long delta, deltatsc; |
2f04fa88 YL |
691 | int pm_referenced = 0; |
692 | ||
1ade93ef JP |
693 | /** |
694 | * check if lapic timer has already been calibrated by platform | |
695 | * specific routine, such as tsc calibration code. if so, we just fill | |
696 | * in the clockevent structure and return. | |
697 | */ | |
698 | ||
279f1461 SS |
699 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
700 | return 0; | |
701 | } else if (lapic_timer_frequency) { | |
1ade93ef JP |
702 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
703 | lapic_timer_frequency); | |
704 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, | |
705 | TICK_NSEC, lapic_clockevent.shift); | |
706 | lapic_clockevent.max_delta_ns = | |
707 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
708 | lapic_clockevent.min_delta_ns = | |
709 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
710 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
711 | return 0; | |
712 | } | |
713 | ||
279f1461 SS |
714 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
715 | "calibrating APIC timer ...\n"); | |
716 | ||
2f04fa88 YL |
717 | local_irq_disable(); |
718 | ||
719 | /* Replace the global interrupt handler */ | |
720 | real_handler = global_clock_event->event_handler; | |
721 | global_clock_event->event_handler = lapic_cal_handler; | |
722 | ||
723 | /* | |
81608f3c | 724 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
725 | * can underflow in the 100ms detection time frame |
726 | */ | |
81608f3c | 727 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
728 | |
729 | /* Let the interrupts run */ | |
730 | local_irq_enable(); | |
731 | ||
732 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
733 | cpu_relax(); | |
734 | ||
735 | local_irq_disable(); | |
736 | ||
737 | /* Restore the real event handler */ | |
738 | global_clock_event->event_handler = real_handler; | |
739 | ||
740 | /* Build delta t1-t2 as apic timer counts down */ | |
741 | delta = lapic_cal_t1 - lapic_cal_t2; | |
742 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
743 | ||
754ef0cd YI |
744 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
745 | ||
b189892d CG |
746 | /* we trust the PM based calibration if possible */ |
747 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 748 | &delta, &deltatsc); |
2f04fa88 YL |
749 | |
750 | /* Calculate the scaled math multiplication factor */ | |
751 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
752 | lapic_clockevent.shift); | |
753 | lapic_clockevent.max_delta_ns = | |
4aed89d6 | 754 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
2f04fa88 YL |
755 | lapic_clockevent.min_delta_ns = |
756 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
757 | ||
1ade93ef | 758 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
2f04fa88 YL |
759 | |
760 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
411462f6 | 761 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
2f04fa88 | 762 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
1ade93ef | 763 | lapic_timer_frequency); |
2f04fa88 | 764 | |
59e21e3d | 765 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
2f04fa88 YL |
766 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
767 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
768 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
769 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
770 | } |
771 | ||
772 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
773 | "%u.%04u MHz.\n", | |
1ade93ef JP |
774 | lapic_timer_frequency / (1000000 / HZ), |
775 | lapic_timer_frequency % (1000000 / HZ)); | |
2f04fa88 YL |
776 | |
777 | /* | |
778 | * Do a sanity check on the APIC calibration result | |
779 | */ | |
1ade93ef | 780 | if (lapic_timer_frequency < (1000000 / HZ)) { |
2f04fa88 | 781 | local_irq_enable(); |
ba21ebb6 | 782 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
783 | return -1; |
784 | } | |
785 | ||
786 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
787 | ||
b189892d CG |
788 | /* |
789 | * PM timer calibration failed or not turned on | |
790 | * so lets try APIC timer based calibration | |
791 | */ | |
2f04fa88 YL |
792 | if (!pm_referenced) { |
793 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
794 | ||
795 | /* | |
796 | * Setup the apic timer manually | |
797 | */ | |
798 | levt->event_handler = lapic_cal_handler; | |
b23d8e52 | 799 | lapic_timer_set_periodic(levt); |
2f04fa88 YL |
800 | lapic_cal_loops = -1; |
801 | ||
802 | /* Let the interrupts run */ | |
803 | local_irq_enable(); | |
804 | ||
805 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
806 | cpu_relax(); | |
807 | ||
2f04fa88 | 808 | /* Stop the lapic timer */ |
c948c260 | 809 | local_irq_disable(); |
b23d8e52 | 810 | lapic_timer_shutdown(levt); |
2f04fa88 | 811 | |
2f04fa88 YL |
812 | /* Jiffies delta */ |
813 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
814 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
815 | ||
816 | /* Check, if the jiffies result is consistent */ | |
817 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
818 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
819 | else | |
820 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
c948c260 TG |
821 | } |
822 | local_irq_enable(); | |
2f04fa88 YL |
823 | |
824 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 825 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
826 | return -1; |
827 | } | |
828 | ||
829 | return 0; | |
830 | } | |
831 | ||
e83a5fdc HS |
832 | /* |
833 | * Setup the boot APIC | |
834 | * | |
835 | * Calibrate and verify the result. | |
836 | */ | |
0e078e2f TG |
837 | void __init setup_boot_APIC_clock(void) |
838 | { | |
839 | /* | |
274cfe59 CG |
840 | * The local apic timer can be disabled via the kernel |
841 | * commandline or from the CPU detection code. Register the lapic | |
842 | * timer as a dummy clock event source on SMP systems, so the | |
843 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
844 | */ |
845 | if (disable_apic_timer) { | |
ba21ebb6 | 846 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 847 | /* No broadcast on UP ! */ |
9d09951d TG |
848 | if (num_possible_cpus() > 1) { |
849 | lapic_clockevent.mult = 1; | |
0e078e2f | 850 | setup_APIC_timer(); |
9d09951d | 851 | } |
0e078e2f TG |
852 | return; |
853 | } | |
854 | ||
89b3b1f4 | 855 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
856 | /* No broadcast on UP ! */ |
857 | if (num_possible_cpus() > 1) | |
858 | setup_APIC_timer(); | |
859 | return; | |
860 | } | |
861 | ||
0e078e2f TG |
862 | /* |
863 | * If nmi_watchdog is set to IO_APIC, we need the | |
864 | * PIT/HPET going. Otherwise register lapic as a dummy | |
865 | * device. | |
866 | */ | |
072b198a | 867 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
0e078e2f | 868 | |
274cfe59 | 869 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
870 | setup_APIC_timer(); |
871 | } | |
872 | ||
148f9bb8 | 873 | void setup_secondary_APIC_clock(void) |
0e078e2f | 874 | { |
0e078e2f TG |
875 | setup_APIC_timer(); |
876 | } | |
877 | ||
878 | /* | |
879 | * The guts of the apic timer interrupt | |
880 | */ | |
881 | static void local_apic_timer_interrupt(void) | |
882 | { | |
883 | int cpu = smp_processor_id(); | |
884 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
885 | ||
886 | /* | |
887 | * Normally we should not be here till LAPIC has been initialized but | |
888 | * in some cases like kdump, its possible that there is a pending LAPIC | |
889 | * timer interrupt from previous kernel's context and is delivered in | |
890 | * new kernel the moment interrupts are enabled. | |
891 | * | |
892 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
893 | * its possible that when we get here evt->event_handler is NULL. | |
894 | * Check for event_handler being NULL and discard the interrupt as | |
895 | * spurious. | |
896 | */ | |
897 | if (!evt->event_handler) { | |
ba21ebb6 | 898 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f | 899 | /* Switch it off */ |
b23d8e52 | 900 | lapic_timer_shutdown(evt); |
0e078e2f TG |
901 | return; |
902 | } | |
903 | ||
904 | /* | |
905 | * the NMI deadlock-detector uses this. | |
906 | */ | |
915b0d01 | 907 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
908 | |
909 | evt->event_handler(evt); | |
910 | } | |
911 | ||
912 | /* | |
913 | * Local APIC timer interrupt. This is the most natural way for doing | |
914 | * local interrupts, but local timer interrupts can be emulated by | |
915 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
916 | * | |
917 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
918 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
919 | */ | |
1d9090e2 | 920 | __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
921 | { |
922 | struct pt_regs *old_regs = set_irq_regs(regs); | |
923 | ||
924 | /* | |
925 | * NOTE! We'd better ACK the irq immediately, | |
926 | * because timer handling can be slow. | |
eddc0e92 | 927 | * |
0e078e2f TG |
928 | * update_process_times() expects us to have done irq_enter(). |
929 | * Besides, if we don't timer interrupts ignore the global | |
930 | * interrupt lock, which is the WrongThing (tm) to do. | |
0e078e2f | 931 | */ |
eddc0e92 | 932 | entering_ack_irq(); |
0e078e2f | 933 | local_apic_timer_interrupt(); |
eddc0e92 | 934 | exiting_irq(); |
274cfe59 | 935 | |
0e078e2f TG |
936 | set_irq_regs(old_regs); |
937 | } | |
938 | ||
1d9090e2 | 939 | __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) |
cf910e83 SA |
940 | { |
941 | struct pt_regs *old_regs = set_irq_regs(regs); | |
942 | ||
0e078e2f | 943 | /* |
cf910e83 SA |
944 | * NOTE! We'd better ACK the irq immediately, |
945 | * because timer handling can be slow. | |
946 | * | |
0e078e2f TG |
947 | * update_process_times() expects us to have done irq_enter(). |
948 | * Besides, if we don't timer interrupts ignore the global | |
949 | * interrupt lock, which is the WrongThing (tm) to do. | |
950 | */ | |
cf910e83 SA |
951 | entering_ack_irq(); |
952 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); | |
0e078e2f | 953 | local_apic_timer_interrupt(); |
cf910e83 SA |
954 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
955 | exiting_irq(); | |
274cfe59 | 956 | |
0e078e2f TG |
957 | set_irq_regs(old_regs); |
958 | } | |
959 | ||
960 | int setup_profiling_timer(unsigned int multiplier) | |
961 | { | |
962 | return -EINVAL; | |
963 | } | |
964 | ||
0e078e2f TG |
965 | /* |
966 | * Local APIC start and shutdown | |
967 | */ | |
968 | ||
969 | /** | |
970 | * clear_local_APIC - shutdown the local APIC | |
971 | * | |
972 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
973 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
974 | * leftovers during boot. | |
975 | */ | |
976 | void clear_local_APIC(void) | |
977 | { | |
2584a82d | 978 | int maxlvt; |
0e078e2f TG |
979 | u32 v; |
980 | ||
d3432896 | 981 | /* APIC hasn't been mapped yet */ |
fc1edaf9 | 982 | if (!x2apic_mode && !apic_phys) |
d3432896 AK |
983 | return; |
984 | ||
985 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
986 | /* |
987 | * Masking an LVT entry can trigger a local APIC error | |
988 | * if the vector is zero. Mask LVTERR first to prevent this. | |
989 | */ | |
990 | if (maxlvt >= 3) { | |
991 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
992 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
993 | } | |
994 | /* | |
995 | * Careful: we have to set masks only first to deassert | |
996 | * any level-triggered sources. | |
997 | */ | |
998 | v = apic_read(APIC_LVTT); | |
999 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
1000 | v = apic_read(APIC_LVT0); | |
1001 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
1002 | v = apic_read(APIC_LVT1); | |
1003 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
1004 | if (maxlvt >= 4) { | |
1005 | v = apic_read(APIC_LVTPC); | |
1006 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1007 | } | |
1008 | ||
6764014b | 1009 | /* lets not touch this if we didn't frob it */ |
4efc0670 | 1010 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6764014b CG |
1011 | if (maxlvt >= 5) { |
1012 | v = apic_read(APIC_LVTTHMR); | |
1013 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
1014 | } | |
1015 | #endif | |
5ca8681c AK |
1016 | #ifdef CONFIG_X86_MCE_INTEL |
1017 | if (maxlvt >= 6) { | |
1018 | v = apic_read(APIC_LVTCMCI); | |
1019 | if (!(v & APIC_LVT_MASKED)) | |
1020 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | |
1021 | } | |
1022 | #endif | |
1023 | ||
0e078e2f TG |
1024 | /* |
1025 | * Clean APIC state for other OSs: | |
1026 | */ | |
1027 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
1028 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1029 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1030 | if (maxlvt >= 3) | |
1031 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
1032 | if (maxlvt >= 4) | |
1033 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
1034 | |
1035 | /* Integrated APIC (!82489DX) ? */ | |
1036 | if (lapic_is_integrated()) { | |
1037 | if (maxlvt > 3) | |
1038 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
1039 | apic_write(APIC_ESR, 0); | |
1040 | apic_read(APIC_ESR); | |
1041 | } | |
0e078e2f TG |
1042 | } |
1043 | ||
1044 | /** | |
1045 | * disable_local_APIC - clear and disable the local APIC | |
1046 | */ | |
1047 | void disable_local_APIC(void) | |
1048 | { | |
1049 | unsigned int value; | |
1050 | ||
4a13ad0b | 1051 | /* APIC hasn't been mapped yet */ |
fd19dce7 | 1052 | if (!x2apic_mode && !apic_phys) |
4a13ad0b JB |
1053 | return; |
1054 | ||
0e078e2f TG |
1055 | clear_local_APIC(); |
1056 | ||
1057 | /* | |
1058 | * Disable APIC (implies clearing of registers | |
1059 | * for 82489DX!). | |
1060 | */ | |
1061 | value = apic_read(APIC_SPIV); | |
1062 | value &= ~APIC_SPIV_APIC_ENABLED; | |
1063 | apic_write(APIC_SPIV, value); | |
990b183e CG |
1064 | |
1065 | #ifdef CONFIG_X86_32 | |
1066 | /* | |
1067 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
1068 | * restore the disabled state. | |
1069 | */ | |
1070 | if (enabled_via_apicbase) { | |
1071 | unsigned int l, h; | |
1072 | ||
1073 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1074 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
1075 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1076 | } | |
1077 | #endif | |
0e078e2f TG |
1078 | } |
1079 | ||
fe4024dc CG |
1080 | /* |
1081 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
1082 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
1083 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
1084 | * for the case where Linux didn't enable the LAPIC. | |
1085 | */ | |
0e078e2f TG |
1086 | void lapic_shutdown(void) |
1087 | { | |
1088 | unsigned long flags; | |
1089 | ||
93984fbd | 1090 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
0e078e2f TG |
1091 | return; |
1092 | ||
1093 | local_irq_save(flags); | |
1094 | ||
fe4024dc CG |
1095 | #ifdef CONFIG_X86_32 |
1096 | if (!enabled_via_apicbase) | |
1097 | clear_local_APIC(); | |
1098 | else | |
1099 | #endif | |
1100 | disable_local_APIC(); | |
1101 | ||
0e078e2f TG |
1102 | |
1103 | local_irq_restore(flags); | |
1104 | } | |
1105 | ||
0e078e2f TG |
1106 | /** |
1107 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1108 | */ | |
1da177e4 LT |
1109 | void __init sync_Arb_IDs(void) |
1110 | { | |
296cb951 CG |
1111 | /* |
1112 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1113 | * needed on AMD. | |
1114 | */ | |
1115 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1116 | return; |
1117 | ||
1118 | /* | |
1119 | * Wait for idle. | |
1120 | */ | |
1121 | apic_wait_icr_idle(); | |
1122 | ||
1123 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1124 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1125 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1126 | } |
1127 | ||
1da177e4 LT |
1128 | /* |
1129 | * An initial setup of the virtual wire mode. | |
1130 | */ | |
1131 | void __init init_bsp_APIC(void) | |
1132 | { | |
11a8e778 | 1133 | unsigned int value; |
1da177e4 LT |
1134 | |
1135 | /* | |
1136 | * Don't do the setup now if we have a SMP BIOS as the | |
1137 | * through-I/O-APIC virtual wire mode might be active. | |
1138 | */ | |
93984fbd | 1139 | if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) |
1da177e4 LT |
1140 | return; |
1141 | ||
1da177e4 LT |
1142 | /* |
1143 | * Do not trust the local APIC being empty at bootup. | |
1144 | */ | |
1145 | clear_local_APIC(); | |
1146 | ||
1147 | /* | |
1148 | * Enable APIC. | |
1149 | */ | |
1150 | value = apic_read(APIC_SPIV); | |
1151 | value &= ~APIC_VECTOR_MASK; | |
1152 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1153 | |
1154 | #ifdef CONFIG_X86_32 | |
1155 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1156 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1157 | (boot_cpu_data.x86 == 15)) | |
1158 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1159 | else | |
1160 | #endif | |
1161 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1162 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1163 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1164 | |
1165 | /* | |
1166 | * Set up the virtual wire mode. | |
1167 | */ | |
11a8e778 | 1168 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1169 | value = APIC_DM_NMI; |
638c0411 CG |
1170 | if (!lapic_is_integrated()) /* 82489DX */ |
1171 | value |= APIC_LVT_LEVEL_TRIGGER; | |
b7c4948e HK |
1172 | if (apic_extnmi == APIC_EXTNMI_NONE) |
1173 | value |= APIC_LVT_MASKED; | |
11a8e778 | 1174 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1175 | } |
1176 | ||
148f9bb8 | 1177 | static void lapic_setup_esr(void) |
c43da2f5 | 1178 | { |
9df08f10 CG |
1179 | unsigned int oldvalue, value, maxlvt; |
1180 | ||
1181 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1182 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1183 | return; |
1184 | } | |
c43da2f5 | 1185 | |
08125d3e | 1186 | if (apic->disable_esr) { |
c43da2f5 | 1187 | /* |
9df08f10 CG |
1188 | * Something untraceable is creating bad interrupts on |
1189 | * secondary quads ... for the moment, just leave the | |
1190 | * ESR disabled - we can't do anything useful with the | |
1191 | * errors anyway - mbligh | |
c43da2f5 | 1192 | */ |
ba21ebb6 | 1193 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1194 | return; |
c43da2f5 | 1195 | } |
9df08f10 CG |
1196 | |
1197 | maxlvt = lapic_get_maxlvt(); | |
1198 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1199 | apic_write(APIC_ESR, 0); | |
1200 | oldvalue = apic_read(APIC_ESR); | |
1201 | ||
1202 | /* enables sending errors */ | |
1203 | value = ERROR_APIC_VECTOR; | |
1204 | apic_write(APIC_LVTERR, value); | |
1205 | ||
1206 | /* | |
1207 | * spec says clear errors after enabling vector. | |
1208 | */ | |
1209 | if (maxlvt > 3) | |
1210 | apic_write(APIC_ESR, 0); | |
1211 | value = apic_read(APIC_ESR); | |
1212 | if (value != oldvalue) | |
1213 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1214 | "vector: 0x%08x after: 0x%08x\n", | |
1215 | oldvalue, value); | |
c43da2f5 CG |
1216 | } |
1217 | ||
0e078e2f TG |
1218 | /** |
1219 | * setup_local_APIC - setup the local APIC | |
0aa002fe TH |
1220 | * |
1221 | * Used to setup local APIC while initializing BSP or bringin up APs. | |
1222 | * Always called with preemption disabled. | |
0e078e2f | 1223 | */ |
148f9bb8 | 1224 | void setup_local_APIC(void) |
1da177e4 | 1225 | { |
0aa002fe | 1226 | int cpu = smp_processor_id(); |
8c3ba8d0 KJ |
1227 | unsigned int value, queued; |
1228 | int i, j, acked = 0; | |
1229 | unsigned long long tsc = 0, ntsc; | |
b47dcbdc | 1230 | long long max_loops = cpu_khz ? cpu_khz : 1000000; |
8c3ba8d0 | 1231 | |
59e21e3d | 1232 | if (boot_cpu_has(X86_FEATURE_TSC)) |
4ea1636b | 1233 | tsc = rdtsc(); |
1da177e4 | 1234 | |
f1182638 | 1235 | if (disable_apic) { |
7167d08e | 1236 | disable_ioapic_support(); |
f1182638 JB |
1237 | return; |
1238 | } | |
1239 | ||
89c38c28 CG |
1240 | #ifdef CONFIG_X86_32 |
1241 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1242 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1243 | apic_write(APIC_ESR, 0); |
1244 | apic_write(APIC_ESR, 0); | |
1245 | apic_write(APIC_ESR, 0); | |
1246 | apic_write(APIC_ESR, 0); | |
1247 | } | |
1248 | #endif | |
cdd6c482 | 1249 | perf_events_lapic_init(); |
89c38c28 | 1250 | |
1da177e4 LT |
1251 | /* |
1252 | * Double-check whether this APIC is really registered. | |
1253 | * This is meaningless in clustered apic mode, so we skip it. | |
1254 | */ | |
c2777f98 | 1255 | BUG_ON(!apic->apic_id_registered()); |
1da177e4 LT |
1256 | |
1257 | /* | |
1258 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1259 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1260 | * document number 292116). So here it goes... | |
1261 | */ | |
a5c43296 | 1262 | apic->init_apic_ldr(); |
1da177e4 | 1263 | |
6f802c4b TH |
1264 | #ifdef CONFIG_X86_32 |
1265 | /* | |
acb8bc09 TH |
1266 | * APIC LDR is initialized. If logical_apicid mapping was |
1267 | * initialized during get_smp_config(), make sure it matches the | |
1268 | * actual value. | |
6f802c4b | 1269 | */ |
acb8bc09 TH |
1270 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
1271 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); | |
1272 | /* always use the value from LDR */ | |
6f802c4b TH |
1273 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
1274 | logical_smp_processor_id(); | |
1275 | #endif | |
1276 | ||
1da177e4 LT |
1277 | /* |
1278 | * Set Task Priority to 'accept all'. We never change this | |
1279 | * later on. | |
1280 | */ | |
1281 | value = apic_read(APIC_TASKPRI); | |
1282 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1283 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1284 | |
da7ed9f9 VG |
1285 | /* |
1286 | * After a crash, we no longer service the interrupts and a pending | |
1287 | * interrupt from previous kernel might still have ISR bit set. | |
1288 | * | |
1289 | * Most probably by now CPU has serviced that pending interrupt and | |
1290 | * it might not have done the ack_APIC_irq() because it thought, | |
1291 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1292 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1293 | * the interrupt. Hence a vector might get locked. It was noticed | |
1294 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1295 | */ | |
8c3ba8d0 KJ |
1296 | do { |
1297 | queued = 0; | |
1298 | for (i = APIC_ISR_NR - 1; i >= 0; i--) | |
1299 | queued |= apic_read(APIC_IRR + i*0x10); | |
1300 | ||
1301 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1302 | value = apic_read(APIC_ISR + i*0x10); | |
1303 | for (j = 31; j >= 0; j--) { | |
1304 | if (value & (1<<j)) { | |
1305 | ack_APIC_irq(); | |
1306 | acked++; | |
1307 | } | |
1308 | } | |
da7ed9f9 | 1309 | } |
8c3ba8d0 KJ |
1310 | if (acked > 256) { |
1311 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", | |
1312 | acked); | |
1313 | break; | |
1314 | } | |
42fa4250 | 1315 | if (queued) { |
59e21e3d | 1316 | if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { |
4ea1636b | 1317 | ntsc = rdtsc(); |
42fa4250 SF |
1318 | max_loops = (cpu_khz << 10) - (ntsc - tsc); |
1319 | } else | |
1320 | max_loops--; | |
1321 | } | |
8c3ba8d0 KJ |
1322 | } while (queued && max_loops > 0); |
1323 | WARN_ON(max_loops <= 0); | |
da7ed9f9 | 1324 | |
1da177e4 LT |
1325 | /* |
1326 | * Now that we are all set up, enable the APIC | |
1327 | */ | |
1328 | value = apic_read(APIC_SPIV); | |
1329 | value &= ~APIC_VECTOR_MASK; | |
1330 | /* | |
1331 | * Enable APIC | |
1332 | */ | |
1333 | value |= APIC_SPIV_APIC_ENABLED; | |
1334 | ||
89c38c28 CG |
1335 | #ifdef CONFIG_X86_32 |
1336 | /* | |
1337 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1338 | * certain networking cards. If high frequency interrupts are | |
1339 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1340 | * entry is masked/unmasked at a high rate as well then sooner or | |
1341 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1342 | * from the device. If focus CPU is disabled then the hang goes | |
1343 | * away, oh well :-( | |
1344 | * | |
1345 | * [ This bug can be reproduced easily with a level-triggered | |
1346 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1347 | * BX chipset. ] | |
1348 | */ | |
1349 | /* | |
1350 | * Actually disabling the focus CPU check just makes the hang less | |
1351 | * frequent as it makes the interrupt distributon model be more | |
1352 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1353 | * See also the comment in end_level_ioapic_irq(). --macro | |
1354 | */ | |
1355 | ||
1356 | /* | |
1357 | * - enable focus processor (bit==0) | |
1358 | * - 64bit mode always use processor focus | |
1359 | * so no need to set it | |
1360 | */ | |
1361 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1362 | #endif | |
3f14c746 | 1363 | |
1da177e4 LT |
1364 | /* |
1365 | * Set spurious IRQ vector | |
1366 | */ | |
1367 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1368 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1369 | |
1370 | /* | |
1371 | * Set up LVT0, LVT1: | |
1372 | * | |
1373 | * set up through-local-APIC on the BP's LINT0. This is not | |
1374 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1375 | * we delegate interrupts to the 8259A. | |
1376 | */ | |
1377 | /* | |
1378 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1379 | */ | |
1380 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
0aa002fe | 1381 | if (!cpu && (pic_mode || !value)) { |
1da177e4 | 1382 | value = APIC_DM_EXTINT; |
0aa002fe | 1383 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
1da177e4 LT |
1384 | } else { |
1385 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
0aa002fe | 1386 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
1da177e4 | 1387 | } |
11a8e778 | 1388 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1389 | |
1390 | /* | |
b7c4948e HK |
1391 | * Only the BSP sees the LINT1 NMI signal by default. This can be |
1392 | * modified by apic_extnmi= boot option. | |
1da177e4 | 1393 | */ |
b7c4948e HK |
1394 | if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || |
1395 | apic_extnmi == APIC_EXTNMI_ALL) | |
1da177e4 LT |
1396 | value = APIC_DM_NMI; |
1397 | else | |
1398 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1399 | if (!lapic_is_integrated()) /* 82489DX */ |
1400 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1401 | apic_write(APIC_LVT1, value); |
89c38c28 | 1402 | |
be71b855 AK |
1403 | #ifdef CONFIG_X86_MCE_INTEL |
1404 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | |
0aa002fe | 1405 | if (!cpu) |
be71b855 AK |
1406 | cmci_recheck(); |
1407 | #endif | |
739f33b3 | 1408 | } |
1da177e4 | 1409 | |
05f7e46d | 1410 | static void end_local_APIC_setup(void) |
739f33b3 AK |
1411 | { |
1412 | lapic_setup_esr(); | |
fa6b95fc CG |
1413 | |
1414 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1415 | { |
1416 | unsigned int value; | |
1417 | /* Disable the local apic timer */ | |
1418 | value = apic_read(APIC_LVTT); | |
1419 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1420 | apic_write(APIC_LVTT, value); | |
1421 | } | |
fa6b95fc CG |
1422 | #endif |
1423 | ||
0e078e2f | 1424 | apic_pm_activate(); |
2fb270f3 JB |
1425 | } |
1426 | ||
05f7e46d TG |
1427 | /* |
1428 | * APIC setup function for application processors. Called from smpboot.c | |
1429 | */ | |
1430 | void apic_ap_setup(void) | |
2fb270f3 | 1431 | { |
05f7e46d | 1432 | setup_local_APIC(); |
2fb270f3 | 1433 | end_local_APIC_setup(); |
1da177e4 | 1434 | } |
1da177e4 | 1435 | |
06cd9a7d | 1436 | #ifdef CONFIG_X86_X2APIC |
bfb05070 | 1437 | int x2apic_mode; |
12e189d3 TG |
1438 | |
1439 | enum { | |
1440 | X2APIC_OFF, | |
1441 | X2APIC_ON, | |
1442 | X2APIC_DISABLED, | |
1443 | }; | |
1444 | static int x2apic_state; | |
1445 | ||
d786ad32 | 1446 | static void __x2apic_disable(void) |
44e25ff9 TG |
1447 | { |
1448 | u64 msr; | |
1449 | ||
93984fbd | 1450 | if (!boot_cpu_has(X86_FEATURE_APIC)) |
659006bf TG |
1451 | return; |
1452 | ||
44e25ff9 TG |
1453 | rdmsrl(MSR_IA32_APICBASE, msr); |
1454 | if (!(msr & X2APIC_ENABLE)) | |
1455 | return; | |
1456 | /* Disable xapic and x2apic first and then reenable xapic mode */ | |
1457 | wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); | |
1458 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); | |
1459 | printk_once(KERN_INFO "x2apic disabled\n"); | |
1460 | } | |
1461 | ||
d786ad32 | 1462 | static void __x2apic_enable(void) |
659006bf TG |
1463 | { |
1464 | u64 msr; | |
1465 | ||
1466 | rdmsrl(MSR_IA32_APICBASE, msr); | |
1467 | if (msr & X2APIC_ENABLE) | |
1468 | return; | |
1469 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); | |
1470 | printk_once(KERN_INFO "x2apic enabled\n"); | |
1471 | } | |
1472 | ||
bfb05070 TG |
1473 | static int __init setup_nox2apic(char *str) |
1474 | { | |
1475 | if (x2apic_enabled()) { | |
1476 | int apicid = native_apic_msr_read(APIC_ID); | |
1477 | ||
1478 | if (apicid >= 255) { | |
1479 | pr_warning("Apicid: %08x, cannot enforce nox2apic\n", | |
1480 | apicid); | |
1481 | return 0; | |
1482 | } | |
44e25ff9 TG |
1483 | pr_warning("x2apic already enabled.\n"); |
1484 | __x2apic_disable(); | |
1485 | } | |
1486 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
12e189d3 | 1487 | x2apic_state = X2APIC_DISABLED; |
44e25ff9 | 1488 | x2apic_mode = 0; |
bfb05070 TG |
1489 | return 0; |
1490 | } | |
1491 | early_param("nox2apic", setup_nox2apic); | |
1492 | ||
659006bf TG |
1493 | /* Called from cpu_init() to enable x2apic on (secondary) cpus */ |
1494 | void x2apic_setup(void) | |
1495 | { | |
1496 | /* | |
1497 | * If x2apic is not in ON state, disable it if already enabled | |
1498 | * from BIOS. | |
1499 | */ | |
1500 | if (x2apic_state != X2APIC_ON) { | |
1501 | __x2apic_disable(); | |
1502 | return; | |
1503 | } | |
1504 | __x2apic_enable(); | |
1505 | } | |
1506 | ||
44e25ff9 | 1507 | static __init void x2apic_disable(void) |
fb209bd8 | 1508 | { |
a57e456a | 1509 | u32 x2apic_id, state = x2apic_state; |
fb209bd8 | 1510 | |
a57e456a TG |
1511 | x2apic_mode = 0; |
1512 | x2apic_state = X2APIC_DISABLED; | |
1513 | ||
1514 | if (state != X2APIC_ON) | |
1515 | return; | |
fb209bd8 | 1516 | |
6d2d49d2 TG |
1517 | x2apic_id = read_apic_id(); |
1518 | if (x2apic_id >= 255) | |
1519 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); | |
9aa16365 | 1520 | |
6d2d49d2 TG |
1521 | __x2apic_disable(); |
1522 | register_lapic_address(mp_lapic_addr); | |
fb209bd8 YL |
1523 | } |
1524 | ||
659006bf | 1525 | static __init void x2apic_enable(void) |
6e1cb38a | 1526 | { |
659006bf | 1527 | if (x2apic_state != X2APIC_OFF) |
06cd9a7d YL |
1528 | return; |
1529 | ||
659006bf | 1530 | x2apic_mode = 1; |
12e189d3 | 1531 | x2apic_state = X2APIC_ON; |
659006bf | 1532 | __x2apic_enable(); |
6e1cb38a | 1533 | } |
d524165c | 1534 | |
62e61633 | 1535 | static __init void try_to_enable_x2apic(int remap_mode) |
07806c50 | 1536 | { |
659006bf | 1537 | if (x2apic_state == X2APIC_DISABLED) |
07806c50 JL |
1538 | return; |
1539 | ||
62e61633 | 1540 | if (remap_mode != IRQ_REMAP_X2APIC_MODE) { |
07806c50 JL |
1541 | /* IR is required if there is APIC ID > 255 even when running |
1542 | * under KVM | |
1543 | */ | |
1544 | if (max_physical_apicid > 255 || | |
8329aa9f | 1545 | !hypervisor_x2apic_available()) { |
62e61633 | 1546 | pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); |
44e25ff9 | 1547 | x2apic_disable(); |
07806c50 JL |
1548 | return; |
1549 | } | |
1550 | ||
1551 | /* | |
1552 | * without IR all CPUs can be addressed by IOAPIC/MSI | |
1553 | * only in physical mode | |
1554 | */ | |
55eae7de | 1555 | x2apic_phys = 1; |
07806c50 | 1556 | } |
659006bf | 1557 | x2apic_enable(); |
55eae7de TG |
1558 | } |
1559 | ||
1560 | void __init check_x2apic(void) | |
1561 | { | |
1562 | if (x2apic_enabled()) { | |
1563 | pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); | |
1564 | x2apic_mode = 1; | |
12e189d3 | 1565 | x2apic_state = X2APIC_ON; |
62436a4d | 1566 | } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { |
12e189d3 | 1567 | x2apic_state = X2APIC_DISABLED; |
55eae7de TG |
1568 | } |
1569 | } | |
1570 | #else /* CONFIG_X86_X2APIC */ | |
1571 | static int __init validate_x2apic(void) | |
1572 | { | |
1573 | if (!apic_is_x2apic_enabled()) | |
1574 | return 0; | |
1575 | /* | |
1576 | * Checkme: Can we simply turn off x2apic here instead of panic? | |
1577 | */ | |
1578 | panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); | |
1579 | } | |
1580 | early_initcall(validate_x2apic); | |
1581 | ||
62e61633 | 1582 | static inline void try_to_enable_x2apic(int remap_mode) { } |
659006bf | 1583 | static inline void __x2apic_enable(void) { } |
55eae7de TG |
1584 | #endif /* !CONFIG_X86_X2APIC */ |
1585 | ||
1586 | static int __init try_to_enable_IR(void) | |
1587 | { | |
1588 | #ifdef CONFIG_X86_IO_APIC | |
1589 | if (!x2apic_enabled() && skip_ioapic_setup) { | |
1590 | pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); | |
1591 | return -1; | |
1592 | } | |
ce69a784 | 1593 | #endif |
55eae7de | 1594 | return irq_remapping_enable(); |
ce69a784 GN |
1595 | } |
1596 | ||
1597 | void __init enable_IR_x2apic(void) | |
1598 | { | |
1599 | unsigned long flags; | |
07806c50 | 1600 | int ret, ir_stat; |
b7f42ab2 | 1601 | |
07806c50 JL |
1602 | ir_stat = irq_remapping_prepare(); |
1603 | if (ir_stat < 0 && !x2apic_supported()) | |
e670761f | 1604 | return; |
ce69a784 | 1605 | |
31dce14a | 1606 | ret = save_ioapic_entries(); |
5ffa4eb2 | 1607 | if (ret) { |
ba21ebb6 | 1608 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
fb209bd8 | 1609 | return; |
5ffa4eb2 | 1610 | } |
6e1cb38a | 1611 | |
05c3dc2c | 1612 | local_irq_save(flags); |
b81bb373 | 1613 | legacy_pic->mask_all(); |
31dce14a | 1614 | mask_ioapic_entries(); |
05c3dc2c | 1615 | |
6a6256f9 | 1616 | /* If irq_remapping_prepare() succeeded, try to enable it */ |
07806c50 JL |
1617 | if (ir_stat >= 0) |
1618 | ir_stat = try_to_enable_IR(); | |
1619 | /* ir_stat contains the remap mode or an error code */ | |
1620 | try_to_enable_x2apic(ir_stat); | |
a31bc327 | 1621 | |
07806c50 | 1622 | if (ir_stat < 0) |
31dce14a | 1623 | restore_ioapic_entries(); |
b81bb373 | 1624 | legacy_pic->restore_mask(); |
6e1cb38a | 1625 | local_irq_restore(flags); |
6e1cb38a | 1626 | } |
93758238 | 1627 | |
be7a656f | 1628 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1629 | /* |
1630 | * Detect and enable local APICs on non-SMP boards. | |
1631 | * Original code written by Keir Fraser. | |
1632 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1633 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1634 | */ |
0e078e2f | 1635 | static int __init detect_init_APIC(void) |
1da177e4 | 1636 | { |
93984fbd | 1637 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
ba21ebb6 | 1638 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1639 | return -1; |
1640 | } | |
1641 | ||
1642 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1da177e4 LT |
1643 | return 0; |
1644 | } | |
be7a656f | 1645 | #else |
5a7ae78f | 1646 | |
25874a29 | 1647 | static int __init apic_verify(void) |
5a7ae78f TG |
1648 | { |
1649 | u32 features, h, l; | |
1650 | ||
1651 | /* | |
1652 | * The APIC feature bit should now be enabled | |
1653 | * in `cpuid' | |
1654 | */ | |
1655 | features = cpuid_edx(1); | |
1656 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
1657 | pr_warning("Could not enable APIC!\n"); | |
1658 | return -1; | |
1659 | } | |
1660 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1661 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1662 | ||
1663 | /* The BIOS may have set up the APIC at some other address */ | |
cbf2829b BD |
1664 | if (boot_cpu_data.x86 >= 6) { |
1665 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1666 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1667 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1668 | } | |
5a7ae78f TG |
1669 | |
1670 | pr_info("Found and enabled local APIC!\n"); | |
1671 | return 0; | |
1672 | } | |
1673 | ||
25874a29 | 1674 | int __init apic_force_enable(unsigned long addr) |
5a7ae78f TG |
1675 | { |
1676 | u32 h, l; | |
1677 | ||
1678 | if (disable_apic) | |
1679 | return -1; | |
1680 | ||
1681 | /* | |
1682 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1683 | * MSR. This can only be done in software for Intel P6 or later | |
1684 | * and AMD K7 (Model > 1) or later. | |
1685 | */ | |
cbf2829b BD |
1686 | if (boot_cpu_data.x86 >= 6) { |
1687 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1688 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1689 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | |
1690 | l &= ~MSR_IA32_APICBASE_BASE; | |
1691 | l |= MSR_IA32_APICBASE_ENABLE | addr; | |
1692 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1693 | enabled_via_apicbase = 1; | |
1694 | } | |
5a7ae78f TG |
1695 | } |
1696 | return apic_verify(); | |
1697 | } | |
1698 | ||
be7a656f YL |
1699 | /* |
1700 | * Detect and initialize APIC | |
1701 | */ | |
1702 | static int __init detect_init_APIC(void) | |
1703 | { | |
be7a656f YL |
1704 | /* Disabled by kernel option? */ |
1705 | if (disable_apic) | |
1706 | return -1; | |
1707 | ||
1708 | switch (boot_cpu_data.x86_vendor) { | |
1709 | case X86_VENDOR_AMD: | |
1710 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1711 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1712 | break; |
1713 | goto no_apic; | |
1714 | case X86_VENDOR_INTEL: | |
1715 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
93984fbd | 1716 | (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) |
be7a656f YL |
1717 | break; |
1718 | goto no_apic; | |
1719 | default: | |
1720 | goto no_apic; | |
1721 | } | |
1722 | ||
93984fbd | 1723 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
be7a656f YL |
1724 | /* |
1725 | * Over-ride BIOS and try to enable the local APIC only if | |
1726 | * "lapic" specified. | |
1727 | */ | |
1728 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1729 | pr_info("Local APIC disabled by BIOS -- " |
1730 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1731 | return -1; |
1732 | } | |
a906fdaa | 1733 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
5a7ae78f TG |
1734 | return -1; |
1735 | } else { | |
1736 | if (apic_verify()) | |
1737 | return -1; | |
be7a656f | 1738 | } |
be7a656f YL |
1739 | |
1740 | apic_pm_activate(); | |
1741 | ||
1742 | return 0; | |
1743 | ||
1744 | no_apic: | |
ba21ebb6 | 1745 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1746 | return -1; |
1747 | } | |
1748 | #endif | |
1da177e4 | 1749 | |
0e078e2f TG |
1750 | /** |
1751 | * init_apic_mappings - initialize APIC mappings | |
1752 | */ | |
1da177e4 LT |
1753 | void __init init_apic_mappings(void) |
1754 | { | |
4401da61 YL |
1755 | unsigned int new_apicid; |
1756 | ||
fc1edaf9 | 1757 | if (x2apic_mode) { |
4c9961d5 | 1758 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1759 | return; |
1760 | } | |
1761 | ||
4797f6b0 | 1762 | /* If no local APIC can be found return early */ |
1da177e4 | 1763 | if (!smp_found_config && detect_init_APIC()) { |
4797f6b0 YL |
1764 | /* lets NOP'ify apic operations */ |
1765 | pr_info("APIC: disable apic facility\n"); | |
1766 | apic_disable(); | |
1767 | } else { | |
1da177e4 LT |
1768 | apic_phys = mp_lapic_addr; |
1769 | ||
4797f6b0 YL |
1770 | /* |
1771 | * acpi lapic path already maps that address in | |
1772 | * acpi_register_lapic_address() | |
1773 | */ | |
5989cd6a | 1774 | if (!acpi_lapic && !smp_found_config) |
326a2e6b | 1775 | register_lapic_address(apic_phys); |
cec6be6d | 1776 | } |
1da177e4 LT |
1777 | |
1778 | /* | |
1779 | * Fetch the APIC ID of the BSP in case we have a | |
1780 | * default configuration (or the MP table is broken). | |
1781 | */ | |
4401da61 YL |
1782 | new_apicid = read_apic_id(); |
1783 | if (boot_cpu_physical_apicid != new_apicid) { | |
1784 | boot_cpu_physical_apicid = new_apicid; | |
103428e5 CG |
1785 | /* |
1786 | * yeah -- we lie about apic_version | |
1787 | * in case if apic was disabled via boot option | |
1788 | * but it's not a problem for SMP compiled kernel | |
1789 | * since smp_sanity_check is prepared for such a case | |
1790 | * and disable smp mode | |
1791 | */ | |
4401da61 YL |
1792 | apic_version[new_apicid] = |
1793 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
08306ce6 | 1794 | } |
1da177e4 LT |
1795 | } |
1796 | ||
c0104d38 YL |
1797 | void __init register_lapic_address(unsigned long address) |
1798 | { | |
1799 | mp_lapic_addr = address; | |
1800 | ||
0450193b YL |
1801 | if (!x2apic_mode) { |
1802 | set_fixmap_nocache(FIX_APIC_BASE, address); | |
1803 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
1804 | APIC_BASE, mp_lapic_addr); | |
1805 | } | |
c0104d38 YL |
1806 | if (boot_cpu_physical_apicid == -1U) { |
1807 | boot_cpu_physical_apicid = read_apic_id(); | |
1808 | apic_version[boot_cpu_physical_apicid] = | |
1809 | GET_APIC_VERSION(apic_read(APIC_LVR)); | |
1810 | } | |
1811 | } | |
1812 | ||
56d91f13 | 1813 | int apic_version[MAX_LOCAL_APIC]; |
1b313f4a | 1814 | |
1da177e4 | 1815 | /* |
0e078e2f | 1816 | * Local APIC interrupts |
1da177e4 LT |
1817 | */ |
1818 | ||
0e078e2f TG |
1819 | /* |
1820 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1821 | */ | |
d786ad32 | 1822 | static void __smp_spurious_interrupt(u8 vector) |
1da177e4 | 1823 | { |
dc1528dd YL |
1824 | u32 v; |
1825 | ||
1da177e4 | 1826 | /* |
0e078e2f TG |
1827 | * Check if this really is a spurious interrupt and ACK it |
1828 | * if it is a vectored one. Just in case... | |
1829 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1830 | */ |
2414e021 JB |
1831 | v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); |
1832 | if (v & (1 << (vector & 0x1f))) | |
0e078e2f | 1833 | ack_APIC_irq(); |
c4d58cbd | 1834 | |
915b0d01 HS |
1835 | inc_irq_stat(irq_spurious_count); |
1836 | ||
dc1528dd | 1837 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
2414e021 JB |
1838 | pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " |
1839 | "should never happen.\n", vector, smp_processor_id()); | |
eddc0e92 SA |
1840 | } |
1841 | ||
1d9090e2 | 1842 | __visible void smp_spurious_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
1843 | { |
1844 | entering_irq(); | |
2414e021 | 1845 | __smp_spurious_interrupt(~regs->orig_ax); |
eddc0e92 | 1846 | exiting_irq(); |
0e078e2f | 1847 | } |
1da177e4 | 1848 | |
1d9090e2 | 1849 | __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) |
cf910e83 | 1850 | { |
2414e021 JB |
1851 | u8 vector = ~regs->orig_ax; |
1852 | ||
cf910e83 | 1853 | entering_irq(); |
2414e021 JB |
1854 | trace_spurious_apic_entry(vector); |
1855 | __smp_spurious_interrupt(vector); | |
1856 | trace_spurious_apic_exit(vector); | |
cf910e83 | 1857 | exiting_irq(); |
0e078e2f | 1858 | } |
1da177e4 | 1859 | |
0e078e2f TG |
1860 | /* |
1861 | * This interrupt should never happen with our APIC/SMP architecture | |
1862 | */ | |
d786ad32 | 1863 | static void __smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1864 | { |
60283df7 | 1865 | u32 v; |
2b398bd9 YS |
1866 | u32 i = 0; |
1867 | static const char * const error_interrupt_reason[] = { | |
1868 | "Send CS error", /* APIC Error Bit 0 */ | |
1869 | "Receive CS error", /* APIC Error Bit 1 */ | |
1870 | "Send accept error", /* APIC Error Bit 2 */ | |
1871 | "Receive accept error", /* APIC Error Bit 3 */ | |
1872 | "Redirectable IPI", /* APIC Error Bit 4 */ | |
1873 | "Send illegal vector", /* APIC Error Bit 5 */ | |
1874 | "Received illegal vector", /* APIC Error Bit 6 */ | |
1875 | "Illegal register address", /* APIC Error Bit 7 */ | |
1876 | }; | |
1da177e4 | 1877 | |
0e078e2f | 1878 | /* First tickle the hardware, only then report what went on. -- REW */ |
023de4a0 MR |
1879 | if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ |
1880 | apic_write(APIC_ESR, 0); | |
60283df7 | 1881 | v = apic_read(APIC_ESR); |
0e078e2f TG |
1882 | ack_APIC_irq(); |
1883 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1884 | |
60283df7 RW |
1885 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", |
1886 | smp_processor_id(), v); | |
2b398bd9 | 1887 | |
60283df7 RW |
1888 | v &= 0xff; |
1889 | while (v) { | |
1890 | if (v & 0x1) | |
2b398bd9 YS |
1891 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); |
1892 | i++; | |
60283df7 | 1893 | v >>= 1; |
4b8073e4 | 1894 | } |
2b398bd9 YS |
1895 | |
1896 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); | |
1897 | ||
eddc0e92 SA |
1898 | } |
1899 | ||
1d9090e2 | 1900 | __visible void smp_error_interrupt(struct pt_regs *regs) |
eddc0e92 SA |
1901 | { |
1902 | entering_irq(); | |
1903 | __smp_error_interrupt(regs); | |
1904 | exiting_irq(); | |
1da177e4 LT |
1905 | } |
1906 | ||
1d9090e2 | 1907 | __visible void smp_trace_error_interrupt(struct pt_regs *regs) |
cf910e83 SA |
1908 | { |
1909 | entering_irq(); | |
1910 | trace_error_apic_entry(ERROR_APIC_VECTOR); | |
1911 | __smp_error_interrupt(regs); | |
1912 | trace_error_apic_exit(ERROR_APIC_VECTOR); | |
1913 | exiting_irq(); | |
1da177e4 LT |
1914 | } |
1915 | ||
b5841765 | 1916 | /** |
36c9d674 CG |
1917 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1918 | */ | |
05f7e46d | 1919 | static void __init connect_bsp_APIC(void) |
b5841765 | 1920 | { |
36c9d674 CG |
1921 | #ifdef CONFIG_X86_32 |
1922 | if (pic_mode) { | |
1923 | /* | |
1924 | * Do not trust the local APIC being empty at bootup. | |
1925 | */ | |
1926 | clear_local_APIC(); | |
1927 | /* | |
1928 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1929 | * local APIC to INT and NMI lines. | |
1930 | */ | |
1931 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1932 | "enabling APIC mode.\n"); | |
c0eaa453 | 1933 | imcr_pic_to_apic(); |
36c9d674 CG |
1934 | } |
1935 | #endif | |
b5841765 GC |
1936 | } |
1937 | ||
274cfe59 CG |
1938 | /** |
1939 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1940 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1941 | * | |
1942 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1943 | * APIC is disabled. | |
1944 | */ | |
0e078e2f | 1945 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1946 | { |
1b4ee4e4 CG |
1947 | unsigned int value; |
1948 | ||
c177b0bc CG |
1949 | #ifdef CONFIG_X86_32 |
1950 | if (pic_mode) { | |
1951 | /* | |
1952 | * Put the board back into PIC mode (has an effect only on | |
1953 | * certain older boards). Note that APIC interrupts, including | |
1954 | * IPIs, won't work beyond this point! The only exception are | |
1955 | * INIT IPIs. | |
1956 | */ | |
1957 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1958 | "entering PIC mode.\n"); | |
c0eaa453 | 1959 | imcr_apic_to_pic(); |
c177b0bc CG |
1960 | return; |
1961 | } | |
1962 | #endif | |
1963 | ||
0e078e2f | 1964 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1965 | |
0e078e2f TG |
1966 | /* For the spurious interrupt use vector F, and enable it */ |
1967 | value = apic_read(APIC_SPIV); | |
1968 | value &= ~APIC_VECTOR_MASK; | |
1969 | value |= APIC_SPIV_APIC_ENABLED; | |
1970 | value |= 0xf; | |
1971 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1972 | |
0e078e2f TG |
1973 | if (!virt_wire_setup) { |
1974 | /* | |
1975 | * For LVT0 make it edge triggered, active high, | |
1976 | * external and enabled | |
1977 | */ | |
1978 | value = apic_read(APIC_LVT0); | |
1979 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1980 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1981 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1982 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1983 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1984 | apic_write(APIC_LVT0, value); | |
1985 | } else { | |
1986 | /* Disable LVT0 */ | |
1987 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1988 | } | |
b8ce3359 | 1989 | |
c177b0bc CG |
1990 | /* |
1991 | * For LVT1 make it edge triggered, active high, | |
1992 | * nmi and enabled | |
1993 | */ | |
0e078e2f TG |
1994 | value = apic_read(APIC_LVT1); |
1995 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1996 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1997 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1998 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1999 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
2000 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
2001 | } |
2002 | ||
7e1f85f9 | 2003 | int generic_processor_info(int apicid, int version) |
be8a5685 | 2004 | { |
14cb6dcf VG |
2005 | int cpu, max = nr_cpu_ids; |
2006 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, | |
2007 | phys_cpu_present_map); | |
2008 | ||
151e0c7d HD |
2009 | /* |
2010 | * boot_cpu_physical_apicid is designed to have the apicid | |
2011 | * returned by read_apic_id(), i.e, the apicid of the | |
2012 | * currently booting-up processor. However, on some platforms, | |
5b4d1dbc | 2013 | * it is temporarily modified by the apicid reported as BSP |
151e0c7d HD |
2014 | * through MP table. Concretely: |
2015 | * | |
2016 | * - arch/x86/kernel/mpparse.c: MP_processor_info() | |
2017 | * - arch/x86/mm/amdtopology.c: amd_numa_init() | |
151e0c7d HD |
2018 | * |
2019 | * This function is executed with the modified | |
2020 | * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel | |
2021 | * parameter doesn't work to disable APs on kdump 2nd kernel. | |
2022 | * | |
2023 | * Since fixing handling of boot_cpu_physical_apicid requires | |
2024 | * another discussion and tests on each platform, we leave it | |
2025 | * for now and here we use read_apic_id() directly in this | |
2026 | * function, generic_processor_info(). | |
2027 | */ | |
2028 | if (disabled_cpu_apicid != BAD_APICID && | |
2029 | disabled_cpu_apicid != read_apic_id() && | |
2030 | disabled_cpu_apicid == apicid) { | |
2031 | int thiscpu = num_processors + disabled_cpus; | |
2032 | ||
5b4d1dbc | 2033 | pr_warning("APIC: Disabling requested cpu." |
151e0c7d HD |
2034 | " Processor %d/0x%x ignored.\n", |
2035 | thiscpu, apicid); | |
2036 | ||
2037 | disabled_cpus++; | |
2038 | return -ENODEV; | |
2039 | } | |
2040 | ||
14cb6dcf VG |
2041 | /* |
2042 | * If boot cpu has not been detected yet, then only allow upto | |
2043 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu | |
2044 | */ | |
2045 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && | |
2046 | apicid != boot_cpu_physical_apicid) { | |
2047 | int thiscpu = max + disabled_cpus - 1; | |
2048 | ||
2049 | pr_warning( | |
3c8fad91 | 2050 | "APIC: NR_CPUS/possible_cpus limit of %i almost" |
14cb6dcf VG |
2051 | " reached. Keeping one slot for boot cpu." |
2052 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
2053 | ||
2054 | disabled_cpus++; | |
7e1f85f9 | 2055 | return -ENODEV; |
14cb6dcf | 2056 | } |
be8a5685 | 2057 | |
3b11ce7f | 2058 | if (num_processors >= nr_cpu_ids) { |
3b11ce7f MT |
2059 | int thiscpu = max + disabled_cpus; |
2060 | ||
2061 | pr_warning( | |
3c8fad91 | 2062 | "APIC: NR_CPUS/possible_cpus limit of %i reached." |
3b11ce7f MT |
2063 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); |
2064 | ||
2065 | disabled_cpus++; | |
7e1f85f9 | 2066 | return -EINVAL; |
be8a5685 AS |
2067 | } |
2068 | ||
2069 | num_processors++; | |
be8a5685 AS |
2070 | if (apicid == boot_cpu_physical_apicid) { |
2071 | /* | |
2072 | * x86_bios_cpu_apicid is required to have processors listed | |
2073 | * in same order as logical cpu numbers. Hence the first | |
2074 | * entry is BSP, and so on. | |
e5fea868 YL |
2075 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
2076 | * for BSP. | |
be8a5685 AS |
2077 | */ |
2078 | cpu = 0; | |
e5fea868 YL |
2079 | } else |
2080 | cpu = cpumask_next_zero(-1, cpu_present_mask); | |
2081 | ||
1f12e32f TG |
2082 | /* |
2083 | * This can happen on physical hotplug. The sanity check at boot time | |
2084 | * is done from native_smp_prepare_cpus() after num_possible_cpus() is | |
2085 | * established. | |
2086 | */ | |
2087 | if (topology_update_package_map(apicid, cpu) < 0) { | |
2088 | int thiscpu = max + disabled_cpus; | |
2089 | ||
3c8fad91 | 2090 | pr_warning("APIC: Package limit reached. Processor %d/0x%x ignored.\n", |
1f12e32f TG |
2091 | thiscpu, apicid); |
2092 | disabled_cpus++; | |
2093 | return -ENOSPC; | |
2094 | } | |
2095 | ||
e5fea868 YL |
2096 | /* |
2097 | * Validate version | |
2098 | */ | |
2099 | if (version == 0x0) { | |
2100 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", | |
2101 | cpu, apicid); | |
2102 | version = 0x10; | |
be8a5685 | 2103 | } |
e5fea868 YL |
2104 | apic_version[apicid] = version; |
2105 | ||
2106 | if (version != apic_version[boot_cpu_physical_apicid]) { | |
2107 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", | |
2108 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
2109 | } | |
2110 | ||
2111 | physid_set(apicid, phys_cpu_present_map); | |
e0da3364 YL |
2112 | if (apicid > max_physical_apicid) |
2113 | max_physical_apicid = apicid; | |
2114 | ||
3e5095d1 | 2115 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
2116 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
2117 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 2118 | #endif |
acb8bc09 TH |
2119 | #ifdef CONFIG_X86_32 |
2120 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = | |
2121 | apic->x86_32_early_logical_apicid(cpu); | |
2122 | #endif | |
1de88cd4 MT |
2123 | set_cpu_possible(cpu, true); |
2124 | set_cpu_present(cpu, true); | |
7e1f85f9 JL |
2125 | |
2126 | return cpu; | |
be8a5685 AS |
2127 | } |
2128 | ||
0c81c746 SS |
2129 | int hard_smp_processor_id(void) |
2130 | { | |
2131 | return read_apic_id(); | |
2132 | } | |
1dcdd3d1 IM |
2133 | |
2134 | void default_init_apic_ldr(void) | |
2135 | { | |
2136 | unsigned long val; | |
2137 | ||
2138 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
2139 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
2140 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
2141 | apic_write(APIC_LDR, val); | |
2142 | } | |
2143 | ||
ff164324 AG |
2144 | int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
2145 | const struct cpumask *andmask, | |
2146 | unsigned int *apicid) | |
6398268d | 2147 | { |
ea3807ea | 2148 | unsigned int cpu; |
6398268d AG |
2149 | |
2150 | for_each_cpu_and(cpu, cpumask, andmask) { | |
2151 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | |
2152 | break; | |
2153 | } | |
ff164324 | 2154 | |
ea3807ea | 2155 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
2156 | *apicid = per_cpu(x86_cpu_to_apicid, cpu); |
2157 | return 0; | |
a5a39156 | 2158 | } |
ea3807ea AG |
2159 | |
2160 | return -EINVAL; | |
6398268d AG |
2161 | } |
2162 | ||
1551df64 MT |
2163 | /* |
2164 | * Override the generic EOI implementation with an optimized version. | |
2165 | * Only called during early boot when only one CPU is active and with | |
2166 | * interrupts disabled, so we know this does not race with actual APIC driver | |
2167 | * use. | |
2168 | */ | |
2169 | void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) | |
2170 | { | |
2171 | struct apic **drv; | |
2172 | ||
2173 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { | |
2174 | /* Should happen once for each apic */ | |
2175 | WARN_ON((*drv)->eoi_write == eoi_write); | |
2176 | (*drv)->eoi_write = eoi_write; | |
2177 | } | |
2178 | } | |
2179 | ||
374aab33 | 2180 | static void __init apic_bsp_up_setup(void) |
05f7e46d | 2181 | { |
374aab33 TG |
2182 | #ifdef CONFIG_X86_64 |
2183 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); | |
2184 | #else | |
05f7e46d | 2185 | /* |
374aab33 TG |
2186 | * Hack: In case of kdump, after a crash, kernel might be booting |
2187 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
2188 | * might be zero if read from MP tables. Get it from LAPIC. | |
05f7e46d | 2189 | */ |
374aab33 TG |
2190 | # ifdef CONFIG_CRASH_DUMP |
2191 | boot_cpu_physical_apicid = read_apic_id(); | |
2192 | # endif | |
2193 | #endif | |
2194 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
05f7e46d TG |
2195 | } |
2196 | ||
2197 | /** | |
2198 | * apic_bsp_setup - Setup function for local apic and io-apic | |
374aab33 | 2199 | * @upmode: Force UP mode (for APIC_init_uniprocessor) |
05f7e46d TG |
2200 | * |
2201 | * Returns: | |
2202 | * apic_id of BSP APIC | |
2203 | */ | |
374aab33 | 2204 | int __init apic_bsp_setup(bool upmode) |
05f7e46d TG |
2205 | { |
2206 | int id; | |
2207 | ||
2208 | connect_bsp_APIC(); | |
374aab33 TG |
2209 | if (upmode) |
2210 | apic_bsp_up_setup(); | |
05f7e46d TG |
2211 | setup_local_APIC(); |
2212 | ||
2213 | if (x2apic_mode) | |
2214 | id = apic_read(APIC_LDR); | |
2215 | else | |
2216 | id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
2217 | ||
2218 | enable_IO_APIC(); | |
374aab33 TG |
2219 | end_local_APIC_setup(); |
2220 | irq_remap_enable_fault_handling(); | |
05f7e46d | 2221 | setup_IO_APIC(); |
9c4d9c73 TG |
2222 | /* Setup local timer */ |
2223 | x86_init.timers.setup_percpu_clockev(); | |
05f7e46d TG |
2224 | return id; |
2225 | } | |
2226 | ||
e714a91f TG |
2227 | /* |
2228 | * This initializes the IO-APIC and APIC hardware if this is | |
2229 | * a UP kernel. | |
2230 | */ | |
2231 | int __init APIC_init_uniprocessor(void) | |
2232 | { | |
2233 | if (disable_apic) { | |
2234 | pr_info("Apic disabled\n"); | |
2235 | return -1; | |
2236 | } | |
2237 | #ifdef CONFIG_X86_64 | |
93984fbd | 2238 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
e714a91f TG |
2239 | disable_apic = 1; |
2240 | pr_info("Apic disabled by BIOS\n"); | |
2241 | return -1; | |
2242 | } | |
2243 | #else | |
93984fbd | 2244 | if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC)) |
e714a91f TG |
2245 | return -1; |
2246 | ||
2247 | /* | |
2248 | * Complain if the BIOS pretends there is one. | |
2249 | */ | |
93984fbd | 2250 | if (!boot_cpu_has(X86_FEATURE_APIC) && |
e714a91f TG |
2251 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
2252 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", | |
2253 | boot_cpu_physical_apicid); | |
2254 | return -1; | |
2255 | } | |
2256 | #endif | |
2257 | ||
374aab33 TG |
2258 | if (!smp_found_config) |
2259 | disable_ioapic_support(); | |
e714a91f | 2260 | |
374aab33 | 2261 | default_setup_apic_routing(); |
374aab33 | 2262 | apic_bsp_setup(true); |
e714a91f TG |
2263 | return 0; |
2264 | } | |
2265 | ||
30b8b006 TG |
2266 | #ifdef CONFIG_UP_LATE_INIT |
2267 | void __init up_late_init(void) | |
2268 | { | |
2269 | APIC_init_uniprocessor(); | |
2270 | } | |
2271 | #endif | |
2272 | ||
89039b37 | 2273 | /* |
0e078e2f | 2274 | * Power management |
89039b37 | 2275 | */ |
0e078e2f TG |
2276 | #ifdef CONFIG_PM |
2277 | ||
2278 | static struct { | |
274cfe59 CG |
2279 | /* |
2280 | * 'active' is true if the local APIC was enabled by us and | |
2281 | * not the BIOS; this signifies that we are also responsible | |
2282 | * for disabling it before entering apm/acpi suspend | |
2283 | */ | |
0e078e2f TG |
2284 | int active; |
2285 | /* r/w apic fields */ | |
2286 | unsigned int apic_id; | |
2287 | unsigned int apic_taskpri; | |
2288 | unsigned int apic_ldr; | |
2289 | unsigned int apic_dfr; | |
2290 | unsigned int apic_spiv; | |
2291 | unsigned int apic_lvtt; | |
2292 | unsigned int apic_lvtpc; | |
2293 | unsigned int apic_lvt0; | |
2294 | unsigned int apic_lvt1; | |
2295 | unsigned int apic_lvterr; | |
2296 | unsigned int apic_tmict; | |
2297 | unsigned int apic_tdcr; | |
2298 | unsigned int apic_thmr; | |
42baa258 | 2299 | unsigned int apic_cmci; |
0e078e2f TG |
2300 | } apic_pm_state; |
2301 | ||
f3c6ea1b | 2302 | static int lapic_suspend(void) |
0e078e2f TG |
2303 | { |
2304 | unsigned long flags; | |
2305 | int maxlvt; | |
89039b37 | 2306 | |
0e078e2f TG |
2307 | if (!apic_pm_state.active) |
2308 | return 0; | |
89039b37 | 2309 | |
0e078e2f | 2310 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 2311 | |
2d7a66d0 | 2312 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
2313 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
2314 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
2315 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
2316 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
2317 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
2318 | if (maxlvt >= 4) | |
2319 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
2320 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
2321 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
2322 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
2323 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
2324 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
4efc0670 | 2325 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2326 | if (maxlvt >= 5) |
2327 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2328 | #endif | |
42baa258 JG |
2329 | #ifdef CONFIG_X86_MCE_INTEL |
2330 | if (maxlvt >= 6) | |
2331 | apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); | |
2332 | #endif | |
24968cfd | 2333 | |
0e078e2f TG |
2334 | local_irq_save(flags); |
2335 | disable_local_APIC(); | |
fc1edaf9 | 2336 | |
70733e0c | 2337 | irq_remapping_disable(); |
fc1edaf9 | 2338 | |
0e078e2f TG |
2339 | local_irq_restore(flags); |
2340 | return 0; | |
1da177e4 LT |
2341 | } |
2342 | ||
f3c6ea1b | 2343 | static void lapic_resume(void) |
1da177e4 | 2344 | { |
0e078e2f TG |
2345 | unsigned int l, h; |
2346 | unsigned long flags; | |
31dce14a | 2347 | int maxlvt; |
b24696bc | 2348 | |
0e078e2f | 2349 | if (!apic_pm_state.active) |
f3c6ea1b | 2350 | return; |
89b831ef | 2351 | |
0e078e2f | 2352 | local_irq_save(flags); |
336224ba JR |
2353 | |
2354 | /* | |
2355 | * IO-APIC and PIC have their own resume routines. | |
2356 | * We just mask them here to make sure the interrupt | |
2357 | * subsystem is completely quiet while we enable x2apic | |
2358 | * and interrupt-remapping. | |
2359 | */ | |
2360 | mask_ioapic_entries(); | |
2361 | legacy_pic->mask_all(); | |
92206c90 | 2362 | |
659006bf TG |
2363 | if (x2apic_mode) { |
2364 | __x2apic_enable(); | |
2365 | } else { | |
92206c90 CG |
2366 | /* |
2367 | * Make sure the APICBASE points to the right address | |
2368 | * | |
2369 | * FIXME! This will be wrong if we ever support suspend on | |
2370 | * SMP! We'll need to do this as part of the CPU restore! | |
2371 | */ | |
cbf2829b BD |
2372 | if (boot_cpu_data.x86 >= 6) { |
2373 | rdmsr(MSR_IA32_APICBASE, l, h); | |
2374 | l &= ~MSR_IA32_APICBASE_BASE; | |
2375 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2376 | wrmsr(MSR_IA32_APICBASE, l, h); | |
2377 | } | |
d5e629a6 | 2378 | } |
6e1cb38a | 2379 | |
b24696bc | 2380 | maxlvt = lapic_get_maxlvt(); |
0e078e2f TG |
2381 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2382 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2383 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2384 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2385 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2386 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2387 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2388 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
42baa258 | 2389 | #ifdef CONFIG_X86_THERMAL_VECTOR |
0e078e2f TG |
2390 | if (maxlvt >= 5) |
2391 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
42baa258 JG |
2392 | #endif |
2393 | #ifdef CONFIG_X86_MCE_INTEL | |
2394 | if (maxlvt >= 6) | |
2395 | apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); | |
0e078e2f TG |
2396 | #endif |
2397 | if (maxlvt >= 4) | |
2398 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2399 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2400 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2401 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2402 | apic_write(APIC_ESR, 0); | |
2403 | apic_read(APIC_ESR); | |
2404 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2405 | apic_write(APIC_ESR, 0); | |
2406 | apic_read(APIC_ESR); | |
92206c90 | 2407 | |
70733e0c | 2408 | irq_remapping_reenable(x2apic_mode); |
31dce14a | 2409 | |
0e078e2f | 2410 | local_irq_restore(flags); |
0e078e2f | 2411 | } |
b8ce3359 | 2412 | |
274cfe59 CG |
2413 | /* |
2414 | * This device has no shutdown method - fully functioning local APICs | |
2415 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2416 | */ | |
2417 | ||
f3c6ea1b | 2418 | static struct syscore_ops lapic_syscore_ops = { |
0e078e2f TG |
2419 | .resume = lapic_resume, |
2420 | .suspend = lapic_suspend, | |
2421 | }; | |
b8ce3359 | 2422 | |
148f9bb8 | 2423 | static void apic_pm_activate(void) |
0e078e2f TG |
2424 | { |
2425 | apic_pm_state.active = 1; | |
1da177e4 LT |
2426 | } |
2427 | ||
0e078e2f | 2428 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2429 | { |
0e078e2f | 2430 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
93984fbd | 2431 | if (boot_cpu_has(X86_FEATURE_APIC)) |
f3c6ea1b | 2432 | register_syscore_ops(&lapic_syscore_ops); |
e83a5fdc | 2433 | |
f3c6ea1b | 2434 | return 0; |
1da177e4 | 2435 | } |
b24696bc FY |
2436 | |
2437 | /* local apic needs to resume before other devices access its registers. */ | |
2438 | core_initcall(init_lapic_sysfs); | |
0e078e2f TG |
2439 | |
2440 | #else /* CONFIG_PM */ | |
2441 | ||
2442 | static void apic_pm_activate(void) { } | |
2443 | ||
2444 | #endif /* CONFIG_PM */ | |
1da177e4 | 2445 | |
f28c0ae2 | 2446 | #ifdef CONFIG_X86_64 |
e0e42142 | 2447 | |
148f9bb8 PG |
2448 | static int multi_checked; |
2449 | static int multi; | |
e0e42142 | 2450 | |
148f9bb8 | 2451 | static int set_multi(const struct dmi_system_id *d) |
e0e42142 YL |
2452 | { |
2453 | if (multi) | |
2454 | return 0; | |
6f0aced6 | 2455 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
e0e42142 YL |
2456 | multi = 1; |
2457 | return 0; | |
2458 | } | |
2459 | ||
148f9bb8 | 2460 | static const struct dmi_system_id multi_dmi_table[] = { |
e0e42142 YL |
2461 | { |
2462 | .callback = set_multi, | |
2463 | .ident = "IBM System Summit2", | |
2464 | .matches = { | |
2465 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), | |
2466 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), | |
2467 | }, | |
2468 | }, | |
2469 | {} | |
2470 | }; | |
2471 | ||
148f9bb8 | 2472 | static void dmi_check_multi(void) |
e0e42142 YL |
2473 | { |
2474 | if (multi_checked) | |
2475 | return; | |
2476 | ||
2477 | dmi_check_system(multi_dmi_table); | |
2478 | multi_checked = 1; | |
2479 | } | |
2480 | ||
2481 | /* | |
2482 | * apic_is_clustered_box() -- Check if we can expect good TSC | |
2483 | * | |
2484 | * Thus far, the major user of this is IBM's Summit2 series: | |
2485 | * Clustered boxes may have unsynced TSC problems if they are | |
2486 | * multi-chassis. | |
2487 | * Use DMI to check them | |
2488 | */ | |
148f9bb8 | 2489 | int apic_is_clustered_box(void) |
e0e42142 YL |
2490 | { |
2491 | dmi_check_multi(); | |
411cf9ee | 2492 | return multi; |
1da177e4 | 2493 | } |
f28c0ae2 | 2494 | #endif |
1da177e4 LT |
2495 | |
2496 | /* | |
0e078e2f | 2497 | * APIC command line parameters |
1da177e4 | 2498 | */ |
789fa735 | 2499 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2500 | { |
1da177e4 | 2501 | disable_apic = 1; |
9175fc06 | 2502 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2503 | return 0; |
2504 | } | |
2505 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2506 | |
2c8c0e6b | 2507 | /* same as disableapic, for compatibility */ |
789fa735 | 2508 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2509 | { |
789fa735 | 2510 | return setup_disableapic(arg); |
6935d1f9 | 2511 | } |
2c8c0e6b | 2512 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2513 | |
2e7c2838 LT |
2514 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2515 | { | |
2516 | local_apic_timer_c2_ok = 1; | |
2517 | return 0; | |
2518 | } | |
2519 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2520 | ||
36fef094 | 2521 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2522 | { |
1da177e4 | 2523 | disable_apic_timer = 1; |
36fef094 | 2524 | return 0; |
6935d1f9 | 2525 | } |
36fef094 CG |
2526 | early_param("noapictimer", parse_disable_apic_timer); |
2527 | ||
2528 | static int __init parse_nolapic_timer(char *arg) | |
2529 | { | |
2530 | disable_apic_timer = 1; | |
2531 | return 0; | |
6935d1f9 | 2532 | } |
36fef094 | 2533 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2534 | |
79af9bec CG |
2535 | static int __init apic_set_verbosity(char *arg) |
2536 | { | |
2537 | if (!arg) { | |
2538 | #ifdef CONFIG_X86_64 | |
2539 | skip_ioapic_setup = 0; | |
79af9bec CG |
2540 | return 0; |
2541 | #endif | |
2542 | return -EINVAL; | |
2543 | } | |
2544 | ||
2545 | if (strcmp("debug", arg) == 0) | |
2546 | apic_verbosity = APIC_DEBUG; | |
2547 | else if (strcmp("verbose", arg) == 0) | |
2548 | apic_verbosity = APIC_VERBOSE; | |
2549 | else { | |
ba21ebb6 | 2550 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2551 | " use apic=verbose or apic=debug\n", arg); |
2552 | return -EINVAL; | |
2553 | } | |
2554 | ||
2555 | return 0; | |
2556 | } | |
2557 | early_param("apic", apic_set_verbosity); | |
2558 | ||
1e934dda YL |
2559 | static int __init lapic_insert_resource(void) |
2560 | { | |
2561 | if (!apic_phys) | |
2562 | return -1; | |
2563 | ||
2564 | /* Put local APIC into the resource map. */ | |
2565 | lapic_resource.start = apic_phys; | |
2566 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2567 | insert_resource(&iomem_resource, &lapic_resource); | |
2568 | ||
2569 | return 0; | |
2570 | } | |
2571 | ||
2572 | /* | |
2573 | * need call insert after e820_reserve_resources() | |
2574 | * that is using request_resource | |
2575 | */ | |
2576 | late_initcall(lapic_insert_resource); | |
151e0c7d HD |
2577 | |
2578 | static int __init apic_set_disabled_cpu_apicid(char *arg) | |
2579 | { | |
2580 | if (!arg || !get_option(&arg, &disabled_cpu_apicid)) | |
2581 | return -EINVAL; | |
2582 | ||
2583 | return 0; | |
2584 | } | |
2585 | early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); | |
b7c4948e HK |
2586 | |
2587 | static int __init apic_set_extnmi(char *arg) | |
2588 | { | |
2589 | if (!arg) | |
2590 | return -EINVAL; | |
2591 | ||
2592 | if (!strncmp("all", arg, 3)) | |
2593 | apic_extnmi = APIC_EXTNMI_ALL; | |
2594 | else if (!strncmp("none", arg, 4)) | |
2595 | apic_extnmi = APIC_EXTNMI_NONE; | |
2596 | else if (!strncmp("bsp", arg, 3)) | |
2597 | apic_extnmi = APIC_EXTNMI_BSP; | |
2598 | else { | |
2599 | pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); | |
2600 | return -EINVAL; | |
2601 | } | |
2602 | ||
2603 | return 0; | |
2604 | } | |
2605 | early_param("apic_extnmi", apic_set_extnmi); |