Commit | Line | Data |
---|---|---|
c140df97 | 1 | /* |
1da177e4 | 2 | * Firmware replacement code. |
c140df97 | 3 | * |
8caac563 PM |
4 | * Work around broken BIOSes that don't set an aperture, only set the |
5 | * aperture in the AGP bridge, or set too small aperture. | |
6 | * | |
c140df97 IM |
7 | * If all fails map the aperture over some low memory. This is cheaper than |
8 | * doing bounce buffering. The memory is lost. This is done at early boot | |
9 | * because only the bootmem allocator can allocate 32+MB. | |
10 | * | |
1da177e4 | 11 | * Copyright 2002 Andi Kleen, SuSE Labs. |
1da177e4 | 12 | */ |
1da177e4 LT |
13 | #include <linux/kernel.h> |
14 | #include <linux/types.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/bootmem.h> | |
17 | #include <linux/mmzone.h> | |
18 | #include <linux/pci_ids.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/bitops.h> | |
56dd669a | 21 | #include <linux/ioport.h> |
2050d45d | 22 | #include <linux/suspend.h> |
acde31dc | 23 | #include <linux/kmemleak.h> |
1da177e4 LT |
24 | #include <asm/e820.h> |
25 | #include <asm/io.h> | |
46a7fa27 | 26 | #include <asm/iommu.h> |
395624fc | 27 | #include <asm/gart.h> |
1da177e4 | 28 | #include <asm/pci-direct.h> |
ca8642f6 | 29 | #include <asm/dma.h> |
a32073bf | 30 | #include <asm/k8.h> |
de957628 | 31 | #include <asm/x86_init.h> |
1da177e4 | 32 | |
0440d4c0 | 33 | int gart_iommu_aperture; |
7de6a4cd PM |
34 | int gart_iommu_aperture_disabled __initdata; |
35 | int gart_iommu_aperture_allowed __initdata; | |
1da177e4 LT |
36 | |
37 | int fallback_aper_order __initdata = 1; /* 64MB */ | |
7de6a4cd | 38 | int fallback_aper_force __initdata; |
1da177e4 LT |
39 | |
40 | int fix_aperture __initdata = 1; | |
41 | ||
55c0d721 YL |
42 | struct bus_dev_range { |
43 | int bus; | |
44 | int dev_base; | |
45 | int dev_limit; | |
46 | }; | |
47 | ||
48 | static struct bus_dev_range bus_dev_ranges[] __initdata = { | |
49 | { 0x00, 0x18, 0x20}, | |
50 | { 0xff, 0x00, 0x20}, | |
51 | { 0xfe, 0x00, 0x20} | |
52 | }; | |
53 | ||
56dd669a AD |
54 | static struct resource gart_resource = { |
55 | .name = "GART", | |
56 | .flags = IORESOURCE_MEM, | |
57 | }; | |
58 | ||
59 | static void __init insert_aperture_resource(u32 aper_base, u32 aper_size) | |
60 | { | |
61 | gart_resource.start = aper_base; | |
62 | gart_resource.end = aper_base + aper_size - 1; | |
63 | insert_resource(&iomem_resource, &gart_resource); | |
64 | } | |
65 | ||
42442ed5 AM |
66 | /* This code runs before the PCI subsystem is initialized, so just |
67 | access the northbridge directly. */ | |
1da177e4 | 68 | |
c140df97 | 69 | static u32 __init allocate_aperture(void) |
1da177e4 | 70 | { |
1da177e4 | 71 | u32 aper_size; |
c140df97 | 72 | void *p; |
1da177e4 | 73 | |
7677b2ef YL |
74 | /* aper_size should <= 1G */ |
75 | if (fallback_aper_order > 5) | |
76 | fallback_aper_order = 5; | |
c140df97 | 77 | aper_size = (32 * 1024 * 1024) << fallback_aper_order; |
1da177e4 | 78 | |
c140df97 IM |
79 | /* |
80 | * Aperture has to be naturally aligned. This means a 2GB aperture | |
81 | * won't have much chance of finding a place in the lower 4GB of | |
82 | * memory. Unfortunately we cannot move it up because that would | |
83 | * make the IOMMU useless. | |
1da177e4 | 84 | */ |
7677b2ef YL |
85 | /* |
86 | * using 512M as goal, in case kexec will load kernel_big | |
87 | * that will do the on position decompress, and could overlap with | |
88 | * that positon with gart that is used. | |
89 | * sequende: | |
90 | * kernel_small | |
91 | * ==> kexec (with kdump trigger path or previous doesn't shutdown gart) | |
92 | * ==> kernel_small(gart area become e820_reserved) | |
93 | * ==> kexec (with kdump trigger path or previous doesn't shutdown gart) | |
94 | * ==> kerne_big (uncompressed size will be big than 64M or 128M) | |
95 | * so don't use 512M below as gart iommu, leave the space for kernel | |
96 | * code for safe | |
97 | */ | |
98 | p = __alloc_bootmem_nopanic(aper_size, aper_size, 512ULL<<20); | |
acde31dc CM |
99 | /* |
100 | * Kmemleak should not scan this block as it may not be mapped via the | |
101 | * kernel direct mapping. | |
102 | */ | |
103 | kmemleak_ignore(p); | |
1da177e4 | 104 | if (!p || __pa(p)+aper_size > 0xffffffff) { |
31183ba8 IM |
105 | printk(KERN_ERR |
106 | "Cannot allocate aperture memory hole (%p,%uK)\n", | |
107 | p, aper_size>>10); | |
1da177e4 | 108 | if (p) |
82d1bb72 | 109 | free_bootmem(__pa(p), aper_size); |
1da177e4 LT |
110 | return 0; |
111 | } | |
31183ba8 IM |
112 | printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n", |
113 | aper_size >> 10, __pa(p)); | |
56dd669a | 114 | insert_aperture_resource((u32)__pa(p), aper_size); |
2050d45d PM |
115 | register_nosave_region((u32)__pa(p) >> PAGE_SHIFT, |
116 | (u32)__pa(p+aper_size) >> PAGE_SHIFT); | |
c140df97 IM |
117 | |
118 | return (u32)__pa(p); | |
1da177e4 LT |
119 | } |
120 | ||
1da177e4 | 121 | |
42442ed5 | 122 | /* Find a PCI capability */ |
dd564d0c | 123 | static u32 __init find_cap(int bus, int slot, int func, int cap) |
c140df97 | 124 | { |
1da177e4 | 125 | int bytes; |
c140df97 IM |
126 | u8 pos; |
127 | ||
55c0d721 | 128 | if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & |
c140df97 | 129 | PCI_STATUS_CAP_LIST)) |
1da177e4 | 130 | return 0; |
c140df97 | 131 | |
55c0d721 | 132 | pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); |
c140df97 | 133 | for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { |
1da177e4 | 134 | u8 id; |
c140df97 IM |
135 | |
136 | pos &= ~3; | |
55c0d721 | 137 | id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); |
1da177e4 LT |
138 | if (id == 0xff) |
139 | break; | |
c140df97 IM |
140 | if (id == cap) |
141 | return pos; | |
55c0d721 | 142 | pos = read_pci_config_byte(bus, slot, func, |
c140df97 IM |
143 | pos+PCI_CAP_LIST_NEXT); |
144 | } | |
1da177e4 | 145 | return 0; |
c140df97 | 146 | } |
1da177e4 LT |
147 | |
148 | /* Read a standard AGPv3 bridge header */ | |
dd564d0c | 149 | static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order) |
c140df97 | 150 | { |
1da177e4 LT |
151 | u32 apsize; |
152 | u32 apsizereg; | |
153 | int nbits; | |
154 | u32 aper_low, aper_hi; | |
155 | u64 aper; | |
1edc1ab3 | 156 | u32 old_order; |
1da177e4 | 157 | |
55c0d721 YL |
158 | printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func); |
159 | apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14); | |
1da177e4 | 160 | if (apsizereg == 0xffffffff) { |
31183ba8 | 161 | printk(KERN_ERR "APSIZE in AGP bridge unreadable\n"); |
1da177e4 LT |
162 | return 0; |
163 | } | |
164 | ||
1edc1ab3 YL |
165 | /* old_order could be the value from NB gart setting */ |
166 | old_order = *order; | |
167 | ||
1da177e4 LT |
168 | apsize = apsizereg & 0xfff; |
169 | /* Some BIOS use weird encodings not in the AGPv3 table. */ | |
c140df97 IM |
170 | if (apsize & 0xff) |
171 | apsize |= 0xf00; | |
1da177e4 LT |
172 | nbits = hweight16(apsize); |
173 | *order = 7 - nbits; | |
174 | if ((int)*order < 0) /* < 32MB */ | |
175 | *order = 0; | |
c140df97 | 176 | |
55c0d721 YL |
177 | aper_low = read_pci_config(bus, slot, func, 0x10); |
178 | aper_hi = read_pci_config(bus, slot, func, 0x14); | |
1da177e4 LT |
179 | aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); |
180 | ||
1edc1ab3 YL |
181 | /* |
182 | * On some sick chips, APSIZE is 0. It means it wants 4G | |
183 | * so let double check that order, and lets trust AMD NB settings: | |
184 | */ | |
8c9fd91a YL |
185 | printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n", |
186 | aper, 32 << old_order); | |
187 | if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) { | |
1edc1ab3 YL |
188 | printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n", |
189 | 32 << *order, apsizereg); | |
190 | *order = old_order; | |
191 | } | |
192 | ||
31183ba8 IM |
193 | printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n", |
194 | aper, 32 << *order, apsizereg); | |
1da177e4 | 195 | |
8c9fd91a | 196 | if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20)) |
c140df97 IM |
197 | return 0; |
198 | return (u32)aper; | |
199 | } | |
1da177e4 | 200 | |
c140df97 IM |
201 | /* |
202 | * Look for an AGP bridge. Windows only expects the aperture in the | |
203 | * AGP bridge and some BIOS forget to initialize the Northbridge too. | |
204 | * Work around this here. | |
205 | * | |
206 | * Do an PCI bus scan by hand because we're running before the PCI | |
207 | * subsystem. | |
208 | * | |
209 | * All K8 AGP bridges are AGPv3 compliant, so we can do this scan | |
210 | * generically. It's probably overkill to always scan all slots because | |
211 | * the AGP bridges should be always an own bus on the HT hierarchy, | |
212 | * but do it here for future safety. | |
213 | */ | |
dd564d0c | 214 | static u32 __init search_agp_bridge(u32 *order, int *valid_agp) |
1da177e4 | 215 | { |
55c0d721 | 216 | int bus, slot, func; |
1da177e4 LT |
217 | |
218 | /* Poor man's PCI discovery */ | |
55c0d721 | 219 | for (bus = 0; bus < 256; bus++) { |
c140df97 IM |
220 | for (slot = 0; slot < 32; slot++) { |
221 | for (func = 0; func < 8; func++) { | |
1da177e4 LT |
222 | u32 class, cap; |
223 | u8 type; | |
55c0d721 | 224 | class = read_pci_config(bus, slot, func, |
1da177e4 LT |
225 | PCI_CLASS_REVISION); |
226 | if (class == 0xffffffff) | |
c140df97 IM |
227 | break; |
228 | ||
229 | switch (class >> 16) { | |
1da177e4 LT |
230 | case PCI_CLASS_BRIDGE_HOST: |
231 | case PCI_CLASS_BRIDGE_OTHER: /* needed? */ | |
232 | /* AGP bridge? */ | |
55c0d721 | 233 | cap = find_cap(bus, slot, func, |
c140df97 | 234 | PCI_CAP_ID_AGP); |
1da177e4 LT |
235 | if (!cap) |
236 | break; | |
c140df97 | 237 | *valid_agp = 1; |
55c0d721 | 238 | return read_agp(bus, slot, func, cap, |
c140df97 IM |
239 | order); |
240 | } | |
241 | ||
1da177e4 | 242 | /* No multi-function device? */ |
55c0d721 | 243 | type = read_pci_config_byte(bus, slot, func, |
1da177e4 LT |
244 | PCI_HEADER_TYPE); |
245 | if (!(type & 0x80)) | |
246 | break; | |
c140df97 IM |
247 | } |
248 | } | |
1da177e4 | 249 | } |
31183ba8 | 250 | printk(KERN_INFO "No AGP bridge found\n"); |
c140df97 | 251 | |
1da177e4 LT |
252 | return 0; |
253 | } | |
254 | ||
aaf23042 YL |
255 | static int gart_fix_e820 __initdata = 1; |
256 | ||
257 | static int __init parse_gart_mem(char *p) | |
258 | { | |
259 | if (!p) | |
260 | return -EINVAL; | |
261 | ||
262 | if (!strncmp(p, "off", 3)) | |
263 | gart_fix_e820 = 0; | |
264 | else if (!strncmp(p, "on", 2)) | |
265 | gart_fix_e820 = 1; | |
266 | ||
267 | return 0; | |
268 | } | |
269 | early_param("gart_fix_e820", parse_gart_mem); | |
270 | ||
271 | void __init early_gart_iommu_check(void) | |
272 | { | |
273 | /* | |
274 | * in case it is enabled before, esp for kexec/kdump, | |
275 | * previous kernel already enable that. memset called | |
276 | * by allocate_aperture/__alloc_bootmem_nopanic cause restart. | |
277 | * or second kernel have different position for GART hole. and new | |
278 | * kernel could use hole as RAM that is still used by GART set by | |
279 | * first kernel | |
280 | * or BIOS forget to put that in reserved. | |
281 | * try to update e820 to make that region as reserved. | |
282 | */ | |
f3eee542 YL |
283 | u32 agp_aper_base = 0, agp_aper_order = 0; |
284 | int i, fix, slot, valid_agp = 0; | |
aaf23042 YL |
285 | u32 ctl; |
286 | u32 aper_size = 0, aper_order = 0, last_aper_order = 0; | |
287 | u64 aper_base = 0, last_aper_base = 0; | |
fa5b8a30 | 288 | int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0; |
aaf23042 YL |
289 | |
290 | if (!early_pci_allowed()) | |
291 | return; | |
292 | ||
fa5b8a30 | 293 | /* This is mostly duplicate of iommu_hole_init */ |
f3eee542 YL |
294 | agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp); |
295 | ||
aaf23042 | 296 | fix = 0; |
55c0d721 YL |
297 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
298 | int bus; | |
299 | int dev_base, dev_limit; | |
300 | ||
301 | bus = bus_dev_ranges[i].bus; | |
302 | dev_base = bus_dev_ranges[i].dev_base; | |
303 | dev_limit = bus_dev_ranges[i].dev_limit; | |
304 | ||
305 | for (slot = dev_base; slot < dev_limit; slot++) { | |
306 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
307 | continue; | |
308 | ||
309 | ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); | |
310 | aper_enabled = ctl & AMD64_GARTEN; | |
311 | aper_order = (ctl >> 1) & 7; | |
312 | aper_size = (32 * 1024 * 1024) << aper_order; | |
313 | aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; | |
314 | aper_base <<= 25; | |
315 | ||
fa5b8a30 PM |
316 | if (last_valid) { |
317 | if ((aper_order != last_aper_order) || | |
318 | (aper_base != last_aper_base) || | |
319 | (aper_enabled != last_aper_enabled)) { | |
320 | fix = 1; | |
321 | break; | |
322 | } | |
55c0d721 | 323 | } |
fa5b8a30 | 324 | |
55c0d721 YL |
325 | last_aper_order = aper_order; |
326 | last_aper_base = aper_base; | |
327 | last_aper_enabled = aper_enabled; | |
fa5b8a30 | 328 | last_valid = 1; |
aaf23042 | 329 | } |
aaf23042 YL |
330 | } |
331 | ||
332 | if (!fix && !aper_enabled) | |
333 | return; | |
334 | ||
335 | if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL) | |
336 | fix = 1; | |
337 | ||
338 | if (gart_fix_e820 && !fix && aper_enabled) { | |
0754557d YL |
339 | if (e820_any_mapped(aper_base, aper_base + aper_size, |
340 | E820_RAM)) { | |
0abbc78a | 341 | /* reserve it, so we can reuse it in second kernel */ |
aaf23042 | 342 | printk(KERN_INFO "update e820 for GART\n"); |
d0be6bde | 343 | e820_add_region(aper_base, aper_size, E820_RESERVED); |
aaf23042 YL |
344 | update_e820(); |
345 | } | |
aaf23042 YL |
346 | } |
347 | ||
f3eee542 | 348 | if (valid_agp) |
4f384f8b PM |
349 | return; |
350 | ||
f3eee542 | 351 | /* disable them all at first */ |
55c0d721 YL |
352 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
353 | int bus; | |
354 | int dev_base, dev_limit; | |
355 | ||
356 | bus = bus_dev_ranges[i].bus; | |
357 | dev_base = bus_dev_ranges[i].dev_base; | |
358 | dev_limit = bus_dev_ranges[i].dev_limit; | |
aaf23042 | 359 | |
55c0d721 YL |
360 | for (slot = dev_base; slot < dev_limit; slot++) { |
361 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
362 | continue; | |
363 | ||
364 | ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); | |
365 | ctl &= ~AMD64_GARTEN; | |
366 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); | |
367 | } | |
aaf23042 YL |
368 | } |
369 | ||
370 | } | |
371 | ||
8c9fd91a YL |
372 | static int __initdata printed_gart_size_msg; |
373 | ||
0440d4c0 | 374 | void __init gart_iommu_hole_init(void) |
c140df97 | 375 | { |
8c9fd91a | 376 | u32 agp_aper_base = 0, agp_aper_order = 0; |
50895c5d | 377 | u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0; |
1da177e4 | 378 | u64 aper_base, last_aper_base = 0; |
55c0d721 YL |
379 | int fix, slot, valid_agp = 0; |
380 | int i, node; | |
1da177e4 | 381 | |
0440d4c0 JR |
382 | if (gart_iommu_aperture_disabled || !fix_aperture || |
383 | !early_pci_allowed()) | |
1da177e4 LT |
384 | return; |
385 | ||
753811dc | 386 | printk(KERN_INFO "Checking aperture...\n"); |
1da177e4 | 387 | |
8c9fd91a YL |
388 | if (!fallback_aper_force) |
389 | agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp); | |
390 | ||
1da177e4 | 391 | fix = 0; |
47db4c3e | 392 | node = 0; |
55c0d721 YL |
393 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
394 | int bus; | |
395 | int dev_base, dev_limit; | |
4b83873d | 396 | u32 ctl; |
55c0d721 YL |
397 | |
398 | bus = bus_dev_ranges[i].bus; | |
399 | dev_base = bus_dev_ranges[i].dev_base; | |
400 | dev_limit = bus_dev_ranges[i].dev_limit; | |
401 | ||
402 | for (slot = dev_base; slot < dev_limit; slot++) { | |
403 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
404 | continue; | |
405 | ||
406 | iommu_detected = 1; | |
407 | gart_iommu_aperture = 1; | |
de957628 | 408 | x86_init.iommu.iommu_init = gart_iommu_init; |
55c0d721 | 409 | |
4b83873d JR |
410 | ctl = read_pci_config(bus, slot, 3, |
411 | AMD64_GARTAPERTURECTL); | |
412 | ||
413 | /* | |
414 | * Before we do anything else disable the GART. It may | |
415 | * still be enabled if we boot into a crash-kernel here. | |
416 | * Reconfiguring the GART while it is enabled could have | |
417 | * unknown side-effects. | |
418 | */ | |
419 | ctl &= ~GARTEN; | |
420 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); | |
421 | ||
422 | aper_order = (ctl >> 1) & 7; | |
55c0d721 YL |
423 | aper_size = (32 * 1024 * 1024) << aper_order; |
424 | aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; | |
425 | aper_base <<= 25; | |
426 | ||
427 | printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n", | |
428 | node, aper_base, aper_size >> 20); | |
429 | node++; | |
430 | ||
431 | if (!aperture_valid(aper_base, aper_size, 64<<20)) { | |
432 | if (valid_agp && agp_aper_base && | |
433 | agp_aper_base == aper_base && | |
434 | agp_aper_order == aper_order) { | |
435 | /* the same between two setting from NB and agp */ | |
c987d12f YL |
436 | if (!no_iommu && |
437 | max_pfn > MAX_DMA32_PFN && | |
438 | !printed_gart_size_msg) { | |
55c0d721 YL |
439 | printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n"); |
440 | printk(KERN_ERR "please increase GART size in your BIOS setup\n"); | |
441 | printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n"); | |
442 | printed_gart_size_msg = 1; | |
443 | } | |
444 | } else { | |
445 | fix = 1; | |
446 | goto out; | |
8c9fd91a | 447 | } |
8c9fd91a | 448 | } |
1da177e4 | 449 | |
55c0d721 YL |
450 | if ((last_aper_order && aper_order != last_aper_order) || |
451 | (last_aper_base && aper_base != last_aper_base)) { | |
452 | fix = 1; | |
453 | goto out; | |
454 | } | |
455 | last_aper_order = aper_order; | |
456 | last_aper_base = aper_base; | |
1da177e4 | 457 | } |
c140df97 | 458 | } |
1da177e4 | 459 | |
55c0d721 | 460 | out: |
56dd669a AD |
461 | if (!fix && !fallback_aper_force) { |
462 | if (last_aper_base) { | |
463 | unsigned long n = (32 * 1024 * 1024) << last_aper_order; | |
c140df97 | 464 | |
56dd669a AD |
465 | insert_aperture_resource((u32)last_aper_base, n); |
466 | } | |
c140df97 | 467 | return; |
56dd669a | 468 | } |
1da177e4 | 469 | |
8c9fd91a YL |
470 | if (!fallback_aper_force) { |
471 | aper_alloc = agp_aper_base; | |
472 | aper_order = agp_aper_order; | |
473 | } | |
c140df97 IM |
474 | |
475 | if (aper_alloc) { | |
1da177e4 | 476 | /* Got the aperture from the AGP bridge */ |
c987d12f | 477 | } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) || |
1da177e4 LT |
478 | force_iommu || |
479 | valid_agp || | |
c140df97 | 480 | fallback_aper_force) { |
9b156845 | 481 | printk(KERN_INFO |
31183ba8 | 482 | "Your BIOS doesn't leave a aperture memory hole\n"); |
9b156845 | 483 | printk(KERN_INFO |
31183ba8 | 484 | "Please enable the IOMMU option in the BIOS setup\n"); |
9b156845 | 485 | printk(KERN_INFO |
31183ba8 IM |
486 | "This costs you %d MB of RAM\n", |
487 | 32 << fallback_aper_order); | |
1da177e4 LT |
488 | |
489 | aper_order = fallback_aper_order; | |
490 | aper_alloc = allocate_aperture(); | |
c140df97 IM |
491 | if (!aper_alloc) { |
492 | /* | |
493 | * Could disable AGP and IOMMU here, but it's | |
494 | * probably not worth it. But the later users | |
495 | * cannot deal with bad apertures and turning | |
496 | * on the aperture over memory causes very | |
497 | * strange problems, so it's better to panic | |
498 | * early. | |
499 | */ | |
1da177e4 LT |
500 | panic("Not enough memory for aperture"); |
501 | } | |
c140df97 IM |
502 | } else { |
503 | return; | |
504 | } | |
1da177e4 LT |
505 | |
506 | /* Fix up the north bridges */ | |
55c0d721 YL |
507 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
508 | int bus; | |
509 | int dev_base, dev_limit; | |
510 | ||
511 | bus = bus_dev_ranges[i].bus; | |
512 | dev_base = bus_dev_ranges[i].dev_base; | |
513 | dev_limit = bus_dev_ranges[i].dev_limit; | |
514 | for (slot = dev_base; slot < dev_limit; slot++) { | |
515 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
516 | continue; | |
517 | ||
518 | /* Don't enable translation yet. That is done later. | |
519 | Assume this BIOS didn't initialise the GART so | |
520 | just overwrite all previous bits */ | |
521 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, aper_order << 1); | |
522 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25); | |
523 | } | |
c140df97 | 524 | } |
6703f6d1 RW |
525 | |
526 | set_up_gart_resume(aper_order, aper_alloc); | |
c140df97 | 527 | } |