Commit | Line | Data |
---|---|---|
c140df97 | 1 | /* |
1da177e4 | 2 | * Firmware replacement code. |
c140df97 | 3 | * |
8caac563 PM |
4 | * Work around broken BIOSes that don't set an aperture, only set the |
5 | * aperture in the AGP bridge, or set too small aperture. | |
6 | * | |
c140df97 IM |
7 | * If all fails map the aperture over some low memory. This is cheaper than |
8 | * doing bounce buffering. The memory is lost. This is done at early boot | |
9 | * because only the bootmem allocator can allocate 32+MB. | |
10 | * | |
1da177e4 | 11 | * Copyright 2002 Andi Kleen, SuSE Labs. |
1da177e4 | 12 | */ |
1da177e4 LT |
13 | #include <linux/kernel.h> |
14 | #include <linux/types.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/bootmem.h> | |
17 | #include <linux/mmzone.h> | |
18 | #include <linux/pci_ids.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/bitops.h> | |
56dd669a | 21 | #include <linux/ioport.h> |
2050d45d | 22 | #include <linux/suspend.h> |
1da177e4 LT |
23 | #include <asm/e820.h> |
24 | #include <asm/io.h> | |
46a7fa27 | 25 | #include <asm/iommu.h> |
395624fc | 26 | #include <asm/gart.h> |
1da177e4 | 27 | #include <asm/pci-direct.h> |
ca8642f6 | 28 | #include <asm/dma.h> |
a32073bf | 29 | #include <asm/k8.h> |
1da177e4 | 30 | |
0440d4c0 | 31 | int gart_iommu_aperture; |
7de6a4cd PM |
32 | int gart_iommu_aperture_disabled __initdata; |
33 | int gart_iommu_aperture_allowed __initdata; | |
1da177e4 LT |
34 | |
35 | int fallback_aper_order __initdata = 1; /* 64MB */ | |
7de6a4cd | 36 | int fallback_aper_force __initdata; |
1da177e4 LT |
37 | |
38 | int fix_aperture __initdata = 1; | |
39 | ||
55c0d721 YL |
40 | struct bus_dev_range { |
41 | int bus; | |
42 | int dev_base; | |
43 | int dev_limit; | |
44 | }; | |
45 | ||
46 | static struct bus_dev_range bus_dev_ranges[] __initdata = { | |
47 | { 0x00, 0x18, 0x20}, | |
48 | { 0xff, 0x00, 0x20}, | |
49 | { 0xfe, 0x00, 0x20} | |
50 | }; | |
51 | ||
56dd669a AD |
52 | static struct resource gart_resource = { |
53 | .name = "GART", | |
54 | .flags = IORESOURCE_MEM, | |
55 | }; | |
56 | ||
57 | static void __init insert_aperture_resource(u32 aper_base, u32 aper_size) | |
58 | { | |
59 | gart_resource.start = aper_base; | |
60 | gart_resource.end = aper_base + aper_size - 1; | |
61 | insert_resource(&iomem_resource, &gart_resource); | |
62 | } | |
63 | ||
42442ed5 AM |
64 | /* This code runs before the PCI subsystem is initialized, so just |
65 | access the northbridge directly. */ | |
1da177e4 | 66 | |
c140df97 | 67 | static u32 __init allocate_aperture(void) |
1da177e4 | 68 | { |
1da177e4 | 69 | u32 aper_size; |
c140df97 | 70 | void *p; |
1da177e4 | 71 | |
7677b2ef YL |
72 | /* aper_size should <= 1G */ |
73 | if (fallback_aper_order > 5) | |
74 | fallback_aper_order = 5; | |
c140df97 | 75 | aper_size = (32 * 1024 * 1024) << fallback_aper_order; |
1da177e4 | 76 | |
c140df97 IM |
77 | /* |
78 | * Aperture has to be naturally aligned. This means a 2GB aperture | |
79 | * won't have much chance of finding a place in the lower 4GB of | |
80 | * memory. Unfortunately we cannot move it up because that would | |
81 | * make the IOMMU useless. | |
1da177e4 | 82 | */ |
7677b2ef YL |
83 | /* |
84 | * using 512M as goal, in case kexec will load kernel_big | |
85 | * that will do the on position decompress, and could overlap with | |
86 | * that positon with gart that is used. | |
87 | * sequende: | |
88 | * kernel_small | |
89 | * ==> kexec (with kdump trigger path or previous doesn't shutdown gart) | |
90 | * ==> kernel_small(gart area become e820_reserved) | |
91 | * ==> kexec (with kdump trigger path or previous doesn't shutdown gart) | |
92 | * ==> kerne_big (uncompressed size will be big than 64M or 128M) | |
93 | * so don't use 512M below as gart iommu, leave the space for kernel | |
94 | * code for safe | |
95 | */ | |
96 | p = __alloc_bootmem_nopanic(aper_size, aper_size, 512ULL<<20); | |
1da177e4 | 97 | if (!p || __pa(p)+aper_size > 0xffffffff) { |
31183ba8 IM |
98 | printk(KERN_ERR |
99 | "Cannot allocate aperture memory hole (%p,%uK)\n", | |
100 | p, aper_size>>10); | |
1da177e4 | 101 | if (p) |
82d1bb72 | 102 | free_bootmem(__pa(p), aper_size); |
1da177e4 LT |
103 | return 0; |
104 | } | |
31183ba8 IM |
105 | printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n", |
106 | aper_size >> 10, __pa(p)); | |
56dd669a | 107 | insert_aperture_resource((u32)__pa(p), aper_size); |
2050d45d PM |
108 | register_nosave_region((u32)__pa(p) >> PAGE_SHIFT, |
109 | (u32)__pa(p+aper_size) >> PAGE_SHIFT); | |
c140df97 IM |
110 | |
111 | return (u32)__pa(p); | |
1da177e4 LT |
112 | } |
113 | ||
1da177e4 | 114 | |
42442ed5 | 115 | /* Find a PCI capability */ |
dd564d0c | 116 | static u32 __init find_cap(int bus, int slot, int func, int cap) |
c140df97 | 117 | { |
1da177e4 | 118 | int bytes; |
c140df97 IM |
119 | u8 pos; |
120 | ||
55c0d721 | 121 | if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) & |
c140df97 | 122 | PCI_STATUS_CAP_LIST)) |
1da177e4 | 123 | return 0; |
c140df97 | 124 | |
55c0d721 | 125 | pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST); |
c140df97 | 126 | for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { |
1da177e4 | 127 | u8 id; |
c140df97 IM |
128 | |
129 | pos &= ~3; | |
55c0d721 | 130 | id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID); |
1da177e4 LT |
131 | if (id == 0xff) |
132 | break; | |
c140df97 IM |
133 | if (id == cap) |
134 | return pos; | |
55c0d721 | 135 | pos = read_pci_config_byte(bus, slot, func, |
c140df97 IM |
136 | pos+PCI_CAP_LIST_NEXT); |
137 | } | |
1da177e4 | 138 | return 0; |
c140df97 | 139 | } |
1da177e4 LT |
140 | |
141 | /* Read a standard AGPv3 bridge header */ | |
dd564d0c | 142 | static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order) |
c140df97 | 143 | { |
1da177e4 LT |
144 | u32 apsize; |
145 | u32 apsizereg; | |
146 | int nbits; | |
147 | u32 aper_low, aper_hi; | |
148 | u64 aper; | |
1edc1ab3 | 149 | u32 old_order; |
1da177e4 | 150 | |
55c0d721 YL |
151 | printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func); |
152 | apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14); | |
1da177e4 | 153 | if (apsizereg == 0xffffffff) { |
31183ba8 | 154 | printk(KERN_ERR "APSIZE in AGP bridge unreadable\n"); |
1da177e4 LT |
155 | return 0; |
156 | } | |
157 | ||
1edc1ab3 YL |
158 | /* old_order could be the value from NB gart setting */ |
159 | old_order = *order; | |
160 | ||
1da177e4 LT |
161 | apsize = apsizereg & 0xfff; |
162 | /* Some BIOS use weird encodings not in the AGPv3 table. */ | |
c140df97 IM |
163 | if (apsize & 0xff) |
164 | apsize |= 0xf00; | |
1da177e4 LT |
165 | nbits = hweight16(apsize); |
166 | *order = 7 - nbits; | |
167 | if ((int)*order < 0) /* < 32MB */ | |
168 | *order = 0; | |
c140df97 | 169 | |
55c0d721 YL |
170 | aper_low = read_pci_config(bus, slot, func, 0x10); |
171 | aper_hi = read_pci_config(bus, slot, func, 0x14); | |
1da177e4 LT |
172 | aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); |
173 | ||
1edc1ab3 YL |
174 | /* |
175 | * On some sick chips, APSIZE is 0. It means it wants 4G | |
176 | * so let double check that order, and lets trust AMD NB settings: | |
177 | */ | |
8c9fd91a YL |
178 | printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n", |
179 | aper, 32 << old_order); | |
180 | if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) { | |
1edc1ab3 YL |
181 | printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n", |
182 | 32 << *order, apsizereg); | |
183 | *order = old_order; | |
184 | } | |
185 | ||
31183ba8 IM |
186 | printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n", |
187 | aper, 32 << *order, apsizereg); | |
1da177e4 | 188 | |
8c9fd91a | 189 | if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20)) |
c140df97 IM |
190 | return 0; |
191 | return (u32)aper; | |
192 | } | |
1da177e4 | 193 | |
c140df97 IM |
194 | /* |
195 | * Look for an AGP bridge. Windows only expects the aperture in the | |
196 | * AGP bridge and some BIOS forget to initialize the Northbridge too. | |
197 | * Work around this here. | |
198 | * | |
199 | * Do an PCI bus scan by hand because we're running before the PCI | |
200 | * subsystem. | |
201 | * | |
202 | * All K8 AGP bridges are AGPv3 compliant, so we can do this scan | |
203 | * generically. It's probably overkill to always scan all slots because | |
204 | * the AGP bridges should be always an own bus on the HT hierarchy, | |
205 | * but do it here for future safety. | |
206 | */ | |
dd564d0c | 207 | static u32 __init search_agp_bridge(u32 *order, int *valid_agp) |
1da177e4 | 208 | { |
55c0d721 | 209 | int bus, slot, func; |
1da177e4 LT |
210 | |
211 | /* Poor man's PCI discovery */ | |
55c0d721 | 212 | for (bus = 0; bus < 256; bus++) { |
c140df97 IM |
213 | for (slot = 0; slot < 32; slot++) { |
214 | for (func = 0; func < 8; func++) { | |
1da177e4 LT |
215 | u32 class, cap; |
216 | u8 type; | |
55c0d721 | 217 | class = read_pci_config(bus, slot, func, |
1da177e4 LT |
218 | PCI_CLASS_REVISION); |
219 | if (class == 0xffffffff) | |
c140df97 IM |
220 | break; |
221 | ||
222 | switch (class >> 16) { | |
1da177e4 LT |
223 | case PCI_CLASS_BRIDGE_HOST: |
224 | case PCI_CLASS_BRIDGE_OTHER: /* needed? */ | |
225 | /* AGP bridge? */ | |
55c0d721 | 226 | cap = find_cap(bus, slot, func, |
c140df97 | 227 | PCI_CAP_ID_AGP); |
1da177e4 LT |
228 | if (!cap) |
229 | break; | |
c140df97 | 230 | *valid_agp = 1; |
55c0d721 | 231 | return read_agp(bus, slot, func, cap, |
c140df97 IM |
232 | order); |
233 | } | |
234 | ||
1da177e4 | 235 | /* No multi-function device? */ |
55c0d721 | 236 | type = read_pci_config_byte(bus, slot, func, |
1da177e4 LT |
237 | PCI_HEADER_TYPE); |
238 | if (!(type & 0x80)) | |
239 | break; | |
c140df97 IM |
240 | } |
241 | } | |
1da177e4 | 242 | } |
31183ba8 | 243 | printk(KERN_INFO "No AGP bridge found\n"); |
c140df97 | 244 | |
1da177e4 LT |
245 | return 0; |
246 | } | |
247 | ||
aaf23042 YL |
248 | static int gart_fix_e820 __initdata = 1; |
249 | ||
250 | static int __init parse_gart_mem(char *p) | |
251 | { | |
252 | if (!p) | |
253 | return -EINVAL; | |
254 | ||
255 | if (!strncmp(p, "off", 3)) | |
256 | gart_fix_e820 = 0; | |
257 | else if (!strncmp(p, "on", 2)) | |
258 | gart_fix_e820 = 1; | |
259 | ||
260 | return 0; | |
261 | } | |
262 | early_param("gart_fix_e820", parse_gart_mem); | |
263 | ||
264 | void __init early_gart_iommu_check(void) | |
265 | { | |
266 | /* | |
267 | * in case it is enabled before, esp for kexec/kdump, | |
268 | * previous kernel already enable that. memset called | |
269 | * by allocate_aperture/__alloc_bootmem_nopanic cause restart. | |
270 | * or second kernel have different position for GART hole. and new | |
271 | * kernel could use hole as RAM that is still used by GART set by | |
272 | * first kernel | |
273 | * or BIOS forget to put that in reserved. | |
274 | * try to update e820 to make that region as reserved. | |
275 | */ | |
fa5b8a30 | 276 | int i, fix, slot; |
aaf23042 YL |
277 | u32 ctl; |
278 | u32 aper_size = 0, aper_order = 0, last_aper_order = 0; | |
279 | u64 aper_base = 0, last_aper_base = 0; | |
fa5b8a30 | 280 | int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0; |
aaf23042 YL |
281 | |
282 | if (!early_pci_allowed()) | |
283 | return; | |
284 | ||
fa5b8a30 | 285 | /* This is mostly duplicate of iommu_hole_init */ |
aaf23042 | 286 | fix = 0; |
55c0d721 YL |
287 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
288 | int bus; | |
289 | int dev_base, dev_limit; | |
290 | ||
291 | bus = bus_dev_ranges[i].bus; | |
292 | dev_base = bus_dev_ranges[i].dev_base; | |
293 | dev_limit = bus_dev_ranges[i].dev_limit; | |
294 | ||
295 | for (slot = dev_base; slot < dev_limit; slot++) { | |
296 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
297 | continue; | |
298 | ||
299 | ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); | |
300 | aper_enabled = ctl & AMD64_GARTEN; | |
301 | aper_order = (ctl >> 1) & 7; | |
302 | aper_size = (32 * 1024 * 1024) << aper_order; | |
303 | aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; | |
304 | aper_base <<= 25; | |
305 | ||
fa5b8a30 PM |
306 | if (last_valid) { |
307 | if ((aper_order != last_aper_order) || | |
308 | (aper_base != last_aper_base) || | |
309 | (aper_enabled != last_aper_enabled)) { | |
310 | fix = 1; | |
311 | break; | |
312 | } | |
55c0d721 | 313 | } |
fa5b8a30 | 314 | |
55c0d721 YL |
315 | last_aper_order = aper_order; |
316 | last_aper_base = aper_base; | |
317 | last_aper_enabled = aper_enabled; | |
fa5b8a30 | 318 | last_valid = 1; |
aaf23042 | 319 | } |
aaf23042 YL |
320 | } |
321 | ||
322 | if (!fix && !aper_enabled) | |
323 | return; | |
324 | ||
325 | if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL) | |
326 | fix = 1; | |
327 | ||
328 | if (gart_fix_e820 && !fix && aper_enabled) { | |
0754557d YL |
329 | if (e820_any_mapped(aper_base, aper_base + aper_size, |
330 | E820_RAM)) { | |
0abbc78a | 331 | /* reserve it, so we can reuse it in second kernel */ |
aaf23042 | 332 | printk(KERN_INFO "update e820 for GART\n"); |
d0be6bde | 333 | e820_add_region(aper_base, aper_size, E820_RESERVED); |
aaf23042 YL |
334 | update_e820(); |
335 | } | |
aaf23042 YL |
336 | } |
337 | ||
4f384f8b PM |
338 | if (!fix) |
339 | return; | |
340 | ||
aaf23042 | 341 | /* different nodes have different setting, disable them all at first*/ |
55c0d721 YL |
342 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
343 | int bus; | |
344 | int dev_base, dev_limit; | |
345 | ||
346 | bus = bus_dev_ranges[i].bus; | |
347 | dev_base = bus_dev_ranges[i].dev_base; | |
348 | dev_limit = bus_dev_ranges[i].dev_limit; | |
aaf23042 | 349 | |
55c0d721 YL |
350 | for (slot = dev_base; slot < dev_limit; slot++) { |
351 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
352 | continue; | |
353 | ||
354 | ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); | |
355 | ctl &= ~AMD64_GARTEN; | |
356 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl); | |
357 | } | |
aaf23042 YL |
358 | } |
359 | ||
360 | } | |
361 | ||
8c9fd91a YL |
362 | static int __initdata printed_gart_size_msg; |
363 | ||
0440d4c0 | 364 | void __init gart_iommu_hole_init(void) |
c140df97 | 365 | { |
8c9fd91a | 366 | u32 agp_aper_base = 0, agp_aper_order = 0; |
50895c5d | 367 | u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0; |
1da177e4 | 368 | u64 aper_base, last_aper_base = 0; |
55c0d721 YL |
369 | int fix, slot, valid_agp = 0; |
370 | int i, node; | |
1da177e4 | 371 | |
0440d4c0 JR |
372 | if (gart_iommu_aperture_disabled || !fix_aperture || |
373 | !early_pci_allowed()) | |
1da177e4 LT |
374 | return; |
375 | ||
753811dc | 376 | printk(KERN_INFO "Checking aperture...\n"); |
1da177e4 | 377 | |
8c9fd91a YL |
378 | if (!fallback_aper_force) |
379 | agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp); | |
380 | ||
1da177e4 | 381 | fix = 0; |
47db4c3e | 382 | node = 0; |
55c0d721 YL |
383 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
384 | int bus; | |
385 | int dev_base, dev_limit; | |
386 | ||
387 | bus = bus_dev_ranges[i].bus; | |
388 | dev_base = bus_dev_ranges[i].dev_base; | |
389 | dev_limit = bus_dev_ranges[i].dev_limit; | |
390 | ||
391 | for (slot = dev_base; slot < dev_limit; slot++) { | |
392 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
393 | continue; | |
394 | ||
395 | iommu_detected = 1; | |
396 | gart_iommu_aperture = 1; | |
397 | ||
398 | aper_order = (read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL) >> 1) & 7; | |
399 | aper_size = (32 * 1024 * 1024) << aper_order; | |
400 | aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff; | |
401 | aper_base <<= 25; | |
402 | ||
403 | printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n", | |
404 | node, aper_base, aper_size >> 20); | |
405 | node++; | |
406 | ||
407 | if (!aperture_valid(aper_base, aper_size, 64<<20)) { | |
408 | if (valid_agp && agp_aper_base && | |
409 | agp_aper_base == aper_base && | |
410 | agp_aper_order == aper_order) { | |
411 | /* the same between two setting from NB and agp */ | |
c987d12f YL |
412 | if (!no_iommu && |
413 | max_pfn > MAX_DMA32_PFN && | |
414 | !printed_gart_size_msg) { | |
55c0d721 YL |
415 | printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n"); |
416 | printk(KERN_ERR "please increase GART size in your BIOS setup\n"); | |
417 | printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n"); | |
418 | printed_gart_size_msg = 1; | |
419 | } | |
420 | } else { | |
421 | fix = 1; | |
422 | goto out; | |
8c9fd91a | 423 | } |
8c9fd91a | 424 | } |
1da177e4 | 425 | |
55c0d721 YL |
426 | if ((last_aper_order && aper_order != last_aper_order) || |
427 | (last_aper_base && aper_base != last_aper_base)) { | |
428 | fix = 1; | |
429 | goto out; | |
430 | } | |
431 | last_aper_order = aper_order; | |
432 | last_aper_base = aper_base; | |
1da177e4 | 433 | } |
c140df97 | 434 | } |
1da177e4 | 435 | |
55c0d721 | 436 | out: |
56dd669a AD |
437 | if (!fix && !fallback_aper_force) { |
438 | if (last_aper_base) { | |
439 | unsigned long n = (32 * 1024 * 1024) << last_aper_order; | |
c140df97 | 440 | |
56dd669a AD |
441 | insert_aperture_resource((u32)last_aper_base, n); |
442 | } | |
c140df97 | 443 | return; |
56dd669a | 444 | } |
1da177e4 | 445 | |
8c9fd91a YL |
446 | if (!fallback_aper_force) { |
447 | aper_alloc = agp_aper_base; | |
448 | aper_order = agp_aper_order; | |
449 | } | |
c140df97 IM |
450 | |
451 | if (aper_alloc) { | |
1da177e4 | 452 | /* Got the aperture from the AGP bridge */ |
63f02fd7 AK |
453 | } else if (swiotlb && !valid_agp) { |
454 | /* Do nothing */ | |
c987d12f | 455 | } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) || |
1da177e4 LT |
456 | force_iommu || |
457 | valid_agp || | |
c140df97 | 458 | fallback_aper_force) { |
9b156845 | 459 | printk(KERN_INFO |
31183ba8 | 460 | "Your BIOS doesn't leave a aperture memory hole\n"); |
9b156845 | 461 | printk(KERN_INFO |
31183ba8 | 462 | "Please enable the IOMMU option in the BIOS setup\n"); |
9b156845 | 463 | printk(KERN_INFO |
31183ba8 IM |
464 | "This costs you %d MB of RAM\n", |
465 | 32 << fallback_aper_order); | |
1da177e4 LT |
466 | |
467 | aper_order = fallback_aper_order; | |
468 | aper_alloc = allocate_aperture(); | |
c140df97 IM |
469 | if (!aper_alloc) { |
470 | /* | |
471 | * Could disable AGP and IOMMU here, but it's | |
472 | * probably not worth it. But the later users | |
473 | * cannot deal with bad apertures and turning | |
474 | * on the aperture over memory causes very | |
475 | * strange problems, so it's better to panic | |
476 | * early. | |
477 | */ | |
1da177e4 LT |
478 | panic("Not enough memory for aperture"); |
479 | } | |
c140df97 IM |
480 | } else { |
481 | return; | |
482 | } | |
1da177e4 LT |
483 | |
484 | /* Fix up the north bridges */ | |
55c0d721 YL |
485 | for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) { |
486 | int bus; | |
487 | int dev_base, dev_limit; | |
488 | ||
489 | bus = bus_dev_ranges[i].bus; | |
490 | dev_base = bus_dev_ranges[i].dev_base; | |
491 | dev_limit = bus_dev_ranges[i].dev_limit; | |
492 | for (slot = dev_base; slot < dev_limit; slot++) { | |
493 | if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00))) | |
494 | continue; | |
495 | ||
496 | /* Don't enable translation yet. That is done later. | |
497 | Assume this BIOS didn't initialise the GART so | |
498 | just overwrite all previous bits */ | |
499 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, aper_order << 1); | |
500 | write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25); | |
501 | } | |
c140df97 | 502 | } |
6703f6d1 RW |
503 | |
504 | set_up_gart_resume(aper_order, aper_alloc); | |
c140df97 | 505 | } |