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bb24c471 JP |
1 | /* |
2 | * apb_timer.c: Driver for Langwell APB timers | |
3 | * | |
4 | * (C) Copyright 2009 Intel Corporation | |
5 | * Author: Jacob Pan (jacob.jun.pan@intel.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
12 | * Note: | |
13 | * Langwell is the south complex of Intel Moorestown MID platform. There are | |
14 | * eight external timers in total that can be used by the operating system. | |
15 | * The timer information, such as frequency and addresses, is provided to the | |
16 | * OS via SFI tables. | |
17 | * Timer interrupts are routed via FW/HW emulated IOAPIC independently via | |
18 | * individual redirection table entries (RTE). | |
19 | * Unlike HPET, there is no master counter, therefore one of the timers are | |
20 | * used as clocksource. The overall allocation looks like: | |
21 | * - timer 0 - NR_CPUs for per cpu timer | |
22 | * - one timer for clocksource | |
23 | * - one timer for watchdog driver. | |
24 | * It is also worth notice that APB timer does not support true one-shot mode, | |
25 | * free-running mode will be used here to emulate one-shot mode. | |
26 | * APB timer can also be used as broadcast timer along with per cpu local APIC | |
27 | * timer, but by default APB timer has higher rating than local APIC timers. | |
28 | */ | |
29 | ||
30 | #include <linux/clocksource.h> | |
31 | #include <linux/clockchips.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/sysdev.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bb24c471 JP |
37 | #include <linux/pm.h> |
38 | #include <linux/pci.h> | |
39 | #include <linux/sfi.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/cpu.h> | |
42 | #include <linux/irq.h> | |
43 | ||
44 | #include <asm/fixmap.h> | |
45 | #include <asm/apb_timer.h> | |
46 | ||
c7bbf52a PA |
47 | #define APBT_MASK CLOCKSOURCE_MASK(32) |
48 | #define APBT_SHIFT 22 | |
49 | #define APBT_CLOCKEVENT_RATING 150 | |
50 | #define APBT_CLOCKSOURCE_RATING 250 | |
51 | #define APBT_MIN_DELTA_USEC 200 | |
bb24c471 JP |
52 | |
53 | #define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt) | |
54 | #define APBT_CLOCKEVENT0_NUM (0) | |
55 | #define APBT_CLOCKEVENT1_NUM (1) | |
56 | #define APBT_CLOCKSOURCE_NUM (2) | |
57 | ||
58 | static unsigned long apbt_address; | |
59 | static int apb_timer_block_enabled; | |
60 | static void __iomem *apbt_virt_address; | |
61 | static int phy_cs_timer_id; | |
62 | ||
63 | /* | |
64 | * Common DW APB timer info | |
65 | */ | |
66 | static uint64_t apbt_freq; | |
67 | ||
68 | static void apbt_set_mode(enum clock_event_mode mode, | |
c7bbf52a | 69 | struct clock_event_device *evt); |
bb24c471 | 70 | static int apbt_next_event(unsigned long delta, |
c7bbf52a | 71 | struct clock_event_device *evt); |
bb24c471 | 72 | static cycle_t apbt_read_clocksource(struct clocksource *cs); |
322aafa6 | 73 | static void apbt_restart_clocksource(struct clocksource *cs); |
bb24c471 JP |
74 | |
75 | struct apbt_dev { | |
c7bbf52a PA |
76 | struct clock_event_device evt; |
77 | unsigned int num; | |
78 | int cpu; | |
79 | unsigned int irq; | |
80 | unsigned int tick; | |
81 | unsigned int count; | |
82 | unsigned int flags; | |
83 | char name[10]; | |
bb24c471 JP |
84 | }; |
85 | ||
86 | int disable_apbt_percpu __cpuinitdata; | |
87 | ||
3010673e JP |
88 | static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev); |
89 | ||
bb24c471 JP |
90 | #ifdef CONFIG_SMP |
91 | static unsigned int apbt_num_timers_used; | |
bb24c471 JP |
92 | static struct apbt_dev *apbt_devs; |
93 | #endif | |
94 | ||
c7bbf52a | 95 | static inline unsigned long apbt_readl_reg(unsigned long a) |
bb24c471 | 96 | { |
c7bbf52a | 97 | return readl(apbt_virt_address + a); |
bb24c471 JP |
98 | } |
99 | ||
100 | static inline void apbt_writel_reg(unsigned long d, unsigned long a) | |
101 | { | |
c7bbf52a | 102 | writel(d, apbt_virt_address + a); |
bb24c471 JP |
103 | } |
104 | ||
105 | static inline unsigned long apbt_readl(int n, unsigned long a) | |
106 | { | |
c7bbf52a | 107 | return readl(apbt_virt_address + a + n * APBTMRS_REG_SIZE); |
bb24c471 JP |
108 | } |
109 | ||
110 | static inline void apbt_writel(int n, unsigned long d, unsigned long a) | |
111 | { | |
c7bbf52a | 112 | writel(d, apbt_virt_address + a + n * APBTMRS_REG_SIZE); |
bb24c471 JP |
113 | } |
114 | ||
115 | static inline void apbt_set_mapping(void) | |
116 | { | |
c7bbf52a PA |
117 | struct sfi_timer_table_entry *mtmr; |
118 | ||
119 | if (apbt_virt_address) { | |
120 | pr_debug("APBT base already mapped\n"); | |
121 | return; | |
122 | } | |
123 | mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM); | |
124 | if (mtmr == NULL) { | |
125 | printk(KERN_ERR "Failed to get MTMR %d from SFI\n", | |
126 | APBT_CLOCKEVENT0_NUM); | |
127 | return; | |
128 | } | |
129 | apbt_address = (unsigned long)mtmr->phys_addr; | |
130 | if (!apbt_address) { | |
131 | printk(KERN_WARNING "No timer base from SFI, use default\n"); | |
132 | apbt_address = APBT_DEFAULT_BASE; | |
133 | } | |
134 | apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE); | |
135 | if (apbt_virt_address) { | |
136 | pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\ | |
137 | (void *)apbt_address, (void *)apbt_virt_address); | |
138 | } else { | |
139 | pr_debug("Failed mapping APBT phy address at %p\n",\ | |
140 | (void *)apbt_address); | |
141 | goto panic_noapbt; | |
142 | } | |
143 | apbt_freq = mtmr->freq_hz / USEC_PER_SEC; | |
144 | sfi_free_mtmr(mtmr); | |
145 | ||
146 | /* Now figure out the physical timer id for clocksource device */ | |
147 | mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM); | |
148 | if (mtmr == NULL) | |
149 | goto panic_noapbt; | |
150 | ||
151 | /* Now figure out the physical timer id */ | |
152 | phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) | |
153 | / APBTMRS_REG_SIZE; | |
154 | pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id); | |
155 | return; | |
bb24c471 JP |
156 | |
157 | panic_noapbt: | |
c7bbf52a | 158 | panic("Failed to setup APB system timer\n"); |
bb24c471 JP |
159 | |
160 | } | |
161 | ||
162 | static inline void apbt_clear_mapping(void) | |
163 | { | |
c7bbf52a PA |
164 | iounmap(apbt_virt_address); |
165 | apbt_virt_address = NULL; | |
bb24c471 JP |
166 | } |
167 | ||
168 | /* | |
169 | * APBT timer interrupt enable / disable | |
170 | */ | |
171 | static inline int is_apbt_capable(void) | |
172 | { | |
c7bbf52a | 173 | return apbt_virt_address ? 1 : 0; |
bb24c471 JP |
174 | } |
175 | ||
176 | static struct clocksource clocksource_apbt = { | |
c7bbf52a PA |
177 | .name = "apbt", |
178 | .rating = APBT_CLOCKSOURCE_RATING, | |
179 | .read = apbt_read_clocksource, | |
180 | .mask = APBT_MASK, | |
181 | .shift = APBT_SHIFT, | |
182 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
183 | .resume = apbt_restart_clocksource, | |
bb24c471 JP |
184 | }; |
185 | ||
186 | /* boot APB clock event device */ | |
187 | static struct clock_event_device apbt_clockevent = { | |
c7bbf52a PA |
188 | .name = "apbt0", |
189 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
190 | .set_mode = apbt_set_mode, | |
191 | .set_next_event = apbt_next_event, | |
192 | .shift = APBT_SHIFT, | |
193 | .irq = 0, | |
194 | .rating = APBT_CLOCKEVENT_RATING, | |
bb24c471 JP |
195 | }; |
196 | ||
197 | /* | |
198 | * if user does not want to use per CPU apb timer, just give it a lower rating | |
199 | * than local apic timer and skip the late per cpu timer init. | |
200 | */ | |
201 | static inline int __init setup_x86_mrst_timer(char *arg) | |
202 | { | |
c7bbf52a PA |
203 | if (!arg) |
204 | return -EINVAL; | |
205 | ||
206 | if (strcmp("apbt_only", arg) == 0) | |
207 | disable_apbt_percpu = 0; | |
208 | else if (strcmp("lapic_and_apbt", arg) == 0) | |
209 | disable_apbt_percpu = 1; | |
210 | else { | |
211 | pr_warning("X86 MRST timer option %s not recognised" | |
212 | " use x86_mrst_timer=apbt_only or lapic_and_apbt\n", | |
213 | arg); | |
214 | return -EINVAL; | |
215 | } | |
216 | return 0; | |
bb24c471 JP |
217 | } |
218 | __setup("x86_mrst_timer=", setup_x86_mrst_timer); | |
219 | ||
220 | /* | |
221 | * start count down from 0xffff_ffff. this is done by toggling the enable bit | |
222 | * then load initial load count to ~0. | |
223 | */ | |
224 | static void apbt_start_counter(int n) | |
225 | { | |
c7bbf52a PA |
226 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
227 | ||
228 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
229 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
230 | apbt_writel(n, ~0, APBTMR_N_LOAD_COUNT); | |
231 | /* enable, mask interrupt */ | |
232 | ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; | |
233 | ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT); | |
234 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
235 | /* read it once to get cached counter value initialized */ | |
236 | apbt_read_clocksource(&clocksource_apbt); | |
bb24c471 JP |
237 | } |
238 | ||
239 | static irqreturn_t apbt_interrupt_handler(int irq, void *data) | |
240 | { | |
c7bbf52a PA |
241 | struct apbt_dev *dev = (struct apbt_dev *)data; |
242 | struct clock_event_device *aevt = &dev->evt; | |
243 | ||
244 | if (!aevt->event_handler) { | |
245 | printk(KERN_INFO "Spurious APBT timer interrupt on %d\n", | |
246 | dev->num); | |
247 | return IRQ_NONE; | |
248 | } | |
249 | aevt->event_handler(aevt); | |
250 | return IRQ_HANDLED; | |
bb24c471 JP |
251 | } |
252 | ||
322aafa6 | 253 | static void apbt_restart_clocksource(struct clocksource *cs) |
bb24c471 | 254 | { |
c7bbf52a | 255 | apbt_start_counter(phy_cs_timer_id); |
bb24c471 JP |
256 | } |
257 | ||
258 | /* Setup IRQ routing via IOAPIC */ | |
259 | #ifdef CONFIG_SMP | |
260 | static void apbt_setup_irq(struct apbt_dev *adev) | |
261 | { | |
c7bbf52a PA |
262 | struct irq_chip *chip; |
263 | struct irq_desc *desc; | |
264 | ||
265 | /* timer0 irq has been setup early */ | |
266 | if (adev->irq == 0) | |
267 | return; | |
268 | desc = irq_to_desc(adev->irq); | |
269 | chip = get_irq_chip(adev->irq); | |
270 | disable_irq(adev->irq); | |
271 | desc->status |= IRQ_MOVE_PCNTXT; | |
272 | irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); | |
273 | /* APB timer irqs are set up as mp_irqs, timer is edge triggerred */ | |
274 | set_irq_chip_and_handler_name(adev->irq, chip, handle_edge_irq, "edge"); | |
275 | enable_irq(adev->irq); | |
276 | if (system_state == SYSTEM_BOOTING) | |
277 | if (request_irq(adev->irq, apbt_interrupt_handler, | |
278 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, | |
279 | adev->name, adev)) { | |
280 | printk(KERN_ERR "Failed request IRQ for APBT%d\n", | |
281 | adev->num); | |
282 | } | |
bb24c471 JP |
283 | } |
284 | #endif | |
285 | ||
286 | static void apbt_enable_int(int n) | |
287 | { | |
c7bbf52a PA |
288 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
289 | /* clear pending intr */ | |
290 | apbt_readl(n, APBTMR_N_EOI); | |
291 | ctrl &= ~APBTMR_CONTROL_INT; | |
292 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
bb24c471 JP |
293 | } |
294 | ||
295 | static void apbt_disable_int(int n) | |
296 | { | |
c7bbf52a | 297 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
bb24c471 | 298 | |
c7bbf52a PA |
299 | ctrl |= APBTMR_CONTROL_INT; |
300 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
bb24c471 JP |
301 | } |
302 | ||
303 | ||
304 | static int __init apbt_clockevent_register(void) | |
305 | { | |
c7bbf52a PA |
306 | struct sfi_timer_table_entry *mtmr; |
307 | struct apbt_dev *adev = &__get_cpu_var(cpu_apbt_dev); | |
308 | ||
309 | mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM); | |
310 | if (mtmr == NULL) { | |
311 | printk(KERN_ERR "Failed to get MTMR %d from SFI\n", | |
312 | APBT_CLOCKEVENT0_NUM); | |
313 | return -ENODEV; | |
314 | } | |
315 | ||
316 | /* | |
317 | * We need to calculate the scaled math multiplication factor for | |
318 | * nanosecond to apbt tick conversion. | |
319 | * mult = (nsec/cycle)*2^APBT_SHIFT | |
320 | */ | |
321 | apbt_clockevent.mult = div_sc((unsigned long) mtmr->freq_hz | |
322 | , NSEC_PER_SEC, APBT_SHIFT); | |
323 | ||
324 | /* Calculate the min / max delta */ | |
325 | apbt_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
326 | &apbt_clockevent); | |
327 | apbt_clockevent.min_delta_ns = clockevent_delta2ns( | |
328 | APBT_MIN_DELTA_USEC*apbt_freq, | |
329 | &apbt_clockevent); | |
330 | /* | |
331 | * Start apbt with the boot cpu mask and make it | |
332 | * global if not used for per cpu timer. | |
333 | */ | |
334 | apbt_clockevent.cpumask = cpumask_of(smp_processor_id()); | |
335 | adev->num = smp_processor_id(); | |
336 | memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device)); | |
337 | ||
338 | if (disable_apbt_percpu) { | |
339 | apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100; | |
3010673e | 340 | global_clock_event = &adev->evt; |
c7bbf52a PA |
341 | printk(KERN_DEBUG "%s clockevent registered as global\n", |
342 | global_clock_event->name); | |
343 | } | |
344 | ||
345 | if (request_irq(apbt_clockevent.irq, apbt_interrupt_handler, | |
346 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, | |
347 | apbt_clockevent.name, adev)) { | |
348 | printk(KERN_ERR "Failed request IRQ for APBT%d\n", | |
349 | apbt_clockevent.irq); | |
350 | } | |
351 | ||
352 | clockevents_register_device(&adev->evt); | |
353 | /* Start APBT 0 interrupts */ | |
354 | apbt_enable_int(APBT_CLOCKEVENT0_NUM); | |
355 | ||
356 | sfi_free_mtmr(mtmr); | |
357 | return 0; | |
bb24c471 JP |
358 | } |
359 | ||
360 | #ifdef CONFIG_SMP | |
361 | /* Should be called with per cpu */ | |
362 | void apbt_setup_secondary_clock(void) | |
363 | { | |
c7bbf52a PA |
364 | struct apbt_dev *adev; |
365 | struct clock_event_device *aevt; | |
366 | int cpu; | |
367 | ||
368 | /* Don't register boot CPU clockevent */ | |
369 | cpu = smp_processor_id(); | |
370 | if (cpu == boot_cpu_id) | |
371 | return; | |
372 | /* | |
373 | * We need to calculate the scaled math multiplication factor for | |
374 | * nanosecond to apbt tick conversion. | |
375 | * mult = (nsec/cycle)*2^APBT_SHIFT | |
376 | */ | |
377 | printk(KERN_INFO "Init per CPU clockevent %d\n", cpu); | |
378 | adev = &per_cpu(cpu_apbt_dev, cpu); | |
379 | aevt = &adev->evt; | |
380 | ||
381 | memcpy(aevt, &apbt_clockevent, sizeof(*aevt)); | |
382 | aevt->cpumask = cpumask_of(cpu); | |
383 | aevt->name = adev->name; | |
384 | aevt->mode = CLOCK_EVT_MODE_UNUSED; | |
385 | ||
386 | printk(KERN_INFO "Registering CPU %d clockevent device %s, mask %08x\n", | |
387 | cpu, aevt->name, *(u32 *)aevt->cpumask); | |
388 | ||
389 | apbt_setup_irq(adev); | |
390 | ||
391 | clockevents_register_device(aevt); | |
392 | ||
393 | apbt_enable_int(cpu); | |
394 | ||
395 | return; | |
bb24c471 JP |
396 | } |
397 | ||
398 | /* | |
399 | * this notify handler process CPU hotplug events. in case of S0i3, nonboot | |
400 | * cpus are disabled/enabled frequently, for performance reasons, we keep the | |
401 | * per cpu timer irq registered so that we do need to do free_irq/request_irq. | |
402 | * | |
403 | * TODO: it might be more reliable to directly disable percpu clockevent device | |
404 | * without the notifier chain. currently, cpu 0 may get interrupts from other | |
405 | * cpu timers during the offline process due to the ordering of notification. | |
406 | * the extra interrupt is harmless. | |
407 | */ | |
408 | static int apbt_cpuhp_notify(struct notifier_block *n, | |
c7bbf52a | 409 | unsigned long action, void *hcpu) |
bb24c471 | 410 | { |
c7bbf52a PA |
411 | unsigned long cpu = (unsigned long)hcpu; |
412 | struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu); | |
413 | ||
414 | switch (action & 0xf) { | |
415 | case CPU_DEAD: | |
416 | apbt_disable_int(cpu); | |
417 | if (system_state == SYSTEM_RUNNING) | |
418 | pr_debug("skipping APBT CPU %lu offline\n", cpu); | |
419 | else if (adev) { | |
420 | pr_debug("APBT clockevent for cpu %lu offline\n", cpu); | |
421 | free_irq(adev->irq, adev); | |
422 | } | |
423 | break; | |
424 | default: | |
425 | pr_debug(KERN_INFO "APBT notified %lu, no action\n", action); | |
426 | } | |
427 | return NOTIFY_OK; | |
bb24c471 JP |
428 | } |
429 | ||
430 | static __init int apbt_late_init(void) | |
431 | { | |
c7bbf52a PA |
432 | if (disable_apbt_percpu) |
433 | return 0; | |
434 | /* This notifier should be called after workqueue is ready */ | |
435 | hotcpu_notifier(apbt_cpuhp_notify, -20); | |
436 | return 0; | |
bb24c471 JP |
437 | } |
438 | fs_initcall(apbt_late_init); | |
439 | #else | |
440 | ||
441 | void apbt_setup_secondary_clock(void) {} | |
442 | ||
443 | #endif /* CONFIG_SMP */ | |
444 | ||
445 | static void apbt_set_mode(enum clock_event_mode mode, | |
c7bbf52a | 446 | struct clock_event_device *evt) |
bb24c471 | 447 | { |
c7bbf52a PA |
448 | unsigned long ctrl; |
449 | uint64_t delta; | |
450 | int timer_num; | |
451 | struct apbt_dev *adev = EVT_TO_APBT_DEV(evt); | |
452 | ||
453 | timer_num = adev->num; | |
454 | pr_debug("%s CPU %d timer %d mode=%d\n", | |
455 | __func__, first_cpu(*evt->cpumask), timer_num, mode); | |
456 | ||
457 | switch (mode) { | |
458 | case CLOCK_EVT_MODE_PERIODIC: | |
459 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * apbt_clockevent.mult; | |
460 | delta >>= apbt_clockevent.shift; | |
461 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
462 | ctrl |= APBTMR_CONTROL_MODE_PERIODIC; | |
463 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
464 | /* | |
465 | * DW APB p. 46, have to disable timer before load counter, | |
466 | * may cause sync problem. | |
467 | */ | |
468 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
469 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
470 | udelay(1); | |
471 | pr_debug("Setting clock period %d for HZ %d\n", (int)delta, HZ); | |
472 | apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT); | |
473 | ctrl |= APBTMR_CONTROL_ENABLE; | |
474 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
475 | break; | |
476 | /* APB timer does not have one-shot mode, use free running mode */ | |
477 | case CLOCK_EVT_MODE_ONESHOT: | |
478 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
479 | /* | |
480 | * set free running mode, this mode will let timer reload max | |
481 | * timeout which will give time (3min on 25MHz clock) to rearm | |
482 | * the next event, therefore emulate the one-shot mode. | |
483 | */ | |
484 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
485 | ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; | |
486 | ||
487 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
488 | /* write again to set free running mode */ | |
489 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
490 | ||
491 | /* | |
492 | * DW APB p. 46, load counter with all 1s before starting free | |
493 | * running mode. | |
494 | */ | |
495 | apbt_writel(timer_num, ~0, APBTMR_N_LOAD_COUNT); | |
496 | ctrl &= ~APBTMR_CONTROL_INT; | |
497 | ctrl |= APBTMR_CONTROL_ENABLE; | |
498 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
499 | break; | |
500 | ||
501 | case CLOCK_EVT_MODE_UNUSED: | |
502 | case CLOCK_EVT_MODE_SHUTDOWN: | |
503 | apbt_disable_int(timer_num); | |
504 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
505 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
506 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
507 | break; | |
508 | ||
509 | case CLOCK_EVT_MODE_RESUME: | |
510 | apbt_enable_int(timer_num); | |
511 | break; | |
512 | } | |
bb24c471 JP |
513 | } |
514 | ||
515 | static int apbt_next_event(unsigned long delta, | |
c7bbf52a | 516 | struct clock_event_device *evt) |
bb24c471 | 517 | { |
c7bbf52a PA |
518 | unsigned long ctrl; |
519 | int timer_num; | |
520 | ||
521 | struct apbt_dev *adev = EVT_TO_APBT_DEV(evt); | |
522 | ||
523 | timer_num = adev->num; | |
524 | /* Disable timer */ | |
525 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
526 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
527 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
528 | /* write new count */ | |
529 | apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT); | |
530 | ctrl |= APBTMR_CONTROL_ENABLE; | |
531 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
532 | return 0; | |
bb24c471 JP |
533 | } |
534 | ||
535 | /* | |
536 | * APB timer clock is not in sync with pclk on Langwell, which translates to | |
537 | * unreliable read value caused by sampling error. the error does not add up | |
538 | * overtime and only happens when sampling a 0 as a 1 by mistake. so the time | |
539 | * would go backwards. the following code is trying to prevent time traveling | |
540 | * backwards. little bit paranoid. | |
541 | */ | |
542 | static cycle_t apbt_read_clocksource(struct clocksource *cs) | |
543 | { | |
c7bbf52a PA |
544 | unsigned long t0, t1, t2; |
545 | static unsigned long last_read; | |
bb24c471 JP |
546 | |
547 | bad_count: | |
c7bbf52a PA |
548 | t1 = apbt_readl(phy_cs_timer_id, |
549 | APBTMR_N_CURRENT_VALUE); | |
550 | t2 = apbt_readl(phy_cs_timer_id, | |
551 | APBTMR_N_CURRENT_VALUE); | |
552 | if (unlikely(t1 < t2)) { | |
553 | pr_debug("APBT: read current count error %lx:%lx:%lx\n", | |
554 | t1, t2, t2 - t1); | |
555 | goto bad_count; | |
556 | } | |
557 | /* | |
558 | * check against cached last read, makes sure time does not go back. | |
559 | * it could be a normal rollover but we will do tripple check anyway | |
560 | */ | |
561 | if (unlikely(t2 > last_read)) { | |
562 | /* check if we have a normal rollover */ | |
563 | unsigned long raw_intr_status = | |
564 | apbt_readl_reg(APBTMRS_RAW_INT_STATUS); | |
565 | /* | |
566 | * cs timer interrupt is masked but raw intr bit is set if | |
567 | * rollover occurs. then we read EOI reg to clear it. | |
568 | */ | |
569 | if (raw_intr_status & (1 << phy_cs_timer_id)) { | |
570 | apbt_readl(phy_cs_timer_id, APBTMR_N_EOI); | |
571 | goto out; | |
572 | } | |
573 | pr_debug("APB CS going back %lx:%lx:%lx ", | |
574 | t2, last_read, t2 - last_read); | |
bb24c471 | 575 | bad_count_x3: |
c7bbf52a PA |
576 | pr_debug(KERN_INFO "tripple check enforced\n"); |
577 | t0 = apbt_readl(phy_cs_timer_id, | |
578 | APBTMR_N_CURRENT_VALUE); | |
579 | udelay(1); | |
580 | t1 = apbt_readl(phy_cs_timer_id, | |
581 | APBTMR_N_CURRENT_VALUE); | |
582 | udelay(1); | |
583 | t2 = apbt_readl(phy_cs_timer_id, | |
584 | APBTMR_N_CURRENT_VALUE); | |
585 | if ((t2 > t1) || (t1 > t0)) { | |
586 | printk(KERN_ERR "Error: APB CS tripple check failed\n"); | |
587 | goto bad_count_x3; | |
588 | } | |
589 | } | |
bb24c471 | 590 | out: |
c7bbf52a PA |
591 | last_read = t2; |
592 | return (cycle_t)~t2; | |
bb24c471 JP |
593 | } |
594 | ||
595 | static int apbt_clocksource_register(void) | |
596 | { | |
c7bbf52a PA |
597 | u64 start, now; |
598 | cycle_t t1; | |
599 | ||
600 | /* Start the counter, use timer 2 as source, timer 0/1 for event */ | |
601 | apbt_start_counter(phy_cs_timer_id); | |
602 | ||
603 | /* Verify whether apbt counter works */ | |
604 | t1 = apbt_read_clocksource(&clocksource_apbt); | |
605 | rdtscll(start); | |
606 | ||
607 | /* | |
608 | * We don't know the TSC frequency yet, but waiting for | |
609 | * 200000 TSC cycles is safe: | |
610 | * 4 GHz == 50us | |
611 | * 1 GHz == 200us | |
612 | */ | |
613 | do { | |
614 | rep_nop(); | |
615 | rdtscll(now); | |
616 | } while ((now - start) < 200000UL); | |
617 | ||
618 | /* APBT is the only always on clocksource, it has to work! */ | |
619 | if (t1 == apbt_read_clocksource(&clocksource_apbt)) | |
620 | panic("APBT counter not counting. APBT disabled\n"); | |
621 | ||
622 | /* | |
623 | * initialize and register APBT clocksource | |
624 | * convert that to ns/clock cycle | |
625 | * mult = (ns/c) * 2^APBT_SHIFT | |
626 | */ | |
627 | clocksource_apbt.mult = div_sc(MSEC_PER_SEC, | |
628 | (unsigned long) apbt_freq, APBT_SHIFT); | |
629 | clocksource_register(&clocksource_apbt); | |
630 | ||
631 | return 0; | |
bb24c471 JP |
632 | } |
633 | ||
634 | /* | |
635 | * Early setup the APBT timer, only use timer 0 for booting then switch to | |
636 | * per CPU timer if possible. | |
637 | * returns 1 if per cpu apbt is setup | |
638 | * returns 0 if no per cpu apbt is chosen | |
639 | * panic if set up failed, this is the only platform timer on Moorestown. | |
640 | */ | |
641 | void __init apbt_time_init(void) | |
642 | { | |
643 | #ifdef CONFIG_SMP | |
c7bbf52a PA |
644 | int i; |
645 | struct sfi_timer_table_entry *p_mtmr; | |
646 | unsigned int percpu_timer; | |
647 | struct apbt_dev *adev; | |
bb24c471 JP |
648 | #endif |
649 | ||
c7bbf52a PA |
650 | if (apb_timer_block_enabled) |
651 | return; | |
652 | apbt_set_mapping(); | |
653 | if (apbt_virt_address) { | |
654 | pr_debug("Found APBT version 0x%lx\n",\ | |
655 | apbt_readl_reg(APBTMRS_COMP_VERSION)); | |
656 | } else | |
657 | goto out_noapbt; | |
658 | /* | |
659 | * Read the frequency and check for a sane value, for ESL model | |
660 | * we extend the possible clock range to allow time scaling. | |
661 | */ | |
662 | ||
663 | if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) { | |
664 | pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq); | |
665 | goto out_noapbt; | |
666 | } | |
667 | if (apbt_clocksource_register()) { | |
668 | pr_debug("APBT has failed to register clocksource\n"); | |
669 | goto out_noapbt; | |
670 | } | |
671 | if (!apbt_clockevent_register()) | |
672 | apb_timer_block_enabled = 1; | |
673 | else { | |
674 | pr_debug("APBT has failed to register clockevent\n"); | |
675 | goto out_noapbt; | |
676 | } | |
bb24c471 | 677 | #ifdef CONFIG_SMP |
c7bbf52a PA |
678 | /* kernel cmdline disable apb timer, so we will use lapic timers */ |
679 | if (disable_apbt_percpu) { | |
680 | printk(KERN_INFO "apbt: disabled per cpu timer\n"); | |
681 | return; | |
682 | } | |
683 | pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus()); | |
684 | if (num_possible_cpus() <= sfi_mtimer_num) { | |
685 | percpu_timer = 1; | |
686 | apbt_num_timers_used = num_possible_cpus(); | |
687 | } else { | |
688 | percpu_timer = 0; | |
689 | apbt_num_timers_used = 1; | |
690 | adev = &per_cpu(cpu_apbt_dev, 0); | |
691 | adev->flags &= ~APBT_DEV_USED; | |
692 | } | |
693 | pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used); | |
694 | ||
695 | /* here we set up per CPU timer data structure */ | |
696 | apbt_devs = kzalloc(sizeof(struct apbt_dev) * apbt_num_timers_used, | |
697 | GFP_KERNEL); | |
698 | if (!apbt_devs) { | |
699 | printk(KERN_ERR "Failed to allocate APB timer devices\n"); | |
700 | return; | |
701 | } | |
702 | for (i = 0; i < apbt_num_timers_used; i++) { | |
703 | adev = &per_cpu(cpu_apbt_dev, i); | |
704 | adev->num = i; | |
705 | adev->cpu = i; | |
706 | p_mtmr = sfi_get_mtmr(i); | |
707 | if (p_mtmr) { | |
708 | adev->tick = p_mtmr->freq_hz; | |
709 | adev->irq = p_mtmr->irq; | |
710 | } else | |
711 | printk(KERN_ERR "Failed to get timer for cpu %d\n", i); | |
712 | adev->count = 0; | |
713 | sprintf(adev->name, "apbt%d", i); | |
714 | } | |
bb24c471 JP |
715 | #endif |
716 | ||
c7bbf52a | 717 | return; |
bb24c471 JP |
718 | |
719 | out_noapbt: | |
c7bbf52a PA |
720 | apbt_clear_mapping(); |
721 | apb_timer_block_enabled = 0; | |
722 | panic("failed to enable APB timer\n"); | |
bb24c471 JP |
723 | } |
724 | ||
725 | static inline void apbt_disable(int n) | |
726 | { | |
c7bbf52a PA |
727 | if (is_apbt_capable()) { |
728 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); | |
729 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
730 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
731 | } | |
bb24c471 JP |
732 | } |
733 | ||
734 | /* called before apb_timer_enable, use early map */ | |
735 | unsigned long apbt_quick_calibrate() | |
736 | { | |
c7bbf52a PA |
737 | int i, scale; |
738 | u64 old, new; | |
739 | cycle_t t1, t2; | |
740 | unsigned long khz = 0; | |
741 | u32 loop, shift; | |
742 | ||
743 | apbt_set_mapping(); | |
744 | apbt_start_counter(phy_cs_timer_id); | |
745 | ||
746 | /* check if the timer can count down, otherwise return */ | |
747 | old = apbt_read_clocksource(&clocksource_apbt); | |
748 | i = 10000; | |
749 | while (--i) { | |
750 | if (old != apbt_read_clocksource(&clocksource_apbt)) | |
751 | break; | |
752 | } | |
753 | if (!i) | |
754 | goto failed; | |
755 | ||
756 | /* count 16 ms */ | |
757 | loop = (apbt_freq * 1000) << 4; | |
758 | ||
759 | /* restart the timer to ensure it won't get to 0 in the calibration */ | |
760 | apbt_start_counter(phy_cs_timer_id); | |
761 | ||
762 | old = apbt_read_clocksource(&clocksource_apbt); | |
763 | old += loop; | |
764 | ||
765 | t1 = __native_read_tsc(); | |
766 | ||
767 | do { | |
768 | new = apbt_read_clocksource(&clocksource_apbt); | |
769 | } while (new < old); | |
770 | ||
771 | t2 = __native_read_tsc(); | |
772 | ||
773 | shift = 5; | |
774 | if (unlikely(loop >> shift == 0)) { | |
775 | printk(KERN_INFO | |
776 | "APBT TSC calibration failed, not enough resolution\n"); | |
777 | return 0; | |
778 | } | |
779 | scale = (int)div_u64((t2 - t1), loop >> shift); | |
780 | khz = (scale * apbt_freq * 1000) >> shift; | |
781 | printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz); | |
782 | return khz; | |
bb24c471 | 783 | failed: |
c7bbf52a | 784 | return 0; |
bb24c471 | 785 | } |