Commit | Line | Data |
---|---|---|
bb24c471 JP |
1 | /* |
2 | * apb_timer.c: Driver for Langwell APB timers | |
3 | * | |
4 | * (C) Copyright 2009 Intel Corporation | |
5 | * Author: Jacob Pan (jacob.jun.pan@intel.com) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | * | |
12 | * Note: | |
13 | * Langwell is the south complex of Intel Moorestown MID platform. There are | |
14 | * eight external timers in total that can be used by the operating system. | |
15 | * The timer information, such as frequency and addresses, is provided to the | |
16 | * OS via SFI tables. | |
17 | * Timer interrupts are routed via FW/HW emulated IOAPIC independently via | |
18 | * individual redirection table entries (RTE). | |
19 | * Unlike HPET, there is no master counter, therefore one of the timers are | |
20 | * used as clocksource. The overall allocation looks like: | |
21 | * - timer 0 - NR_CPUs for per cpu timer | |
22 | * - one timer for clocksource | |
23 | * - one timer for watchdog driver. | |
24 | * It is also worth notice that APB timer does not support true one-shot mode, | |
25 | * free-running mode will be used here to emulate one-shot mode. | |
26 | * APB timer can also be used as broadcast timer along with per cpu local APIC | |
27 | * timer, but by default APB timer has higher rating than local APIC timers. | |
28 | */ | |
29 | ||
30 | #include <linux/clocksource.h> | |
31 | #include <linux/clockchips.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/sysdev.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
bb24c471 JP |
37 | #include <linux/pm.h> |
38 | #include <linux/pci.h> | |
39 | #include <linux/sfi.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/cpu.h> | |
42 | #include <linux/irq.h> | |
43 | ||
44 | #include <asm/fixmap.h> | |
45 | #include <asm/apb_timer.h> | |
a875c019 | 46 | #include <asm/mrst.h> |
bb24c471 | 47 | |
c7bbf52a PA |
48 | #define APBT_MASK CLOCKSOURCE_MASK(32) |
49 | #define APBT_SHIFT 22 | |
a875c019 | 50 | #define APBT_CLOCKEVENT_RATING 110 |
c7bbf52a PA |
51 | #define APBT_CLOCKSOURCE_RATING 250 |
52 | #define APBT_MIN_DELTA_USEC 200 | |
bb24c471 JP |
53 | |
54 | #define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt) | |
55 | #define APBT_CLOCKEVENT0_NUM (0) | |
56 | #define APBT_CLOCKEVENT1_NUM (1) | |
57 | #define APBT_CLOCKSOURCE_NUM (2) | |
58 | ||
59 | static unsigned long apbt_address; | |
60 | static int apb_timer_block_enabled; | |
61 | static void __iomem *apbt_virt_address; | |
62 | static int phy_cs_timer_id; | |
63 | ||
64 | /* | |
65 | * Common DW APB timer info | |
66 | */ | |
67 | static uint64_t apbt_freq; | |
68 | ||
69 | static void apbt_set_mode(enum clock_event_mode mode, | |
c7bbf52a | 70 | struct clock_event_device *evt); |
bb24c471 | 71 | static int apbt_next_event(unsigned long delta, |
c7bbf52a | 72 | struct clock_event_device *evt); |
bb24c471 | 73 | static cycle_t apbt_read_clocksource(struct clocksource *cs); |
322aafa6 | 74 | static void apbt_restart_clocksource(struct clocksource *cs); |
bb24c471 JP |
75 | |
76 | struct apbt_dev { | |
c7bbf52a PA |
77 | struct clock_event_device evt; |
78 | unsigned int num; | |
79 | int cpu; | |
80 | unsigned int irq; | |
81 | unsigned int tick; | |
82 | unsigned int count; | |
83 | unsigned int flags; | |
84 | char name[10]; | |
bb24c471 JP |
85 | }; |
86 | ||
3010673e JP |
87 | static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev); |
88 | ||
bb24c471 JP |
89 | #ifdef CONFIG_SMP |
90 | static unsigned int apbt_num_timers_used; | |
bb24c471 JP |
91 | static struct apbt_dev *apbt_devs; |
92 | #endif | |
93 | ||
c7bbf52a | 94 | static inline unsigned long apbt_readl_reg(unsigned long a) |
bb24c471 | 95 | { |
c7bbf52a | 96 | return readl(apbt_virt_address + a); |
bb24c471 JP |
97 | } |
98 | ||
99 | static inline void apbt_writel_reg(unsigned long d, unsigned long a) | |
100 | { | |
c7bbf52a | 101 | writel(d, apbt_virt_address + a); |
bb24c471 JP |
102 | } |
103 | ||
104 | static inline unsigned long apbt_readl(int n, unsigned long a) | |
105 | { | |
c7bbf52a | 106 | return readl(apbt_virt_address + a + n * APBTMRS_REG_SIZE); |
bb24c471 JP |
107 | } |
108 | ||
109 | static inline void apbt_writel(int n, unsigned long d, unsigned long a) | |
110 | { | |
c7bbf52a | 111 | writel(d, apbt_virt_address + a + n * APBTMRS_REG_SIZE); |
bb24c471 JP |
112 | } |
113 | ||
114 | static inline void apbt_set_mapping(void) | |
115 | { | |
c7bbf52a PA |
116 | struct sfi_timer_table_entry *mtmr; |
117 | ||
118 | if (apbt_virt_address) { | |
119 | pr_debug("APBT base already mapped\n"); | |
120 | return; | |
121 | } | |
122 | mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM); | |
123 | if (mtmr == NULL) { | |
124 | printk(KERN_ERR "Failed to get MTMR %d from SFI\n", | |
125 | APBT_CLOCKEVENT0_NUM); | |
126 | return; | |
127 | } | |
128 | apbt_address = (unsigned long)mtmr->phys_addr; | |
129 | if (!apbt_address) { | |
130 | printk(KERN_WARNING "No timer base from SFI, use default\n"); | |
131 | apbt_address = APBT_DEFAULT_BASE; | |
132 | } | |
133 | apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE); | |
134 | if (apbt_virt_address) { | |
135 | pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\ | |
136 | (void *)apbt_address, (void *)apbt_virt_address); | |
137 | } else { | |
138 | pr_debug("Failed mapping APBT phy address at %p\n",\ | |
139 | (void *)apbt_address); | |
140 | goto panic_noapbt; | |
141 | } | |
142 | apbt_freq = mtmr->freq_hz / USEC_PER_SEC; | |
143 | sfi_free_mtmr(mtmr); | |
144 | ||
145 | /* Now figure out the physical timer id for clocksource device */ | |
146 | mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM); | |
147 | if (mtmr == NULL) | |
148 | goto panic_noapbt; | |
149 | ||
150 | /* Now figure out the physical timer id */ | |
151 | phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) | |
152 | / APBTMRS_REG_SIZE; | |
153 | pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id); | |
154 | return; | |
bb24c471 JP |
155 | |
156 | panic_noapbt: | |
c7bbf52a | 157 | panic("Failed to setup APB system timer\n"); |
bb24c471 JP |
158 | |
159 | } | |
160 | ||
161 | static inline void apbt_clear_mapping(void) | |
162 | { | |
c7bbf52a PA |
163 | iounmap(apbt_virt_address); |
164 | apbt_virt_address = NULL; | |
bb24c471 JP |
165 | } |
166 | ||
167 | /* | |
168 | * APBT timer interrupt enable / disable | |
169 | */ | |
170 | static inline int is_apbt_capable(void) | |
171 | { | |
c7bbf52a | 172 | return apbt_virt_address ? 1 : 0; |
bb24c471 JP |
173 | } |
174 | ||
175 | static struct clocksource clocksource_apbt = { | |
c7bbf52a PA |
176 | .name = "apbt", |
177 | .rating = APBT_CLOCKSOURCE_RATING, | |
178 | .read = apbt_read_clocksource, | |
179 | .mask = APBT_MASK, | |
180 | .shift = APBT_SHIFT, | |
181 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
182 | .resume = apbt_restart_clocksource, | |
bb24c471 JP |
183 | }; |
184 | ||
185 | /* boot APB clock event device */ | |
186 | static struct clock_event_device apbt_clockevent = { | |
c7bbf52a PA |
187 | .name = "apbt0", |
188 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
189 | .set_mode = apbt_set_mode, | |
190 | .set_next_event = apbt_next_event, | |
191 | .shift = APBT_SHIFT, | |
192 | .irq = 0, | |
193 | .rating = APBT_CLOCKEVENT_RATING, | |
bb24c471 JP |
194 | }; |
195 | ||
bb24c471 JP |
196 | /* |
197 | * start count down from 0xffff_ffff. this is done by toggling the enable bit | |
198 | * then load initial load count to ~0. | |
199 | */ | |
200 | static void apbt_start_counter(int n) | |
201 | { | |
c7bbf52a PA |
202 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
203 | ||
204 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
205 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
206 | apbt_writel(n, ~0, APBTMR_N_LOAD_COUNT); | |
207 | /* enable, mask interrupt */ | |
208 | ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; | |
209 | ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT); | |
210 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
211 | /* read it once to get cached counter value initialized */ | |
212 | apbt_read_clocksource(&clocksource_apbt); | |
bb24c471 JP |
213 | } |
214 | ||
215 | static irqreturn_t apbt_interrupt_handler(int irq, void *data) | |
216 | { | |
c7bbf52a PA |
217 | struct apbt_dev *dev = (struct apbt_dev *)data; |
218 | struct clock_event_device *aevt = &dev->evt; | |
219 | ||
220 | if (!aevt->event_handler) { | |
221 | printk(KERN_INFO "Spurious APBT timer interrupt on %d\n", | |
222 | dev->num); | |
223 | return IRQ_NONE; | |
224 | } | |
225 | aevt->event_handler(aevt); | |
226 | return IRQ_HANDLED; | |
bb24c471 JP |
227 | } |
228 | ||
322aafa6 | 229 | static void apbt_restart_clocksource(struct clocksource *cs) |
bb24c471 | 230 | { |
c7bbf52a | 231 | apbt_start_counter(phy_cs_timer_id); |
bb24c471 JP |
232 | } |
233 | ||
bb24c471 JP |
234 | static void apbt_enable_int(int n) |
235 | { | |
c7bbf52a PA |
236 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
237 | /* clear pending intr */ | |
238 | apbt_readl(n, APBTMR_N_EOI); | |
239 | ctrl &= ~APBTMR_CONTROL_INT; | |
240 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
bb24c471 JP |
241 | } |
242 | ||
243 | static void apbt_disable_int(int n) | |
244 | { | |
c7bbf52a | 245 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); |
bb24c471 | 246 | |
c7bbf52a PA |
247 | ctrl |= APBTMR_CONTROL_INT; |
248 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
bb24c471 JP |
249 | } |
250 | ||
251 | ||
252 | static int __init apbt_clockevent_register(void) | |
253 | { | |
c7bbf52a PA |
254 | struct sfi_timer_table_entry *mtmr; |
255 | struct apbt_dev *adev = &__get_cpu_var(cpu_apbt_dev); | |
256 | ||
257 | mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM); | |
258 | if (mtmr == NULL) { | |
259 | printk(KERN_ERR "Failed to get MTMR %d from SFI\n", | |
260 | APBT_CLOCKEVENT0_NUM); | |
261 | return -ENODEV; | |
262 | } | |
263 | ||
264 | /* | |
265 | * We need to calculate the scaled math multiplication factor for | |
266 | * nanosecond to apbt tick conversion. | |
267 | * mult = (nsec/cycle)*2^APBT_SHIFT | |
268 | */ | |
269 | apbt_clockevent.mult = div_sc((unsigned long) mtmr->freq_hz | |
270 | , NSEC_PER_SEC, APBT_SHIFT); | |
271 | ||
272 | /* Calculate the min / max delta */ | |
273 | apbt_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
274 | &apbt_clockevent); | |
275 | apbt_clockevent.min_delta_ns = clockevent_delta2ns( | |
276 | APBT_MIN_DELTA_USEC*apbt_freq, | |
277 | &apbt_clockevent); | |
278 | /* | |
279 | * Start apbt with the boot cpu mask and make it | |
280 | * global if not used for per cpu timer. | |
281 | */ | |
282 | apbt_clockevent.cpumask = cpumask_of(smp_processor_id()); | |
283 | adev->num = smp_processor_id(); | |
284 | memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device)); | |
285 | ||
a875c019 | 286 | if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) { |
c7bbf52a | 287 | apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100; |
3010673e | 288 | global_clock_event = &adev->evt; |
c7bbf52a PA |
289 | printk(KERN_DEBUG "%s clockevent registered as global\n", |
290 | global_clock_event->name); | |
291 | } | |
292 | ||
293 | if (request_irq(apbt_clockevent.irq, apbt_interrupt_handler, | |
294 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, | |
295 | apbt_clockevent.name, adev)) { | |
296 | printk(KERN_ERR "Failed request IRQ for APBT%d\n", | |
297 | apbt_clockevent.irq); | |
298 | } | |
299 | ||
300 | clockevents_register_device(&adev->evt); | |
301 | /* Start APBT 0 interrupts */ | |
302 | apbt_enable_int(APBT_CLOCKEVENT0_NUM); | |
303 | ||
304 | sfi_free_mtmr(mtmr); | |
305 | return 0; | |
bb24c471 JP |
306 | } |
307 | ||
308 | #ifdef CONFIG_SMP | |
a5ef2e70 TG |
309 | |
310 | static void apbt_setup_irq(struct apbt_dev *adev) | |
311 | { | |
312 | /* timer0 irq has been setup early */ | |
313 | if (adev->irq == 0) | |
314 | return; | |
315 | ||
316 | if (system_state == SYSTEM_BOOTING) { | |
317 | irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT); | |
318 | /* APB timer irqs are set up as mp_irqs, timer is edge type */ | |
319 | __set_irq_handler(adev->irq, handle_edge_irq, 0, "edge"); | |
320 | if (request_irq(adev->irq, apbt_interrupt_handler, | |
321 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, | |
322 | adev->name, adev)) { | |
323 | printk(KERN_ERR "Failed request IRQ for APBT%d\n", | |
324 | adev->num); | |
325 | } | |
326 | } else | |
327 | enable_irq(adev->irq); | |
328 | } | |
329 | ||
bb24c471 JP |
330 | /* Should be called with per cpu */ |
331 | void apbt_setup_secondary_clock(void) | |
332 | { | |
c7bbf52a PA |
333 | struct apbt_dev *adev; |
334 | struct clock_event_device *aevt; | |
335 | int cpu; | |
336 | ||
337 | /* Don't register boot CPU clockevent */ | |
338 | cpu = smp_processor_id(); | |
f6e9456c | 339 | if (!cpu) |
c7bbf52a PA |
340 | return; |
341 | /* | |
342 | * We need to calculate the scaled math multiplication factor for | |
343 | * nanosecond to apbt tick conversion. | |
344 | * mult = (nsec/cycle)*2^APBT_SHIFT | |
345 | */ | |
346 | printk(KERN_INFO "Init per CPU clockevent %d\n", cpu); | |
347 | adev = &per_cpu(cpu_apbt_dev, cpu); | |
348 | aevt = &adev->evt; | |
349 | ||
350 | memcpy(aevt, &apbt_clockevent, sizeof(*aevt)); | |
351 | aevt->cpumask = cpumask_of(cpu); | |
352 | aevt->name = adev->name; | |
353 | aevt->mode = CLOCK_EVT_MODE_UNUSED; | |
354 | ||
355 | printk(KERN_INFO "Registering CPU %d clockevent device %s, mask %08x\n", | |
356 | cpu, aevt->name, *(u32 *)aevt->cpumask); | |
357 | ||
358 | apbt_setup_irq(adev); | |
359 | ||
360 | clockevents_register_device(aevt); | |
361 | ||
362 | apbt_enable_int(cpu); | |
363 | ||
364 | return; | |
bb24c471 JP |
365 | } |
366 | ||
367 | /* | |
368 | * this notify handler process CPU hotplug events. in case of S0i3, nonboot | |
369 | * cpus are disabled/enabled frequently, for performance reasons, we keep the | |
370 | * per cpu timer irq registered so that we do need to do free_irq/request_irq. | |
371 | * | |
372 | * TODO: it might be more reliable to directly disable percpu clockevent device | |
373 | * without the notifier chain. currently, cpu 0 may get interrupts from other | |
374 | * cpu timers during the offline process due to the ordering of notification. | |
375 | * the extra interrupt is harmless. | |
376 | */ | |
377 | static int apbt_cpuhp_notify(struct notifier_block *n, | |
c7bbf52a | 378 | unsigned long action, void *hcpu) |
bb24c471 | 379 | { |
c7bbf52a PA |
380 | unsigned long cpu = (unsigned long)hcpu; |
381 | struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu); | |
382 | ||
383 | switch (action & 0xf) { | |
384 | case CPU_DEAD: | |
a5ef2e70 | 385 | disable_irq(adev->irq); |
c7bbf52a | 386 | apbt_disable_int(cpu); |
a5ef2e70 | 387 | if (system_state == SYSTEM_RUNNING) { |
c7bbf52a | 388 | pr_debug("skipping APBT CPU %lu offline\n", cpu); |
a5ef2e70 | 389 | } else if (adev) { |
c7bbf52a PA |
390 | pr_debug("APBT clockevent for cpu %lu offline\n", cpu); |
391 | free_irq(adev->irq, adev); | |
392 | } | |
393 | break; | |
394 | default: | |
d0ed0c32 | 395 | pr_debug("APBT notified %lu, no action\n", action); |
c7bbf52a PA |
396 | } |
397 | return NOTIFY_OK; | |
bb24c471 JP |
398 | } |
399 | ||
400 | static __init int apbt_late_init(void) | |
401 | { | |
a875c019 JP |
402 | if (mrst_timer_options == MRST_TIMER_LAPIC_APBT || |
403 | !apb_timer_block_enabled) | |
c7bbf52a PA |
404 | return 0; |
405 | /* This notifier should be called after workqueue is ready */ | |
406 | hotcpu_notifier(apbt_cpuhp_notify, -20); | |
407 | return 0; | |
bb24c471 JP |
408 | } |
409 | fs_initcall(apbt_late_init); | |
410 | #else | |
411 | ||
412 | void apbt_setup_secondary_clock(void) {} | |
413 | ||
414 | #endif /* CONFIG_SMP */ | |
415 | ||
416 | static void apbt_set_mode(enum clock_event_mode mode, | |
c7bbf52a | 417 | struct clock_event_device *evt) |
bb24c471 | 418 | { |
c7bbf52a PA |
419 | unsigned long ctrl; |
420 | uint64_t delta; | |
421 | int timer_num; | |
422 | struct apbt_dev *adev = EVT_TO_APBT_DEV(evt); | |
423 | ||
a875c019 JP |
424 | BUG_ON(!apbt_virt_address); |
425 | ||
c7bbf52a PA |
426 | timer_num = adev->num; |
427 | pr_debug("%s CPU %d timer %d mode=%d\n", | |
428 | __func__, first_cpu(*evt->cpumask), timer_num, mode); | |
429 | ||
430 | switch (mode) { | |
431 | case CLOCK_EVT_MODE_PERIODIC: | |
432 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * apbt_clockevent.mult; | |
433 | delta >>= apbt_clockevent.shift; | |
434 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
435 | ctrl |= APBTMR_CONTROL_MODE_PERIODIC; | |
436 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
437 | /* | |
438 | * DW APB p. 46, have to disable timer before load counter, | |
439 | * may cause sync problem. | |
440 | */ | |
441 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
442 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
443 | udelay(1); | |
444 | pr_debug("Setting clock period %d for HZ %d\n", (int)delta, HZ); | |
445 | apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT); | |
446 | ctrl |= APBTMR_CONTROL_ENABLE; | |
447 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
448 | break; | |
449 | /* APB timer does not have one-shot mode, use free running mode */ | |
450 | case CLOCK_EVT_MODE_ONESHOT: | |
451 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
452 | /* | |
453 | * set free running mode, this mode will let timer reload max | |
454 | * timeout which will give time (3min on 25MHz clock) to rearm | |
455 | * the next event, therefore emulate the one-shot mode. | |
456 | */ | |
457 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
458 | ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; | |
459 | ||
460 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
461 | /* write again to set free running mode */ | |
462 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
463 | ||
464 | /* | |
465 | * DW APB p. 46, load counter with all 1s before starting free | |
466 | * running mode. | |
467 | */ | |
468 | apbt_writel(timer_num, ~0, APBTMR_N_LOAD_COUNT); | |
469 | ctrl &= ~APBTMR_CONTROL_INT; | |
470 | ctrl |= APBTMR_CONTROL_ENABLE; | |
471 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
472 | break; | |
473 | ||
474 | case CLOCK_EVT_MODE_UNUSED: | |
475 | case CLOCK_EVT_MODE_SHUTDOWN: | |
476 | apbt_disable_int(timer_num); | |
477 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
478 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
479 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
480 | break; | |
481 | ||
482 | case CLOCK_EVT_MODE_RESUME: | |
483 | apbt_enable_int(timer_num); | |
484 | break; | |
485 | } | |
bb24c471 JP |
486 | } |
487 | ||
488 | static int apbt_next_event(unsigned long delta, | |
c7bbf52a | 489 | struct clock_event_device *evt) |
bb24c471 | 490 | { |
c7bbf52a PA |
491 | unsigned long ctrl; |
492 | int timer_num; | |
493 | ||
494 | struct apbt_dev *adev = EVT_TO_APBT_DEV(evt); | |
495 | ||
496 | timer_num = adev->num; | |
497 | /* Disable timer */ | |
498 | ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL); | |
499 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
500 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
501 | /* write new count */ | |
502 | apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT); | |
503 | ctrl |= APBTMR_CONTROL_ENABLE; | |
504 | apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL); | |
505 | return 0; | |
bb24c471 JP |
506 | } |
507 | ||
508 | /* | |
509 | * APB timer clock is not in sync with pclk on Langwell, which translates to | |
510 | * unreliable read value caused by sampling error. the error does not add up | |
511 | * overtime and only happens when sampling a 0 as a 1 by mistake. so the time | |
512 | * would go backwards. the following code is trying to prevent time traveling | |
513 | * backwards. little bit paranoid. | |
514 | */ | |
515 | static cycle_t apbt_read_clocksource(struct clocksource *cs) | |
516 | { | |
c7bbf52a PA |
517 | unsigned long t0, t1, t2; |
518 | static unsigned long last_read; | |
bb24c471 JP |
519 | |
520 | bad_count: | |
c7bbf52a PA |
521 | t1 = apbt_readl(phy_cs_timer_id, |
522 | APBTMR_N_CURRENT_VALUE); | |
523 | t2 = apbt_readl(phy_cs_timer_id, | |
524 | APBTMR_N_CURRENT_VALUE); | |
525 | if (unlikely(t1 < t2)) { | |
526 | pr_debug("APBT: read current count error %lx:%lx:%lx\n", | |
527 | t1, t2, t2 - t1); | |
528 | goto bad_count; | |
529 | } | |
530 | /* | |
531 | * check against cached last read, makes sure time does not go back. | |
532 | * it could be a normal rollover but we will do tripple check anyway | |
533 | */ | |
534 | if (unlikely(t2 > last_read)) { | |
535 | /* check if we have a normal rollover */ | |
536 | unsigned long raw_intr_status = | |
537 | apbt_readl_reg(APBTMRS_RAW_INT_STATUS); | |
538 | /* | |
539 | * cs timer interrupt is masked but raw intr bit is set if | |
540 | * rollover occurs. then we read EOI reg to clear it. | |
541 | */ | |
542 | if (raw_intr_status & (1 << phy_cs_timer_id)) { | |
543 | apbt_readl(phy_cs_timer_id, APBTMR_N_EOI); | |
544 | goto out; | |
545 | } | |
546 | pr_debug("APB CS going back %lx:%lx:%lx ", | |
547 | t2, last_read, t2 - last_read); | |
bb24c471 | 548 | bad_count_x3: |
d0ed0c32 | 549 | pr_debug("triple check enforced\n"); |
c7bbf52a PA |
550 | t0 = apbt_readl(phy_cs_timer_id, |
551 | APBTMR_N_CURRENT_VALUE); | |
552 | udelay(1); | |
553 | t1 = apbt_readl(phy_cs_timer_id, | |
554 | APBTMR_N_CURRENT_VALUE); | |
555 | udelay(1); | |
556 | t2 = apbt_readl(phy_cs_timer_id, | |
557 | APBTMR_N_CURRENT_VALUE); | |
558 | if ((t2 > t1) || (t1 > t0)) { | |
559 | printk(KERN_ERR "Error: APB CS tripple check failed\n"); | |
560 | goto bad_count_x3; | |
561 | } | |
562 | } | |
bb24c471 | 563 | out: |
c7bbf52a PA |
564 | last_read = t2; |
565 | return (cycle_t)~t2; | |
bb24c471 JP |
566 | } |
567 | ||
568 | static int apbt_clocksource_register(void) | |
569 | { | |
c7bbf52a PA |
570 | u64 start, now; |
571 | cycle_t t1; | |
572 | ||
573 | /* Start the counter, use timer 2 as source, timer 0/1 for event */ | |
574 | apbt_start_counter(phy_cs_timer_id); | |
575 | ||
576 | /* Verify whether apbt counter works */ | |
577 | t1 = apbt_read_clocksource(&clocksource_apbt); | |
578 | rdtscll(start); | |
579 | ||
580 | /* | |
581 | * We don't know the TSC frequency yet, but waiting for | |
582 | * 200000 TSC cycles is safe: | |
583 | * 4 GHz == 50us | |
584 | * 1 GHz == 200us | |
585 | */ | |
586 | do { | |
587 | rep_nop(); | |
588 | rdtscll(now); | |
589 | } while ((now - start) < 200000UL); | |
590 | ||
591 | /* APBT is the only always on clocksource, it has to work! */ | |
592 | if (t1 == apbt_read_clocksource(&clocksource_apbt)) | |
593 | panic("APBT counter not counting. APBT disabled\n"); | |
594 | ||
595 | /* | |
596 | * initialize and register APBT clocksource | |
597 | * convert that to ns/clock cycle | |
598 | * mult = (ns/c) * 2^APBT_SHIFT | |
599 | */ | |
600 | clocksource_apbt.mult = div_sc(MSEC_PER_SEC, | |
601 | (unsigned long) apbt_freq, APBT_SHIFT); | |
602 | clocksource_register(&clocksource_apbt); | |
603 | ||
604 | return 0; | |
bb24c471 JP |
605 | } |
606 | ||
607 | /* | |
608 | * Early setup the APBT timer, only use timer 0 for booting then switch to | |
609 | * per CPU timer if possible. | |
610 | * returns 1 if per cpu apbt is setup | |
611 | * returns 0 if no per cpu apbt is chosen | |
612 | * panic if set up failed, this is the only platform timer on Moorestown. | |
613 | */ | |
614 | void __init apbt_time_init(void) | |
615 | { | |
616 | #ifdef CONFIG_SMP | |
c7bbf52a PA |
617 | int i; |
618 | struct sfi_timer_table_entry *p_mtmr; | |
619 | unsigned int percpu_timer; | |
620 | struct apbt_dev *adev; | |
bb24c471 JP |
621 | #endif |
622 | ||
c7bbf52a PA |
623 | if (apb_timer_block_enabled) |
624 | return; | |
625 | apbt_set_mapping(); | |
626 | if (apbt_virt_address) { | |
627 | pr_debug("Found APBT version 0x%lx\n",\ | |
628 | apbt_readl_reg(APBTMRS_COMP_VERSION)); | |
629 | } else | |
630 | goto out_noapbt; | |
631 | /* | |
632 | * Read the frequency and check for a sane value, for ESL model | |
633 | * we extend the possible clock range to allow time scaling. | |
634 | */ | |
635 | ||
636 | if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) { | |
637 | pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq); | |
638 | goto out_noapbt; | |
639 | } | |
640 | if (apbt_clocksource_register()) { | |
641 | pr_debug("APBT has failed to register clocksource\n"); | |
642 | goto out_noapbt; | |
643 | } | |
644 | if (!apbt_clockevent_register()) | |
645 | apb_timer_block_enabled = 1; | |
646 | else { | |
647 | pr_debug("APBT has failed to register clockevent\n"); | |
648 | goto out_noapbt; | |
649 | } | |
bb24c471 | 650 | #ifdef CONFIG_SMP |
c7bbf52a | 651 | /* kernel cmdline disable apb timer, so we will use lapic timers */ |
a875c019 | 652 | if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) { |
c7bbf52a PA |
653 | printk(KERN_INFO "apbt: disabled per cpu timer\n"); |
654 | return; | |
655 | } | |
656 | pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus()); | |
657 | if (num_possible_cpus() <= sfi_mtimer_num) { | |
658 | percpu_timer = 1; | |
659 | apbt_num_timers_used = num_possible_cpus(); | |
660 | } else { | |
661 | percpu_timer = 0; | |
662 | apbt_num_timers_used = 1; | |
663 | adev = &per_cpu(cpu_apbt_dev, 0); | |
664 | adev->flags &= ~APBT_DEV_USED; | |
665 | } | |
666 | pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used); | |
667 | ||
668 | /* here we set up per CPU timer data structure */ | |
669 | apbt_devs = kzalloc(sizeof(struct apbt_dev) * apbt_num_timers_used, | |
670 | GFP_KERNEL); | |
671 | if (!apbt_devs) { | |
672 | printk(KERN_ERR "Failed to allocate APB timer devices\n"); | |
673 | return; | |
674 | } | |
675 | for (i = 0; i < apbt_num_timers_used; i++) { | |
676 | adev = &per_cpu(cpu_apbt_dev, i); | |
677 | adev->num = i; | |
678 | adev->cpu = i; | |
679 | p_mtmr = sfi_get_mtmr(i); | |
680 | if (p_mtmr) { | |
681 | adev->tick = p_mtmr->freq_hz; | |
682 | adev->irq = p_mtmr->irq; | |
683 | } else | |
684 | printk(KERN_ERR "Failed to get timer for cpu %d\n", i); | |
685 | adev->count = 0; | |
686 | sprintf(adev->name, "apbt%d", i); | |
687 | } | |
bb24c471 JP |
688 | #endif |
689 | ||
c7bbf52a | 690 | return; |
bb24c471 JP |
691 | |
692 | out_noapbt: | |
c7bbf52a PA |
693 | apbt_clear_mapping(); |
694 | apb_timer_block_enabled = 0; | |
695 | panic("failed to enable APB timer\n"); | |
bb24c471 JP |
696 | } |
697 | ||
698 | static inline void apbt_disable(int n) | |
699 | { | |
c7bbf52a PA |
700 | if (is_apbt_capable()) { |
701 | unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL); | |
702 | ctrl &= ~APBTMR_CONTROL_ENABLE; | |
703 | apbt_writel(n, ctrl, APBTMR_N_CONTROL); | |
704 | } | |
bb24c471 JP |
705 | } |
706 | ||
707 | /* called before apb_timer_enable, use early map */ | |
708 | unsigned long apbt_quick_calibrate() | |
709 | { | |
c7bbf52a PA |
710 | int i, scale; |
711 | u64 old, new; | |
712 | cycle_t t1, t2; | |
713 | unsigned long khz = 0; | |
714 | u32 loop, shift; | |
715 | ||
716 | apbt_set_mapping(); | |
717 | apbt_start_counter(phy_cs_timer_id); | |
718 | ||
719 | /* check if the timer can count down, otherwise return */ | |
720 | old = apbt_read_clocksource(&clocksource_apbt); | |
721 | i = 10000; | |
722 | while (--i) { | |
723 | if (old != apbt_read_clocksource(&clocksource_apbt)) | |
724 | break; | |
725 | } | |
726 | if (!i) | |
727 | goto failed; | |
728 | ||
729 | /* count 16 ms */ | |
730 | loop = (apbt_freq * 1000) << 4; | |
731 | ||
732 | /* restart the timer to ensure it won't get to 0 in the calibration */ | |
733 | apbt_start_counter(phy_cs_timer_id); | |
734 | ||
735 | old = apbt_read_clocksource(&clocksource_apbt); | |
736 | old += loop; | |
737 | ||
738 | t1 = __native_read_tsc(); | |
739 | ||
740 | do { | |
741 | new = apbt_read_clocksource(&clocksource_apbt); | |
742 | } while (new < old); | |
743 | ||
744 | t2 = __native_read_tsc(); | |
745 | ||
746 | shift = 5; | |
747 | if (unlikely(loop >> shift == 0)) { | |
748 | printk(KERN_INFO | |
749 | "APBT TSC calibration failed, not enough resolution\n"); | |
750 | return 0; | |
751 | } | |
752 | scale = (int)div_u64((t2 - t1), loop >> shift); | |
753 | khz = (scale * apbt_freq * 1000) >> shift; | |
754 | printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz); | |
755 | return khz; | |
bb24c471 | 756 | failed: |
c7bbf52a | 757 | return 0; |
bb24c471 | 758 | } |