Commit | Line | Data |
---|---|---|
f6e2e6b6 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/list.h> | |
7441e9cb | 24 | #include <linux/sysdev.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
f6e2e6b6 JR |
27 | #include <asm/pci-direct.h> |
28 | #include <asm/amd_iommu_types.h> | |
c6da992e | 29 | #include <asm/amd_iommu.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
f6e2e6b6 JR |
31 | |
32 | /* | |
33 | * definitions for the ACPI scanning code | |
34 | */ | |
f6e2e6b6 | 35 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
36 | |
37 | #define ACPI_IVHD_TYPE 0x10 | |
38 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
39 | #define ACPI_IVMD_TYPE 0x21 | |
40 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
41 | ||
42 | #define IVHD_DEV_ALL 0x01 | |
43 | #define IVHD_DEV_SELECT 0x02 | |
44 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
45 | #define IVHD_DEV_RANGE_END 0x04 | |
46 | #define IVHD_DEV_ALIAS 0x42 | |
47 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
48 | #define IVHD_DEV_EXT_SELECT 0x46 | |
49 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
50 | ||
51 | #define IVHD_FLAG_HT_TUN_EN 0x00 | |
52 | #define IVHD_FLAG_PASSPW_EN 0x01 | |
53 | #define IVHD_FLAG_RESPASSPW_EN 0x02 | |
54 | #define IVHD_FLAG_ISOC_EN 0x03 | |
55 | ||
56 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
57 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
58 | ||
59 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
60 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
61 | #define ACPI_DEVFLAG_NMI 0x04 | |
62 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
63 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
64 | #define ACPI_DEVFLAG_LINT0 0x40 | |
65 | #define ACPI_DEVFLAG_LINT1 0x80 | |
66 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
67 | ||
b65233a9 JR |
68 | /* |
69 | * ACPI table definitions | |
70 | * | |
71 | * These data structures are laid over the table to parse the important values | |
72 | * out of it. | |
73 | */ | |
74 | ||
75 | /* | |
76 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
77 | * or more ivhd_entrys. | |
78 | */ | |
f6e2e6b6 JR |
79 | struct ivhd_header { |
80 | u8 type; | |
81 | u8 flags; | |
82 | u16 length; | |
83 | u16 devid; | |
84 | u16 cap_ptr; | |
85 | u64 mmio_phys; | |
86 | u16 pci_seg; | |
87 | u16 info; | |
88 | u32 reserved; | |
89 | } __attribute__((packed)); | |
90 | ||
b65233a9 JR |
91 | /* |
92 | * A device entry describing which devices a specific IOMMU translates and | |
93 | * which requestor ids they use. | |
94 | */ | |
f6e2e6b6 JR |
95 | struct ivhd_entry { |
96 | u8 type; | |
97 | u16 devid; | |
98 | u8 flags; | |
99 | u32 ext; | |
100 | } __attribute__((packed)); | |
101 | ||
b65233a9 JR |
102 | /* |
103 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
104 | * ranges for devices and regions that should be unity mapped. | |
105 | */ | |
f6e2e6b6 JR |
106 | struct ivmd_header { |
107 | u8 type; | |
108 | u8 flags; | |
109 | u16 length; | |
110 | u16 devid; | |
111 | u16 aux; | |
112 | u64 resv; | |
113 | u64 range_start; | |
114 | u64 range_length; | |
115 | } __attribute__((packed)); | |
116 | ||
c1cbebee JR |
117 | static int __initdata amd_iommu_detected; |
118 | ||
b65233a9 JR |
119 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
120 | to handle */ | |
2e22847f | 121 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 JR |
122 | we find in ACPI */ |
123 | unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */ | |
3ce1f93c | 124 | int amd_iommu_isolate = 1; /* if 1, device isolation is enabled */ |
afa9fdc2 | 125 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 126 | |
2e22847f | 127 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 128 | system */ |
928abd25 | 129 | |
b65233a9 JR |
130 | /* |
131 | * Pointer to the device table which is shared by all AMD IOMMUs | |
132 | * it is indexed by the PCI device id or the HT unit id and contains | |
133 | * information about the domain the device belongs to as well as the | |
134 | * page table root pointer. | |
135 | */ | |
928abd25 | 136 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
137 | |
138 | /* | |
139 | * The alias table is a driver specific data structure which contains the | |
140 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
141 | * More than one device can share the same requestor id. | |
142 | */ | |
928abd25 | 143 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
144 | |
145 | /* | |
146 | * The rlookup table is used to find the IOMMU which is responsible | |
147 | * for a specific device. It is also indexed by the PCI device id. | |
148 | */ | |
928abd25 | 149 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 JR |
150 | |
151 | /* | |
152 | * The pd table (protection domain table) is used to find the protection domain | |
153 | * data structure a device belongs to. Indexed with the PCI device id too. | |
154 | */ | |
928abd25 | 155 | struct protection_domain **amd_iommu_pd_table; |
b65233a9 JR |
156 | |
157 | /* | |
158 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
159 | * to know which ones are already in use. | |
160 | */ | |
928abd25 JR |
161 | unsigned long *amd_iommu_pd_alloc_bitmap; |
162 | ||
b65233a9 JR |
163 | static u32 dev_table_size; /* size of the device table */ |
164 | static u32 alias_table_size; /* size of the alias table */ | |
165 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 166 | |
208ec8c9 JR |
167 | static inline void update_last_devid(u16 devid) |
168 | { | |
169 | if (devid > amd_iommu_last_bdf) | |
170 | amd_iommu_last_bdf = devid; | |
171 | } | |
172 | ||
c571484e JR |
173 | static inline unsigned long tbl_size(int entry_size) |
174 | { | |
175 | unsigned shift = PAGE_SHIFT + | |
176 | get_order(amd_iommu_last_bdf * entry_size); | |
177 | ||
178 | return 1UL << shift; | |
179 | } | |
180 | ||
b65233a9 JR |
181 | /**************************************************************************** |
182 | * | |
183 | * AMD IOMMU MMIO register space handling functions | |
184 | * | |
185 | * These functions are used to program the IOMMU device registers in | |
186 | * MMIO space required for that driver. | |
187 | * | |
188 | ****************************************************************************/ | |
3e8064ba | 189 | |
b65233a9 JR |
190 | /* |
191 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
192 | * exclusion range are passed through untranslated | |
193 | */ | |
b2026aa2 JR |
194 | static void __init iommu_set_exclusion_range(struct amd_iommu *iommu) |
195 | { | |
196 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
197 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
198 | u64 entry; | |
199 | ||
200 | if (!iommu->exclusion_start) | |
201 | return; | |
202 | ||
203 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
204 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
205 | &entry, sizeof(entry)); | |
206 | ||
207 | entry = limit; | |
208 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
209 | &entry, sizeof(entry)); | |
210 | } | |
211 | ||
b65233a9 | 212 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
213 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
214 | { | |
f609891f | 215 | u64 entry; |
b2026aa2 JR |
216 | |
217 | BUG_ON(iommu->mmio_base == NULL); | |
218 | ||
219 | entry = virt_to_phys(amd_iommu_dev_table); | |
220 | entry |= (dev_table_size >> 12) - 1; | |
221 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
222 | &entry, sizeof(entry)); | |
223 | } | |
224 | ||
b65233a9 | 225 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
b2026aa2 JR |
226 | static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
227 | { | |
228 | u32 ctrl; | |
229 | ||
230 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
231 | ctrl |= (1 << bit); | |
232 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
233 | } | |
234 | ||
235 | static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit) | |
236 | { | |
237 | u32 ctrl; | |
238 | ||
199d0d50 | 239 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
240 | ctrl &= ~(1 << bit); |
241 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
242 | } | |
243 | ||
b65233a9 | 244 | /* Function to enable the hardware */ |
b2026aa2 JR |
245 | void __init iommu_enable(struct amd_iommu *iommu) |
246 | { | |
3eaf28a1 JR |
247 | printk(KERN_INFO "AMD IOMMU: Enabling IOMMU " |
248 | "at %02x:%02x.%x cap 0x%hx\n", | |
249 | iommu->dev->bus->number, | |
250 | PCI_SLOT(iommu->dev->devfn), | |
251 | PCI_FUNC(iommu->dev->devfn), | |
252 | iommu->cap_ptr); | |
b2026aa2 JR |
253 | |
254 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); | |
b2026aa2 JR |
255 | } |
256 | ||
126c52be JR |
257 | /* Function to enable IOMMU event logging and event interrupts */ |
258 | void __init iommu_enable_event_logging(struct amd_iommu *iommu) | |
259 | { | |
260 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); | |
261 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); | |
262 | } | |
263 | ||
b65233a9 JR |
264 | /* |
265 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
266 | * the system has one. | |
267 | */ | |
6c56747b JR |
268 | static u8 * __init iommu_map_mmio_space(u64 address) |
269 | { | |
270 | u8 *ret; | |
271 | ||
272 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) | |
273 | return NULL; | |
274 | ||
275 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
276 | if (ret != NULL) | |
277 | return ret; | |
278 | ||
279 | release_mem_region(address, MMIO_REGION_LENGTH); | |
280 | ||
281 | return NULL; | |
282 | } | |
283 | ||
284 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
285 | { | |
286 | if (iommu->mmio_base) | |
287 | iounmap(iommu->mmio_base); | |
288 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
289 | } | |
290 | ||
b65233a9 JR |
291 | /**************************************************************************** |
292 | * | |
293 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
294 | * parsing. In this pass we try to find out the highest device id this | |
295 | * code has to handle. Upon this information the size of the shared data | |
296 | * structures is determined later. | |
297 | * | |
298 | ****************************************************************************/ | |
299 | ||
b514e555 JR |
300 | /* |
301 | * This function calculates the length of a given IVHD entry | |
302 | */ | |
303 | static inline int ivhd_entry_length(u8 *ivhd) | |
304 | { | |
305 | return 0x04 << (*ivhd >> 6); | |
306 | } | |
307 | ||
b65233a9 JR |
308 | /* |
309 | * This function reads the last device id the IOMMU has to handle from the PCI | |
310 | * capability header for this IOMMU | |
311 | */ | |
3e8064ba JR |
312 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
313 | { | |
314 | u32 cap; | |
315 | ||
316 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 317 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
318 | |
319 | return 0; | |
320 | } | |
321 | ||
b65233a9 JR |
322 | /* |
323 | * After reading the highest device id from the IOMMU PCI capability header | |
324 | * this function looks if there is a higher device id defined in the ACPI table | |
325 | */ | |
3e8064ba JR |
326 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
327 | { | |
328 | u8 *p = (void *)h, *end = (void *)h; | |
329 | struct ivhd_entry *dev; | |
330 | ||
331 | p += sizeof(*h); | |
332 | end += h->length; | |
333 | ||
334 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
335 | PCI_SLOT(h->devid), | |
336 | PCI_FUNC(h->devid), | |
337 | h->cap_ptr); | |
338 | ||
339 | while (p < end) { | |
340 | dev = (struct ivhd_entry *)p; | |
341 | switch (dev->type) { | |
342 | case IVHD_DEV_SELECT: | |
343 | case IVHD_DEV_RANGE_END: | |
344 | case IVHD_DEV_ALIAS: | |
345 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 346 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 347 | update_last_devid(dev->devid); |
3e8064ba JR |
348 | break; |
349 | default: | |
350 | break; | |
351 | } | |
b514e555 | 352 | p += ivhd_entry_length(p); |
3e8064ba JR |
353 | } |
354 | ||
355 | WARN_ON(p != end); | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
b65233a9 JR |
360 | /* |
361 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
362 | * id which we need to handle. This is the first of three functions which parse | |
363 | * the ACPI table. So we check the checksum here. | |
364 | */ | |
3e8064ba JR |
365 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
366 | { | |
367 | int i; | |
368 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
369 | struct ivhd_header *h; | |
370 | ||
371 | /* | |
372 | * Validate checksum here so we don't need to do it when | |
373 | * we actually parse the table | |
374 | */ | |
375 | for (i = 0; i < table->length; ++i) | |
376 | checksum += p[i]; | |
377 | if (checksum != 0) | |
378 | /* ACPI table corrupt */ | |
379 | return -ENODEV; | |
380 | ||
381 | p += IVRS_HEADER_LENGTH; | |
382 | ||
383 | end += table->length; | |
384 | while (p < end) { | |
385 | h = (struct ivhd_header *)p; | |
386 | switch (h->type) { | |
387 | case ACPI_IVHD_TYPE: | |
388 | find_last_devid_from_ivhd(h); | |
389 | break; | |
390 | default: | |
391 | break; | |
392 | } | |
393 | p += h->length; | |
394 | } | |
395 | WARN_ON(p != end); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
b65233a9 JR |
400 | /**************************************************************************** |
401 | * | |
402 | * The following functions belong the the code path which parses the ACPI table | |
403 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
404 | * data structures, initialize the device/alias/rlookup table and also | |
405 | * basically initialize the hardware. | |
406 | * | |
407 | ****************************************************************************/ | |
408 | ||
409 | /* | |
410 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
411 | * write commands to that buffer later and the IOMMU will execute them | |
412 | * asynchronously | |
413 | */ | |
b36ca91e JR |
414 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
415 | { | |
d0312b21 | 416 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 417 | get_order(CMD_BUFFER_SIZE)); |
d0312b21 | 418 | u64 entry; |
b36ca91e JR |
419 | |
420 | if (cmd_buf == NULL) | |
421 | return NULL; | |
422 | ||
423 | iommu->cmd_buf_size = CMD_BUFFER_SIZE; | |
424 | ||
b36ca91e JR |
425 | entry = (u64)virt_to_phys(cmd_buf); |
426 | entry |= MMIO_CMD_SIZE_512; | |
427 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, | |
428 | &entry, sizeof(entry)); | |
429 | ||
cf558d25 JR |
430 | /* set head and tail to zero manually */ |
431 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
432 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
433 | ||
b36ca91e JR |
434 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); |
435 | ||
436 | return cmd_buf; | |
437 | } | |
438 | ||
439 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
440 | { | |
23c1713f JR |
441 | free_pages((unsigned long)iommu->cmd_buf, |
442 | get_order(iommu->cmd_buf_size)); | |
b36ca91e JR |
443 | } |
444 | ||
335503e5 JR |
445 | /* allocates the memory where the IOMMU will log its events to */ |
446 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
447 | { | |
448 | u64 entry; | |
449 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
450 | get_order(EVT_BUFFER_SIZE)); | |
451 | ||
452 | if (iommu->evt_buf == NULL) | |
453 | return NULL; | |
454 | ||
455 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; | |
456 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, | |
457 | &entry, sizeof(entry)); | |
458 | ||
459 | iommu->evt_buf_size = EVT_BUFFER_SIZE; | |
460 | ||
461 | return iommu->evt_buf; | |
462 | } | |
463 | ||
464 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
465 | { | |
466 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
467 | } | |
468 | ||
b65233a9 | 469 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
470 | static void set_dev_entry_bit(u16 devid, u8 bit) |
471 | { | |
472 | int i = (bit >> 5) & 0x07; | |
473 | int _bit = bit & 0x1f; | |
474 | ||
475 | amd_iommu_dev_table[devid].data[i] |= (1 << _bit); | |
476 | } | |
477 | ||
5ff4789d JR |
478 | /* Writes the specific IOMMU for a device into the rlookup table */ |
479 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
480 | { | |
481 | amd_iommu_rlookup_table[devid] = iommu; | |
482 | } | |
483 | ||
b65233a9 JR |
484 | /* |
485 | * This function takes the device specific flags read from the ACPI | |
486 | * table and sets up the device table entry with that information | |
487 | */ | |
5ff4789d JR |
488 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
489 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
490 | { |
491 | if (flags & ACPI_DEVFLAG_INITPASS) | |
492 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
493 | if (flags & ACPI_DEVFLAG_EXTINT) | |
494 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
495 | if (flags & ACPI_DEVFLAG_NMI) | |
496 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
497 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
498 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
499 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
500 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
501 | if (flags & ACPI_DEVFLAG_LINT0) | |
502 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
503 | if (flags & ACPI_DEVFLAG_LINT1) | |
504 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 505 | |
5ff4789d | 506 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
507 | } |
508 | ||
b65233a9 JR |
509 | /* |
510 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
511 | * it | |
512 | */ | |
3566b778 JR |
513 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
514 | { | |
515 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
516 | ||
517 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
518 | return; | |
519 | ||
520 | if (iommu) { | |
b65233a9 JR |
521 | /* |
522 | * We only can configure exclusion ranges per IOMMU, not | |
523 | * per device. But we can enable the exclusion range per | |
524 | * device. This is done here | |
525 | */ | |
3566b778 JR |
526 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
527 | iommu->exclusion_start = m->range_start; | |
528 | iommu->exclusion_length = m->range_length; | |
529 | } | |
530 | } | |
531 | ||
b65233a9 JR |
532 | /* |
533 | * This function reads some important data from the IOMMU PCI space and | |
534 | * initializes the driver data structure with it. It reads the hardware | |
535 | * capabilities and the first/last device entries | |
536 | */ | |
5d0c8e49 JR |
537 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
538 | { | |
5d0c8e49 | 539 | int cap_ptr = iommu->cap_ptr; |
a80dc3e0 | 540 | u32 range, misc; |
5d0c8e49 | 541 | |
3eaf28a1 JR |
542 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
543 | &iommu->cap); | |
544 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
545 | &range); | |
a80dc3e0 JR |
546 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
547 | &misc); | |
5d0c8e49 | 548 | |
d591b0a3 JR |
549 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
550 | MMIO_GET_FD(range)); | |
551 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
552 | MMIO_GET_LD(range)); | |
a80dc3e0 | 553 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
5d0c8e49 JR |
554 | } |
555 | ||
b65233a9 JR |
556 | /* |
557 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
558 | * initializes the hardware and our data structures with it. | |
559 | */ | |
5d0c8e49 JR |
560 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
561 | struct ivhd_header *h) | |
562 | { | |
563 | u8 *p = (u8 *)h; | |
564 | u8 *end = p, flags = 0; | |
565 | u16 dev_i, devid = 0, devid_start = 0, devid_to = 0; | |
566 | u32 ext_flags = 0; | |
58a3bee5 | 567 | bool alias = false; |
5d0c8e49 JR |
568 | struct ivhd_entry *e; |
569 | ||
570 | /* | |
571 | * First set the recommended feature enable bits from ACPI | |
572 | * into the IOMMU control registers | |
573 | */ | |
574 | h->flags & IVHD_FLAG_HT_TUN_EN ? | |
575 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
576 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
577 | ||
578 | h->flags & IVHD_FLAG_PASSPW_EN ? | |
579 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
580 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
581 | ||
582 | h->flags & IVHD_FLAG_RESPASSPW_EN ? | |
583 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
584 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
585 | ||
586 | h->flags & IVHD_FLAG_ISOC_EN ? | |
587 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
588 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
589 | ||
590 | /* | |
591 | * make IOMMU memory accesses cache coherent | |
592 | */ | |
593 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
594 | ||
595 | /* | |
596 | * Done. Now parse the device entries | |
597 | */ | |
598 | p += sizeof(struct ivhd_header); | |
599 | end += h->length; | |
600 | ||
601 | while (p < end) { | |
602 | e = (struct ivhd_entry *)p; | |
603 | switch (e->type) { | |
604 | case IVHD_DEV_ALL: | |
605 | for (dev_i = iommu->first_device; | |
606 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
607 | set_dev_entry_from_acpi(iommu, dev_i, |
608 | e->flags, 0); | |
5d0c8e49 JR |
609 | break; |
610 | case IVHD_DEV_SELECT: | |
611 | devid = e->devid; | |
5ff4789d | 612 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
613 | break; |
614 | case IVHD_DEV_SELECT_RANGE_START: | |
615 | devid_start = e->devid; | |
616 | flags = e->flags; | |
617 | ext_flags = 0; | |
58a3bee5 | 618 | alias = false; |
5d0c8e49 JR |
619 | break; |
620 | case IVHD_DEV_ALIAS: | |
621 | devid = e->devid; | |
622 | devid_to = e->ext >> 8; | |
5ff4789d | 623 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
624 | amd_iommu_alias_table[devid] = devid_to; |
625 | break; | |
626 | case IVHD_DEV_ALIAS_RANGE: | |
627 | devid_start = e->devid; | |
628 | flags = e->flags; | |
629 | devid_to = e->ext >> 8; | |
630 | ext_flags = 0; | |
58a3bee5 | 631 | alias = true; |
5d0c8e49 JR |
632 | break; |
633 | case IVHD_DEV_EXT_SELECT: | |
634 | devid = e->devid; | |
5ff4789d JR |
635 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
636 | e->ext); | |
5d0c8e49 JR |
637 | break; |
638 | case IVHD_DEV_EXT_SELECT_RANGE: | |
639 | devid_start = e->devid; | |
640 | flags = e->flags; | |
641 | ext_flags = e->ext; | |
58a3bee5 | 642 | alias = false; |
5d0c8e49 JR |
643 | break; |
644 | case IVHD_DEV_RANGE_END: | |
645 | devid = e->devid; | |
646 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
647 | if (alias) | |
648 | amd_iommu_alias_table[dev_i] = devid_to; | |
5ff4789d | 649 | set_dev_entry_from_acpi(iommu, |
5d0c8e49 JR |
650 | amd_iommu_alias_table[dev_i], |
651 | flags, ext_flags); | |
652 | } | |
653 | break; | |
654 | default: | |
655 | break; | |
656 | } | |
657 | ||
b514e555 | 658 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
659 | } |
660 | } | |
661 | ||
b65233a9 | 662 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
663 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
664 | { | |
665 | u16 i; | |
666 | ||
667 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
668 | set_iommu_for_device(iommu, i); | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
e47d402d JR |
673 | static void __init free_iommu_one(struct amd_iommu *iommu) |
674 | { | |
675 | free_command_buffer(iommu); | |
335503e5 | 676 | free_event_buffer(iommu); |
e47d402d JR |
677 | iommu_unmap_mmio_space(iommu); |
678 | } | |
679 | ||
680 | static void __init free_iommu_all(void) | |
681 | { | |
682 | struct amd_iommu *iommu, *next; | |
683 | ||
684 | list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) { | |
685 | list_del(&iommu->list); | |
686 | free_iommu_one(iommu); | |
687 | kfree(iommu); | |
688 | } | |
689 | } | |
690 | ||
b65233a9 JR |
691 | /* |
692 | * This function clues the initialization function for one IOMMU | |
693 | * together and also allocates the command buffer and programs the | |
694 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
695 | */ | |
e47d402d JR |
696 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
697 | { | |
698 | spin_lock_init(&iommu->lock); | |
699 | list_add_tail(&iommu->list, &amd_iommu_list); | |
700 | ||
701 | /* | |
702 | * Copy data from ACPI table entry to the iommu struct | |
703 | */ | |
3eaf28a1 JR |
704 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
705 | if (!iommu->dev) | |
706 | return 1; | |
707 | ||
e47d402d | 708 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 709 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
710 | iommu->mmio_phys = h->mmio_phys; |
711 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
712 | if (!iommu->mmio_base) | |
713 | return -ENOMEM; | |
714 | ||
715 | iommu_set_device_table(iommu); | |
716 | iommu->cmd_buf = alloc_command_buffer(iommu); | |
717 | if (!iommu->cmd_buf) | |
718 | return -ENOMEM; | |
719 | ||
335503e5 JR |
720 | iommu->evt_buf = alloc_event_buffer(iommu); |
721 | if (!iommu->evt_buf) | |
722 | return -ENOMEM; | |
723 | ||
a80dc3e0 JR |
724 | iommu->int_enabled = false; |
725 | ||
e47d402d JR |
726 | init_iommu_from_pci(iommu); |
727 | init_iommu_from_acpi(iommu, h); | |
728 | init_iommu_devices(iommu); | |
729 | ||
8a66712b | 730 | return pci_enable_device(iommu->dev); |
e47d402d JR |
731 | } |
732 | ||
b65233a9 JR |
733 | /* |
734 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
735 | * IOMMU structure and initializes it with init_iommu_one() | |
736 | */ | |
e47d402d JR |
737 | static int __init init_iommu_all(struct acpi_table_header *table) |
738 | { | |
739 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
740 | struct ivhd_header *h; | |
741 | struct amd_iommu *iommu; | |
742 | int ret; | |
743 | ||
e47d402d JR |
744 | end += table->length; |
745 | p += IVRS_HEADER_LENGTH; | |
746 | ||
747 | while (p < end) { | |
748 | h = (struct ivhd_header *)p; | |
749 | switch (*p) { | |
750 | case ACPI_IVHD_TYPE: | |
751 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); | |
752 | if (iommu == NULL) | |
753 | return -ENOMEM; | |
754 | ret = init_iommu_one(iommu, h); | |
755 | if (ret) | |
756 | return ret; | |
757 | break; | |
758 | default: | |
759 | break; | |
760 | } | |
761 | p += h->length; | |
762 | ||
763 | } | |
764 | WARN_ON(p != end); | |
765 | ||
766 | return 0; | |
767 | } | |
768 | ||
a80dc3e0 JR |
769 | /**************************************************************************** |
770 | * | |
771 | * The following functions initialize the MSI interrupts for all IOMMUs | |
772 | * in the system. Its a bit challenging because there could be multiple | |
773 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
774 | * pci_dev. | |
775 | * | |
776 | ****************************************************************************/ | |
777 | ||
778 | static int __init iommu_setup_msix(struct amd_iommu *iommu) | |
779 | { | |
780 | struct amd_iommu *curr; | |
781 | struct msix_entry entries[32]; /* only 32 supported by AMD IOMMU */ | |
782 | int nvec = 0, i; | |
783 | ||
784 | list_for_each_entry(curr, &amd_iommu_list, list) { | |
785 | if (curr->dev == iommu->dev) { | |
786 | entries[nvec].entry = curr->evt_msi_num; | |
787 | entries[nvec].vector = 0; | |
788 | curr->int_enabled = true; | |
789 | nvec++; | |
790 | } | |
791 | } | |
792 | ||
793 | if (pci_enable_msix(iommu->dev, entries, nvec)) { | |
794 | pci_disable_msix(iommu->dev); | |
795 | return 1; | |
796 | } | |
797 | ||
798 | for (i = 0; i < nvec; ++i) { | |
799 | int r = request_irq(entries->vector, amd_iommu_int_handler, | |
800 | IRQF_SAMPLE_RANDOM, | |
801 | "AMD IOMMU", | |
802 | NULL); | |
803 | if (r) | |
804 | goto out_free; | |
805 | } | |
806 | ||
807 | return 0; | |
808 | ||
809 | out_free: | |
810 | for (i -= 1; i >= 0; --i) | |
811 | free_irq(entries->vector, NULL); | |
812 | ||
813 | pci_disable_msix(iommu->dev); | |
814 | ||
815 | return 1; | |
816 | } | |
817 | ||
818 | static int __init iommu_setup_msi(struct amd_iommu *iommu) | |
819 | { | |
820 | int r; | |
821 | struct amd_iommu *curr; | |
822 | ||
823 | list_for_each_entry(curr, &amd_iommu_list, list) { | |
824 | if (curr->dev == iommu->dev) | |
825 | curr->int_enabled = true; | |
826 | } | |
827 | ||
828 | ||
829 | if (pci_enable_msi(iommu->dev)) | |
830 | return 1; | |
831 | ||
832 | r = request_irq(iommu->dev->irq, amd_iommu_int_handler, | |
833 | IRQF_SAMPLE_RANDOM, | |
834 | "AMD IOMMU", | |
835 | NULL); | |
836 | ||
837 | if (r) { | |
838 | pci_disable_msi(iommu->dev); | |
839 | return 1; | |
840 | } | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | static int __init iommu_init_msi(struct amd_iommu *iommu) | |
846 | { | |
847 | if (iommu->int_enabled) | |
848 | return 0; | |
849 | ||
850 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSIX)) | |
851 | return iommu_setup_msix(iommu); | |
852 | else if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) | |
853 | return iommu_setup_msi(iommu); | |
854 | ||
855 | return 1; | |
856 | } | |
857 | ||
b65233a9 JR |
858 | /**************************************************************************** |
859 | * | |
860 | * The next functions belong to the third pass of parsing the ACPI | |
861 | * table. In this last pass the memory mapping requirements are | |
862 | * gathered (like exclusion and unity mapping reanges). | |
863 | * | |
864 | ****************************************************************************/ | |
865 | ||
be2a022c JR |
866 | static void __init free_unity_maps(void) |
867 | { | |
868 | struct unity_map_entry *entry, *next; | |
869 | ||
870 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
871 | list_del(&entry->list); | |
872 | kfree(entry); | |
873 | } | |
874 | } | |
875 | ||
b65233a9 | 876 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
877 | static int __init init_exclusion_range(struct ivmd_header *m) |
878 | { | |
879 | int i; | |
880 | ||
881 | switch (m->type) { | |
882 | case ACPI_IVMD_TYPE: | |
883 | set_device_exclusion_range(m->devid, m); | |
884 | break; | |
885 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 886 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
887 | set_device_exclusion_range(i, m); |
888 | break; | |
889 | case ACPI_IVMD_TYPE_RANGE: | |
890 | for (i = m->devid; i <= m->aux; ++i) | |
891 | set_device_exclusion_range(i, m); | |
892 | break; | |
893 | default: | |
894 | break; | |
895 | } | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
b65233a9 | 900 | /* called for unity map ACPI definition */ |
be2a022c JR |
901 | static int __init init_unity_map_range(struct ivmd_header *m) |
902 | { | |
903 | struct unity_map_entry *e = 0; | |
904 | ||
905 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
906 | if (e == NULL) | |
907 | return -ENOMEM; | |
908 | ||
909 | switch (m->type) { | |
910 | default: | |
911 | case ACPI_IVMD_TYPE: | |
912 | e->devid_start = e->devid_end = m->devid; | |
913 | break; | |
914 | case ACPI_IVMD_TYPE_ALL: | |
915 | e->devid_start = 0; | |
916 | e->devid_end = amd_iommu_last_bdf; | |
917 | break; | |
918 | case ACPI_IVMD_TYPE_RANGE: | |
919 | e->devid_start = m->devid; | |
920 | e->devid_end = m->aux; | |
921 | break; | |
922 | } | |
923 | e->address_start = PAGE_ALIGN(m->range_start); | |
924 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
925 | e->prot = m->flags >> 1; | |
926 | ||
927 | list_add_tail(&e->list, &amd_iommu_unity_map); | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
b65233a9 | 932 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
933 | static int __init init_memory_definitions(struct acpi_table_header *table) |
934 | { | |
935 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
936 | struct ivmd_header *m; | |
937 | ||
be2a022c JR |
938 | end += table->length; |
939 | p += IVRS_HEADER_LENGTH; | |
940 | ||
941 | while (p < end) { | |
942 | m = (struct ivmd_header *)p; | |
943 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
944 | init_exclusion_range(m); | |
945 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
946 | init_unity_map_range(m); | |
947 | ||
948 | p += m->length; | |
949 | } | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
9f5f5fb3 JR |
954 | /* |
955 | * Init the device table to not allow DMA access for devices and | |
956 | * suppress all page faults | |
957 | */ | |
958 | static void init_device_table(void) | |
959 | { | |
960 | u16 devid; | |
961 | ||
962 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
963 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
964 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
965 | } |
966 | } | |
967 | ||
b65233a9 JR |
968 | /* |
969 | * This function finally enables all IOMMUs found in the system after | |
970 | * they have been initialized | |
971 | */ | |
8736197b JR |
972 | static void __init enable_iommus(void) |
973 | { | |
974 | struct amd_iommu *iommu; | |
975 | ||
976 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
977 | iommu_set_exclusion_range(iommu); | |
a80dc3e0 | 978 | iommu_init_msi(iommu); |
126c52be | 979 | iommu_enable_event_logging(iommu); |
8736197b JR |
980 | iommu_enable(iommu); |
981 | } | |
982 | } | |
983 | ||
7441e9cb JR |
984 | /* |
985 | * Suspend/Resume support | |
986 | * disable suspend until real resume implemented | |
987 | */ | |
988 | ||
989 | static int amd_iommu_resume(struct sys_device *dev) | |
990 | { | |
991 | return 0; | |
992 | } | |
993 | ||
994 | static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state) | |
995 | { | |
996 | return -EINVAL; | |
997 | } | |
998 | ||
999 | static struct sysdev_class amd_iommu_sysdev_class = { | |
1000 | .name = "amd_iommu", | |
1001 | .suspend = amd_iommu_suspend, | |
1002 | .resume = amd_iommu_resume, | |
1003 | }; | |
1004 | ||
1005 | static struct sys_device device_amd_iommu = { | |
1006 | .id = 0, | |
1007 | .cls = &amd_iommu_sysdev_class, | |
1008 | }; | |
1009 | ||
b65233a9 JR |
1010 | /* |
1011 | * This is the core init function for AMD IOMMU hardware in the system. | |
1012 | * This function is called from the generic x86 DMA layer initialization | |
1013 | * code. | |
1014 | * | |
1015 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1016 | * three times: | |
1017 | * | |
1018 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1019 | * Upon this information the size of the data structures is | |
1020 | * determined that needs to be allocated. | |
1021 | * | |
1022 | * 2 pass) Initialize the data structures just allocated with the | |
1023 | * information in the ACPI table about available AMD IOMMUs | |
1024 | * in the system. It also maps the PCI devices in the | |
1025 | * system to specific IOMMUs | |
1026 | * | |
1027 | * 3 pass) After the basic data structures are allocated and | |
1028 | * initialized we update them with information about memory | |
1029 | * remapping requirements parsed out of the ACPI table in | |
1030 | * this last pass. | |
1031 | * | |
1032 | * After that the hardware is initialized and ready to go. In the last | |
1033 | * step we do some Linux specific things like registering the driver in | |
1034 | * the dma_ops interface and initializing the suspend/resume support | |
1035 | * functions. Finally it prints some information about AMD IOMMUs and | |
1036 | * the driver state and enables the hardware. | |
1037 | */ | |
fe74c9cf JR |
1038 | int __init amd_iommu_init(void) |
1039 | { | |
1040 | int i, ret = 0; | |
1041 | ||
1042 | ||
8b14518f | 1043 | if (no_iommu) { |
fe74c9cf JR |
1044 | printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n"); |
1045 | return 0; | |
1046 | } | |
1047 | ||
c1cbebee JR |
1048 | if (!amd_iommu_detected) |
1049 | return -ENODEV; | |
1050 | ||
fe74c9cf JR |
1051 | /* |
1052 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1053 | * we need to handle. Upon this information the shared data | |
1054 | * structures for the IOMMUs in the system will be allocated | |
1055 | */ | |
1056 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1057 | return -ENODEV; | |
1058 | ||
c571484e JR |
1059 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1060 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1061 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1062 | |
1063 | ret = -ENOMEM; | |
1064 | ||
1065 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1066 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1067 | get_order(dev_table_size)); |
1068 | if (amd_iommu_dev_table == NULL) | |
1069 | goto out; | |
1070 | ||
1071 | /* | |
1072 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1073 | * IOMMU see for that device | |
1074 | */ | |
1075 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1076 | get_order(alias_table_size)); | |
1077 | if (amd_iommu_alias_table == NULL) | |
1078 | goto free; | |
1079 | ||
1080 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1081 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1082 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1083 | get_order(rlookup_table_size)); |
1084 | if (amd_iommu_rlookup_table == NULL) | |
1085 | goto free; | |
1086 | ||
1087 | /* | |
1088 | * Protection Domain table - maps devices to protection domains | |
1089 | * This table has the same size as the rlookup_table | |
1090 | */ | |
5dc8bff0 | 1091 | amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1092 | get_order(rlookup_table_size)); |
1093 | if (amd_iommu_pd_table == NULL) | |
1094 | goto free; | |
1095 | ||
5dc8bff0 JR |
1096 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1097 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1098 | get_order(MAX_DOMAIN_ID/8)); |
1099 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1100 | goto free; | |
1101 | ||
9f5f5fb3 JR |
1102 | /* init the device table */ |
1103 | init_device_table(); | |
1104 | ||
fe74c9cf | 1105 | /* |
5dc8bff0 | 1106 | * let all alias entries point to itself |
fe74c9cf | 1107 | */ |
3a61ec38 | 1108 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1109 | amd_iommu_alias_table[i] = i; |
1110 | ||
fe74c9cf JR |
1111 | /* |
1112 | * never allocate domain 0 because its used as the non-allocated and | |
1113 | * error value placeholder | |
1114 | */ | |
1115 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1116 | ||
1117 | /* | |
1118 | * now the data structures are allocated and basically initialized | |
1119 | * start the real acpi table scan | |
1120 | */ | |
1121 | ret = -ENODEV; | |
1122 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1123 | goto free; | |
1124 | ||
1125 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) | |
1126 | goto free; | |
1127 | ||
129d6aba | 1128 | ret = sysdev_class_register(&amd_iommu_sysdev_class); |
8736197b JR |
1129 | if (ret) |
1130 | goto free; | |
1131 | ||
129d6aba | 1132 | ret = sysdev_register(&device_amd_iommu); |
7441e9cb JR |
1133 | if (ret) |
1134 | goto free; | |
1135 | ||
129d6aba | 1136 | ret = amd_iommu_init_dma_ops(); |
7441e9cb JR |
1137 | if (ret) |
1138 | goto free; | |
1139 | ||
8736197b JR |
1140 | enable_iommus(); |
1141 | ||
fe74c9cf JR |
1142 | printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n", |
1143 | (1 << (amd_iommu_aperture_order-20))); | |
1144 | ||
1145 | printk(KERN_INFO "AMD IOMMU: device isolation "); | |
1146 | if (amd_iommu_isolate) | |
1147 | printk("enabled\n"); | |
1148 | else | |
1149 | printk("disabled\n"); | |
1150 | ||
afa9fdc2 | 1151 | if (amd_iommu_unmap_flush) |
1c655773 JR |
1152 | printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n"); |
1153 | else | |
1154 | printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n"); | |
1155 | ||
fe74c9cf JR |
1156 | out: |
1157 | return ret; | |
1158 | ||
1159 | free: | |
d58befd3 JR |
1160 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1161 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1162 | |
9a836de0 JR |
1163 | free_pages((unsigned long)amd_iommu_pd_table, |
1164 | get_order(rlookup_table_size)); | |
fe74c9cf | 1165 | |
9a836de0 JR |
1166 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1167 | get_order(rlookup_table_size)); | |
fe74c9cf | 1168 | |
9a836de0 JR |
1169 | free_pages((unsigned long)amd_iommu_alias_table, |
1170 | get_order(alias_table_size)); | |
fe74c9cf | 1171 | |
9a836de0 JR |
1172 | free_pages((unsigned long)amd_iommu_dev_table, |
1173 | get_order(dev_table_size)); | |
fe74c9cf JR |
1174 | |
1175 | free_iommu_all(); | |
1176 | ||
1177 | free_unity_maps(); | |
1178 | ||
1179 | goto out; | |
1180 | } | |
1181 | ||
b65233a9 JR |
1182 | /**************************************************************************** |
1183 | * | |
1184 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1185 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1186 | * IOMMUs | |
1187 | * | |
1188 | ****************************************************************************/ | |
ae7877de JR |
1189 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1190 | { | |
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | void __init amd_iommu_detect(void) | |
1195 | { | |
299a140d | 1196 | if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture)) |
ae7877de JR |
1197 | return; |
1198 | ||
ae7877de JR |
1199 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1200 | iommu_detected = 1; | |
c1cbebee | 1201 | amd_iommu_detected = 1; |
92af4e29 | 1202 | #ifdef CONFIG_GART_IOMMU |
ae7877de JR |
1203 | gart_iommu_aperture_disabled = 1; |
1204 | gart_iommu_aperture = 0; | |
92af4e29 | 1205 | #endif |
ae7877de JR |
1206 | } |
1207 | } | |
1208 | ||
b65233a9 JR |
1209 | /**************************************************************************** |
1210 | * | |
1211 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1212 | * options. | |
1213 | * | |
1214 | ****************************************************************************/ | |
1215 | ||
918ad6c5 JR |
1216 | static int __init parse_amd_iommu_options(char *str) |
1217 | { | |
1218 | for (; *str; ++str) { | |
1c655773 | 1219 | if (strncmp(str, "isolate", 7) == 0) |
918ad6c5 | 1220 | amd_iommu_isolate = 1; |
e5e1f606 JR |
1221 | if (strncmp(str, "share", 5) == 0) |
1222 | amd_iommu_isolate = 0; | |
695b5676 | 1223 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1224 | amd_iommu_unmap_flush = true; |
918ad6c5 JR |
1225 | } |
1226 | ||
1227 | return 1; | |
1228 | } | |
1229 | ||
1230 | static int __init parse_amd_iommu_size_options(char *str) | |
1231 | { | |
0906372e JR |
1232 | unsigned order = PAGE_SHIFT + get_order(memparse(str, &str)); |
1233 | ||
1234 | if ((order > 24) && (order < 31)) | |
1235 | amd_iommu_aperture_order = order; | |
918ad6c5 JR |
1236 | |
1237 | return 1; | |
1238 | } | |
1239 | ||
1240 | __setup("amd_iommu=", parse_amd_iommu_options); | |
1241 | __setup("amd_iommu_size=", parse_amd_iommu_size_options); |