Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
a66022c4 | 21 | #include <linux/bitmap.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
6a9401a7 | 31 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
0feae533 JR |
45 | /* |
46 | * Domain for untranslated devices - only allocated | |
47 | * if iommu=pt passed on kernel cmd line. | |
48 | */ | |
49 | static struct protection_domain *pt_domain; | |
50 | ||
26961efe | 51 | static struct iommu_ops amd_iommu_ops; |
26961efe | 52 | |
431b2a20 JR |
53 | /* |
54 | * general struct to manage commands send to an IOMMU | |
55 | */ | |
d6449536 | 56 | struct iommu_cmd { |
b6c02715 JR |
57 | u32 data[4]; |
58 | }; | |
59 | ||
a345b23b | 60 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
04bfdd84 | 61 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 62 | |
15898bbc JR |
63 | /**************************************************************************** |
64 | * | |
65 | * Helper functions | |
66 | * | |
67 | ****************************************************************************/ | |
68 | ||
69 | static inline u16 get_device_id(struct device *dev) | |
70 | { | |
71 | struct pci_dev *pdev = to_pci_dev(dev); | |
72 | ||
73 | return calc_devid(pdev->bus->number, pdev->devfn); | |
74 | } | |
75 | ||
657cbb6b JR |
76 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
77 | { | |
78 | return dev->archdata.iommu; | |
79 | } | |
80 | ||
71c70984 JR |
81 | /* |
82 | * In this function the list of preallocated protection domains is traversed to | |
83 | * find the domain for a specific device | |
84 | */ | |
85 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
86 | { | |
87 | struct dma_ops_domain *entry, *ret = NULL; | |
88 | unsigned long flags; | |
89 | u16 alias = amd_iommu_alias_table[devid]; | |
90 | ||
91 | if (list_empty(&iommu_pd_list)) | |
92 | return NULL; | |
93 | ||
94 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
95 | ||
96 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
97 | if (entry->target_dev == devid || | |
98 | entry->target_dev == alias) { | |
99 | ret = entry; | |
100 | break; | |
101 | } | |
102 | } | |
103 | ||
104 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
105 | ||
106 | return ret; | |
107 | } | |
108 | ||
98fc5a69 JR |
109 | /* |
110 | * This function checks if the driver got a valid device from the caller to | |
111 | * avoid dereferencing invalid pointers. | |
112 | */ | |
113 | static bool check_device(struct device *dev) | |
114 | { | |
115 | u16 devid; | |
116 | ||
117 | if (!dev || !dev->dma_mask) | |
118 | return false; | |
119 | ||
120 | /* No device or no PCI device */ | |
339d3261 | 121 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
122 | return false; |
123 | ||
124 | devid = get_device_id(dev); | |
125 | ||
126 | /* Out of our scope? */ | |
127 | if (devid > amd_iommu_last_bdf) | |
128 | return false; | |
129 | ||
130 | if (amd_iommu_rlookup_table[devid] == NULL) | |
131 | return false; | |
132 | ||
133 | return true; | |
134 | } | |
135 | ||
657cbb6b JR |
136 | static int iommu_init_device(struct device *dev) |
137 | { | |
138 | struct iommu_dev_data *dev_data; | |
139 | struct pci_dev *pdev; | |
140 | u16 devid, alias; | |
141 | ||
142 | if (dev->archdata.iommu) | |
143 | return 0; | |
144 | ||
145 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
146 | if (!dev_data) | |
147 | return -ENOMEM; | |
148 | ||
b00d3bcf JR |
149 | dev_data->dev = dev; |
150 | ||
657cbb6b JR |
151 | devid = get_device_id(dev); |
152 | alias = amd_iommu_alias_table[devid]; | |
153 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); | |
154 | if (pdev) | |
155 | dev_data->alias = &pdev->dev; | |
156 | ||
24100055 JR |
157 | atomic_set(&dev_data->bind, 0); |
158 | ||
657cbb6b JR |
159 | dev->archdata.iommu = dev_data; |
160 | ||
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static void iommu_uninit_device(struct device *dev) | |
166 | { | |
167 | kfree(dev->archdata.iommu); | |
168 | } | |
b7cc9554 JR |
169 | |
170 | void __init amd_iommu_uninit_devices(void) | |
171 | { | |
172 | struct pci_dev *pdev = NULL; | |
173 | ||
174 | for_each_pci_dev(pdev) { | |
175 | ||
176 | if (!check_device(&pdev->dev)) | |
177 | continue; | |
178 | ||
179 | iommu_uninit_device(&pdev->dev); | |
180 | } | |
181 | } | |
182 | ||
183 | int __init amd_iommu_init_devices(void) | |
184 | { | |
185 | struct pci_dev *pdev = NULL; | |
186 | int ret = 0; | |
187 | ||
188 | for_each_pci_dev(pdev) { | |
189 | ||
190 | if (!check_device(&pdev->dev)) | |
191 | continue; | |
192 | ||
193 | ret = iommu_init_device(&pdev->dev); | |
194 | if (ret) | |
195 | goto out_free; | |
196 | } | |
197 | ||
198 | return 0; | |
199 | ||
200 | out_free: | |
201 | ||
202 | amd_iommu_uninit_devices(); | |
203 | ||
204 | return ret; | |
205 | } | |
7f26508b JR |
206 | #ifdef CONFIG_AMD_IOMMU_STATS |
207 | ||
208 | /* | |
209 | * Initialization code for statistics collection | |
210 | */ | |
211 | ||
da49f6df | 212 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 213 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 214 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 215 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 216 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 217 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 218 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 219 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 220 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 221 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 222 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 223 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 224 | |
7f26508b | 225 | static struct dentry *stats_dir; |
7f26508b JR |
226 | static struct dentry *de_fflush; |
227 | ||
228 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
229 | { | |
230 | if (stats_dir == NULL) | |
231 | return; | |
232 | ||
233 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
234 | &cnt->value); | |
235 | } | |
236 | ||
237 | static void amd_iommu_stats_init(void) | |
238 | { | |
239 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
240 | if (stats_dir == NULL) | |
241 | return; | |
242 | ||
7f26508b JR |
243 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
244 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
245 | |
246 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 247 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 248 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 249 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 250 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 251 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 252 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 253 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 254 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 255 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 256 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 257 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
258 | } |
259 | ||
260 | #endif | |
261 | ||
a80dc3e0 JR |
262 | /**************************************************************************** |
263 | * | |
264 | * Interrupt handling functions | |
265 | * | |
266 | ****************************************************************************/ | |
267 | ||
e3e59876 JR |
268 | static void dump_dte_entry(u16 devid) |
269 | { | |
270 | int i; | |
271 | ||
272 | for (i = 0; i < 8; ++i) | |
273 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
274 | amd_iommu_dev_table[devid].data[i]); | |
275 | } | |
276 | ||
945b4ac4 JR |
277 | static void dump_command(unsigned long phys_addr) |
278 | { | |
279 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
280 | int i; | |
281 | ||
282 | for (i = 0; i < 4; ++i) | |
283 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
284 | } | |
285 | ||
a345b23b | 286 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
287 | { |
288 | u32 *event = __evt; | |
289 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
290 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
291 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
292 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
293 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
294 | ||
4c6f40d4 | 295 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
296 | |
297 | switch (type) { | |
298 | case EVENT_TYPE_ILL_DEV: | |
299 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
300 | "address=0x%016llx flags=0x%04x]\n", | |
301 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
302 | address, flags); | |
e3e59876 | 303 | dump_dte_entry(devid); |
90008ee4 JR |
304 | break; |
305 | case EVENT_TYPE_IO_FAULT: | |
306 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
307 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
308 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
309 | domid, address, flags); | |
310 | break; | |
311 | case EVENT_TYPE_DEV_TAB_ERR: | |
312 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
313 | "address=0x%016llx flags=0x%04x]\n", | |
314 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
315 | address, flags); | |
316 | break; | |
317 | case EVENT_TYPE_PAGE_TAB_ERR: | |
318 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
319 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
320 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
321 | domid, address, flags); | |
322 | break; | |
323 | case EVENT_TYPE_ILL_CMD: | |
324 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
8eed9833 | 325 | iommu->reset_in_progress = true; |
a345b23b | 326 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 327 | dump_command(address); |
90008ee4 JR |
328 | break; |
329 | case EVENT_TYPE_CMD_HARD_ERR: | |
330 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
331 | "flags=0x%04x]\n", address, flags); | |
332 | break; | |
333 | case EVENT_TYPE_IOTLB_INV_TO: | |
334 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
335 | "address=0x%016llx]\n", | |
336 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
337 | address); | |
338 | break; | |
339 | case EVENT_TYPE_INV_DEV_REQ: | |
340 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
341 | "address=0x%016llx flags=0x%04x]\n", | |
342 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
343 | address, flags); | |
344 | break; | |
345 | default: | |
346 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
347 | } | |
348 | } | |
349 | ||
350 | static void iommu_poll_events(struct amd_iommu *iommu) | |
351 | { | |
352 | u32 head, tail; | |
353 | unsigned long flags; | |
354 | ||
355 | spin_lock_irqsave(&iommu->lock, flags); | |
356 | ||
357 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
358 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
359 | ||
360 | while (head != tail) { | |
a345b23b | 361 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
362 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
363 | } | |
364 | ||
365 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
366 | ||
367 | spin_unlock_irqrestore(&iommu->lock, flags); | |
368 | } | |
369 | ||
a80dc3e0 JR |
370 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
371 | { | |
90008ee4 JR |
372 | struct amd_iommu *iommu; |
373 | ||
3bd22172 | 374 | for_each_iommu(iommu) |
90008ee4 JR |
375 | iommu_poll_events(iommu); |
376 | ||
377 | return IRQ_HANDLED; | |
a80dc3e0 JR |
378 | } |
379 | ||
431b2a20 JR |
380 | /**************************************************************************** |
381 | * | |
382 | * IOMMU command queuing functions | |
383 | * | |
384 | ****************************************************************************/ | |
385 | ||
ded46737 JR |
386 | static void build_completion_wait(struct iommu_cmd *cmd) |
387 | { | |
388 | memset(cmd, 0, sizeof(*cmd)); | |
389 | cmd->data[0] = CMD_COMPL_WAIT_INT_MASK; | |
390 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); | |
391 | } | |
392 | ||
431b2a20 JR |
393 | /* |
394 | * Writes the command to the IOMMUs command buffer and informs the | |
395 | * hardware about the new command. Must be called with iommu->lock held. | |
396 | */ | |
d6449536 | 397 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
398 | { |
399 | u32 tail, head; | |
400 | u8 *target; | |
401 | ||
549c90dc | 402 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
a19ae1ec | 403 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
8a7c5ef3 | 404 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
405 | memcpy_toio(target, cmd, sizeof(*cmd)); |
406 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
407 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
408 | if (tail == head) | |
409 | return -ENOMEM; | |
410 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
431b2a20 JR |
415 | /* |
416 | * General queuing function for commands. Takes iommu->lock and calls | |
417 | * __iommu_queue_command(). | |
418 | */ | |
d6449536 | 419 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
420 | { |
421 | unsigned long flags; | |
422 | int ret; | |
423 | ||
424 | spin_lock_irqsave(&iommu->lock, flags); | |
425 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 426 | if (!ret) |
0cfd7aa9 | 427 | iommu->need_sync = true; |
a19ae1ec JR |
428 | spin_unlock_irqrestore(&iommu->lock, flags); |
429 | ||
430 | return ret; | |
431 | } | |
432 | ||
8d201968 JR |
433 | /* |
434 | * This function waits until an IOMMU has completed a completion | |
435 | * wait command | |
436 | */ | |
437 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
438 | { | |
439 | int ready = 0; | |
440 | unsigned status = 0; | |
441 | unsigned long i = 0; | |
442 | ||
da49f6df JR |
443 | INC_STATS_COUNTER(compl_wait); |
444 | ||
8d201968 JR |
445 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
446 | ++i; | |
447 | /* wait for the bit to become one */ | |
448 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
449 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
450 | } | |
451 | ||
452 | /* set bit back to zero */ | |
453 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
454 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
455 | ||
8eed9833 JR |
456 | if (unlikely(i == EXIT_LOOP_COUNT)) |
457 | iommu->reset_in_progress = true; | |
8d201968 JR |
458 | } |
459 | ||
460 | /* | |
461 | * This function queues a completion wait command into the command | |
462 | * buffer of an IOMMU | |
463 | */ | |
464 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
465 | { | |
466 | struct iommu_cmd cmd; | |
467 | ||
ded46737 | 468 | build_completion_wait(&cmd); |
8d201968 JR |
469 | |
470 | return __iommu_queue_command(iommu, &cmd); | |
471 | } | |
472 | ||
431b2a20 JR |
473 | /* |
474 | * This function is called whenever we need to ensure that the IOMMU has | |
475 | * completed execution of all commands we sent. It sends a | |
476 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
477 | * us about that by writing a value to a physical address we pass with | |
478 | * the command. | |
479 | */ | |
a19ae1ec JR |
480 | static int iommu_completion_wait(struct amd_iommu *iommu) |
481 | { | |
8d201968 JR |
482 | int ret = 0; |
483 | unsigned long flags; | |
a19ae1ec | 484 | |
7e4f88da JR |
485 | spin_lock_irqsave(&iommu->lock, flags); |
486 | ||
09ee17eb JR |
487 | if (!iommu->need_sync) |
488 | goto out; | |
489 | ||
8d201968 | 490 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 491 | |
0cfd7aa9 | 492 | iommu->need_sync = false; |
a19ae1ec JR |
493 | |
494 | if (ret) | |
7e4f88da | 495 | goto out; |
a19ae1ec | 496 | |
8d201968 | 497 | __iommu_wait_for_completion(iommu); |
84df8175 | 498 | |
7e4f88da JR |
499 | out: |
500 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec | 501 | |
8eed9833 JR |
502 | if (iommu->reset_in_progress) |
503 | reset_iommu_command_buffer(iommu); | |
504 | ||
a19ae1ec JR |
505 | return 0; |
506 | } | |
507 | ||
0518a3a4 JR |
508 | static void iommu_flush_complete(struct protection_domain *domain) |
509 | { | |
510 | int i; | |
511 | ||
512 | for (i = 0; i < amd_iommus_present; ++i) { | |
513 | if (!domain->dev_iommu[i]) | |
514 | continue; | |
515 | ||
516 | /* | |
517 | * Devices of this domain are behind this IOMMU | |
518 | * We need to wait for completion of all commands. | |
519 | */ | |
520 | iommu_completion_wait(amd_iommus[i]); | |
521 | } | |
522 | } | |
523 | ||
431b2a20 JR |
524 | /* |
525 | * Command send function for invalidating a device table entry | |
526 | */ | |
3fa43655 JR |
527 | static int iommu_flush_device(struct device *dev) |
528 | { | |
529 | struct amd_iommu *iommu; | |
b00d3bcf | 530 | struct iommu_cmd cmd; |
3fa43655 JR |
531 | u16 devid; |
532 | ||
533 | devid = get_device_id(dev); | |
534 | iommu = amd_iommu_rlookup_table[devid]; | |
535 | ||
b00d3bcf JR |
536 | /* Build command */ |
537 | memset(&cmd, 0, sizeof(cmd)); | |
538 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
539 | cmd.data[0] = devid; | |
540 | ||
541 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
542 | } |
543 | ||
237b6f33 JR |
544 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
545 | u16 domid, int pde, int s) | |
546 | { | |
547 | memset(cmd, 0, sizeof(*cmd)); | |
548 | address &= PAGE_MASK; | |
549 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
550 | cmd->data[1] |= domid; | |
551 | cmd->data[2] = lower_32_bits(address); | |
552 | cmd->data[3] = upper_32_bits(address); | |
553 | if (s) /* size bit - we flush more than one 4kb page */ | |
554 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
555 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
556 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
557 | } | |
558 | ||
431b2a20 JR |
559 | /* |
560 | * Generic command send function for invalidaing TLB entries | |
561 | */ | |
a19ae1ec JR |
562 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
563 | u64 address, u16 domid, int pde, int s) | |
564 | { | |
d6449536 | 565 | struct iommu_cmd cmd; |
ee2fa743 | 566 | int ret; |
a19ae1ec | 567 | |
237b6f33 | 568 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 569 | |
ee2fa743 JR |
570 | ret = iommu_queue_command(iommu, &cmd); |
571 | ||
ee2fa743 | 572 | return ret; |
a19ae1ec JR |
573 | } |
574 | ||
431b2a20 JR |
575 | /* |
576 | * TLB invalidation function which is called from the mapping functions. | |
577 | * It invalidates a single PTE if the range to flush is within a single | |
578 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
579 | */ | |
6de8ad9b JR |
580 | static void __iommu_flush_pages(struct protection_domain *domain, |
581 | u64 address, size_t size, int pde) | |
a19ae1ec | 582 | { |
6de8ad9b | 583 | int s = 0, i; |
dcd1e92e | 584 | unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
585 | |
586 | address &= PAGE_MASK; | |
587 | ||
999ba417 JR |
588 | if (pages > 1) { |
589 | /* | |
590 | * If we have to flush more than one page, flush all | |
591 | * TLB entries for this domain | |
592 | */ | |
593 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
594 | s = 1; | |
a19ae1ec JR |
595 | } |
596 | ||
999ba417 | 597 | |
6de8ad9b JR |
598 | for (i = 0; i < amd_iommus_present; ++i) { |
599 | if (!domain->dev_iommu[i]) | |
600 | continue; | |
601 | ||
602 | /* | |
603 | * Devices of this domain are behind this IOMMU | |
604 | * We need a TLB flush | |
605 | */ | |
606 | iommu_queue_inv_iommu_pages(amd_iommus[i], address, | |
607 | domain->id, pde, s); | |
608 | } | |
609 | ||
610 | return; | |
611 | } | |
612 | ||
613 | static void iommu_flush_pages(struct protection_domain *domain, | |
614 | u64 address, size_t size) | |
615 | { | |
616 | __iommu_flush_pages(domain, address, size, 0); | |
a19ae1ec | 617 | } |
b6c02715 | 618 | |
1c655773 | 619 | /* Flush the whole IO/TLB for a given protection domain */ |
dcd1e92e | 620 | static void iommu_flush_tlb(struct protection_domain *domain) |
1c655773 | 621 | { |
dcd1e92e | 622 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
623 | } |
624 | ||
42a49f96 | 625 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
dcd1e92e | 626 | static void iommu_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 627 | { |
dcd1e92e | 628 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
629 | } |
630 | ||
b00d3bcf | 631 | |
43f49609 | 632 | /* |
b00d3bcf | 633 | * This function flushes the DTEs for all devices in domain |
43f49609 | 634 | */ |
b00d3bcf JR |
635 | static void iommu_flush_domain_devices(struct protection_domain *domain) |
636 | { | |
637 | struct iommu_dev_data *dev_data; | |
638 | unsigned long flags; | |
639 | ||
640 | spin_lock_irqsave(&domain->lock, flags); | |
641 | ||
642 | list_for_each_entry(dev_data, &domain->dev_list, list) | |
643 | iommu_flush_device(dev_data->dev); | |
644 | ||
645 | spin_unlock_irqrestore(&domain->lock, flags); | |
646 | } | |
647 | ||
648 | static void iommu_flush_all_domain_devices(void) | |
43f49609 | 649 | { |
09b42804 | 650 | struct protection_domain *domain; |
e394d72a | 651 | unsigned long flags; |
18811f55 | 652 | |
09b42804 | 653 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); |
bfd1be18 | 654 | |
09b42804 | 655 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
b00d3bcf | 656 | iommu_flush_domain_devices(domain); |
09b42804 | 657 | iommu_flush_complete(domain); |
bfd1be18 | 658 | } |
e394d72a | 659 | |
09b42804 | 660 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); |
e394d72a JR |
661 | } |
662 | ||
b00d3bcf JR |
663 | void amd_iommu_flush_all_devices(void) |
664 | { | |
665 | iommu_flush_all_domain_devices(); | |
666 | } | |
667 | ||
09b42804 JR |
668 | /* |
669 | * This function uses heavy locking and may disable irqs for some time. But | |
670 | * this is no issue because it is only called during resume. | |
671 | */ | |
bfd1be18 | 672 | void amd_iommu_flush_all_domains(void) |
e394d72a | 673 | { |
e3306664 | 674 | struct protection_domain *domain; |
09b42804 JR |
675 | unsigned long flags; |
676 | ||
677 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
e394d72a | 678 | |
e3306664 | 679 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
09b42804 | 680 | spin_lock(&domain->lock); |
e3306664 JR |
681 | iommu_flush_tlb_pde(domain); |
682 | iommu_flush_complete(domain); | |
09b42804 | 683 | spin_unlock(&domain->lock); |
e3306664 | 684 | } |
09b42804 JR |
685 | |
686 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
bfd1be18 JR |
687 | } |
688 | ||
a345b23b JR |
689 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
690 | { | |
691 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
692 | ||
b26e81b8 JR |
693 | if (iommu->reset_in_progress) |
694 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
695 | ||
a345b23b | 696 | amd_iommu_reset_cmd_buffer(iommu); |
b00d3bcf JR |
697 | amd_iommu_flush_all_devices(); |
698 | amd_iommu_flush_all_domains(); | |
b26e81b8 JR |
699 | |
700 | iommu->reset_in_progress = false; | |
a345b23b JR |
701 | } |
702 | ||
431b2a20 JR |
703 | /**************************************************************************** |
704 | * | |
705 | * The functions below are used the create the page table mappings for | |
706 | * unity mapped regions. | |
707 | * | |
708 | ****************************************************************************/ | |
709 | ||
308973d3 JR |
710 | /* |
711 | * This function is used to add another level to an IO page table. Adding | |
712 | * another level increases the size of the address space by 9 bits to a size up | |
713 | * to 64 bits. | |
714 | */ | |
715 | static bool increase_address_space(struct protection_domain *domain, | |
716 | gfp_t gfp) | |
717 | { | |
718 | u64 *pte; | |
719 | ||
720 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
721 | /* address space already 64 bit large */ | |
722 | return false; | |
723 | ||
724 | pte = (void *)get_zeroed_page(gfp); | |
725 | if (!pte) | |
726 | return false; | |
727 | ||
728 | *pte = PM_LEVEL_PDE(domain->mode, | |
729 | virt_to_phys(domain->pt_root)); | |
730 | domain->pt_root = pte; | |
731 | domain->mode += 1; | |
732 | domain->updated = true; | |
733 | ||
734 | return true; | |
735 | } | |
736 | ||
737 | static u64 *alloc_pte(struct protection_domain *domain, | |
738 | unsigned long address, | |
cbb9d729 | 739 | unsigned long page_size, |
308973d3 JR |
740 | u64 **pte_page, |
741 | gfp_t gfp) | |
742 | { | |
cbb9d729 | 743 | int level, end_lvl; |
308973d3 | 744 | u64 *pte, *page; |
cbb9d729 JR |
745 | |
746 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
747 | |
748 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
749 | increase_address_space(domain, gfp); | |
750 | ||
cbb9d729 JR |
751 | level = domain->mode - 1; |
752 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
753 | address = PAGE_SIZE_ALIGN(address, page_size); | |
754 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
755 | |
756 | while (level > end_lvl) { | |
757 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
758 | page = (u64 *)get_zeroed_page(gfp); | |
759 | if (!page) | |
760 | return NULL; | |
761 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
762 | } | |
763 | ||
cbb9d729 JR |
764 | /* No level skipping support yet */ |
765 | if (PM_PTE_LEVEL(*pte) != level) | |
766 | return NULL; | |
767 | ||
308973d3 JR |
768 | level -= 1; |
769 | ||
770 | pte = IOMMU_PTE_PAGE(*pte); | |
771 | ||
772 | if (pte_page && level == end_lvl) | |
773 | *pte_page = pte; | |
774 | ||
775 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
776 | } | |
777 | ||
778 | return pte; | |
779 | } | |
780 | ||
781 | /* | |
782 | * This function checks if there is a PTE for a given dma address. If | |
783 | * there is one, it returns the pointer to it. | |
784 | */ | |
24cd7723 | 785 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
786 | { |
787 | int level; | |
788 | u64 *pte; | |
789 | ||
24cd7723 JR |
790 | if (address > PM_LEVEL_SIZE(domain->mode)) |
791 | return NULL; | |
792 | ||
793 | level = domain->mode - 1; | |
794 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 795 | |
24cd7723 JR |
796 | while (level > 0) { |
797 | ||
798 | /* Not Present */ | |
308973d3 JR |
799 | if (!IOMMU_PTE_PRESENT(*pte)) |
800 | return NULL; | |
801 | ||
24cd7723 JR |
802 | /* Large PTE */ |
803 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
804 | unsigned long pte_mask, __pte; | |
805 | ||
806 | /* | |
807 | * If we have a series of large PTEs, make | |
808 | * sure to return a pointer to the first one. | |
809 | */ | |
810 | pte_mask = PTE_PAGE_SIZE(*pte); | |
811 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
812 | __pte = ((unsigned long)pte) & pte_mask; | |
813 | ||
814 | return (u64 *)__pte; | |
815 | } | |
816 | ||
817 | /* No level skipping support yet */ | |
818 | if (PM_PTE_LEVEL(*pte) != level) | |
819 | return NULL; | |
820 | ||
308973d3 JR |
821 | level -= 1; |
822 | ||
24cd7723 | 823 | /* Walk to the next level */ |
308973d3 JR |
824 | pte = IOMMU_PTE_PAGE(*pte); |
825 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
826 | } |
827 | ||
828 | return pte; | |
829 | } | |
830 | ||
431b2a20 JR |
831 | /* |
832 | * Generic mapping functions. It maps a physical address into a DMA | |
833 | * address space. It allocates the page table pages if necessary. | |
834 | * In the future it can be extended to a generic mapping function | |
835 | * supporting all features of AMD IOMMU page tables like level skipping | |
836 | * and full 64 bit address spaces. | |
837 | */ | |
38e817fe JR |
838 | static int iommu_map_page(struct protection_domain *dom, |
839 | unsigned long bus_addr, | |
840 | unsigned long phys_addr, | |
abdc5eb3 | 841 | int prot, |
cbb9d729 | 842 | unsigned long page_size) |
bd0e5211 | 843 | { |
8bda3092 | 844 | u64 __pte, *pte; |
cbb9d729 | 845 | int i, count; |
abdc5eb3 | 846 | |
bad1cac2 | 847 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
848 | return -EINVAL; |
849 | ||
cbb9d729 JR |
850 | bus_addr = PAGE_ALIGN(bus_addr); |
851 | phys_addr = PAGE_ALIGN(phys_addr); | |
852 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
853 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
854 | ||
855 | for (i = 0; i < count; ++i) | |
856 | if (IOMMU_PTE_PRESENT(pte[i])) | |
857 | return -EBUSY; | |
bd0e5211 | 858 | |
cbb9d729 JR |
859 | if (page_size > PAGE_SIZE) { |
860 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
861 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
862 | } else | |
863 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 864 | |
bd0e5211 JR |
865 | if (prot & IOMMU_PROT_IR) |
866 | __pte |= IOMMU_PTE_IR; | |
867 | if (prot & IOMMU_PROT_IW) | |
868 | __pte |= IOMMU_PTE_IW; | |
869 | ||
cbb9d729 JR |
870 | for (i = 0; i < count; ++i) |
871 | pte[i] = __pte; | |
bd0e5211 | 872 | |
04bfdd84 JR |
873 | update_domain(dom); |
874 | ||
bd0e5211 JR |
875 | return 0; |
876 | } | |
877 | ||
24cd7723 JR |
878 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
879 | unsigned long bus_addr, | |
880 | unsigned long page_size) | |
eb74ff6c | 881 | { |
24cd7723 JR |
882 | unsigned long long unmap_size, unmapped; |
883 | u64 *pte; | |
884 | ||
885 | BUG_ON(!is_power_of_2(page_size)); | |
886 | ||
887 | unmapped = 0; | |
eb74ff6c | 888 | |
24cd7723 JR |
889 | while (unmapped < page_size) { |
890 | ||
891 | pte = fetch_pte(dom, bus_addr); | |
892 | ||
893 | if (!pte) { | |
894 | /* | |
895 | * No PTE for this address | |
896 | * move forward in 4kb steps | |
897 | */ | |
898 | unmap_size = PAGE_SIZE; | |
899 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
900 | /* 4kb PTE found for this address */ | |
901 | unmap_size = PAGE_SIZE; | |
902 | *pte = 0ULL; | |
903 | } else { | |
904 | int count, i; | |
905 | ||
906 | /* Large PTE found which maps this address */ | |
907 | unmap_size = PTE_PAGE_SIZE(*pte); | |
908 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
909 | for (i = 0; i < count; i++) | |
910 | pte[i] = 0ULL; | |
911 | } | |
912 | ||
913 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
914 | unmapped += unmap_size; | |
915 | } | |
916 | ||
917 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 918 | |
24cd7723 | 919 | return unmapped; |
eb74ff6c | 920 | } |
eb74ff6c | 921 | |
431b2a20 JR |
922 | /* |
923 | * This function checks if a specific unity mapping entry is needed for | |
924 | * this specific IOMMU. | |
925 | */ | |
bd0e5211 JR |
926 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
927 | struct unity_map_entry *entry) | |
928 | { | |
929 | u16 bdf, i; | |
930 | ||
931 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
932 | bdf = amd_iommu_alias_table[i]; | |
933 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
934 | return 1; | |
935 | } | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
431b2a20 JR |
940 | /* |
941 | * This function actually applies the mapping to the page table of the | |
942 | * dma_ops domain. | |
943 | */ | |
bd0e5211 JR |
944 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
945 | struct unity_map_entry *e) | |
946 | { | |
947 | u64 addr; | |
948 | int ret; | |
949 | ||
950 | for (addr = e->address_start; addr < e->address_end; | |
951 | addr += PAGE_SIZE) { | |
abdc5eb3 | 952 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 953 | PAGE_SIZE); |
bd0e5211 JR |
954 | if (ret) |
955 | return ret; | |
956 | /* | |
957 | * if unity mapping is in aperture range mark the page | |
958 | * as allocated in the aperture | |
959 | */ | |
960 | if (addr < dma_dom->aperture_size) | |
c3239567 | 961 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 962 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
963 | } |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
171e7b37 JR |
968 | /* |
969 | * Init the unity mappings for a specific IOMMU in the system | |
970 | * | |
971 | * Basically iterates over all unity mapping entries and applies them to | |
972 | * the default domain DMA of that IOMMU if necessary. | |
973 | */ | |
974 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
975 | { | |
976 | struct unity_map_entry *entry; | |
977 | int ret; | |
978 | ||
979 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
980 | if (!iommu_for_unity_map(iommu, entry)) | |
981 | continue; | |
982 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
983 | if (ret) | |
984 | return ret; | |
985 | } | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
431b2a20 JR |
990 | /* |
991 | * Inits the unity mappings required for a specific device | |
992 | */ | |
bd0e5211 JR |
993 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
994 | u16 devid) | |
995 | { | |
996 | struct unity_map_entry *e; | |
997 | int ret; | |
998 | ||
999 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1000 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1001 | continue; | |
1002 | ret = dma_ops_unity_map(dma_dom, e); | |
1003 | if (ret) | |
1004 | return ret; | |
1005 | } | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
431b2a20 JR |
1010 | /**************************************************************************** |
1011 | * | |
1012 | * The next functions belong to the address allocator for the dma_ops | |
1013 | * interface functions. They work like the allocators in the other IOMMU | |
1014 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1015 | * the aperture. Maybe it could be enhanced in the future to a more | |
1016 | * efficient allocator. | |
1017 | * | |
1018 | ****************************************************************************/ | |
d3086444 | 1019 | |
431b2a20 | 1020 | /* |
384de729 | 1021 | * The address allocator core functions. |
431b2a20 JR |
1022 | * |
1023 | * called with domain->lock held | |
1024 | */ | |
384de729 | 1025 | |
171e7b37 JR |
1026 | /* |
1027 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1028 | * ranges. | |
1029 | */ | |
1030 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1031 | unsigned long start_page, | |
1032 | unsigned int pages) | |
1033 | { | |
1034 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1035 | ||
1036 | if (start_page + pages > last_page) | |
1037 | pages = last_page - start_page; | |
1038 | ||
1039 | for (i = start_page; i < start_page + pages; ++i) { | |
1040 | int index = i / APERTURE_RANGE_PAGES; | |
1041 | int page = i % APERTURE_RANGE_PAGES; | |
1042 | __set_bit(page, dom->aperture[index]->bitmap); | |
1043 | } | |
1044 | } | |
1045 | ||
9cabe89b JR |
1046 | /* |
1047 | * This function is used to add a new aperture range to an existing | |
1048 | * aperture in case of dma_ops domain allocation or address allocation | |
1049 | * failure. | |
1050 | */ | |
576175c2 | 1051 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1052 | bool populate, gfp_t gfp) |
1053 | { | |
1054 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1055 | struct amd_iommu *iommu; |
d91afd15 | 1056 | unsigned long i; |
9cabe89b | 1057 | |
f5e9705c JR |
1058 | #ifdef CONFIG_IOMMU_STRESS |
1059 | populate = false; | |
1060 | #endif | |
1061 | ||
9cabe89b JR |
1062 | if (index >= APERTURE_MAX_RANGES) |
1063 | return -ENOMEM; | |
1064 | ||
1065 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1066 | if (!dma_dom->aperture[index]) | |
1067 | return -ENOMEM; | |
1068 | ||
1069 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1070 | if (!dma_dom->aperture[index]->bitmap) | |
1071 | goto out_free; | |
1072 | ||
1073 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1074 | ||
1075 | if (populate) { | |
1076 | unsigned long address = dma_dom->aperture_size; | |
1077 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1078 | u64 *pte, *pte_page; | |
1079 | ||
1080 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1081 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1082 | &pte_page, gfp); |
1083 | if (!pte) | |
1084 | goto out_free; | |
1085 | ||
1086 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1087 | ||
1088 | address += APERTURE_RANGE_SIZE / 64; | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1093 | ||
b595076a | 1094 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1095 | for_each_iommu(iommu) { |
1096 | if (iommu->exclusion_start && | |
1097 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1098 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1099 | unsigned long startpage; | |
1100 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1101 | iommu->exclusion_length, | |
1102 | PAGE_SIZE); | |
1103 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1104 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1105 | } | |
00cd122a JR |
1106 | } |
1107 | ||
1108 | /* | |
1109 | * Check for areas already mapped as present in the new aperture | |
1110 | * range and mark those pages as reserved in the allocator. Such | |
1111 | * mappings may already exist as a result of requested unity | |
1112 | * mappings for devices. | |
1113 | */ | |
1114 | for (i = dma_dom->aperture[index]->offset; | |
1115 | i < dma_dom->aperture_size; | |
1116 | i += PAGE_SIZE) { | |
24cd7723 | 1117 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1118 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1119 | continue; | |
1120 | ||
1121 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1122 | } | |
1123 | ||
04bfdd84 JR |
1124 | update_domain(&dma_dom->domain); |
1125 | ||
9cabe89b JR |
1126 | return 0; |
1127 | ||
1128 | out_free: | |
04bfdd84 JR |
1129 | update_domain(&dma_dom->domain); |
1130 | ||
9cabe89b JR |
1131 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1132 | ||
1133 | kfree(dma_dom->aperture[index]); | |
1134 | dma_dom->aperture[index] = NULL; | |
1135 | ||
1136 | return -ENOMEM; | |
1137 | } | |
1138 | ||
384de729 JR |
1139 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1140 | struct dma_ops_domain *dom, | |
1141 | unsigned int pages, | |
1142 | unsigned long align_mask, | |
1143 | u64 dma_mask, | |
1144 | unsigned long start) | |
1145 | { | |
803b8cb4 | 1146 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1147 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1148 | int i = start >> APERTURE_RANGE_SHIFT; | |
1149 | unsigned long boundary_size; | |
1150 | unsigned long address = -1; | |
1151 | unsigned long limit; | |
1152 | ||
803b8cb4 JR |
1153 | next_bit >>= PAGE_SHIFT; |
1154 | ||
384de729 JR |
1155 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1156 | PAGE_SIZE) >> PAGE_SHIFT; | |
1157 | ||
1158 | for (;i < max_index; ++i) { | |
1159 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1160 | ||
1161 | if (dom->aperture[i]->offset >= dma_mask) | |
1162 | break; | |
1163 | ||
1164 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1165 | dma_mask >> PAGE_SHIFT); | |
1166 | ||
1167 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1168 | limit, next_bit, pages, 0, | |
1169 | boundary_size, align_mask); | |
1170 | if (address != -1) { | |
1171 | address = dom->aperture[i]->offset + | |
1172 | (address << PAGE_SHIFT); | |
803b8cb4 | 1173 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1174 | break; |
1175 | } | |
1176 | ||
1177 | next_bit = 0; | |
1178 | } | |
1179 | ||
1180 | return address; | |
1181 | } | |
1182 | ||
d3086444 JR |
1183 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1184 | struct dma_ops_domain *dom, | |
6d4f343f | 1185 | unsigned int pages, |
832a90c3 JR |
1186 | unsigned long align_mask, |
1187 | u64 dma_mask) | |
d3086444 | 1188 | { |
d3086444 | 1189 | unsigned long address; |
d3086444 | 1190 | |
fe16f088 JR |
1191 | #ifdef CONFIG_IOMMU_STRESS |
1192 | dom->next_address = 0; | |
1193 | dom->need_flush = true; | |
1194 | #endif | |
d3086444 | 1195 | |
384de729 | 1196 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1197 | dma_mask, dom->next_address); |
d3086444 | 1198 | |
1c655773 | 1199 | if (address == -1) { |
803b8cb4 | 1200 | dom->next_address = 0; |
384de729 JR |
1201 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1202 | dma_mask, 0); | |
1c655773 JR |
1203 | dom->need_flush = true; |
1204 | } | |
d3086444 | 1205 | |
384de729 | 1206 | if (unlikely(address == -1)) |
8fd524b3 | 1207 | address = DMA_ERROR_CODE; |
d3086444 JR |
1208 | |
1209 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1210 | ||
1211 | return address; | |
1212 | } | |
1213 | ||
431b2a20 JR |
1214 | /* |
1215 | * The address free function. | |
1216 | * | |
1217 | * called with domain->lock held | |
1218 | */ | |
d3086444 JR |
1219 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1220 | unsigned long address, | |
1221 | unsigned int pages) | |
1222 | { | |
384de729 JR |
1223 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1224 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1225 | |
384de729 JR |
1226 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1227 | ||
47bccd6b JR |
1228 | #ifdef CONFIG_IOMMU_STRESS |
1229 | if (i < 4) | |
1230 | return; | |
1231 | #endif | |
80be308d | 1232 | |
803b8cb4 | 1233 | if (address >= dom->next_address) |
80be308d | 1234 | dom->need_flush = true; |
384de729 JR |
1235 | |
1236 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1237 | |
a66022c4 | 1238 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1239 | |
d3086444 JR |
1240 | } |
1241 | ||
431b2a20 JR |
1242 | /**************************************************************************** |
1243 | * | |
1244 | * The next functions belong to the domain allocation. A domain is | |
1245 | * allocated for every IOMMU as the default domain. If device isolation | |
1246 | * is enabled, every device get its own domain. The most important thing | |
1247 | * about domains is the page table mapping the DMA address space they | |
1248 | * contain. | |
1249 | * | |
1250 | ****************************************************************************/ | |
1251 | ||
aeb26f55 JR |
1252 | /* |
1253 | * This function adds a protection domain to the global protection domain list | |
1254 | */ | |
1255 | static void add_domain_to_list(struct protection_domain *domain) | |
1256 | { | |
1257 | unsigned long flags; | |
1258 | ||
1259 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1260 | list_add(&domain->list, &amd_iommu_pd_list); | |
1261 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1262 | } | |
1263 | ||
1264 | /* | |
1265 | * This function removes a protection domain to the global | |
1266 | * protection domain list | |
1267 | */ | |
1268 | static void del_domain_from_list(struct protection_domain *domain) | |
1269 | { | |
1270 | unsigned long flags; | |
1271 | ||
1272 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1273 | list_del(&domain->list); | |
1274 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1275 | } | |
1276 | ||
ec487d1a JR |
1277 | static u16 domain_id_alloc(void) |
1278 | { | |
1279 | unsigned long flags; | |
1280 | int id; | |
1281 | ||
1282 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1283 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1284 | BUG_ON(id == 0); | |
1285 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1286 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1287 | else | |
1288 | id = 0; | |
1289 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1290 | ||
1291 | return id; | |
1292 | } | |
1293 | ||
a2acfb75 JR |
1294 | static void domain_id_free(int id) |
1295 | { | |
1296 | unsigned long flags; | |
1297 | ||
1298 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1299 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1300 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1301 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1302 | } | |
a2acfb75 | 1303 | |
86db2e5d | 1304 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1305 | { |
1306 | int i, j; | |
1307 | u64 *p1, *p2, *p3; | |
1308 | ||
86db2e5d | 1309 | p1 = domain->pt_root; |
ec487d1a JR |
1310 | |
1311 | if (!p1) | |
1312 | return; | |
1313 | ||
1314 | for (i = 0; i < 512; ++i) { | |
1315 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1316 | continue; | |
1317 | ||
1318 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1319 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1320 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1321 | continue; | |
1322 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1323 | free_page((unsigned long)p3); | |
1324 | } | |
1325 | ||
1326 | free_page((unsigned long)p2); | |
1327 | } | |
1328 | ||
1329 | free_page((unsigned long)p1); | |
86db2e5d JR |
1330 | |
1331 | domain->pt_root = NULL; | |
ec487d1a JR |
1332 | } |
1333 | ||
431b2a20 JR |
1334 | /* |
1335 | * Free a domain, only used if something went wrong in the | |
1336 | * allocation path and we need to free an already allocated page table | |
1337 | */ | |
ec487d1a JR |
1338 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1339 | { | |
384de729 JR |
1340 | int i; |
1341 | ||
ec487d1a JR |
1342 | if (!dom) |
1343 | return; | |
1344 | ||
aeb26f55 JR |
1345 | del_domain_from_list(&dom->domain); |
1346 | ||
86db2e5d | 1347 | free_pagetable(&dom->domain); |
ec487d1a | 1348 | |
384de729 JR |
1349 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1350 | if (!dom->aperture[i]) | |
1351 | continue; | |
1352 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1353 | kfree(dom->aperture[i]); | |
1354 | } | |
ec487d1a JR |
1355 | |
1356 | kfree(dom); | |
1357 | } | |
1358 | ||
431b2a20 JR |
1359 | /* |
1360 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1361 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1362 | * structures required for the dma_ops interface |
1363 | */ | |
87a64d52 | 1364 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1365 | { |
1366 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1367 | |
1368 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1369 | if (!dma_dom) | |
1370 | return NULL; | |
1371 | ||
1372 | spin_lock_init(&dma_dom->domain.lock); | |
1373 | ||
1374 | dma_dom->domain.id = domain_id_alloc(); | |
1375 | if (dma_dom->domain.id == 0) | |
1376 | goto free_dma_dom; | |
7c392cbe | 1377 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1378 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1379 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1380 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1381 | dma_dom->domain.priv = dma_dom; |
1382 | if (!dma_dom->domain.pt_root) | |
1383 | goto free_dma_dom; | |
ec487d1a | 1384 | |
1c655773 | 1385 | dma_dom->need_flush = false; |
bd60b735 | 1386 | dma_dom->target_dev = 0xffff; |
1c655773 | 1387 | |
aeb26f55 JR |
1388 | add_domain_to_list(&dma_dom->domain); |
1389 | ||
576175c2 | 1390 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1391 | goto free_dma_dom; |
ec487d1a | 1392 | |
431b2a20 | 1393 | /* |
ec487d1a JR |
1394 | * mark the first page as allocated so we never return 0 as |
1395 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1396 | */ |
384de729 | 1397 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1398 | dma_dom->next_address = 0; |
ec487d1a | 1399 | |
ec487d1a JR |
1400 | |
1401 | return dma_dom; | |
1402 | ||
1403 | free_dma_dom: | |
1404 | dma_ops_domain_free(dma_dom); | |
1405 | ||
1406 | return NULL; | |
1407 | } | |
1408 | ||
5b28df6f JR |
1409 | /* |
1410 | * little helper function to check whether a given protection domain is a | |
1411 | * dma_ops domain | |
1412 | */ | |
1413 | static bool dma_ops_domain(struct protection_domain *domain) | |
1414 | { | |
1415 | return domain->flags & PD_DMA_OPS_MASK; | |
1416 | } | |
1417 | ||
407d733e | 1418 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1419 | { |
b20ac0d4 | 1420 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1421 | |
38ddf41b JR |
1422 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1423 | << DEV_ENTRY_MODE_SHIFT; | |
1424 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1425 | |
b20ac0d4 | 1426 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1427 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1428 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1429 | } |
1430 | ||
1431 | static void clear_dte_entry(u16 devid) | |
1432 | { | |
15898bbc JR |
1433 | /* remove entry from the device table seen by the hardware */ |
1434 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1435 | amd_iommu_dev_table[devid].data[1] = 0; | |
1436 | amd_iommu_dev_table[devid].data[2] = 0; | |
1437 | ||
1438 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1439 | } |
1440 | ||
1441 | static void do_attach(struct device *dev, struct protection_domain *domain) | |
1442 | { | |
1443 | struct iommu_dev_data *dev_data; | |
1444 | struct amd_iommu *iommu; | |
1445 | u16 devid; | |
1446 | ||
1447 | devid = get_device_id(dev); | |
1448 | iommu = amd_iommu_rlookup_table[devid]; | |
1449 | dev_data = get_dev_data(dev); | |
1450 | ||
1451 | /* Update data structures */ | |
1452 | dev_data->domain = domain; | |
1453 | list_add(&dev_data->list, &domain->dev_list); | |
1454 | set_dte_entry(devid, domain); | |
1455 | ||
1456 | /* Do reference counting */ | |
1457 | domain->dev_iommu[iommu->index] += 1; | |
1458 | domain->dev_cnt += 1; | |
1459 | ||
1460 | /* Flush the DTE entry */ | |
3fa43655 | 1461 | iommu_flush_device(dev); |
7f760ddd JR |
1462 | } |
1463 | ||
1464 | static void do_detach(struct device *dev) | |
1465 | { | |
1466 | struct iommu_dev_data *dev_data; | |
1467 | struct amd_iommu *iommu; | |
1468 | u16 devid; | |
1469 | ||
1470 | devid = get_device_id(dev); | |
1471 | iommu = amd_iommu_rlookup_table[devid]; | |
1472 | dev_data = get_dev_data(dev); | |
15898bbc JR |
1473 | |
1474 | /* decrease reference counters */ | |
7f760ddd JR |
1475 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1476 | dev_data->domain->dev_cnt -= 1; | |
1477 | ||
1478 | /* Update data structures */ | |
1479 | dev_data->domain = NULL; | |
1480 | list_del(&dev_data->list); | |
1481 | clear_dte_entry(devid); | |
15898bbc | 1482 | |
7f760ddd | 1483 | /* Flush the DTE entry */ |
3fa43655 | 1484 | iommu_flush_device(dev); |
2b681faf JR |
1485 | } |
1486 | ||
1487 | /* | |
1488 | * If a device is not yet associated with a domain, this function does | |
1489 | * assigns it visible for the hardware | |
1490 | */ | |
15898bbc JR |
1491 | static int __attach_device(struct device *dev, |
1492 | struct protection_domain *domain) | |
2b681faf | 1493 | { |
657cbb6b | 1494 | struct iommu_dev_data *dev_data, *alias_data; |
84fe6c19 | 1495 | int ret; |
657cbb6b | 1496 | |
657cbb6b JR |
1497 | dev_data = get_dev_data(dev); |
1498 | alias_data = get_dev_data(dev_data->alias); | |
7f760ddd | 1499 | |
657cbb6b JR |
1500 | if (!alias_data) |
1501 | return -EINVAL; | |
15898bbc | 1502 | |
2b681faf JR |
1503 | /* lock domain */ |
1504 | spin_lock(&domain->lock); | |
1505 | ||
15898bbc | 1506 | /* Some sanity checks */ |
84fe6c19 | 1507 | ret = -EBUSY; |
657cbb6b JR |
1508 | if (alias_data->domain != NULL && |
1509 | alias_data->domain != domain) | |
84fe6c19 | 1510 | goto out_unlock; |
eba6ac60 | 1511 | |
657cbb6b JR |
1512 | if (dev_data->domain != NULL && |
1513 | dev_data->domain != domain) | |
84fe6c19 | 1514 | goto out_unlock; |
15898bbc JR |
1515 | |
1516 | /* Do real assignment */ | |
7f760ddd JR |
1517 | if (dev_data->alias != dev) { |
1518 | alias_data = get_dev_data(dev_data->alias); | |
1519 | if (alias_data->domain == NULL) | |
1520 | do_attach(dev_data->alias, domain); | |
24100055 JR |
1521 | |
1522 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1523 | } |
15898bbc | 1524 | |
7f760ddd JR |
1525 | if (dev_data->domain == NULL) |
1526 | do_attach(dev, domain); | |
eba6ac60 | 1527 | |
24100055 JR |
1528 | atomic_inc(&dev_data->bind); |
1529 | ||
84fe6c19 JL |
1530 | ret = 0; |
1531 | ||
1532 | out_unlock: | |
1533 | ||
eba6ac60 JR |
1534 | /* ready */ |
1535 | spin_unlock(&domain->lock); | |
15898bbc | 1536 | |
84fe6c19 | 1537 | return ret; |
0feae533 | 1538 | } |
b20ac0d4 | 1539 | |
407d733e JR |
1540 | /* |
1541 | * If a device is not yet associated with a domain, this function does | |
1542 | * assigns it visible for the hardware | |
1543 | */ | |
15898bbc JR |
1544 | static int attach_device(struct device *dev, |
1545 | struct protection_domain *domain) | |
0feae533 | 1546 | { |
eba6ac60 | 1547 | unsigned long flags; |
15898bbc | 1548 | int ret; |
eba6ac60 JR |
1549 | |
1550 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1551 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1552 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1553 | ||
0feae533 JR |
1554 | /* |
1555 | * We might boot into a crash-kernel here. The crashed kernel | |
1556 | * left the caches in the IOMMU dirty. So we have to flush | |
1557 | * here to evict all dirty stuff. | |
1558 | */ | |
dcd1e92e | 1559 | iommu_flush_tlb_pde(domain); |
15898bbc JR |
1560 | |
1561 | return ret; | |
b20ac0d4 JR |
1562 | } |
1563 | ||
355bf553 JR |
1564 | /* |
1565 | * Removes a device from a protection domain (unlocked) | |
1566 | */ | |
15898bbc | 1567 | static void __detach_device(struct device *dev) |
355bf553 | 1568 | { |
657cbb6b | 1569 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
24100055 | 1570 | struct iommu_dev_data *alias_data; |
2ca76279 | 1571 | struct protection_domain *domain; |
7c392cbe | 1572 | unsigned long flags; |
c4596114 | 1573 | |
7f760ddd | 1574 | BUG_ON(!dev_data->domain); |
355bf553 | 1575 | |
2ca76279 JR |
1576 | domain = dev_data->domain; |
1577 | ||
1578 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1579 | |
7f760ddd | 1580 | if (dev_data->alias != dev) { |
24100055 | 1581 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd JR |
1582 | if (atomic_dec_and_test(&alias_data->bind)) |
1583 | do_detach(dev_data->alias); | |
24100055 JR |
1584 | } |
1585 | ||
7f760ddd JR |
1586 | if (atomic_dec_and_test(&dev_data->bind)) |
1587 | do_detach(dev); | |
1588 | ||
2ca76279 | 1589 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1590 | |
1591 | /* | |
1592 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1593 | * passthrough domain if it is detached from any other domain. |
1594 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1595 | */ |
d3ad9373 JR |
1596 | if (iommu_pass_through && |
1597 | (dev_data->domain == NULL && domain != pt_domain)) | |
15898bbc | 1598 | __attach_device(dev, pt_domain); |
355bf553 JR |
1599 | } |
1600 | ||
1601 | /* | |
1602 | * Removes a device from a protection domain (with devtable_lock held) | |
1603 | */ | |
15898bbc | 1604 | static void detach_device(struct device *dev) |
355bf553 JR |
1605 | { |
1606 | unsigned long flags; | |
1607 | ||
1608 | /* lock device table */ | |
1609 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1610 | __detach_device(dev); |
355bf553 JR |
1611 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1612 | } | |
e275a2a0 | 1613 | |
15898bbc JR |
1614 | /* |
1615 | * Find out the protection domain structure for a given PCI device. This | |
1616 | * will give us the pointer to the page table root for example. | |
1617 | */ | |
1618 | static struct protection_domain *domain_for_device(struct device *dev) | |
1619 | { | |
1620 | struct protection_domain *dom; | |
657cbb6b | 1621 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc JR |
1622 | unsigned long flags; |
1623 | u16 devid, alias; | |
1624 | ||
657cbb6b JR |
1625 | devid = get_device_id(dev); |
1626 | alias = amd_iommu_alias_table[devid]; | |
1627 | dev_data = get_dev_data(dev); | |
1628 | alias_data = get_dev_data(dev_data->alias); | |
1629 | if (!alias_data) | |
1630 | return NULL; | |
15898bbc JR |
1631 | |
1632 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1633 | dom = dev_data->domain; |
15898bbc | 1634 | if (dom == NULL && |
657cbb6b JR |
1635 | alias_data->domain != NULL) { |
1636 | __attach_device(dev, alias_data->domain); | |
1637 | dom = alias_data->domain; | |
15898bbc JR |
1638 | } |
1639 | ||
1640 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1641 | ||
1642 | return dom; | |
1643 | } | |
1644 | ||
e275a2a0 JR |
1645 | static int device_change_notifier(struct notifier_block *nb, |
1646 | unsigned long action, void *data) | |
1647 | { | |
1648 | struct device *dev = data; | |
98fc5a69 | 1649 | u16 devid; |
e275a2a0 JR |
1650 | struct protection_domain *domain; |
1651 | struct dma_ops_domain *dma_domain; | |
1652 | struct amd_iommu *iommu; | |
1ac4cbbc | 1653 | unsigned long flags; |
e275a2a0 | 1654 | |
98fc5a69 JR |
1655 | if (!check_device(dev)) |
1656 | return 0; | |
e275a2a0 | 1657 | |
98fc5a69 JR |
1658 | devid = get_device_id(dev); |
1659 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1660 | |
1661 | switch (action) { | |
c1eee67b | 1662 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1663 | |
1664 | domain = domain_for_device(dev); | |
1665 | ||
e275a2a0 JR |
1666 | if (!domain) |
1667 | goto out; | |
a1ca331c JR |
1668 | if (iommu_pass_through) |
1669 | break; | |
15898bbc | 1670 | detach_device(dev); |
1ac4cbbc JR |
1671 | break; |
1672 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1673 | |
1674 | iommu_init_device(dev); | |
1675 | ||
1676 | domain = domain_for_device(dev); | |
1677 | ||
1ac4cbbc JR |
1678 | /* allocate a protection domain if a device is added */ |
1679 | dma_domain = find_protection_domain(devid); | |
1680 | if (dma_domain) | |
1681 | goto out; | |
87a64d52 | 1682 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1683 | if (!dma_domain) |
1684 | goto out; | |
1685 | dma_domain->target_dev = devid; | |
1686 | ||
1687 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1688 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1689 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1690 | ||
e275a2a0 | 1691 | break; |
657cbb6b JR |
1692 | case BUS_NOTIFY_DEL_DEVICE: |
1693 | ||
1694 | iommu_uninit_device(dev); | |
1695 | ||
e275a2a0 JR |
1696 | default: |
1697 | goto out; | |
1698 | } | |
1699 | ||
3fa43655 | 1700 | iommu_flush_device(dev); |
e275a2a0 JR |
1701 | iommu_completion_wait(iommu); |
1702 | ||
1703 | out: | |
1704 | return 0; | |
1705 | } | |
1706 | ||
b25ae679 | 1707 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1708 | .notifier_call = device_change_notifier, |
1709 | }; | |
355bf553 | 1710 | |
8638c491 JR |
1711 | void amd_iommu_init_notifier(void) |
1712 | { | |
1713 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1714 | } | |
1715 | ||
431b2a20 JR |
1716 | /***************************************************************************** |
1717 | * | |
1718 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1719 | * | |
1720 | *****************************************************************************/ | |
1721 | ||
1722 | /* | |
1723 | * In the dma_ops path we only have the struct device. This function | |
1724 | * finds the corresponding IOMMU, the protection domain and the | |
1725 | * requestor id for a given device. | |
1726 | * If the device is not yet associated with a domain this is also done | |
1727 | * in this function. | |
1728 | */ | |
94f6d190 | 1729 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1730 | { |
94f6d190 | 1731 | struct protection_domain *domain; |
b20ac0d4 | 1732 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1733 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1734 | |
f99c0f1c | 1735 | if (!check_device(dev)) |
94f6d190 | 1736 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1737 | |
94f6d190 JR |
1738 | domain = domain_for_device(dev); |
1739 | if (domain != NULL && !dma_ops_domain(domain)) | |
1740 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1741 | |
94f6d190 JR |
1742 | if (domain != NULL) |
1743 | return domain; | |
b20ac0d4 | 1744 | |
15898bbc | 1745 | /* Device not bount yet - bind it */ |
94f6d190 | 1746 | dma_dom = find_protection_domain(devid); |
15898bbc | 1747 | if (!dma_dom) |
94f6d190 JR |
1748 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1749 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1750 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1751 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1752 | |
94f6d190 | 1753 | return &dma_dom->domain; |
b20ac0d4 JR |
1754 | } |
1755 | ||
04bfdd84 JR |
1756 | static void update_device_table(struct protection_domain *domain) |
1757 | { | |
492667da | 1758 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1759 | |
492667da JR |
1760 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
1761 | u16 devid = get_device_id(dev_data->dev); | |
1762 | set_dte_entry(devid, domain); | |
04bfdd84 JR |
1763 | } |
1764 | } | |
1765 | ||
1766 | static void update_domain(struct protection_domain *domain) | |
1767 | { | |
1768 | if (!domain->updated) | |
1769 | return; | |
1770 | ||
1771 | update_device_table(domain); | |
b00d3bcf | 1772 | iommu_flush_domain_devices(domain); |
601367d7 | 1773 | iommu_flush_tlb_pde(domain); |
04bfdd84 JR |
1774 | |
1775 | domain->updated = false; | |
1776 | } | |
1777 | ||
8bda3092 JR |
1778 | /* |
1779 | * This function fetches the PTE for a given address in the aperture | |
1780 | */ | |
1781 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1782 | unsigned long address) | |
1783 | { | |
384de729 | 1784 | struct aperture_range *aperture; |
8bda3092 JR |
1785 | u64 *pte, *pte_page; |
1786 | ||
384de729 JR |
1787 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1788 | if (!aperture) | |
1789 | return NULL; | |
1790 | ||
1791 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1792 | if (!pte) { |
cbb9d729 | 1793 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1794 | GFP_ATOMIC); |
384de729 JR |
1795 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1796 | } else | |
8c8c143c | 1797 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1798 | |
04bfdd84 | 1799 | update_domain(&dom->domain); |
8bda3092 JR |
1800 | |
1801 | return pte; | |
1802 | } | |
1803 | ||
431b2a20 JR |
1804 | /* |
1805 | * This is the generic map function. It maps one 4kb page at paddr to | |
1806 | * the given address in the DMA address space for the domain. | |
1807 | */ | |
680525e0 | 1808 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1809 | unsigned long address, |
1810 | phys_addr_t paddr, | |
1811 | int direction) | |
1812 | { | |
1813 | u64 *pte, __pte; | |
1814 | ||
1815 | WARN_ON(address > dom->aperture_size); | |
1816 | ||
1817 | paddr &= PAGE_MASK; | |
1818 | ||
8bda3092 | 1819 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1820 | if (!pte) |
8fd524b3 | 1821 | return DMA_ERROR_CODE; |
cb76c322 JR |
1822 | |
1823 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1824 | ||
1825 | if (direction == DMA_TO_DEVICE) | |
1826 | __pte |= IOMMU_PTE_IR; | |
1827 | else if (direction == DMA_FROM_DEVICE) | |
1828 | __pte |= IOMMU_PTE_IW; | |
1829 | else if (direction == DMA_BIDIRECTIONAL) | |
1830 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1831 | ||
1832 | WARN_ON(*pte); | |
1833 | ||
1834 | *pte = __pte; | |
1835 | ||
1836 | return (dma_addr_t)address; | |
1837 | } | |
1838 | ||
431b2a20 JR |
1839 | /* |
1840 | * The generic unmapping function for on page in the DMA address space. | |
1841 | */ | |
680525e0 | 1842 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1843 | unsigned long address) |
1844 | { | |
384de729 | 1845 | struct aperture_range *aperture; |
cb76c322 JR |
1846 | u64 *pte; |
1847 | ||
1848 | if (address >= dom->aperture_size) | |
1849 | return; | |
1850 | ||
384de729 JR |
1851 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1852 | if (!aperture) | |
1853 | return; | |
1854 | ||
1855 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1856 | if (!pte) | |
1857 | return; | |
cb76c322 | 1858 | |
8c8c143c | 1859 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1860 | |
1861 | WARN_ON(!*pte); | |
1862 | ||
1863 | *pte = 0ULL; | |
1864 | } | |
1865 | ||
431b2a20 JR |
1866 | /* |
1867 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1868 | * contiguous memory region into DMA address space. It is used by all |
1869 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1870 | * Must be called with the domain lock held. |
1871 | */ | |
cb76c322 | 1872 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1873 | struct dma_ops_domain *dma_dom, |
1874 | phys_addr_t paddr, | |
1875 | size_t size, | |
6d4f343f | 1876 | int dir, |
832a90c3 JR |
1877 | bool align, |
1878 | u64 dma_mask) | |
cb76c322 JR |
1879 | { |
1880 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1881 | dma_addr_t address, start, ret; |
cb76c322 | 1882 | unsigned int pages; |
6d4f343f | 1883 | unsigned long align_mask = 0; |
cb76c322 JR |
1884 | int i; |
1885 | ||
e3c449f5 | 1886 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1887 | paddr &= PAGE_MASK; |
1888 | ||
8ecaf8f1 JR |
1889 | INC_STATS_COUNTER(total_map_requests); |
1890 | ||
c1858976 JR |
1891 | if (pages > 1) |
1892 | INC_STATS_COUNTER(cross_page); | |
1893 | ||
6d4f343f JR |
1894 | if (align) |
1895 | align_mask = (1UL << get_order(size)) - 1; | |
1896 | ||
11b83888 | 1897 | retry: |
832a90c3 JR |
1898 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1899 | dma_mask); | |
8fd524b3 | 1900 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1901 | /* |
1902 | * setting next_address here will let the address | |
1903 | * allocator only scan the new allocated range in the | |
1904 | * first run. This is a small optimization. | |
1905 | */ | |
1906 | dma_dom->next_address = dma_dom->aperture_size; | |
1907 | ||
576175c2 | 1908 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1909 | goto out; |
1910 | ||
1911 | /* | |
af901ca1 | 1912 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
1913 | * allocation again |
1914 | */ | |
1915 | goto retry; | |
1916 | } | |
cb76c322 JR |
1917 | |
1918 | start = address; | |
1919 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1920 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 1921 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1922 | goto out_unmap; |
1923 | ||
cb76c322 JR |
1924 | paddr += PAGE_SIZE; |
1925 | start += PAGE_SIZE; | |
1926 | } | |
1927 | address += offset; | |
1928 | ||
5774f7c5 JR |
1929 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1930 | ||
afa9fdc2 | 1931 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
dcd1e92e | 1932 | iommu_flush_tlb(&dma_dom->domain); |
1c655773 | 1933 | dma_dom->need_flush = false; |
318afd41 | 1934 | } else if (unlikely(amd_iommu_np_cache)) |
6de8ad9b | 1935 | iommu_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1936 | |
cb76c322 JR |
1937 | out: |
1938 | return address; | |
53812c11 JR |
1939 | |
1940 | out_unmap: | |
1941 | ||
1942 | for (--i; i >= 0; --i) { | |
1943 | start -= PAGE_SIZE; | |
680525e0 | 1944 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
1945 | } |
1946 | ||
1947 | dma_ops_free_addresses(dma_dom, address, pages); | |
1948 | ||
8fd524b3 | 1949 | return DMA_ERROR_CODE; |
cb76c322 JR |
1950 | } |
1951 | ||
431b2a20 JR |
1952 | /* |
1953 | * Does the reverse of the __map_single function. Must be called with | |
1954 | * the domain lock held too | |
1955 | */ | |
cd8c82e8 | 1956 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
1957 | dma_addr_t dma_addr, |
1958 | size_t size, | |
1959 | int dir) | |
1960 | { | |
04e0463e | 1961 | dma_addr_t flush_addr; |
cb76c322 JR |
1962 | dma_addr_t i, start; |
1963 | unsigned int pages; | |
1964 | ||
8fd524b3 | 1965 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1966 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1967 | return; |
1968 | ||
04e0463e | 1969 | flush_addr = dma_addr; |
e3c449f5 | 1970 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1971 | dma_addr &= PAGE_MASK; |
1972 | start = dma_addr; | |
1973 | ||
1974 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1975 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
1976 | start += PAGE_SIZE; |
1977 | } | |
1978 | ||
5774f7c5 JR |
1979 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1980 | ||
cb76c322 | 1981 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1982 | |
80be308d | 1983 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
04e0463e | 1984 | iommu_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
1985 | dma_dom->need_flush = false; |
1986 | } | |
cb76c322 JR |
1987 | } |
1988 | ||
431b2a20 JR |
1989 | /* |
1990 | * The exported map_single function for dma_ops. | |
1991 | */ | |
51491367 FT |
1992 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1993 | unsigned long offset, size_t size, | |
1994 | enum dma_data_direction dir, | |
1995 | struct dma_attrs *attrs) | |
4da70b9e JR |
1996 | { |
1997 | unsigned long flags; | |
4da70b9e | 1998 | struct protection_domain *domain; |
4da70b9e | 1999 | dma_addr_t addr; |
832a90c3 | 2000 | u64 dma_mask; |
51491367 | 2001 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2002 | |
0f2a86f2 JR |
2003 | INC_STATS_COUNTER(cnt_map_single); |
2004 | ||
94f6d190 JR |
2005 | domain = get_domain(dev); |
2006 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2007 | return (dma_addr_t)paddr; |
94f6d190 JR |
2008 | else if (IS_ERR(domain)) |
2009 | return DMA_ERROR_CODE; | |
4da70b9e | 2010 | |
f99c0f1c JR |
2011 | dma_mask = *dev->dma_mask; |
2012 | ||
4da70b9e | 2013 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2014 | |
cd8c82e8 | 2015 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2016 | dma_mask); |
8fd524b3 | 2017 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2018 | goto out; |
2019 | ||
0518a3a4 | 2020 | iommu_flush_complete(domain); |
4da70b9e JR |
2021 | |
2022 | out: | |
2023 | spin_unlock_irqrestore(&domain->lock, flags); | |
2024 | ||
2025 | return addr; | |
2026 | } | |
2027 | ||
431b2a20 JR |
2028 | /* |
2029 | * The exported unmap_single function for dma_ops. | |
2030 | */ | |
51491367 FT |
2031 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2032 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2033 | { |
2034 | unsigned long flags; | |
4da70b9e | 2035 | struct protection_domain *domain; |
4da70b9e | 2036 | |
146a6917 JR |
2037 | INC_STATS_COUNTER(cnt_unmap_single); |
2038 | ||
94f6d190 JR |
2039 | domain = get_domain(dev); |
2040 | if (IS_ERR(domain)) | |
5b28df6f JR |
2041 | return; |
2042 | ||
4da70b9e JR |
2043 | spin_lock_irqsave(&domain->lock, flags); |
2044 | ||
cd8c82e8 | 2045 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2046 | |
0518a3a4 | 2047 | iommu_flush_complete(domain); |
4da70b9e JR |
2048 | |
2049 | spin_unlock_irqrestore(&domain->lock, flags); | |
2050 | } | |
2051 | ||
431b2a20 JR |
2052 | /* |
2053 | * This is a special map_sg function which is used if we should map a | |
2054 | * device which is not handled by an AMD IOMMU in the system. | |
2055 | */ | |
65b050ad JR |
2056 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2057 | int nelems, int dir) | |
2058 | { | |
2059 | struct scatterlist *s; | |
2060 | int i; | |
2061 | ||
2062 | for_each_sg(sglist, s, nelems, i) { | |
2063 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2064 | s->dma_length = s->length; | |
2065 | } | |
2066 | ||
2067 | return nelems; | |
2068 | } | |
2069 | ||
431b2a20 JR |
2070 | /* |
2071 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2072 | * lists). | |
2073 | */ | |
65b050ad | 2074 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2075 | int nelems, enum dma_data_direction dir, |
2076 | struct dma_attrs *attrs) | |
65b050ad JR |
2077 | { |
2078 | unsigned long flags; | |
65b050ad | 2079 | struct protection_domain *domain; |
65b050ad JR |
2080 | int i; |
2081 | struct scatterlist *s; | |
2082 | phys_addr_t paddr; | |
2083 | int mapped_elems = 0; | |
832a90c3 | 2084 | u64 dma_mask; |
65b050ad | 2085 | |
d03f067a JR |
2086 | INC_STATS_COUNTER(cnt_map_sg); |
2087 | ||
94f6d190 JR |
2088 | domain = get_domain(dev); |
2089 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2090 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2091 | else if (IS_ERR(domain)) |
2092 | return 0; | |
dbcc112e | 2093 | |
832a90c3 | 2094 | dma_mask = *dev->dma_mask; |
65b050ad | 2095 | |
65b050ad JR |
2096 | spin_lock_irqsave(&domain->lock, flags); |
2097 | ||
2098 | for_each_sg(sglist, s, nelems, i) { | |
2099 | paddr = sg_phys(s); | |
2100 | ||
cd8c82e8 | 2101 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2102 | paddr, s->length, dir, false, |
2103 | dma_mask); | |
65b050ad JR |
2104 | |
2105 | if (s->dma_address) { | |
2106 | s->dma_length = s->length; | |
2107 | mapped_elems++; | |
2108 | } else | |
2109 | goto unmap; | |
65b050ad JR |
2110 | } |
2111 | ||
0518a3a4 | 2112 | iommu_flush_complete(domain); |
65b050ad JR |
2113 | |
2114 | out: | |
2115 | spin_unlock_irqrestore(&domain->lock, flags); | |
2116 | ||
2117 | return mapped_elems; | |
2118 | unmap: | |
2119 | for_each_sg(sglist, s, mapped_elems, i) { | |
2120 | if (s->dma_address) | |
cd8c82e8 | 2121 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2122 | s->dma_length, dir); |
2123 | s->dma_address = s->dma_length = 0; | |
2124 | } | |
2125 | ||
2126 | mapped_elems = 0; | |
2127 | ||
2128 | goto out; | |
2129 | } | |
2130 | ||
431b2a20 JR |
2131 | /* |
2132 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2133 | * lists). | |
2134 | */ | |
65b050ad | 2135 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2136 | int nelems, enum dma_data_direction dir, |
2137 | struct dma_attrs *attrs) | |
65b050ad JR |
2138 | { |
2139 | unsigned long flags; | |
65b050ad JR |
2140 | struct protection_domain *domain; |
2141 | struct scatterlist *s; | |
65b050ad JR |
2142 | int i; |
2143 | ||
55877a6b JR |
2144 | INC_STATS_COUNTER(cnt_unmap_sg); |
2145 | ||
94f6d190 JR |
2146 | domain = get_domain(dev); |
2147 | if (IS_ERR(domain)) | |
5b28df6f JR |
2148 | return; |
2149 | ||
65b050ad JR |
2150 | spin_lock_irqsave(&domain->lock, flags); |
2151 | ||
2152 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2153 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2154 | s->dma_length, dir); |
65b050ad JR |
2155 | s->dma_address = s->dma_length = 0; |
2156 | } | |
2157 | ||
0518a3a4 | 2158 | iommu_flush_complete(domain); |
65b050ad JR |
2159 | |
2160 | spin_unlock_irqrestore(&domain->lock, flags); | |
2161 | } | |
2162 | ||
431b2a20 JR |
2163 | /* |
2164 | * The exported alloc_coherent function for dma_ops. | |
2165 | */ | |
5d8b53cf JR |
2166 | static void *alloc_coherent(struct device *dev, size_t size, |
2167 | dma_addr_t *dma_addr, gfp_t flag) | |
2168 | { | |
2169 | unsigned long flags; | |
2170 | void *virt_addr; | |
5d8b53cf | 2171 | struct protection_domain *domain; |
5d8b53cf | 2172 | phys_addr_t paddr; |
832a90c3 | 2173 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2174 | |
c8f0fb36 JR |
2175 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2176 | ||
94f6d190 JR |
2177 | domain = get_domain(dev); |
2178 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2179 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2180 | *dma_addr = __pa(virt_addr); | |
2181 | return virt_addr; | |
94f6d190 JR |
2182 | } else if (IS_ERR(domain)) |
2183 | return NULL; | |
5d8b53cf | 2184 | |
f99c0f1c JR |
2185 | dma_mask = dev->coherent_dma_mask; |
2186 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2187 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2188 | |
2189 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2190 | if (!virt_addr) | |
b25ae679 | 2191 | return NULL; |
5d8b53cf | 2192 | |
5d8b53cf JR |
2193 | paddr = virt_to_phys(virt_addr); |
2194 | ||
832a90c3 JR |
2195 | if (!dma_mask) |
2196 | dma_mask = *dev->dma_mask; | |
2197 | ||
5d8b53cf JR |
2198 | spin_lock_irqsave(&domain->lock, flags); |
2199 | ||
cd8c82e8 | 2200 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2201 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2202 | |
8fd524b3 | 2203 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2204 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2205 | goto out_free; |
367d04c4 | 2206 | } |
5d8b53cf | 2207 | |
0518a3a4 | 2208 | iommu_flush_complete(domain); |
5d8b53cf | 2209 | |
5d8b53cf JR |
2210 | spin_unlock_irqrestore(&domain->lock, flags); |
2211 | ||
2212 | return virt_addr; | |
5b28df6f JR |
2213 | |
2214 | out_free: | |
2215 | ||
2216 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2217 | ||
2218 | return NULL; | |
5d8b53cf JR |
2219 | } |
2220 | ||
431b2a20 JR |
2221 | /* |
2222 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2223 | */ |
5d8b53cf JR |
2224 | static void free_coherent(struct device *dev, size_t size, |
2225 | void *virt_addr, dma_addr_t dma_addr) | |
2226 | { | |
2227 | unsigned long flags; | |
5d8b53cf | 2228 | struct protection_domain *domain; |
5d8b53cf | 2229 | |
5d31ee7e JR |
2230 | INC_STATS_COUNTER(cnt_free_coherent); |
2231 | ||
94f6d190 JR |
2232 | domain = get_domain(dev); |
2233 | if (IS_ERR(domain)) | |
5b28df6f JR |
2234 | goto free_mem; |
2235 | ||
5d8b53cf JR |
2236 | spin_lock_irqsave(&domain->lock, flags); |
2237 | ||
cd8c82e8 | 2238 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2239 | |
0518a3a4 | 2240 | iommu_flush_complete(domain); |
5d8b53cf JR |
2241 | |
2242 | spin_unlock_irqrestore(&domain->lock, flags); | |
2243 | ||
2244 | free_mem: | |
2245 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2246 | } | |
2247 | ||
b39ba6ad JR |
2248 | /* |
2249 | * This function is called by the DMA layer to find out if we can handle a | |
2250 | * particular device. It is part of the dma_ops. | |
2251 | */ | |
2252 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2253 | { | |
420aef8a | 2254 | return check_device(dev); |
b39ba6ad JR |
2255 | } |
2256 | ||
c432f3df | 2257 | /* |
431b2a20 JR |
2258 | * The function for pre-allocating protection domains. |
2259 | * | |
c432f3df JR |
2260 | * If the driver core informs the DMA layer if a driver grabs a device |
2261 | * we don't need to preallocate the protection domains anymore. | |
2262 | * For now we have to. | |
2263 | */ | |
0e93dd88 | 2264 | static void prealloc_protection_domains(void) |
c432f3df JR |
2265 | { |
2266 | struct pci_dev *dev = NULL; | |
2267 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2268 | u16 devid; |
c432f3df | 2269 | |
d18c69d3 | 2270 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2271 | |
2272 | /* Do we handle this device? */ | |
2273 | if (!check_device(&dev->dev)) | |
c432f3df | 2274 | continue; |
98fc5a69 JR |
2275 | |
2276 | /* Is there already any domain for it? */ | |
15898bbc | 2277 | if (domain_for_device(&dev->dev)) |
c432f3df | 2278 | continue; |
98fc5a69 JR |
2279 | |
2280 | devid = get_device_id(&dev->dev); | |
2281 | ||
87a64d52 | 2282 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2283 | if (!dma_dom) |
2284 | continue; | |
2285 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2286 | dma_dom->target_dev = devid; |
2287 | ||
15898bbc | 2288 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2289 | |
bd60b735 | 2290 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2291 | } |
2292 | } | |
2293 | ||
160c1d8e | 2294 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2295 | .alloc_coherent = alloc_coherent, |
2296 | .free_coherent = free_coherent, | |
51491367 FT |
2297 | .map_page = map_page, |
2298 | .unmap_page = unmap_page, | |
6631ee9d JR |
2299 | .map_sg = map_sg, |
2300 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2301 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2302 | }; |
2303 | ||
431b2a20 JR |
2304 | /* |
2305 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2306 | */ | |
f5325094 JR |
2307 | |
2308 | void __init amd_iommu_init_api(void) | |
2309 | { | |
2310 | register_iommu(&amd_iommu_ops); | |
2311 | } | |
2312 | ||
6631ee9d JR |
2313 | int __init amd_iommu_init_dma_ops(void) |
2314 | { | |
2315 | struct amd_iommu *iommu; | |
6631ee9d JR |
2316 | int ret; |
2317 | ||
431b2a20 JR |
2318 | /* |
2319 | * first allocate a default protection domain for every IOMMU we | |
2320 | * found in the system. Devices not assigned to any other | |
2321 | * protection domain will be assigned to the default one. | |
2322 | */ | |
3bd22172 | 2323 | for_each_iommu(iommu) { |
87a64d52 | 2324 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2325 | if (iommu->default_dom == NULL) |
2326 | return -ENOMEM; | |
e2dc14a2 | 2327 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2328 | ret = iommu_init_unity_mappings(iommu); |
2329 | if (ret) | |
2330 | goto free_domains; | |
2331 | } | |
2332 | ||
431b2a20 | 2333 | /* |
8793abeb | 2334 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2335 | */ |
8793abeb | 2336 | prealloc_protection_domains(); |
6631ee9d JR |
2337 | |
2338 | iommu_detected = 1; | |
75f1cdf1 | 2339 | swiotlb = 0; |
6631ee9d | 2340 | |
431b2a20 | 2341 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2342 | dma_ops = &amd_iommu_dma_ops; |
2343 | ||
7f26508b JR |
2344 | amd_iommu_stats_init(); |
2345 | ||
6631ee9d JR |
2346 | return 0; |
2347 | ||
2348 | free_domains: | |
2349 | ||
3bd22172 | 2350 | for_each_iommu(iommu) { |
6631ee9d JR |
2351 | if (iommu->default_dom) |
2352 | dma_ops_domain_free(iommu->default_dom); | |
2353 | } | |
2354 | ||
2355 | return ret; | |
2356 | } | |
6d98cd80 JR |
2357 | |
2358 | /***************************************************************************** | |
2359 | * | |
2360 | * The following functions belong to the exported interface of AMD IOMMU | |
2361 | * | |
2362 | * This interface allows access to lower level functions of the IOMMU | |
2363 | * like protection domain handling and assignement of devices to domains | |
2364 | * which is not possible with the dma_ops interface. | |
2365 | * | |
2366 | *****************************************************************************/ | |
2367 | ||
6d98cd80 JR |
2368 | static void cleanup_domain(struct protection_domain *domain) |
2369 | { | |
492667da | 2370 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2371 | unsigned long flags; |
6d98cd80 JR |
2372 | |
2373 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2374 | ||
492667da JR |
2375 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
2376 | struct device *dev = dev_data->dev; | |
2377 | ||
04e856c0 | 2378 | __detach_device(dev); |
492667da JR |
2379 | atomic_set(&dev_data->bind, 0); |
2380 | } | |
6d98cd80 JR |
2381 | |
2382 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2383 | } | |
2384 | ||
2650815f JR |
2385 | static void protection_domain_free(struct protection_domain *domain) |
2386 | { | |
2387 | if (!domain) | |
2388 | return; | |
2389 | ||
aeb26f55 JR |
2390 | del_domain_from_list(domain); |
2391 | ||
2650815f JR |
2392 | if (domain->id) |
2393 | domain_id_free(domain->id); | |
2394 | ||
2395 | kfree(domain); | |
2396 | } | |
2397 | ||
2398 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2399 | { |
2400 | struct protection_domain *domain; | |
2401 | ||
2402 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2403 | if (!domain) | |
2650815f | 2404 | return NULL; |
c156e347 JR |
2405 | |
2406 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2407 | mutex_init(&domain->api_lock); |
c156e347 JR |
2408 | domain->id = domain_id_alloc(); |
2409 | if (!domain->id) | |
2650815f | 2410 | goto out_err; |
7c392cbe | 2411 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2412 | |
aeb26f55 JR |
2413 | add_domain_to_list(domain); |
2414 | ||
2650815f JR |
2415 | return domain; |
2416 | ||
2417 | out_err: | |
2418 | kfree(domain); | |
2419 | ||
2420 | return NULL; | |
2421 | } | |
2422 | ||
2423 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2424 | { | |
2425 | struct protection_domain *domain; | |
2426 | ||
2427 | domain = protection_domain_alloc(); | |
2428 | if (!domain) | |
c156e347 | 2429 | goto out_free; |
2650815f JR |
2430 | |
2431 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2432 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2433 | if (!domain->pt_root) | |
2434 | goto out_free; | |
2435 | ||
2436 | dom->priv = domain; | |
2437 | ||
2438 | return 0; | |
2439 | ||
2440 | out_free: | |
2650815f | 2441 | protection_domain_free(domain); |
c156e347 JR |
2442 | |
2443 | return -ENOMEM; | |
2444 | } | |
2445 | ||
98383fc3 JR |
2446 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2447 | { | |
2448 | struct protection_domain *domain = dom->priv; | |
2449 | ||
2450 | if (!domain) | |
2451 | return; | |
2452 | ||
2453 | if (domain->dev_cnt > 0) | |
2454 | cleanup_domain(domain); | |
2455 | ||
2456 | BUG_ON(domain->dev_cnt != 0); | |
2457 | ||
2458 | free_pagetable(domain); | |
2459 | ||
8b408fe4 | 2460 | protection_domain_free(domain); |
98383fc3 JR |
2461 | |
2462 | dom->priv = NULL; | |
2463 | } | |
2464 | ||
684f2888 JR |
2465 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2466 | struct device *dev) | |
2467 | { | |
657cbb6b | 2468 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2469 | struct amd_iommu *iommu; |
684f2888 JR |
2470 | u16 devid; |
2471 | ||
98fc5a69 | 2472 | if (!check_device(dev)) |
684f2888 JR |
2473 | return; |
2474 | ||
98fc5a69 | 2475 | devid = get_device_id(dev); |
684f2888 | 2476 | |
657cbb6b | 2477 | if (dev_data->domain != NULL) |
15898bbc | 2478 | detach_device(dev); |
684f2888 JR |
2479 | |
2480 | iommu = amd_iommu_rlookup_table[devid]; | |
2481 | if (!iommu) | |
2482 | return; | |
2483 | ||
3fa43655 | 2484 | iommu_flush_device(dev); |
684f2888 JR |
2485 | iommu_completion_wait(iommu); |
2486 | } | |
2487 | ||
01106066 JR |
2488 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2489 | struct device *dev) | |
2490 | { | |
2491 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2492 | struct iommu_dev_data *dev_data; |
01106066 | 2493 | struct amd_iommu *iommu; |
15898bbc | 2494 | int ret; |
01106066 JR |
2495 | u16 devid; |
2496 | ||
98fc5a69 | 2497 | if (!check_device(dev)) |
01106066 JR |
2498 | return -EINVAL; |
2499 | ||
657cbb6b JR |
2500 | dev_data = dev->archdata.iommu; |
2501 | ||
98fc5a69 | 2502 | devid = get_device_id(dev); |
01106066 JR |
2503 | |
2504 | iommu = amd_iommu_rlookup_table[devid]; | |
2505 | if (!iommu) | |
2506 | return -EINVAL; | |
2507 | ||
657cbb6b | 2508 | if (dev_data->domain) |
15898bbc | 2509 | detach_device(dev); |
01106066 | 2510 | |
15898bbc | 2511 | ret = attach_device(dev, domain); |
01106066 JR |
2512 | |
2513 | iommu_completion_wait(iommu); | |
2514 | ||
15898bbc | 2515 | return ret; |
01106066 JR |
2516 | } |
2517 | ||
468e2366 JR |
2518 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2519 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2520 | { |
468e2366 | 2521 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2522 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2523 | int prot = 0; |
2524 | int ret; | |
2525 | ||
2526 | if (iommu_prot & IOMMU_READ) | |
2527 | prot |= IOMMU_PROT_IR; | |
2528 | if (iommu_prot & IOMMU_WRITE) | |
2529 | prot |= IOMMU_PROT_IW; | |
2530 | ||
5d214fe6 | 2531 | mutex_lock(&domain->api_lock); |
795e74f7 | 2532 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2533 | mutex_unlock(&domain->api_lock); |
2534 | ||
795e74f7 | 2535 | return ret; |
c6229ca6 JR |
2536 | } |
2537 | ||
468e2366 JR |
2538 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2539 | int gfp_order) | |
eb74ff6c | 2540 | { |
eb74ff6c | 2541 | struct protection_domain *domain = dom->priv; |
468e2366 | 2542 | unsigned long page_size, unmap_size; |
eb74ff6c | 2543 | |
468e2366 | 2544 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2545 | |
5d214fe6 | 2546 | mutex_lock(&domain->api_lock); |
468e2366 | 2547 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2548 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2549 | |
601367d7 | 2550 | iommu_flush_tlb_pde(domain); |
5d214fe6 | 2551 | |
468e2366 | 2552 | return get_order(unmap_size); |
eb74ff6c JR |
2553 | } |
2554 | ||
645c4c8d JR |
2555 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2556 | unsigned long iova) | |
2557 | { | |
2558 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2559 | unsigned long offset_mask; |
645c4c8d | 2560 | phys_addr_t paddr; |
f03152bb | 2561 | u64 *pte, __pte; |
645c4c8d | 2562 | |
24cd7723 | 2563 | pte = fetch_pte(domain, iova); |
645c4c8d | 2564 | |
a6d41a40 | 2565 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2566 | return 0; |
2567 | ||
f03152bb JR |
2568 | if (PM_PTE_LEVEL(*pte) == 0) |
2569 | offset_mask = PAGE_SIZE - 1; | |
2570 | else | |
2571 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2572 | ||
2573 | __pte = *pte & PM_ADDR_MASK; | |
2574 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2575 | |
2576 | return paddr; | |
2577 | } | |
2578 | ||
dbb9fd86 SY |
2579 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2580 | unsigned long cap) | |
2581 | { | |
80a506b8 JR |
2582 | switch (cap) { |
2583 | case IOMMU_CAP_CACHE_COHERENCY: | |
2584 | return 1; | |
2585 | } | |
2586 | ||
dbb9fd86 SY |
2587 | return 0; |
2588 | } | |
2589 | ||
26961efe JR |
2590 | static struct iommu_ops amd_iommu_ops = { |
2591 | .domain_init = amd_iommu_domain_init, | |
2592 | .domain_destroy = amd_iommu_domain_destroy, | |
2593 | .attach_dev = amd_iommu_attach_device, | |
2594 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2595 | .map = amd_iommu_map, |
2596 | .unmap = amd_iommu_unmap, | |
26961efe | 2597 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2598 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2599 | }; |
2600 | ||
0feae533 JR |
2601 | /***************************************************************************** |
2602 | * | |
2603 | * The next functions do a basic initialization of IOMMU for pass through | |
2604 | * mode | |
2605 | * | |
2606 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2607 | * DMA-API translation. | |
2608 | * | |
2609 | *****************************************************************************/ | |
2610 | ||
2611 | int __init amd_iommu_init_passthrough(void) | |
2612 | { | |
15898bbc | 2613 | struct amd_iommu *iommu; |
0feae533 | 2614 | struct pci_dev *dev = NULL; |
15898bbc | 2615 | u16 devid; |
0feae533 | 2616 | |
af901ca1 | 2617 | /* allocate passthrough domain */ |
0feae533 JR |
2618 | pt_domain = protection_domain_alloc(); |
2619 | if (!pt_domain) | |
2620 | return -ENOMEM; | |
2621 | ||
2622 | pt_domain->mode |= PAGE_MODE_NONE; | |
2623 | ||
6c54aabd | 2624 | for_each_pci_dev(dev) { |
98fc5a69 | 2625 | if (!check_device(&dev->dev)) |
0feae533 JR |
2626 | continue; |
2627 | ||
98fc5a69 JR |
2628 | devid = get_device_id(&dev->dev); |
2629 | ||
15898bbc | 2630 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2631 | if (!iommu) |
2632 | continue; | |
2633 | ||
15898bbc | 2634 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2635 | } |
2636 | ||
2637 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2638 | ||
2639 | return 0; | |
2640 | } |