Commit | Line | Data |
---|---|---|
b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 | 57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bc3e127 | 58 | static u64 *alloc_pte(struct protection_domain *domain, |
8bda3092 JR |
59 | unsigned long address, u64 |
60 | **pte_page, gfp_t gfp); | |
00cd122a JR |
61 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
62 | unsigned long start_page, | |
63 | unsigned int pages); | |
9355a081 JR |
64 | static u64 *fetch_pte(struct protection_domain *domain, |
65 | unsigned long address); | |
04bfdd84 | 66 | static void update_domain(struct protection_domain *domain); |
bd0e5211 | 67 | |
c1eee67b CW |
68 | #ifndef BUS_NOTIFY_UNBOUND_DRIVER |
69 | #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005 | |
70 | #endif | |
71 | ||
7f26508b JR |
72 | #ifdef CONFIG_AMD_IOMMU_STATS |
73 | ||
74 | /* | |
75 | * Initialization code for statistics collection | |
76 | */ | |
77 | ||
da49f6df | 78 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 79 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 80 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 81 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 82 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 83 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 84 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 85 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 86 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 87 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 88 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 89 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 90 | |
7f26508b JR |
91 | static struct dentry *stats_dir; |
92 | static struct dentry *de_isolate; | |
93 | static struct dentry *de_fflush; | |
94 | ||
95 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
96 | { | |
97 | if (stats_dir == NULL) | |
98 | return; | |
99 | ||
100 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
101 | &cnt->value); | |
102 | } | |
103 | ||
104 | static void amd_iommu_stats_init(void) | |
105 | { | |
106 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
107 | if (stats_dir == NULL) | |
108 | return; | |
109 | ||
110 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
111 | (u32 *)&amd_iommu_isolate); | |
112 | ||
113 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
114 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
115 | |
116 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 117 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 118 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 119 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 120 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 121 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 122 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 123 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 124 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 125 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 126 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 127 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
128 | } |
129 | ||
130 | #endif | |
131 | ||
431b2a20 | 132 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
133 | static int iommu_has_npcache(struct amd_iommu *iommu) |
134 | { | |
ae9b9403 | 135 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
136 | } |
137 | ||
a80dc3e0 JR |
138 | /**************************************************************************** |
139 | * | |
140 | * Interrupt handling functions | |
141 | * | |
142 | ****************************************************************************/ | |
143 | ||
90008ee4 JR |
144 | static void iommu_print_event(void *__evt) |
145 | { | |
146 | u32 *event = __evt; | |
147 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
148 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
149 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
150 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
151 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
152 | ||
153 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
154 | ||
155 | switch (type) { | |
156 | case EVENT_TYPE_ILL_DEV: | |
157 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
158 | "address=0x%016llx flags=0x%04x]\n", | |
159 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
160 | address, flags); | |
161 | break; | |
162 | case EVENT_TYPE_IO_FAULT: | |
163 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
164 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
165 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
166 | domid, address, flags); | |
167 | break; | |
168 | case EVENT_TYPE_DEV_TAB_ERR: | |
169 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
170 | "address=0x%016llx flags=0x%04x]\n", | |
171 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
172 | address, flags); | |
173 | break; | |
174 | case EVENT_TYPE_PAGE_TAB_ERR: | |
175 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
176 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
177 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
178 | domid, address, flags); | |
179 | break; | |
180 | case EVENT_TYPE_ILL_CMD: | |
181 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
182 | break; | |
183 | case EVENT_TYPE_CMD_HARD_ERR: | |
184 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
185 | "flags=0x%04x]\n", address, flags); | |
186 | break; | |
187 | case EVENT_TYPE_IOTLB_INV_TO: | |
188 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
189 | "address=0x%016llx]\n", | |
190 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
191 | address); | |
192 | break; | |
193 | case EVENT_TYPE_INV_DEV_REQ: | |
194 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
195 | "address=0x%016llx flags=0x%04x]\n", | |
196 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
197 | address, flags); | |
198 | break; | |
199 | default: | |
200 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
201 | } | |
202 | } | |
203 | ||
204 | static void iommu_poll_events(struct amd_iommu *iommu) | |
205 | { | |
206 | u32 head, tail; | |
207 | unsigned long flags; | |
208 | ||
209 | spin_lock_irqsave(&iommu->lock, flags); | |
210 | ||
211 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
212 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
213 | ||
214 | while (head != tail) { | |
215 | iommu_print_event(iommu->evt_buf + head); | |
216 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
217 | } | |
218 | ||
219 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
220 | ||
221 | spin_unlock_irqrestore(&iommu->lock, flags); | |
222 | } | |
223 | ||
a80dc3e0 JR |
224 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
225 | { | |
90008ee4 JR |
226 | struct amd_iommu *iommu; |
227 | ||
3bd22172 | 228 | for_each_iommu(iommu) |
90008ee4 JR |
229 | iommu_poll_events(iommu); |
230 | ||
231 | return IRQ_HANDLED; | |
a80dc3e0 JR |
232 | } |
233 | ||
431b2a20 JR |
234 | /**************************************************************************** |
235 | * | |
236 | * IOMMU command queuing functions | |
237 | * | |
238 | ****************************************************************************/ | |
239 | ||
240 | /* | |
241 | * Writes the command to the IOMMUs command buffer and informs the | |
242 | * hardware about the new command. Must be called with iommu->lock held. | |
243 | */ | |
d6449536 | 244 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
245 | { |
246 | u32 tail, head; | |
247 | u8 *target; | |
248 | ||
249 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 250 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
251 | memcpy_toio(target, cmd, sizeof(*cmd)); |
252 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
253 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
254 | if (tail == head) | |
255 | return -ENOMEM; | |
256 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
431b2a20 JR |
261 | /* |
262 | * General queuing function for commands. Takes iommu->lock and calls | |
263 | * __iommu_queue_command(). | |
264 | */ | |
d6449536 | 265 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
266 | { |
267 | unsigned long flags; | |
268 | int ret; | |
269 | ||
270 | spin_lock_irqsave(&iommu->lock, flags); | |
271 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 272 | if (!ret) |
0cfd7aa9 | 273 | iommu->need_sync = true; |
a19ae1ec JR |
274 | spin_unlock_irqrestore(&iommu->lock, flags); |
275 | ||
276 | return ret; | |
277 | } | |
278 | ||
8d201968 JR |
279 | /* |
280 | * This function waits until an IOMMU has completed a completion | |
281 | * wait command | |
282 | */ | |
283 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
284 | { | |
285 | int ready = 0; | |
286 | unsigned status = 0; | |
287 | unsigned long i = 0; | |
288 | ||
da49f6df JR |
289 | INC_STATS_COUNTER(compl_wait); |
290 | ||
8d201968 JR |
291 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
292 | ++i; | |
293 | /* wait for the bit to become one */ | |
294 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
295 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
296 | } | |
297 | ||
298 | /* set bit back to zero */ | |
299 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
300 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
301 | ||
302 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
303 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
304 | } | |
305 | ||
306 | /* | |
307 | * This function queues a completion wait command into the command | |
308 | * buffer of an IOMMU | |
309 | */ | |
310 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
311 | { | |
312 | struct iommu_cmd cmd; | |
313 | ||
314 | memset(&cmd, 0, sizeof(cmd)); | |
315 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
316 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
317 | ||
318 | return __iommu_queue_command(iommu, &cmd); | |
319 | } | |
320 | ||
431b2a20 JR |
321 | /* |
322 | * This function is called whenever we need to ensure that the IOMMU has | |
323 | * completed execution of all commands we sent. It sends a | |
324 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
325 | * us about that by writing a value to a physical address we pass with | |
326 | * the command. | |
327 | */ | |
a19ae1ec JR |
328 | static int iommu_completion_wait(struct amd_iommu *iommu) |
329 | { | |
8d201968 JR |
330 | int ret = 0; |
331 | unsigned long flags; | |
a19ae1ec | 332 | |
7e4f88da JR |
333 | spin_lock_irqsave(&iommu->lock, flags); |
334 | ||
09ee17eb JR |
335 | if (!iommu->need_sync) |
336 | goto out; | |
337 | ||
8d201968 | 338 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 339 | |
0cfd7aa9 | 340 | iommu->need_sync = false; |
a19ae1ec JR |
341 | |
342 | if (ret) | |
7e4f88da | 343 | goto out; |
a19ae1ec | 344 | |
8d201968 | 345 | __iommu_wait_for_completion(iommu); |
84df8175 | 346 | |
7e4f88da JR |
347 | out: |
348 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
349 | |
350 | return 0; | |
351 | } | |
352 | ||
431b2a20 JR |
353 | /* |
354 | * Command send function for invalidating a device table entry | |
355 | */ | |
a19ae1ec JR |
356 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
357 | { | |
d6449536 | 358 | struct iommu_cmd cmd; |
ee2fa743 | 359 | int ret; |
a19ae1ec JR |
360 | |
361 | BUG_ON(iommu == NULL); | |
362 | ||
363 | memset(&cmd, 0, sizeof(cmd)); | |
364 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
365 | cmd.data[0] = devid; | |
366 | ||
ee2fa743 JR |
367 | ret = iommu_queue_command(iommu, &cmd); |
368 | ||
ee2fa743 | 369 | return ret; |
a19ae1ec JR |
370 | } |
371 | ||
237b6f33 JR |
372 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
373 | u16 domid, int pde, int s) | |
374 | { | |
375 | memset(cmd, 0, sizeof(*cmd)); | |
376 | address &= PAGE_MASK; | |
377 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
378 | cmd->data[1] |= domid; | |
379 | cmd->data[2] = lower_32_bits(address); | |
380 | cmd->data[3] = upper_32_bits(address); | |
381 | if (s) /* size bit - we flush more than one 4kb page */ | |
382 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
383 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
384 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
385 | } | |
386 | ||
431b2a20 JR |
387 | /* |
388 | * Generic command send function for invalidaing TLB entries | |
389 | */ | |
a19ae1ec JR |
390 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
391 | u64 address, u16 domid, int pde, int s) | |
392 | { | |
d6449536 | 393 | struct iommu_cmd cmd; |
ee2fa743 | 394 | int ret; |
a19ae1ec | 395 | |
237b6f33 | 396 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 397 | |
ee2fa743 JR |
398 | ret = iommu_queue_command(iommu, &cmd); |
399 | ||
ee2fa743 | 400 | return ret; |
a19ae1ec JR |
401 | } |
402 | ||
431b2a20 JR |
403 | /* |
404 | * TLB invalidation function which is called from the mapping functions. | |
405 | * It invalidates a single PTE if the range to flush is within a single | |
406 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
407 | */ | |
a19ae1ec JR |
408 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
409 | u64 address, size_t size) | |
410 | { | |
999ba417 | 411 | int s = 0; |
e3c449f5 | 412 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
413 | |
414 | address &= PAGE_MASK; | |
415 | ||
999ba417 JR |
416 | if (pages > 1) { |
417 | /* | |
418 | * If we have to flush more than one page, flush all | |
419 | * TLB entries for this domain | |
420 | */ | |
421 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
422 | s = 1; | |
a19ae1ec JR |
423 | } |
424 | ||
999ba417 JR |
425 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
426 | ||
a19ae1ec JR |
427 | return 0; |
428 | } | |
b6c02715 | 429 | |
1c655773 JR |
430 | /* Flush the whole IO/TLB for a given protection domain */ |
431 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
432 | { | |
433 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
434 | ||
f57d98ae JR |
435 | INC_STATS_COUNTER(domain_flush_single); |
436 | ||
1c655773 JR |
437 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
438 | } | |
439 | ||
42a49f96 CW |
440 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
441 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
442 | { | |
443 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
444 | ||
445 | INC_STATS_COUNTER(domain_flush_single); | |
446 | ||
447 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
448 | } | |
449 | ||
43f49609 JR |
450 | /* |
451 | * This function is used to flush the IO/TLB for a given protection domain | |
452 | * on every IOMMU in the system | |
453 | */ | |
454 | static void iommu_flush_domain(u16 domid) | |
455 | { | |
456 | unsigned long flags; | |
457 | struct amd_iommu *iommu; | |
458 | struct iommu_cmd cmd; | |
459 | ||
18811f55 JR |
460 | INC_STATS_COUNTER(domain_flush_all); |
461 | ||
43f49609 JR |
462 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
463 | domid, 1, 1); | |
464 | ||
3bd22172 | 465 | for_each_iommu(iommu) { |
43f49609 JR |
466 | spin_lock_irqsave(&iommu->lock, flags); |
467 | __iommu_queue_command(iommu, &cmd); | |
468 | __iommu_completion_wait(iommu); | |
469 | __iommu_wait_for_completion(iommu); | |
470 | spin_unlock_irqrestore(&iommu->lock, flags); | |
471 | } | |
472 | } | |
43f49609 | 473 | |
bfd1be18 JR |
474 | void amd_iommu_flush_all_domains(void) |
475 | { | |
476 | int i; | |
477 | ||
478 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
479 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
480 | continue; | |
481 | iommu_flush_domain(i); | |
482 | } | |
483 | } | |
484 | ||
6a0dbcbe | 485 | static void flush_devices_by_domain(struct protection_domain *domain) |
7d7a110c JR |
486 | { |
487 | struct amd_iommu *iommu; | |
488 | int i; | |
489 | ||
490 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
6a0dbcbe JR |
491 | if ((domain == NULL && amd_iommu_pd_table[i] == NULL) || |
492 | (amd_iommu_pd_table[i] != domain)) | |
7d7a110c JR |
493 | continue; |
494 | ||
495 | iommu = amd_iommu_rlookup_table[i]; | |
496 | if (!iommu) | |
497 | continue; | |
498 | ||
499 | iommu_queue_inv_dev_entry(iommu, i); | |
500 | iommu_completion_wait(iommu); | |
501 | } | |
502 | } | |
503 | ||
6a0dbcbe JR |
504 | void amd_iommu_flush_all_devices(void) |
505 | { | |
506 | flush_devices_by_domain(NULL); | |
507 | } | |
508 | ||
431b2a20 JR |
509 | /**************************************************************************** |
510 | * | |
511 | * The functions below are used the create the page table mappings for | |
512 | * unity mapped regions. | |
513 | * | |
514 | ****************************************************************************/ | |
515 | ||
516 | /* | |
517 | * Generic mapping functions. It maps a physical address into a DMA | |
518 | * address space. It allocates the page table pages if necessary. | |
519 | * In the future it can be extended to a generic mapping function | |
520 | * supporting all features of AMD IOMMU page tables like level skipping | |
521 | * and full 64 bit address spaces. | |
522 | */ | |
38e817fe JR |
523 | static int iommu_map_page(struct protection_domain *dom, |
524 | unsigned long bus_addr, | |
525 | unsigned long phys_addr, | |
526 | int prot) | |
bd0e5211 | 527 | { |
8bda3092 | 528 | u64 __pte, *pte; |
bd0e5211 JR |
529 | |
530 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 531 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
532 | |
533 | /* only support 512GB address spaces for now */ | |
534 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
535 | return -EINVAL; | |
536 | ||
8bda3092 | 537 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); |
bd0e5211 JR |
538 | |
539 | if (IOMMU_PTE_PRESENT(*pte)) | |
540 | return -EBUSY; | |
541 | ||
542 | __pte = phys_addr | IOMMU_PTE_P; | |
543 | if (prot & IOMMU_PROT_IR) | |
544 | __pte |= IOMMU_PTE_IR; | |
545 | if (prot & IOMMU_PROT_IW) | |
546 | __pte |= IOMMU_PTE_IW; | |
547 | ||
548 | *pte = __pte; | |
549 | ||
04bfdd84 JR |
550 | update_domain(dom); |
551 | ||
bd0e5211 JR |
552 | return 0; |
553 | } | |
554 | ||
eb74ff6c JR |
555 | static void iommu_unmap_page(struct protection_domain *dom, |
556 | unsigned long bus_addr) | |
557 | { | |
38a76eee | 558 | u64 *pte = fetch_pte(dom, bus_addr); |
eb74ff6c | 559 | |
38a76eee JR |
560 | if (pte) |
561 | *pte = 0; | |
eb74ff6c | 562 | } |
eb74ff6c | 563 | |
431b2a20 JR |
564 | /* |
565 | * This function checks if a specific unity mapping entry is needed for | |
566 | * this specific IOMMU. | |
567 | */ | |
bd0e5211 JR |
568 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
569 | struct unity_map_entry *entry) | |
570 | { | |
571 | u16 bdf, i; | |
572 | ||
573 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
574 | bdf = amd_iommu_alias_table[i]; | |
575 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
576 | return 1; | |
577 | } | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
431b2a20 JR |
582 | /* |
583 | * Init the unity mappings for a specific IOMMU in the system | |
584 | * | |
585 | * Basically iterates over all unity mapping entries and applies them to | |
586 | * the default domain DMA of that IOMMU if necessary. | |
587 | */ | |
bd0e5211 JR |
588 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
589 | { | |
590 | struct unity_map_entry *entry; | |
591 | int ret; | |
592 | ||
593 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
594 | if (!iommu_for_unity_map(iommu, entry)) | |
595 | continue; | |
596 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
597 | if (ret) | |
598 | return ret; | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
431b2a20 JR |
604 | /* |
605 | * This function actually applies the mapping to the page table of the | |
606 | * dma_ops domain. | |
607 | */ | |
bd0e5211 JR |
608 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
609 | struct unity_map_entry *e) | |
610 | { | |
611 | u64 addr; | |
612 | int ret; | |
613 | ||
614 | for (addr = e->address_start; addr < e->address_end; | |
615 | addr += PAGE_SIZE) { | |
38e817fe | 616 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
617 | if (ret) |
618 | return ret; | |
619 | /* | |
620 | * if unity mapping is in aperture range mark the page | |
621 | * as allocated in the aperture | |
622 | */ | |
623 | if (addr < dma_dom->aperture_size) | |
c3239567 | 624 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 625 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
626 | } |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
431b2a20 JR |
631 | /* |
632 | * Inits the unity mappings required for a specific device | |
633 | */ | |
bd0e5211 JR |
634 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
635 | u16 devid) | |
636 | { | |
637 | struct unity_map_entry *e; | |
638 | int ret; | |
639 | ||
640 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
641 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
642 | continue; | |
643 | ret = dma_ops_unity_map(dma_dom, e); | |
644 | if (ret) | |
645 | return ret; | |
646 | } | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
431b2a20 JR |
651 | /**************************************************************************** |
652 | * | |
653 | * The next functions belong to the address allocator for the dma_ops | |
654 | * interface functions. They work like the allocators in the other IOMMU | |
655 | * drivers. Its basically a bitmap which marks the allocated pages in | |
656 | * the aperture. Maybe it could be enhanced in the future to a more | |
657 | * efficient allocator. | |
658 | * | |
659 | ****************************************************************************/ | |
d3086444 | 660 | |
431b2a20 | 661 | /* |
384de729 | 662 | * The address allocator core functions. |
431b2a20 JR |
663 | * |
664 | * called with domain->lock held | |
665 | */ | |
384de729 | 666 | |
00cd122a JR |
667 | /* |
668 | * This function checks if there is a PTE for a given dma address. If | |
669 | * there is one, it returns the pointer to it. | |
670 | */ | |
9355a081 | 671 | static u64 *fetch_pte(struct protection_domain *domain, |
00cd122a JR |
672 | unsigned long address) |
673 | { | |
9355a081 | 674 | int level; |
00cd122a JR |
675 | u64 *pte; |
676 | ||
9355a081 JR |
677 | level = domain->mode - 1; |
678 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 679 | |
9355a081 JR |
680 | while (level > 0) { |
681 | if (!IOMMU_PTE_PRESENT(*pte)) | |
682 | return NULL; | |
00cd122a | 683 | |
9355a081 | 684 | level -= 1; |
00cd122a | 685 | |
9355a081 JR |
686 | pte = IOMMU_PTE_PAGE(*pte); |
687 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
688 | } | |
00cd122a JR |
689 | |
690 | return pte; | |
691 | } | |
692 | ||
9cabe89b JR |
693 | /* |
694 | * This function is used to add a new aperture range to an existing | |
695 | * aperture in case of dma_ops domain allocation or address allocation | |
696 | * failure. | |
697 | */ | |
00cd122a JR |
698 | static int alloc_new_range(struct amd_iommu *iommu, |
699 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
700 | bool populate, gfp_t gfp) |
701 | { | |
702 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 703 | int i; |
9cabe89b | 704 | |
f5e9705c JR |
705 | #ifdef CONFIG_IOMMU_STRESS |
706 | populate = false; | |
707 | #endif | |
708 | ||
9cabe89b JR |
709 | if (index >= APERTURE_MAX_RANGES) |
710 | return -ENOMEM; | |
711 | ||
712 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
713 | if (!dma_dom->aperture[index]) | |
714 | return -ENOMEM; | |
715 | ||
716 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
717 | if (!dma_dom->aperture[index]->bitmap) | |
718 | goto out_free; | |
719 | ||
720 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
721 | ||
722 | if (populate) { | |
723 | unsigned long address = dma_dom->aperture_size; | |
724 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
725 | u64 *pte, *pte_page; | |
726 | ||
727 | for (i = 0; i < num_ptes; ++i) { | |
728 | pte = alloc_pte(&dma_dom->domain, address, | |
729 | &pte_page, gfp); | |
730 | if (!pte) | |
731 | goto out_free; | |
732 | ||
733 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
734 | ||
735 | address += APERTURE_RANGE_SIZE / 64; | |
736 | } | |
737 | } | |
738 | ||
739 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
740 | ||
00cd122a JR |
741 | /* Intialize the exclusion range if necessary */ |
742 | if (iommu->exclusion_start && | |
743 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
744 | iommu->exclusion_start < dma_dom->aperture_size) { | |
745 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
746 | int pages = iommu_num_pages(iommu->exclusion_start, | |
747 | iommu->exclusion_length, | |
748 | PAGE_SIZE); | |
749 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
750 | } | |
751 | ||
752 | /* | |
753 | * Check for areas already mapped as present in the new aperture | |
754 | * range and mark those pages as reserved in the allocator. Such | |
755 | * mappings may already exist as a result of requested unity | |
756 | * mappings for devices. | |
757 | */ | |
758 | for (i = dma_dom->aperture[index]->offset; | |
759 | i < dma_dom->aperture_size; | |
760 | i += PAGE_SIZE) { | |
761 | u64 *pte = fetch_pte(&dma_dom->domain, i); | |
762 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
763 | continue; | |
764 | ||
765 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
766 | } | |
767 | ||
04bfdd84 JR |
768 | update_domain(&dma_dom->domain); |
769 | ||
9cabe89b JR |
770 | return 0; |
771 | ||
772 | out_free: | |
04bfdd84 JR |
773 | update_domain(&dma_dom->domain); |
774 | ||
9cabe89b JR |
775 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
776 | ||
777 | kfree(dma_dom->aperture[index]); | |
778 | dma_dom->aperture[index] = NULL; | |
779 | ||
780 | return -ENOMEM; | |
781 | } | |
782 | ||
384de729 JR |
783 | static unsigned long dma_ops_area_alloc(struct device *dev, |
784 | struct dma_ops_domain *dom, | |
785 | unsigned int pages, | |
786 | unsigned long align_mask, | |
787 | u64 dma_mask, | |
788 | unsigned long start) | |
789 | { | |
803b8cb4 | 790 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
791 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
792 | int i = start >> APERTURE_RANGE_SHIFT; | |
793 | unsigned long boundary_size; | |
794 | unsigned long address = -1; | |
795 | unsigned long limit; | |
796 | ||
803b8cb4 JR |
797 | next_bit >>= PAGE_SHIFT; |
798 | ||
384de729 JR |
799 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
800 | PAGE_SIZE) >> PAGE_SHIFT; | |
801 | ||
802 | for (;i < max_index; ++i) { | |
803 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
804 | ||
805 | if (dom->aperture[i]->offset >= dma_mask) | |
806 | break; | |
807 | ||
808 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
809 | dma_mask >> PAGE_SHIFT); | |
810 | ||
811 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
812 | limit, next_bit, pages, 0, | |
813 | boundary_size, align_mask); | |
814 | if (address != -1) { | |
815 | address = dom->aperture[i]->offset + | |
816 | (address << PAGE_SHIFT); | |
803b8cb4 | 817 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
818 | break; |
819 | } | |
820 | ||
821 | next_bit = 0; | |
822 | } | |
823 | ||
824 | return address; | |
825 | } | |
826 | ||
d3086444 JR |
827 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
828 | struct dma_ops_domain *dom, | |
6d4f343f | 829 | unsigned int pages, |
832a90c3 JR |
830 | unsigned long align_mask, |
831 | u64 dma_mask) | |
d3086444 | 832 | { |
d3086444 | 833 | unsigned long address; |
d3086444 | 834 | |
fe16f088 JR |
835 | #ifdef CONFIG_IOMMU_STRESS |
836 | dom->next_address = 0; | |
837 | dom->need_flush = true; | |
838 | #endif | |
d3086444 | 839 | |
384de729 | 840 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 841 | dma_mask, dom->next_address); |
d3086444 | 842 | |
1c655773 | 843 | if (address == -1) { |
803b8cb4 | 844 | dom->next_address = 0; |
384de729 JR |
845 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
846 | dma_mask, 0); | |
1c655773 JR |
847 | dom->need_flush = true; |
848 | } | |
d3086444 | 849 | |
384de729 | 850 | if (unlikely(address == -1)) |
d3086444 JR |
851 | address = bad_dma_address; |
852 | ||
853 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
854 | ||
855 | return address; | |
856 | } | |
857 | ||
431b2a20 JR |
858 | /* |
859 | * The address free function. | |
860 | * | |
861 | * called with domain->lock held | |
862 | */ | |
d3086444 JR |
863 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
864 | unsigned long address, | |
865 | unsigned int pages) | |
866 | { | |
384de729 JR |
867 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
868 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 869 | |
384de729 JR |
870 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
871 | ||
47bccd6b JR |
872 | #ifdef CONFIG_IOMMU_STRESS |
873 | if (i < 4) | |
874 | return; | |
875 | #endif | |
80be308d | 876 | |
803b8cb4 | 877 | if (address >= dom->next_address) |
80be308d | 878 | dom->need_flush = true; |
384de729 JR |
879 | |
880 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 881 | |
384de729 JR |
882 | iommu_area_free(range->bitmap, address, pages); |
883 | ||
d3086444 JR |
884 | } |
885 | ||
431b2a20 JR |
886 | /**************************************************************************** |
887 | * | |
888 | * The next functions belong to the domain allocation. A domain is | |
889 | * allocated for every IOMMU as the default domain. If device isolation | |
890 | * is enabled, every device get its own domain. The most important thing | |
891 | * about domains is the page table mapping the DMA address space they | |
892 | * contain. | |
893 | * | |
894 | ****************************************************************************/ | |
895 | ||
ec487d1a JR |
896 | static u16 domain_id_alloc(void) |
897 | { | |
898 | unsigned long flags; | |
899 | int id; | |
900 | ||
901 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
902 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
903 | BUG_ON(id == 0); | |
904 | if (id > 0 && id < MAX_DOMAIN_ID) | |
905 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
906 | else | |
907 | id = 0; | |
908 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
909 | ||
910 | return id; | |
911 | } | |
912 | ||
a2acfb75 JR |
913 | static void domain_id_free(int id) |
914 | { | |
915 | unsigned long flags; | |
916 | ||
917 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
918 | if (id > 0 && id < MAX_DOMAIN_ID) | |
919 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
920 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
921 | } | |
a2acfb75 | 922 | |
431b2a20 JR |
923 | /* |
924 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
925 | * ranges. | |
926 | */ | |
ec487d1a JR |
927 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
928 | unsigned long start_page, | |
929 | unsigned int pages) | |
930 | { | |
384de729 | 931 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
932 | |
933 | if (start_page + pages > last_page) | |
934 | pages = last_page - start_page; | |
935 | ||
384de729 JR |
936 | for (i = start_page; i < start_page + pages; ++i) { |
937 | int index = i / APERTURE_RANGE_PAGES; | |
938 | int page = i % APERTURE_RANGE_PAGES; | |
939 | __set_bit(page, dom->aperture[index]->bitmap); | |
940 | } | |
ec487d1a JR |
941 | } |
942 | ||
86db2e5d | 943 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
944 | { |
945 | int i, j; | |
946 | u64 *p1, *p2, *p3; | |
947 | ||
86db2e5d | 948 | p1 = domain->pt_root; |
ec487d1a JR |
949 | |
950 | if (!p1) | |
951 | return; | |
952 | ||
953 | for (i = 0; i < 512; ++i) { | |
954 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
955 | continue; | |
956 | ||
957 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 958 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
959 | if (!IOMMU_PTE_PRESENT(p2[j])) |
960 | continue; | |
961 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
962 | free_page((unsigned long)p3); | |
963 | } | |
964 | ||
965 | free_page((unsigned long)p2); | |
966 | } | |
967 | ||
968 | free_page((unsigned long)p1); | |
86db2e5d JR |
969 | |
970 | domain->pt_root = NULL; | |
ec487d1a JR |
971 | } |
972 | ||
431b2a20 JR |
973 | /* |
974 | * Free a domain, only used if something went wrong in the | |
975 | * allocation path and we need to free an already allocated page table | |
976 | */ | |
ec487d1a JR |
977 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
978 | { | |
384de729 JR |
979 | int i; |
980 | ||
ec487d1a JR |
981 | if (!dom) |
982 | return; | |
983 | ||
86db2e5d | 984 | free_pagetable(&dom->domain); |
ec487d1a | 985 | |
384de729 JR |
986 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
987 | if (!dom->aperture[i]) | |
988 | continue; | |
989 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
990 | kfree(dom->aperture[i]); | |
991 | } | |
ec487d1a JR |
992 | |
993 | kfree(dom); | |
994 | } | |
995 | ||
431b2a20 JR |
996 | /* |
997 | * Allocates a new protection domain usable for the dma_ops functions. | |
998 | * It also intializes the page table and the address allocator data | |
999 | * structures required for the dma_ops interface | |
1000 | */ | |
d9cfed92 | 1001 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1002 | { |
1003 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1004 | |
1005 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1006 | if (!dma_dom) | |
1007 | return NULL; | |
1008 | ||
1009 | spin_lock_init(&dma_dom->domain.lock); | |
1010 | ||
1011 | dma_dom->domain.id = domain_id_alloc(); | |
1012 | if (dma_dom->domain.id == 0) | |
1013 | goto free_dma_dom; | |
1014 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
1015 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 1016 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1017 | dma_dom->domain.priv = dma_dom; |
1018 | if (!dma_dom->domain.pt_root) | |
1019 | goto free_dma_dom; | |
ec487d1a | 1020 | |
1c655773 | 1021 | dma_dom->need_flush = false; |
bd60b735 | 1022 | dma_dom->target_dev = 0xffff; |
1c655773 | 1023 | |
00cd122a | 1024 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1025 | goto free_dma_dom; |
ec487d1a | 1026 | |
431b2a20 | 1027 | /* |
ec487d1a JR |
1028 | * mark the first page as allocated so we never return 0 as |
1029 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1030 | */ |
384de729 | 1031 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1032 | dma_dom->next_address = 0; |
ec487d1a | 1033 | |
ec487d1a JR |
1034 | |
1035 | return dma_dom; | |
1036 | ||
1037 | free_dma_dom: | |
1038 | dma_ops_domain_free(dma_dom); | |
1039 | ||
1040 | return NULL; | |
1041 | } | |
1042 | ||
5b28df6f JR |
1043 | /* |
1044 | * little helper function to check whether a given protection domain is a | |
1045 | * dma_ops domain | |
1046 | */ | |
1047 | static bool dma_ops_domain(struct protection_domain *domain) | |
1048 | { | |
1049 | return domain->flags & PD_DMA_OPS_MASK; | |
1050 | } | |
1051 | ||
431b2a20 JR |
1052 | /* |
1053 | * Find out the protection domain structure for a given PCI device. This | |
1054 | * will give us the pointer to the page table root for example. | |
1055 | */ | |
b20ac0d4 JR |
1056 | static struct protection_domain *domain_for_device(u16 devid) |
1057 | { | |
1058 | struct protection_domain *dom; | |
1059 | unsigned long flags; | |
1060 | ||
1061 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1062 | dom = amd_iommu_pd_table[devid]; | |
1063 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1064 | ||
1065 | return dom; | |
1066 | } | |
1067 | ||
407d733e | 1068 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1069 | { |
b20ac0d4 | 1070 | u64 pte_root = virt_to_phys(domain->pt_root); |
407d733e | 1071 | unsigned long flags; |
863c74eb | 1072 | |
38ddf41b JR |
1073 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1074 | << DEV_ENTRY_MODE_SHIFT; | |
1075 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
1076 | |
1077 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
1078 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
1079 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
1080 | amd_iommu_dev_table[devid].data[2] = domain->id; |
1081 | ||
1082 | amd_iommu_pd_table[devid] = domain; | |
1083 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
407d733e JR |
1084 | } |
1085 | ||
1086 | /* | |
1087 | * If a device is not yet associated with a domain, this function does | |
1088 | * assigns it visible for the hardware | |
1089 | */ | |
1090 | static void attach_device(struct amd_iommu *iommu, | |
1091 | struct protection_domain *domain, | |
1092 | u16 devid) | |
1093 | { | |
1094 | /* set the DTE entry */ | |
1095 | set_dte_entry(devid, domain); | |
1096 | ||
1097 | /* increase reference counter */ | |
1098 | domain->dev_cnt += 1; | |
b20ac0d4 | 1099 | |
42a49f96 CW |
1100 | /* |
1101 | * We might boot into a crash-kernel here. The crashed kernel | |
1102 | * left the caches in the IOMMU dirty. So we have to flush | |
1103 | * here to evict all dirty stuff. | |
1104 | */ | |
b20ac0d4 | 1105 | iommu_queue_inv_dev_entry(iommu, devid); |
42a49f96 | 1106 | iommu_flush_tlb_pde(iommu, domain->id); |
b20ac0d4 JR |
1107 | } |
1108 | ||
355bf553 JR |
1109 | /* |
1110 | * Removes a device from a protection domain (unlocked) | |
1111 | */ | |
1112 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1113 | { | |
1114 | ||
1115 | /* lock domain */ | |
1116 | spin_lock(&domain->lock); | |
1117 | ||
1118 | /* remove domain from the lookup table */ | |
1119 | amd_iommu_pd_table[devid] = NULL; | |
1120 | ||
1121 | /* remove entry from the device table seen by the hardware */ | |
1122 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1123 | amd_iommu_dev_table[devid].data[1] = 0; | |
1124 | amd_iommu_dev_table[devid].data[2] = 0; | |
1125 | ||
1126 | /* decrease reference counter */ | |
1127 | domain->dev_cnt -= 1; | |
1128 | ||
1129 | /* ready */ | |
1130 | spin_unlock(&domain->lock); | |
1131 | } | |
1132 | ||
1133 | /* | |
1134 | * Removes a device from a protection domain (with devtable_lock held) | |
1135 | */ | |
1136 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1137 | { | |
1138 | unsigned long flags; | |
1139 | ||
1140 | /* lock device table */ | |
1141 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1142 | __detach_device(domain, devid); | |
1143 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1144 | } | |
e275a2a0 JR |
1145 | |
1146 | static int device_change_notifier(struct notifier_block *nb, | |
1147 | unsigned long action, void *data) | |
1148 | { | |
1149 | struct device *dev = data; | |
1150 | struct pci_dev *pdev = to_pci_dev(dev); | |
1151 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1152 | struct protection_domain *domain; | |
1153 | struct dma_ops_domain *dma_domain; | |
1154 | struct amd_iommu *iommu; | |
1ac4cbbc | 1155 | unsigned long flags; |
e275a2a0 JR |
1156 | |
1157 | if (devid > amd_iommu_last_bdf) | |
1158 | goto out; | |
1159 | ||
1160 | devid = amd_iommu_alias_table[devid]; | |
1161 | ||
1162 | iommu = amd_iommu_rlookup_table[devid]; | |
1163 | if (iommu == NULL) | |
1164 | goto out; | |
1165 | ||
1166 | domain = domain_for_device(devid); | |
1167 | ||
1168 | if (domain && !dma_ops_domain(domain)) | |
1169 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1170 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1171 | ||
1172 | switch (action) { | |
c1eee67b | 1173 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1174 | if (!domain) |
1175 | goto out; | |
1176 | detach_device(domain, devid); | |
1ac4cbbc JR |
1177 | break; |
1178 | case BUS_NOTIFY_ADD_DEVICE: | |
1179 | /* allocate a protection domain if a device is added */ | |
1180 | dma_domain = find_protection_domain(devid); | |
1181 | if (dma_domain) | |
1182 | goto out; | |
d9cfed92 | 1183 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1184 | if (!dma_domain) |
1185 | goto out; | |
1186 | dma_domain->target_dev = devid; | |
1187 | ||
1188 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1189 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1190 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1191 | ||
e275a2a0 JR |
1192 | break; |
1193 | default: | |
1194 | goto out; | |
1195 | } | |
1196 | ||
1197 | iommu_queue_inv_dev_entry(iommu, devid); | |
1198 | iommu_completion_wait(iommu); | |
1199 | ||
1200 | out: | |
1201 | return 0; | |
1202 | } | |
1203 | ||
b25ae679 | 1204 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1205 | .notifier_call = device_change_notifier, |
1206 | }; | |
355bf553 | 1207 | |
431b2a20 JR |
1208 | /***************************************************************************** |
1209 | * | |
1210 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1211 | * | |
1212 | *****************************************************************************/ | |
1213 | ||
dbcc112e JR |
1214 | /* |
1215 | * This function checks if the driver got a valid device from the caller to | |
1216 | * avoid dereferencing invalid pointers. | |
1217 | */ | |
1218 | static bool check_device(struct device *dev) | |
1219 | { | |
1220 | if (!dev || !dev->dma_mask) | |
1221 | return false; | |
1222 | ||
1223 | return true; | |
1224 | } | |
1225 | ||
bd60b735 JR |
1226 | /* |
1227 | * In this function the list of preallocated protection domains is traversed to | |
1228 | * find the domain for a specific device | |
1229 | */ | |
1230 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1231 | { | |
1232 | struct dma_ops_domain *entry, *ret = NULL; | |
1233 | unsigned long flags; | |
1234 | ||
1235 | if (list_empty(&iommu_pd_list)) | |
1236 | return NULL; | |
1237 | ||
1238 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1239 | ||
1240 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1241 | if (entry->target_dev == devid) { | |
1242 | ret = entry; | |
bd60b735 JR |
1243 | break; |
1244 | } | |
1245 | } | |
1246 | ||
1247 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1248 | ||
1249 | return ret; | |
1250 | } | |
1251 | ||
431b2a20 JR |
1252 | /* |
1253 | * In the dma_ops path we only have the struct device. This function | |
1254 | * finds the corresponding IOMMU, the protection domain and the | |
1255 | * requestor id for a given device. | |
1256 | * If the device is not yet associated with a domain this is also done | |
1257 | * in this function. | |
1258 | */ | |
b20ac0d4 JR |
1259 | static int get_device_resources(struct device *dev, |
1260 | struct amd_iommu **iommu, | |
1261 | struct protection_domain **domain, | |
1262 | u16 *bdf) | |
1263 | { | |
1264 | struct dma_ops_domain *dma_dom; | |
1265 | struct pci_dev *pcidev; | |
1266 | u16 _bdf; | |
1267 | ||
dbcc112e JR |
1268 | *iommu = NULL; |
1269 | *domain = NULL; | |
1270 | *bdf = 0xffff; | |
1271 | ||
1272 | if (dev->bus != &pci_bus_type) | |
1273 | return 0; | |
b20ac0d4 JR |
1274 | |
1275 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1276 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1277 | |
431b2a20 | 1278 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1279 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1280 | return 0; |
b20ac0d4 JR |
1281 | |
1282 | *bdf = amd_iommu_alias_table[_bdf]; | |
1283 | ||
1284 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1285 | if (*iommu == NULL) | |
1286 | return 0; | |
b20ac0d4 JR |
1287 | *domain = domain_for_device(*bdf); |
1288 | if (*domain == NULL) { | |
bd60b735 JR |
1289 | dma_dom = find_protection_domain(*bdf); |
1290 | if (!dma_dom) | |
1291 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1292 | *domain = &dma_dom->domain; |
f1179dc0 | 1293 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1294 | DUMP_printk("Using protection domain %d for device %s\n", |
1295 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1296 | } |
1297 | ||
f91ba190 | 1298 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1299 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1300 | |
b20ac0d4 JR |
1301 | return 1; |
1302 | } | |
1303 | ||
04bfdd84 JR |
1304 | static void update_device_table(struct protection_domain *domain) |
1305 | { | |
1306 | int i; | |
1307 | ||
1308 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
1309 | if (amd_iommu_pd_table[i] != domain) | |
1310 | continue; | |
1311 | set_dte_entry(i, domain); | |
1312 | } | |
1313 | } | |
1314 | ||
1315 | static void update_domain(struct protection_domain *domain) | |
1316 | { | |
1317 | if (!domain->updated) | |
1318 | return; | |
1319 | ||
1320 | update_device_table(domain); | |
1321 | flush_devices_by_domain(domain); | |
1322 | iommu_flush_domain(domain->id); | |
1323 | ||
1324 | domain->updated = false; | |
1325 | } | |
1326 | ||
50020fb6 JR |
1327 | /* |
1328 | * This function is used to add another level to an IO page table. Adding | |
1329 | * another level increases the size of the address space by 9 bits to a size up | |
1330 | * to 64 bits. | |
1331 | */ | |
1332 | static bool increase_address_space(struct protection_domain *domain, | |
1333 | gfp_t gfp) | |
1334 | { | |
1335 | u64 *pte; | |
1336 | ||
1337 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1338 | /* address space already 64 bit large */ | |
1339 | return false; | |
1340 | ||
1341 | pte = (void *)get_zeroed_page(gfp); | |
1342 | if (!pte) | |
1343 | return false; | |
1344 | ||
1345 | *pte = PM_LEVEL_PDE(domain->mode, | |
1346 | virt_to_phys(domain->pt_root)); | |
1347 | domain->pt_root = pte; | |
1348 | domain->mode += 1; | |
1349 | domain->updated = true; | |
1350 | ||
1351 | return true; | |
1352 | } | |
1353 | ||
8bc3e127 | 1354 | static u64 *alloc_pte(struct protection_domain *domain, |
8bda3092 JR |
1355 | unsigned long address, u64 **pte_page, gfp_t gfp) |
1356 | { | |
1357 | u64 *pte, *page; | |
8bc3e127 | 1358 | int level; |
8bda3092 | 1359 | |
8bc3e127 JR |
1360 | while (address > PM_LEVEL_SIZE(domain->mode)) |
1361 | increase_address_space(domain, gfp); | |
8bda3092 | 1362 | |
8bc3e127 JR |
1363 | level = domain->mode - 1; |
1364 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
8bda3092 | 1365 | |
8bc3e127 JR |
1366 | while (level > 0) { |
1367 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1368 | page = (u64 *)get_zeroed_page(gfp); | |
1369 | if (!page) | |
1370 | return NULL; | |
1371 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1372 | } | |
8bda3092 | 1373 | |
8bc3e127 | 1374 | level -= 1; |
8bda3092 | 1375 | |
8bc3e127 | 1376 | pte = IOMMU_PTE_PAGE(*pte); |
8bda3092 | 1377 | |
8bc3e127 JR |
1378 | if (pte_page && level == 0) |
1379 | *pte_page = pte; | |
8bda3092 | 1380 | |
8bc3e127 JR |
1381 | pte = &pte[PM_LEVEL_INDEX(level, address)]; |
1382 | } | |
8bda3092 JR |
1383 | |
1384 | return pte; | |
1385 | } | |
1386 | ||
1387 | /* | |
1388 | * This function fetches the PTE for a given address in the aperture | |
1389 | */ | |
1390 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1391 | unsigned long address) | |
1392 | { | |
384de729 | 1393 | struct aperture_range *aperture; |
8bda3092 JR |
1394 | u64 *pte, *pte_page; |
1395 | ||
384de729 JR |
1396 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1397 | if (!aperture) | |
1398 | return NULL; | |
1399 | ||
1400 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 JR |
1401 | if (!pte) { |
1402 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
384de729 JR |
1403 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1404 | } else | |
1405 | pte += IOMMU_PTE_L0_INDEX(address); | |
8bda3092 | 1406 | |
04bfdd84 JR |
1407 | update_domain(&dom->domain); |
1408 | ||
8bda3092 JR |
1409 | return pte; |
1410 | } | |
1411 | ||
431b2a20 JR |
1412 | /* |
1413 | * This is the generic map function. It maps one 4kb page at paddr to | |
1414 | * the given address in the DMA address space for the domain. | |
1415 | */ | |
cb76c322 JR |
1416 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1417 | struct dma_ops_domain *dom, | |
1418 | unsigned long address, | |
1419 | phys_addr_t paddr, | |
1420 | int direction) | |
1421 | { | |
1422 | u64 *pte, __pte; | |
1423 | ||
1424 | WARN_ON(address > dom->aperture_size); | |
1425 | ||
1426 | paddr &= PAGE_MASK; | |
1427 | ||
8bda3092 | 1428 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1429 | if (!pte) |
1430 | return bad_dma_address; | |
cb76c322 JR |
1431 | |
1432 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1433 | ||
1434 | if (direction == DMA_TO_DEVICE) | |
1435 | __pte |= IOMMU_PTE_IR; | |
1436 | else if (direction == DMA_FROM_DEVICE) | |
1437 | __pte |= IOMMU_PTE_IW; | |
1438 | else if (direction == DMA_BIDIRECTIONAL) | |
1439 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1440 | ||
1441 | WARN_ON(*pte); | |
1442 | ||
1443 | *pte = __pte; | |
1444 | ||
1445 | return (dma_addr_t)address; | |
1446 | } | |
1447 | ||
431b2a20 JR |
1448 | /* |
1449 | * The generic unmapping function for on page in the DMA address space. | |
1450 | */ | |
cb76c322 JR |
1451 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1452 | struct dma_ops_domain *dom, | |
1453 | unsigned long address) | |
1454 | { | |
384de729 | 1455 | struct aperture_range *aperture; |
cb76c322 JR |
1456 | u64 *pte; |
1457 | ||
1458 | if (address >= dom->aperture_size) | |
1459 | return; | |
1460 | ||
384de729 JR |
1461 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1462 | if (!aperture) | |
1463 | return; | |
1464 | ||
1465 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1466 | if (!pte) | |
1467 | return; | |
cb76c322 | 1468 | |
cb76c322 JR |
1469 | pte += IOMMU_PTE_L0_INDEX(address); |
1470 | ||
1471 | WARN_ON(!*pte); | |
1472 | ||
1473 | *pte = 0ULL; | |
1474 | } | |
1475 | ||
431b2a20 JR |
1476 | /* |
1477 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1478 | * contiguous memory region into DMA address space. It is used by all |
1479 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1480 | * Must be called with the domain lock held. |
1481 | */ | |
cb76c322 JR |
1482 | static dma_addr_t __map_single(struct device *dev, |
1483 | struct amd_iommu *iommu, | |
1484 | struct dma_ops_domain *dma_dom, | |
1485 | phys_addr_t paddr, | |
1486 | size_t size, | |
6d4f343f | 1487 | int dir, |
832a90c3 JR |
1488 | bool align, |
1489 | u64 dma_mask) | |
cb76c322 JR |
1490 | { |
1491 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1492 | dma_addr_t address, start, ret; |
cb76c322 | 1493 | unsigned int pages; |
6d4f343f | 1494 | unsigned long align_mask = 0; |
cb76c322 JR |
1495 | int i; |
1496 | ||
e3c449f5 | 1497 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1498 | paddr &= PAGE_MASK; |
1499 | ||
8ecaf8f1 JR |
1500 | INC_STATS_COUNTER(total_map_requests); |
1501 | ||
c1858976 JR |
1502 | if (pages > 1) |
1503 | INC_STATS_COUNTER(cross_page); | |
1504 | ||
6d4f343f JR |
1505 | if (align) |
1506 | align_mask = (1UL << get_order(size)) - 1; | |
1507 | ||
11b83888 | 1508 | retry: |
832a90c3 JR |
1509 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1510 | dma_mask); | |
11b83888 JR |
1511 | if (unlikely(address == bad_dma_address)) { |
1512 | /* | |
1513 | * setting next_address here will let the address | |
1514 | * allocator only scan the new allocated range in the | |
1515 | * first run. This is a small optimization. | |
1516 | */ | |
1517 | dma_dom->next_address = dma_dom->aperture_size; | |
1518 | ||
1519 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1520 | goto out; | |
1521 | ||
1522 | /* | |
1523 | * aperture was sucessfully enlarged by 128 MB, try | |
1524 | * allocation again | |
1525 | */ | |
1526 | goto retry; | |
1527 | } | |
cb76c322 JR |
1528 | |
1529 | start = address; | |
1530 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1531 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1532 | if (ret == bad_dma_address) | |
1533 | goto out_unmap; | |
1534 | ||
cb76c322 JR |
1535 | paddr += PAGE_SIZE; |
1536 | start += PAGE_SIZE; | |
1537 | } | |
1538 | address += offset; | |
1539 | ||
5774f7c5 JR |
1540 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1541 | ||
afa9fdc2 | 1542 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1543 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1544 | dma_dom->need_flush = false; | |
1545 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1546 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1547 | ||
cb76c322 JR |
1548 | out: |
1549 | return address; | |
53812c11 JR |
1550 | |
1551 | out_unmap: | |
1552 | ||
1553 | for (--i; i >= 0; --i) { | |
1554 | start -= PAGE_SIZE; | |
1555 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1556 | } | |
1557 | ||
1558 | dma_ops_free_addresses(dma_dom, address, pages); | |
1559 | ||
1560 | return bad_dma_address; | |
cb76c322 JR |
1561 | } |
1562 | ||
431b2a20 JR |
1563 | /* |
1564 | * Does the reverse of the __map_single function. Must be called with | |
1565 | * the domain lock held too | |
1566 | */ | |
cb76c322 JR |
1567 | static void __unmap_single(struct amd_iommu *iommu, |
1568 | struct dma_ops_domain *dma_dom, | |
1569 | dma_addr_t dma_addr, | |
1570 | size_t size, | |
1571 | int dir) | |
1572 | { | |
1573 | dma_addr_t i, start; | |
1574 | unsigned int pages; | |
1575 | ||
b8d9905d JR |
1576 | if ((dma_addr == bad_dma_address) || |
1577 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1578 | return; |
1579 | ||
e3c449f5 | 1580 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1581 | dma_addr &= PAGE_MASK; |
1582 | start = dma_addr; | |
1583 | ||
1584 | for (i = 0; i < pages; ++i) { | |
1585 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1586 | start += PAGE_SIZE; | |
1587 | } | |
1588 | ||
5774f7c5 JR |
1589 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1590 | ||
cb76c322 | 1591 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1592 | |
80be308d | 1593 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1594 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1595 | dma_dom->need_flush = false; |
1596 | } | |
cb76c322 JR |
1597 | } |
1598 | ||
431b2a20 JR |
1599 | /* |
1600 | * The exported map_single function for dma_ops. | |
1601 | */ | |
51491367 FT |
1602 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1603 | unsigned long offset, size_t size, | |
1604 | enum dma_data_direction dir, | |
1605 | struct dma_attrs *attrs) | |
4da70b9e JR |
1606 | { |
1607 | unsigned long flags; | |
1608 | struct amd_iommu *iommu; | |
1609 | struct protection_domain *domain; | |
1610 | u16 devid; | |
1611 | dma_addr_t addr; | |
832a90c3 | 1612 | u64 dma_mask; |
51491367 | 1613 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1614 | |
0f2a86f2 JR |
1615 | INC_STATS_COUNTER(cnt_map_single); |
1616 | ||
dbcc112e JR |
1617 | if (!check_device(dev)) |
1618 | return bad_dma_address; | |
1619 | ||
832a90c3 | 1620 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1621 | |
1622 | get_device_resources(dev, &iommu, &domain, &devid); | |
1623 | ||
1624 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1625 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1626 | return (dma_addr_t)paddr; |
1627 | ||
5b28df6f JR |
1628 | if (!dma_ops_domain(domain)) |
1629 | return bad_dma_address; | |
1630 | ||
4da70b9e | 1631 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1632 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1633 | dma_mask); | |
4da70b9e JR |
1634 | if (addr == bad_dma_address) |
1635 | goto out; | |
1636 | ||
09ee17eb | 1637 | iommu_completion_wait(iommu); |
4da70b9e JR |
1638 | |
1639 | out: | |
1640 | spin_unlock_irqrestore(&domain->lock, flags); | |
1641 | ||
1642 | return addr; | |
1643 | } | |
1644 | ||
431b2a20 JR |
1645 | /* |
1646 | * The exported unmap_single function for dma_ops. | |
1647 | */ | |
51491367 FT |
1648 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1649 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1650 | { |
1651 | unsigned long flags; | |
1652 | struct amd_iommu *iommu; | |
1653 | struct protection_domain *domain; | |
1654 | u16 devid; | |
1655 | ||
146a6917 JR |
1656 | INC_STATS_COUNTER(cnt_unmap_single); |
1657 | ||
dbcc112e JR |
1658 | if (!check_device(dev) || |
1659 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1660 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1661 | return; |
1662 | ||
5b28df6f JR |
1663 | if (!dma_ops_domain(domain)) |
1664 | return; | |
1665 | ||
4da70b9e JR |
1666 | spin_lock_irqsave(&domain->lock, flags); |
1667 | ||
1668 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1669 | ||
09ee17eb | 1670 | iommu_completion_wait(iommu); |
4da70b9e JR |
1671 | |
1672 | spin_unlock_irqrestore(&domain->lock, flags); | |
1673 | } | |
1674 | ||
431b2a20 JR |
1675 | /* |
1676 | * This is a special map_sg function which is used if we should map a | |
1677 | * device which is not handled by an AMD IOMMU in the system. | |
1678 | */ | |
65b050ad JR |
1679 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1680 | int nelems, int dir) | |
1681 | { | |
1682 | struct scatterlist *s; | |
1683 | int i; | |
1684 | ||
1685 | for_each_sg(sglist, s, nelems, i) { | |
1686 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1687 | s->dma_length = s->length; | |
1688 | } | |
1689 | ||
1690 | return nelems; | |
1691 | } | |
1692 | ||
431b2a20 JR |
1693 | /* |
1694 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1695 | * lists). | |
1696 | */ | |
65b050ad | 1697 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1698 | int nelems, enum dma_data_direction dir, |
1699 | struct dma_attrs *attrs) | |
65b050ad JR |
1700 | { |
1701 | unsigned long flags; | |
1702 | struct amd_iommu *iommu; | |
1703 | struct protection_domain *domain; | |
1704 | u16 devid; | |
1705 | int i; | |
1706 | struct scatterlist *s; | |
1707 | phys_addr_t paddr; | |
1708 | int mapped_elems = 0; | |
832a90c3 | 1709 | u64 dma_mask; |
65b050ad | 1710 | |
d03f067a JR |
1711 | INC_STATS_COUNTER(cnt_map_sg); |
1712 | ||
dbcc112e JR |
1713 | if (!check_device(dev)) |
1714 | return 0; | |
1715 | ||
832a90c3 | 1716 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1717 | |
1718 | get_device_resources(dev, &iommu, &domain, &devid); | |
1719 | ||
1720 | if (!iommu || !domain) | |
1721 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1722 | ||
5b28df6f JR |
1723 | if (!dma_ops_domain(domain)) |
1724 | return 0; | |
1725 | ||
65b050ad JR |
1726 | spin_lock_irqsave(&domain->lock, flags); |
1727 | ||
1728 | for_each_sg(sglist, s, nelems, i) { | |
1729 | paddr = sg_phys(s); | |
1730 | ||
1731 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1732 | paddr, s->length, dir, false, |
1733 | dma_mask); | |
65b050ad JR |
1734 | |
1735 | if (s->dma_address) { | |
1736 | s->dma_length = s->length; | |
1737 | mapped_elems++; | |
1738 | } else | |
1739 | goto unmap; | |
65b050ad JR |
1740 | } |
1741 | ||
09ee17eb | 1742 | iommu_completion_wait(iommu); |
65b050ad JR |
1743 | |
1744 | out: | |
1745 | spin_unlock_irqrestore(&domain->lock, flags); | |
1746 | ||
1747 | return mapped_elems; | |
1748 | unmap: | |
1749 | for_each_sg(sglist, s, mapped_elems, i) { | |
1750 | if (s->dma_address) | |
1751 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1752 | s->dma_length, dir); | |
1753 | s->dma_address = s->dma_length = 0; | |
1754 | } | |
1755 | ||
1756 | mapped_elems = 0; | |
1757 | ||
1758 | goto out; | |
1759 | } | |
1760 | ||
431b2a20 JR |
1761 | /* |
1762 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1763 | * lists). | |
1764 | */ | |
65b050ad | 1765 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1766 | int nelems, enum dma_data_direction dir, |
1767 | struct dma_attrs *attrs) | |
65b050ad JR |
1768 | { |
1769 | unsigned long flags; | |
1770 | struct amd_iommu *iommu; | |
1771 | struct protection_domain *domain; | |
1772 | struct scatterlist *s; | |
1773 | u16 devid; | |
1774 | int i; | |
1775 | ||
55877a6b JR |
1776 | INC_STATS_COUNTER(cnt_unmap_sg); |
1777 | ||
dbcc112e JR |
1778 | if (!check_device(dev) || |
1779 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1780 | return; |
1781 | ||
5b28df6f JR |
1782 | if (!dma_ops_domain(domain)) |
1783 | return; | |
1784 | ||
65b050ad JR |
1785 | spin_lock_irqsave(&domain->lock, flags); |
1786 | ||
1787 | for_each_sg(sglist, s, nelems, i) { | |
1788 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1789 | s->dma_length, dir); | |
65b050ad JR |
1790 | s->dma_address = s->dma_length = 0; |
1791 | } | |
1792 | ||
09ee17eb | 1793 | iommu_completion_wait(iommu); |
65b050ad JR |
1794 | |
1795 | spin_unlock_irqrestore(&domain->lock, flags); | |
1796 | } | |
1797 | ||
431b2a20 JR |
1798 | /* |
1799 | * The exported alloc_coherent function for dma_ops. | |
1800 | */ | |
5d8b53cf JR |
1801 | static void *alloc_coherent(struct device *dev, size_t size, |
1802 | dma_addr_t *dma_addr, gfp_t flag) | |
1803 | { | |
1804 | unsigned long flags; | |
1805 | void *virt_addr; | |
1806 | struct amd_iommu *iommu; | |
1807 | struct protection_domain *domain; | |
1808 | u16 devid; | |
1809 | phys_addr_t paddr; | |
832a90c3 | 1810 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1811 | |
c8f0fb36 JR |
1812 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1813 | ||
dbcc112e JR |
1814 | if (!check_device(dev)) |
1815 | return NULL; | |
5d8b53cf | 1816 | |
13d9fead FT |
1817 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1818 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1819 | |
c97ac535 | 1820 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1821 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1822 | if (!virt_addr) | |
b25ae679 | 1823 | return NULL; |
5d8b53cf | 1824 | |
5d8b53cf JR |
1825 | paddr = virt_to_phys(virt_addr); |
1826 | ||
5d8b53cf JR |
1827 | if (!iommu || !domain) { |
1828 | *dma_addr = (dma_addr_t)paddr; | |
1829 | return virt_addr; | |
1830 | } | |
1831 | ||
5b28df6f JR |
1832 | if (!dma_ops_domain(domain)) |
1833 | goto out_free; | |
1834 | ||
832a90c3 JR |
1835 | if (!dma_mask) |
1836 | dma_mask = *dev->dma_mask; | |
1837 | ||
5d8b53cf JR |
1838 | spin_lock_irqsave(&domain->lock, flags); |
1839 | ||
1840 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1841 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1842 | |
367d04c4 JS |
1843 | if (*dma_addr == bad_dma_address) { |
1844 | spin_unlock_irqrestore(&domain->lock, flags); | |
5b28df6f | 1845 | goto out_free; |
367d04c4 | 1846 | } |
5d8b53cf | 1847 | |
09ee17eb | 1848 | iommu_completion_wait(iommu); |
5d8b53cf | 1849 | |
5d8b53cf JR |
1850 | spin_unlock_irqrestore(&domain->lock, flags); |
1851 | ||
1852 | return virt_addr; | |
5b28df6f JR |
1853 | |
1854 | out_free: | |
1855 | ||
1856 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1857 | ||
1858 | return NULL; | |
5d8b53cf JR |
1859 | } |
1860 | ||
431b2a20 JR |
1861 | /* |
1862 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1863 | */ |
5d8b53cf JR |
1864 | static void free_coherent(struct device *dev, size_t size, |
1865 | void *virt_addr, dma_addr_t dma_addr) | |
1866 | { | |
1867 | unsigned long flags; | |
1868 | struct amd_iommu *iommu; | |
1869 | struct protection_domain *domain; | |
1870 | u16 devid; | |
1871 | ||
5d31ee7e JR |
1872 | INC_STATS_COUNTER(cnt_free_coherent); |
1873 | ||
dbcc112e JR |
1874 | if (!check_device(dev)) |
1875 | return; | |
1876 | ||
5d8b53cf JR |
1877 | get_device_resources(dev, &iommu, &domain, &devid); |
1878 | ||
1879 | if (!iommu || !domain) | |
1880 | goto free_mem; | |
1881 | ||
5b28df6f JR |
1882 | if (!dma_ops_domain(domain)) |
1883 | goto free_mem; | |
1884 | ||
5d8b53cf JR |
1885 | spin_lock_irqsave(&domain->lock, flags); |
1886 | ||
1887 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1888 | |
09ee17eb | 1889 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1890 | |
1891 | spin_unlock_irqrestore(&domain->lock, flags); | |
1892 | ||
1893 | free_mem: | |
1894 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1895 | } | |
1896 | ||
b39ba6ad JR |
1897 | /* |
1898 | * This function is called by the DMA layer to find out if we can handle a | |
1899 | * particular device. It is part of the dma_ops. | |
1900 | */ | |
1901 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1902 | { | |
1903 | u16 bdf; | |
1904 | struct pci_dev *pcidev; | |
1905 | ||
1906 | /* No device or no PCI device */ | |
1907 | if (!dev || dev->bus != &pci_bus_type) | |
1908 | return 0; | |
1909 | ||
1910 | pcidev = to_pci_dev(dev); | |
1911 | ||
1912 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1913 | ||
1914 | /* Out of our scope? */ | |
1915 | if (bdf > amd_iommu_last_bdf) | |
1916 | return 0; | |
1917 | ||
1918 | return 1; | |
1919 | } | |
1920 | ||
c432f3df | 1921 | /* |
431b2a20 JR |
1922 | * The function for pre-allocating protection domains. |
1923 | * | |
c432f3df JR |
1924 | * If the driver core informs the DMA layer if a driver grabs a device |
1925 | * we don't need to preallocate the protection domains anymore. | |
1926 | * For now we have to. | |
1927 | */ | |
0e93dd88 | 1928 | static void prealloc_protection_domains(void) |
c432f3df JR |
1929 | { |
1930 | struct pci_dev *dev = NULL; | |
1931 | struct dma_ops_domain *dma_dom; | |
1932 | struct amd_iommu *iommu; | |
c432f3df JR |
1933 | u16 devid; |
1934 | ||
1935 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1936 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1937 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1938 | continue; |
1939 | devid = amd_iommu_alias_table[devid]; | |
1940 | if (domain_for_device(devid)) | |
1941 | continue; | |
1942 | iommu = amd_iommu_rlookup_table[devid]; | |
1943 | if (!iommu) | |
1944 | continue; | |
d9cfed92 | 1945 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
1946 | if (!dma_dom) |
1947 | continue; | |
1948 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1949 | dma_dom->target_dev = devid; |
1950 | ||
1951 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1952 | } |
1953 | } | |
1954 | ||
160c1d8e | 1955 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1956 | .alloc_coherent = alloc_coherent, |
1957 | .free_coherent = free_coherent, | |
51491367 FT |
1958 | .map_page = map_page, |
1959 | .unmap_page = unmap_page, | |
6631ee9d JR |
1960 | .map_sg = map_sg, |
1961 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1962 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1963 | }; |
1964 | ||
431b2a20 JR |
1965 | /* |
1966 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1967 | */ | |
6631ee9d JR |
1968 | int __init amd_iommu_init_dma_ops(void) |
1969 | { | |
1970 | struct amd_iommu *iommu; | |
6631ee9d JR |
1971 | int ret; |
1972 | ||
431b2a20 JR |
1973 | /* |
1974 | * first allocate a default protection domain for every IOMMU we | |
1975 | * found in the system. Devices not assigned to any other | |
1976 | * protection domain will be assigned to the default one. | |
1977 | */ | |
3bd22172 | 1978 | for_each_iommu(iommu) { |
d9cfed92 | 1979 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
1980 | if (iommu->default_dom == NULL) |
1981 | return -ENOMEM; | |
e2dc14a2 | 1982 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1983 | ret = iommu_init_unity_mappings(iommu); |
1984 | if (ret) | |
1985 | goto free_domains; | |
1986 | } | |
1987 | ||
431b2a20 JR |
1988 | /* |
1989 | * If device isolation is enabled, pre-allocate the protection | |
1990 | * domains for each device. | |
1991 | */ | |
6631ee9d JR |
1992 | if (amd_iommu_isolate) |
1993 | prealloc_protection_domains(); | |
1994 | ||
1995 | iommu_detected = 1; | |
1996 | force_iommu = 1; | |
1997 | bad_dma_address = 0; | |
92af4e29 | 1998 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1999 | gart_iommu_aperture_disabled = 1; |
2000 | gart_iommu_aperture = 0; | |
92af4e29 | 2001 | #endif |
6631ee9d | 2002 | |
431b2a20 | 2003 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2004 | dma_ops = &amd_iommu_dma_ops; |
2005 | ||
26961efe | 2006 | register_iommu(&amd_iommu_ops); |
26961efe | 2007 | |
e275a2a0 JR |
2008 | bus_register_notifier(&pci_bus_type, &device_nb); |
2009 | ||
7f26508b JR |
2010 | amd_iommu_stats_init(); |
2011 | ||
6631ee9d JR |
2012 | return 0; |
2013 | ||
2014 | free_domains: | |
2015 | ||
3bd22172 | 2016 | for_each_iommu(iommu) { |
6631ee9d JR |
2017 | if (iommu->default_dom) |
2018 | dma_ops_domain_free(iommu->default_dom); | |
2019 | } | |
2020 | ||
2021 | return ret; | |
2022 | } | |
6d98cd80 JR |
2023 | |
2024 | /***************************************************************************** | |
2025 | * | |
2026 | * The following functions belong to the exported interface of AMD IOMMU | |
2027 | * | |
2028 | * This interface allows access to lower level functions of the IOMMU | |
2029 | * like protection domain handling and assignement of devices to domains | |
2030 | * which is not possible with the dma_ops interface. | |
2031 | * | |
2032 | *****************************************************************************/ | |
2033 | ||
6d98cd80 JR |
2034 | static void cleanup_domain(struct protection_domain *domain) |
2035 | { | |
2036 | unsigned long flags; | |
2037 | u16 devid; | |
2038 | ||
2039 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2040 | ||
2041 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2042 | if (amd_iommu_pd_table[devid] == domain) | |
2043 | __detach_device(domain, devid); | |
2044 | ||
2045 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2046 | } | |
2047 | ||
c156e347 JR |
2048 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
2049 | { | |
2050 | struct protection_domain *domain; | |
2051 | ||
2052 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2053 | if (!domain) | |
2054 | return -ENOMEM; | |
2055 | ||
2056 | spin_lock_init(&domain->lock); | |
2057 | domain->mode = PAGE_MODE_3_LEVEL; | |
2058 | domain->id = domain_id_alloc(); | |
2059 | if (!domain->id) | |
2060 | goto out_free; | |
2061 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2062 | if (!domain->pt_root) | |
2063 | goto out_free; | |
2064 | ||
2065 | dom->priv = domain; | |
2066 | ||
2067 | return 0; | |
2068 | ||
2069 | out_free: | |
2070 | kfree(domain); | |
2071 | ||
2072 | return -ENOMEM; | |
2073 | } | |
2074 | ||
98383fc3 JR |
2075 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2076 | { | |
2077 | struct protection_domain *domain = dom->priv; | |
2078 | ||
2079 | if (!domain) | |
2080 | return; | |
2081 | ||
2082 | if (domain->dev_cnt > 0) | |
2083 | cleanup_domain(domain); | |
2084 | ||
2085 | BUG_ON(domain->dev_cnt != 0); | |
2086 | ||
2087 | free_pagetable(domain); | |
2088 | ||
2089 | domain_id_free(domain->id); | |
2090 | ||
2091 | kfree(domain); | |
2092 | ||
2093 | dom->priv = NULL; | |
2094 | } | |
2095 | ||
684f2888 JR |
2096 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2097 | struct device *dev) | |
2098 | { | |
2099 | struct protection_domain *domain = dom->priv; | |
2100 | struct amd_iommu *iommu; | |
2101 | struct pci_dev *pdev; | |
2102 | u16 devid; | |
2103 | ||
2104 | if (dev->bus != &pci_bus_type) | |
2105 | return; | |
2106 | ||
2107 | pdev = to_pci_dev(dev); | |
2108 | ||
2109 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2110 | ||
2111 | if (devid > 0) | |
2112 | detach_device(domain, devid); | |
2113 | ||
2114 | iommu = amd_iommu_rlookup_table[devid]; | |
2115 | if (!iommu) | |
2116 | return; | |
2117 | ||
2118 | iommu_queue_inv_dev_entry(iommu, devid); | |
2119 | iommu_completion_wait(iommu); | |
2120 | } | |
2121 | ||
01106066 JR |
2122 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2123 | struct device *dev) | |
2124 | { | |
2125 | struct protection_domain *domain = dom->priv; | |
2126 | struct protection_domain *old_domain; | |
2127 | struct amd_iommu *iommu; | |
2128 | struct pci_dev *pdev; | |
2129 | u16 devid; | |
2130 | ||
2131 | if (dev->bus != &pci_bus_type) | |
2132 | return -EINVAL; | |
2133 | ||
2134 | pdev = to_pci_dev(dev); | |
2135 | ||
2136 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2137 | ||
2138 | if (devid >= amd_iommu_last_bdf || | |
2139 | devid != amd_iommu_alias_table[devid]) | |
2140 | return -EINVAL; | |
2141 | ||
2142 | iommu = amd_iommu_rlookup_table[devid]; | |
2143 | if (!iommu) | |
2144 | return -EINVAL; | |
2145 | ||
2146 | old_domain = domain_for_device(devid); | |
2147 | if (old_domain) | |
71ff3bca | 2148 | detach_device(old_domain, devid); |
01106066 JR |
2149 | |
2150 | attach_device(iommu, domain, devid); | |
2151 | ||
2152 | iommu_completion_wait(iommu); | |
2153 | ||
2154 | return 0; | |
2155 | } | |
2156 | ||
c6229ca6 JR |
2157 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2158 | unsigned long iova, phys_addr_t paddr, | |
2159 | size_t size, int iommu_prot) | |
2160 | { | |
2161 | struct protection_domain *domain = dom->priv; | |
2162 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2163 | int prot = 0; | |
2164 | int ret; | |
2165 | ||
2166 | if (iommu_prot & IOMMU_READ) | |
2167 | prot |= IOMMU_PROT_IR; | |
2168 | if (iommu_prot & IOMMU_WRITE) | |
2169 | prot |= IOMMU_PROT_IW; | |
2170 | ||
2171 | iova &= PAGE_MASK; | |
2172 | paddr &= PAGE_MASK; | |
2173 | ||
2174 | for (i = 0; i < npages; ++i) { | |
2175 | ret = iommu_map_page(domain, iova, paddr, prot); | |
2176 | if (ret) | |
2177 | return ret; | |
2178 | ||
2179 | iova += PAGE_SIZE; | |
2180 | paddr += PAGE_SIZE; | |
2181 | } | |
2182 | ||
2183 | return 0; | |
2184 | } | |
2185 | ||
eb74ff6c JR |
2186 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2187 | unsigned long iova, size_t size) | |
2188 | { | |
2189 | ||
2190 | struct protection_domain *domain = dom->priv; | |
2191 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2192 | ||
2193 | iova &= PAGE_MASK; | |
2194 | ||
2195 | for (i = 0; i < npages; ++i) { | |
2196 | iommu_unmap_page(domain, iova); | |
2197 | iova += PAGE_SIZE; | |
2198 | } | |
2199 | ||
2200 | iommu_flush_domain(domain->id); | |
2201 | } | |
2202 | ||
645c4c8d JR |
2203 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2204 | unsigned long iova) | |
2205 | { | |
2206 | struct protection_domain *domain = dom->priv; | |
2207 | unsigned long offset = iova & ~PAGE_MASK; | |
2208 | phys_addr_t paddr; | |
2209 | u64 *pte; | |
2210 | ||
a6d41a40 | 2211 | pte = fetch_pte(domain, iova); |
645c4c8d | 2212 | |
a6d41a40 | 2213 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2214 | return 0; |
2215 | ||
2216 | paddr = *pte & IOMMU_PAGE_MASK; | |
2217 | paddr |= offset; | |
2218 | ||
2219 | return paddr; | |
2220 | } | |
2221 | ||
dbb9fd86 SY |
2222 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2223 | unsigned long cap) | |
2224 | { | |
2225 | return 0; | |
2226 | } | |
2227 | ||
26961efe JR |
2228 | static struct iommu_ops amd_iommu_ops = { |
2229 | .domain_init = amd_iommu_domain_init, | |
2230 | .domain_destroy = amd_iommu_domain_destroy, | |
2231 | .attach_dev = amd_iommu_attach_device, | |
2232 | .detach_dev = amd_iommu_detach_device, | |
2233 | .map = amd_iommu_map_range, | |
2234 | .unmap = amd_iommu_unmap_range, | |
2235 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2236 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2237 | }; |
2238 |