Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 | 57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bda3092 JR |
58 | static u64* alloc_pte(struct protection_domain *dom, |
59 | unsigned long address, u64 | |
60 | **pte_page, gfp_t gfp); | |
00cd122a JR |
61 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
62 | unsigned long start_page, | |
63 | unsigned int pages); | |
bd0e5211 | 64 | |
c1eee67b CW |
65 | #ifndef BUS_NOTIFY_UNBOUND_DRIVER |
66 | #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005 | |
67 | #endif | |
68 | ||
7f26508b JR |
69 | #ifdef CONFIG_AMD_IOMMU_STATS |
70 | ||
71 | /* | |
72 | * Initialization code for statistics collection | |
73 | */ | |
74 | ||
da49f6df | 75 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 76 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 77 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 78 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 79 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 80 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 81 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 82 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 83 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 84 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 85 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 86 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 87 | |
7f26508b JR |
88 | static struct dentry *stats_dir; |
89 | static struct dentry *de_isolate; | |
90 | static struct dentry *de_fflush; | |
91 | ||
92 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
93 | { | |
94 | if (stats_dir == NULL) | |
95 | return; | |
96 | ||
97 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
98 | &cnt->value); | |
99 | } | |
100 | ||
101 | static void amd_iommu_stats_init(void) | |
102 | { | |
103 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
104 | if (stats_dir == NULL) | |
105 | return; | |
106 | ||
107 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
108 | (u32 *)&amd_iommu_isolate); | |
109 | ||
110 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
111 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
112 | |
113 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 114 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 115 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 116 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 117 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 118 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 119 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 120 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 121 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 122 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 123 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 124 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
125 | } |
126 | ||
127 | #endif | |
128 | ||
431b2a20 | 129 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
130 | static int iommu_has_npcache(struct amd_iommu *iommu) |
131 | { | |
ae9b9403 | 132 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
133 | } |
134 | ||
a80dc3e0 JR |
135 | /**************************************************************************** |
136 | * | |
137 | * Interrupt handling functions | |
138 | * | |
139 | ****************************************************************************/ | |
140 | ||
90008ee4 JR |
141 | static void iommu_print_event(void *__evt) |
142 | { | |
143 | u32 *event = __evt; | |
144 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
145 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
146 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
147 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
148 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
149 | ||
150 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
151 | ||
152 | switch (type) { | |
153 | case EVENT_TYPE_ILL_DEV: | |
154 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
155 | "address=0x%016llx flags=0x%04x]\n", | |
156 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
157 | address, flags); | |
158 | break; | |
159 | case EVENT_TYPE_IO_FAULT: | |
160 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
161 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
162 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
163 | domid, address, flags); | |
164 | break; | |
165 | case EVENT_TYPE_DEV_TAB_ERR: | |
166 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
167 | "address=0x%016llx flags=0x%04x]\n", | |
168 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
169 | address, flags); | |
170 | break; | |
171 | case EVENT_TYPE_PAGE_TAB_ERR: | |
172 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
173 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
174 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
175 | domid, address, flags); | |
176 | break; | |
177 | case EVENT_TYPE_ILL_CMD: | |
178 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
179 | break; | |
180 | case EVENT_TYPE_CMD_HARD_ERR: | |
181 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
182 | "flags=0x%04x]\n", address, flags); | |
183 | break; | |
184 | case EVENT_TYPE_IOTLB_INV_TO: | |
185 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
186 | "address=0x%016llx]\n", | |
187 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
188 | address); | |
189 | break; | |
190 | case EVENT_TYPE_INV_DEV_REQ: | |
191 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
192 | "address=0x%016llx flags=0x%04x]\n", | |
193 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
194 | address, flags); | |
195 | break; | |
196 | default: | |
197 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
198 | } | |
199 | } | |
200 | ||
201 | static void iommu_poll_events(struct amd_iommu *iommu) | |
202 | { | |
203 | u32 head, tail; | |
204 | unsigned long flags; | |
205 | ||
206 | spin_lock_irqsave(&iommu->lock, flags); | |
207 | ||
208 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
209 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
210 | ||
211 | while (head != tail) { | |
212 | iommu_print_event(iommu->evt_buf + head); | |
213 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
214 | } | |
215 | ||
216 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
217 | ||
218 | spin_unlock_irqrestore(&iommu->lock, flags); | |
219 | } | |
220 | ||
a80dc3e0 JR |
221 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
222 | { | |
90008ee4 JR |
223 | struct amd_iommu *iommu; |
224 | ||
3bd22172 | 225 | for_each_iommu(iommu) |
90008ee4 JR |
226 | iommu_poll_events(iommu); |
227 | ||
228 | return IRQ_HANDLED; | |
a80dc3e0 JR |
229 | } |
230 | ||
431b2a20 JR |
231 | /**************************************************************************** |
232 | * | |
233 | * IOMMU command queuing functions | |
234 | * | |
235 | ****************************************************************************/ | |
236 | ||
237 | /* | |
238 | * Writes the command to the IOMMUs command buffer and informs the | |
239 | * hardware about the new command. Must be called with iommu->lock held. | |
240 | */ | |
d6449536 | 241 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
242 | { |
243 | u32 tail, head; | |
244 | u8 *target; | |
245 | ||
246 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 247 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
248 | memcpy_toio(target, cmd, sizeof(*cmd)); |
249 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
250 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
251 | if (tail == head) | |
252 | return -ENOMEM; | |
253 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
431b2a20 JR |
258 | /* |
259 | * General queuing function for commands. Takes iommu->lock and calls | |
260 | * __iommu_queue_command(). | |
261 | */ | |
d6449536 | 262 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
263 | { |
264 | unsigned long flags; | |
265 | int ret; | |
266 | ||
267 | spin_lock_irqsave(&iommu->lock, flags); | |
268 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 269 | if (!ret) |
0cfd7aa9 | 270 | iommu->need_sync = true; |
a19ae1ec JR |
271 | spin_unlock_irqrestore(&iommu->lock, flags); |
272 | ||
273 | return ret; | |
274 | } | |
275 | ||
8d201968 JR |
276 | /* |
277 | * This function waits until an IOMMU has completed a completion | |
278 | * wait command | |
279 | */ | |
280 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
281 | { | |
282 | int ready = 0; | |
283 | unsigned status = 0; | |
284 | unsigned long i = 0; | |
285 | ||
da49f6df JR |
286 | INC_STATS_COUNTER(compl_wait); |
287 | ||
8d201968 JR |
288 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
289 | ++i; | |
290 | /* wait for the bit to become one */ | |
291 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
292 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
293 | } | |
294 | ||
295 | /* set bit back to zero */ | |
296 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
297 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
298 | ||
299 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
300 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
301 | } | |
302 | ||
303 | /* | |
304 | * This function queues a completion wait command into the command | |
305 | * buffer of an IOMMU | |
306 | */ | |
307 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
308 | { | |
309 | struct iommu_cmd cmd; | |
310 | ||
311 | memset(&cmd, 0, sizeof(cmd)); | |
312 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
313 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
314 | ||
315 | return __iommu_queue_command(iommu, &cmd); | |
316 | } | |
317 | ||
431b2a20 JR |
318 | /* |
319 | * This function is called whenever we need to ensure that the IOMMU has | |
320 | * completed execution of all commands we sent. It sends a | |
321 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
322 | * us about that by writing a value to a physical address we pass with | |
323 | * the command. | |
324 | */ | |
a19ae1ec JR |
325 | static int iommu_completion_wait(struct amd_iommu *iommu) |
326 | { | |
8d201968 JR |
327 | int ret = 0; |
328 | unsigned long flags; | |
a19ae1ec | 329 | |
7e4f88da JR |
330 | spin_lock_irqsave(&iommu->lock, flags); |
331 | ||
09ee17eb JR |
332 | if (!iommu->need_sync) |
333 | goto out; | |
334 | ||
8d201968 | 335 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 336 | |
0cfd7aa9 | 337 | iommu->need_sync = false; |
a19ae1ec JR |
338 | |
339 | if (ret) | |
7e4f88da | 340 | goto out; |
a19ae1ec | 341 | |
8d201968 | 342 | __iommu_wait_for_completion(iommu); |
84df8175 | 343 | |
7e4f88da JR |
344 | out: |
345 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
346 | |
347 | return 0; | |
348 | } | |
349 | ||
431b2a20 JR |
350 | /* |
351 | * Command send function for invalidating a device table entry | |
352 | */ | |
a19ae1ec JR |
353 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
354 | { | |
d6449536 | 355 | struct iommu_cmd cmd; |
ee2fa743 | 356 | int ret; |
a19ae1ec JR |
357 | |
358 | BUG_ON(iommu == NULL); | |
359 | ||
360 | memset(&cmd, 0, sizeof(cmd)); | |
361 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
362 | cmd.data[0] = devid; | |
363 | ||
ee2fa743 JR |
364 | ret = iommu_queue_command(iommu, &cmd); |
365 | ||
ee2fa743 | 366 | return ret; |
a19ae1ec JR |
367 | } |
368 | ||
237b6f33 JR |
369 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
370 | u16 domid, int pde, int s) | |
371 | { | |
372 | memset(cmd, 0, sizeof(*cmd)); | |
373 | address &= PAGE_MASK; | |
374 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
375 | cmd->data[1] |= domid; | |
376 | cmd->data[2] = lower_32_bits(address); | |
377 | cmd->data[3] = upper_32_bits(address); | |
378 | if (s) /* size bit - we flush more than one 4kb page */ | |
379 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
380 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
381 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
382 | } | |
383 | ||
431b2a20 JR |
384 | /* |
385 | * Generic command send function for invalidaing TLB entries | |
386 | */ | |
a19ae1ec JR |
387 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
388 | u64 address, u16 domid, int pde, int s) | |
389 | { | |
d6449536 | 390 | struct iommu_cmd cmd; |
ee2fa743 | 391 | int ret; |
a19ae1ec | 392 | |
237b6f33 | 393 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 394 | |
ee2fa743 JR |
395 | ret = iommu_queue_command(iommu, &cmd); |
396 | ||
ee2fa743 | 397 | return ret; |
a19ae1ec JR |
398 | } |
399 | ||
431b2a20 JR |
400 | /* |
401 | * TLB invalidation function which is called from the mapping functions. | |
402 | * It invalidates a single PTE if the range to flush is within a single | |
403 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
404 | */ | |
a19ae1ec JR |
405 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
406 | u64 address, size_t size) | |
407 | { | |
999ba417 | 408 | int s = 0; |
e3c449f5 | 409 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
410 | |
411 | address &= PAGE_MASK; | |
412 | ||
999ba417 JR |
413 | if (pages > 1) { |
414 | /* | |
415 | * If we have to flush more than one page, flush all | |
416 | * TLB entries for this domain | |
417 | */ | |
418 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
419 | s = 1; | |
a19ae1ec JR |
420 | } |
421 | ||
999ba417 JR |
422 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
423 | ||
a19ae1ec JR |
424 | return 0; |
425 | } | |
b6c02715 | 426 | |
1c655773 JR |
427 | /* Flush the whole IO/TLB for a given protection domain */ |
428 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
429 | { | |
430 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
431 | ||
f57d98ae JR |
432 | INC_STATS_COUNTER(domain_flush_single); |
433 | ||
1c655773 JR |
434 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
435 | } | |
436 | ||
43f49609 JR |
437 | /* |
438 | * This function is used to flush the IO/TLB for a given protection domain | |
439 | * on every IOMMU in the system | |
440 | */ | |
441 | static void iommu_flush_domain(u16 domid) | |
442 | { | |
443 | unsigned long flags; | |
444 | struct amd_iommu *iommu; | |
445 | struct iommu_cmd cmd; | |
446 | ||
18811f55 JR |
447 | INC_STATS_COUNTER(domain_flush_all); |
448 | ||
43f49609 JR |
449 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
450 | domid, 1, 1); | |
451 | ||
3bd22172 | 452 | for_each_iommu(iommu) { |
43f49609 JR |
453 | spin_lock_irqsave(&iommu->lock, flags); |
454 | __iommu_queue_command(iommu, &cmd); | |
455 | __iommu_completion_wait(iommu); | |
456 | __iommu_wait_for_completion(iommu); | |
457 | spin_unlock_irqrestore(&iommu->lock, flags); | |
458 | } | |
459 | } | |
43f49609 | 460 | |
bfd1be18 JR |
461 | void amd_iommu_flush_all_domains(void) |
462 | { | |
463 | int i; | |
464 | ||
465 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
466 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
467 | continue; | |
468 | iommu_flush_domain(i); | |
469 | } | |
470 | } | |
471 | ||
7d7a110c JR |
472 | void amd_iommu_flush_all_devices(void) |
473 | { | |
474 | struct amd_iommu *iommu; | |
475 | int i; | |
476 | ||
477 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
478 | if (amd_iommu_pd_table[i] == NULL) | |
479 | continue; | |
480 | ||
481 | iommu = amd_iommu_rlookup_table[i]; | |
482 | if (!iommu) | |
483 | continue; | |
484 | ||
485 | iommu_queue_inv_dev_entry(iommu, i); | |
486 | iommu_completion_wait(iommu); | |
487 | } | |
488 | } | |
489 | ||
431b2a20 JR |
490 | /**************************************************************************** |
491 | * | |
492 | * The functions below are used the create the page table mappings for | |
493 | * unity mapped regions. | |
494 | * | |
495 | ****************************************************************************/ | |
496 | ||
497 | /* | |
498 | * Generic mapping functions. It maps a physical address into a DMA | |
499 | * address space. It allocates the page table pages if necessary. | |
500 | * In the future it can be extended to a generic mapping function | |
501 | * supporting all features of AMD IOMMU page tables like level skipping | |
502 | * and full 64 bit address spaces. | |
503 | */ | |
38e817fe JR |
504 | static int iommu_map_page(struct protection_domain *dom, |
505 | unsigned long bus_addr, | |
506 | unsigned long phys_addr, | |
507 | int prot) | |
bd0e5211 | 508 | { |
8bda3092 | 509 | u64 __pte, *pte; |
bd0e5211 JR |
510 | |
511 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 512 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
513 | |
514 | /* only support 512GB address spaces for now */ | |
515 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
516 | return -EINVAL; | |
517 | ||
8bda3092 | 518 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); |
bd0e5211 JR |
519 | |
520 | if (IOMMU_PTE_PRESENT(*pte)) | |
521 | return -EBUSY; | |
522 | ||
523 | __pte = phys_addr | IOMMU_PTE_P; | |
524 | if (prot & IOMMU_PROT_IR) | |
525 | __pte |= IOMMU_PTE_IR; | |
526 | if (prot & IOMMU_PROT_IW) | |
527 | __pte |= IOMMU_PTE_IW; | |
528 | ||
529 | *pte = __pte; | |
530 | ||
531 | return 0; | |
532 | } | |
533 | ||
eb74ff6c JR |
534 | static void iommu_unmap_page(struct protection_domain *dom, |
535 | unsigned long bus_addr) | |
536 | { | |
537 | u64 *pte; | |
538 | ||
539 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
540 | ||
541 | if (!IOMMU_PTE_PRESENT(*pte)) | |
542 | return; | |
543 | ||
544 | pte = IOMMU_PTE_PAGE(*pte); | |
545 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
546 | ||
547 | if (!IOMMU_PTE_PRESENT(*pte)) | |
548 | return; | |
549 | ||
550 | pte = IOMMU_PTE_PAGE(*pte); | |
551 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
552 | ||
553 | *pte = 0; | |
554 | } | |
eb74ff6c | 555 | |
431b2a20 JR |
556 | /* |
557 | * This function checks if a specific unity mapping entry is needed for | |
558 | * this specific IOMMU. | |
559 | */ | |
bd0e5211 JR |
560 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
561 | struct unity_map_entry *entry) | |
562 | { | |
563 | u16 bdf, i; | |
564 | ||
565 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
566 | bdf = amd_iommu_alias_table[i]; | |
567 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
568 | return 1; | |
569 | } | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
431b2a20 JR |
574 | /* |
575 | * Init the unity mappings for a specific IOMMU in the system | |
576 | * | |
577 | * Basically iterates over all unity mapping entries and applies them to | |
578 | * the default domain DMA of that IOMMU if necessary. | |
579 | */ | |
bd0e5211 JR |
580 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
581 | { | |
582 | struct unity_map_entry *entry; | |
583 | int ret; | |
584 | ||
585 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
586 | if (!iommu_for_unity_map(iommu, entry)) | |
587 | continue; | |
588 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
589 | if (ret) | |
590 | return ret; | |
591 | } | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
431b2a20 JR |
596 | /* |
597 | * This function actually applies the mapping to the page table of the | |
598 | * dma_ops domain. | |
599 | */ | |
bd0e5211 JR |
600 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
601 | struct unity_map_entry *e) | |
602 | { | |
603 | u64 addr; | |
604 | int ret; | |
605 | ||
606 | for (addr = e->address_start; addr < e->address_end; | |
607 | addr += PAGE_SIZE) { | |
38e817fe | 608 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
609 | if (ret) |
610 | return ret; | |
611 | /* | |
612 | * if unity mapping is in aperture range mark the page | |
613 | * as allocated in the aperture | |
614 | */ | |
615 | if (addr < dma_dom->aperture_size) | |
c3239567 | 616 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 617 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
618 | } |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
431b2a20 JR |
623 | /* |
624 | * Inits the unity mappings required for a specific device | |
625 | */ | |
bd0e5211 JR |
626 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
627 | u16 devid) | |
628 | { | |
629 | struct unity_map_entry *e; | |
630 | int ret; | |
631 | ||
632 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
633 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
634 | continue; | |
635 | ret = dma_ops_unity_map(dma_dom, e); | |
636 | if (ret) | |
637 | return ret; | |
638 | } | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
431b2a20 JR |
643 | /**************************************************************************** |
644 | * | |
645 | * The next functions belong to the address allocator for the dma_ops | |
646 | * interface functions. They work like the allocators in the other IOMMU | |
647 | * drivers. Its basically a bitmap which marks the allocated pages in | |
648 | * the aperture. Maybe it could be enhanced in the future to a more | |
649 | * efficient allocator. | |
650 | * | |
651 | ****************************************************************************/ | |
d3086444 | 652 | |
431b2a20 | 653 | /* |
384de729 | 654 | * The address allocator core functions. |
431b2a20 JR |
655 | * |
656 | * called with domain->lock held | |
657 | */ | |
384de729 | 658 | |
00cd122a JR |
659 | /* |
660 | * This function checks if there is a PTE for a given dma address. If | |
661 | * there is one, it returns the pointer to it. | |
662 | */ | |
663 | static u64* fetch_pte(struct protection_domain *domain, | |
664 | unsigned long address) | |
665 | { | |
666 | u64 *pte; | |
667 | ||
668 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
669 | ||
670 | if (!IOMMU_PTE_PRESENT(*pte)) | |
671 | return NULL; | |
672 | ||
673 | pte = IOMMU_PTE_PAGE(*pte); | |
674 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
675 | ||
676 | if (!IOMMU_PTE_PRESENT(*pte)) | |
677 | return NULL; | |
678 | ||
679 | pte = IOMMU_PTE_PAGE(*pte); | |
680 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
681 | ||
682 | return pte; | |
683 | } | |
684 | ||
9cabe89b JR |
685 | /* |
686 | * This function is used to add a new aperture range to an existing | |
687 | * aperture in case of dma_ops domain allocation or address allocation | |
688 | * failure. | |
689 | */ | |
00cd122a JR |
690 | static int alloc_new_range(struct amd_iommu *iommu, |
691 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
692 | bool populate, gfp_t gfp) |
693 | { | |
694 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 695 | int i; |
9cabe89b | 696 | |
f5e9705c JR |
697 | #ifdef CONFIG_IOMMU_STRESS |
698 | populate = false; | |
699 | #endif | |
700 | ||
9cabe89b JR |
701 | if (index >= APERTURE_MAX_RANGES) |
702 | return -ENOMEM; | |
703 | ||
704 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
705 | if (!dma_dom->aperture[index]) | |
706 | return -ENOMEM; | |
707 | ||
708 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
709 | if (!dma_dom->aperture[index]->bitmap) | |
710 | goto out_free; | |
711 | ||
712 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
713 | ||
714 | if (populate) { | |
715 | unsigned long address = dma_dom->aperture_size; | |
716 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
717 | u64 *pte, *pte_page; | |
718 | ||
719 | for (i = 0; i < num_ptes; ++i) { | |
720 | pte = alloc_pte(&dma_dom->domain, address, | |
721 | &pte_page, gfp); | |
722 | if (!pte) | |
723 | goto out_free; | |
724 | ||
725 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
726 | ||
727 | address += APERTURE_RANGE_SIZE / 64; | |
728 | } | |
729 | } | |
730 | ||
731 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
732 | ||
00cd122a JR |
733 | /* Intialize the exclusion range if necessary */ |
734 | if (iommu->exclusion_start && | |
735 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
736 | iommu->exclusion_start < dma_dom->aperture_size) { | |
737 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
738 | int pages = iommu_num_pages(iommu->exclusion_start, | |
739 | iommu->exclusion_length, | |
740 | PAGE_SIZE); | |
741 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
742 | } | |
743 | ||
744 | /* | |
745 | * Check for areas already mapped as present in the new aperture | |
746 | * range and mark those pages as reserved in the allocator. Such | |
747 | * mappings may already exist as a result of requested unity | |
748 | * mappings for devices. | |
749 | */ | |
750 | for (i = dma_dom->aperture[index]->offset; | |
751 | i < dma_dom->aperture_size; | |
752 | i += PAGE_SIZE) { | |
753 | u64 *pte = fetch_pte(&dma_dom->domain, i); | |
754 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
755 | continue; | |
756 | ||
757 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
758 | } | |
759 | ||
9cabe89b JR |
760 | return 0; |
761 | ||
762 | out_free: | |
763 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); | |
764 | ||
765 | kfree(dma_dom->aperture[index]); | |
766 | dma_dom->aperture[index] = NULL; | |
767 | ||
768 | return -ENOMEM; | |
769 | } | |
770 | ||
384de729 JR |
771 | static unsigned long dma_ops_area_alloc(struct device *dev, |
772 | struct dma_ops_domain *dom, | |
773 | unsigned int pages, | |
774 | unsigned long align_mask, | |
775 | u64 dma_mask, | |
776 | unsigned long start) | |
777 | { | |
803b8cb4 | 778 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
779 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
780 | int i = start >> APERTURE_RANGE_SHIFT; | |
781 | unsigned long boundary_size; | |
782 | unsigned long address = -1; | |
783 | unsigned long limit; | |
784 | ||
803b8cb4 JR |
785 | next_bit >>= PAGE_SHIFT; |
786 | ||
384de729 JR |
787 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
788 | PAGE_SIZE) >> PAGE_SHIFT; | |
789 | ||
790 | for (;i < max_index; ++i) { | |
791 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
792 | ||
793 | if (dom->aperture[i]->offset >= dma_mask) | |
794 | break; | |
795 | ||
796 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
797 | dma_mask >> PAGE_SHIFT); | |
798 | ||
799 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
800 | limit, next_bit, pages, 0, | |
801 | boundary_size, align_mask); | |
802 | if (address != -1) { | |
803 | address = dom->aperture[i]->offset + | |
804 | (address << PAGE_SHIFT); | |
803b8cb4 | 805 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
806 | break; |
807 | } | |
808 | ||
809 | next_bit = 0; | |
810 | } | |
811 | ||
812 | return address; | |
813 | } | |
814 | ||
d3086444 JR |
815 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
816 | struct dma_ops_domain *dom, | |
6d4f343f | 817 | unsigned int pages, |
832a90c3 JR |
818 | unsigned long align_mask, |
819 | u64 dma_mask) | |
d3086444 | 820 | { |
d3086444 | 821 | unsigned long address; |
d3086444 | 822 | |
fe16f088 JR |
823 | #ifdef CONFIG_IOMMU_STRESS |
824 | dom->next_address = 0; | |
825 | dom->need_flush = true; | |
826 | #endif | |
d3086444 | 827 | |
384de729 | 828 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 829 | dma_mask, dom->next_address); |
d3086444 | 830 | |
1c655773 | 831 | if (address == -1) { |
803b8cb4 | 832 | dom->next_address = 0; |
384de729 JR |
833 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
834 | dma_mask, 0); | |
1c655773 JR |
835 | dom->need_flush = true; |
836 | } | |
d3086444 | 837 | |
384de729 | 838 | if (unlikely(address == -1)) |
d3086444 JR |
839 | address = bad_dma_address; |
840 | ||
841 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
842 | ||
843 | return address; | |
844 | } | |
845 | ||
431b2a20 JR |
846 | /* |
847 | * The address free function. | |
848 | * | |
849 | * called with domain->lock held | |
850 | */ | |
d3086444 JR |
851 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
852 | unsigned long address, | |
853 | unsigned int pages) | |
854 | { | |
384de729 JR |
855 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
856 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 857 | |
384de729 JR |
858 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
859 | ||
47bccd6b JR |
860 | #ifdef CONFIG_IOMMU_STRESS |
861 | if (i < 4) | |
862 | return; | |
863 | #endif | |
80be308d | 864 | |
803b8cb4 | 865 | if (address >= dom->next_address) |
80be308d | 866 | dom->need_flush = true; |
384de729 JR |
867 | |
868 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 869 | |
384de729 JR |
870 | iommu_area_free(range->bitmap, address, pages); |
871 | ||
d3086444 JR |
872 | } |
873 | ||
431b2a20 JR |
874 | /**************************************************************************** |
875 | * | |
876 | * The next functions belong to the domain allocation. A domain is | |
877 | * allocated for every IOMMU as the default domain. If device isolation | |
878 | * is enabled, every device get its own domain. The most important thing | |
879 | * about domains is the page table mapping the DMA address space they | |
880 | * contain. | |
881 | * | |
882 | ****************************************************************************/ | |
883 | ||
ec487d1a JR |
884 | static u16 domain_id_alloc(void) |
885 | { | |
886 | unsigned long flags; | |
887 | int id; | |
888 | ||
889 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
890 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
891 | BUG_ON(id == 0); | |
892 | if (id > 0 && id < MAX_DOMAIN_ID) | |
893 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
894 | else | |
895 | id = 0; | |
896 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
897 | ||
898 | return id; | |
899 | } | |
900 | ||
a2acfb75 JR |
901 | static void domain_id_free(int id) |
902 | { | |
903 | unsigned long flags; | |
904 | ||
905 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
906 | if (id > 0 && id < MAX_DOMAIN_ID) | |
907 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
908 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
909 | } | |
a2acfb75 | 910 | |
431b2a20 JR |
911 | /* |
912 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
913 | * ranges. | |
914 | */ | |
ec487d1a JR |
915 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
916 | unsigned long start_page, | |
917 | unsigned int pages) | |
918 | { | |
384de729 | 919 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
920 | |
921 | if (start_page + pages > last_page) | |
922 | pages = last_page - start_page; | |
923 | ||
384de729 JR |
924 | for (i = start_page; i < start_page + pages; ++i) { |
925 | int index = i / APERTURE_RANGE_PAGES; | |
926 | int page = i % APERTURE_RANGE_PAGES; | |
927 | __set_bit(page, dom->aperture[index]->bitmap); | |
928 | } | |
ec487d1a JR |
929 | } |
930 | ||
86db2e5d | 931 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
932 | { |
933 | int i, j; | |
934 | u64 *p1, *p2, *p3; | |
935 | ||
86db2e5d | 936 | p1 = domain->pt_root; |
ec487d1a JR |
937 | |
938 | if (!p1) | |
939 | return; | |
940 | ||
941 | for (i = 0; i < 512; ++i) { | |
942 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
943 | continue; | |
944 | ||
945 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 946 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
947 | if (!IOMMU_PTE_PRESENT(p2[j])) |
948 | continue; | |
949 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
950 | free_page((unsigned long)p3); | |
951 | } | |
952 | ||
953 | free_page((unsigned long)p2); | |
954 | } | |
955 | ||
956 | free_page((unsigned long)p1); | |
86db2e5d JR |
957 | |
958 | domain->pt_root = NULL; | |
ec487d1a JR |
959 | } |
960 | ||
431b2a20 JR |
961 | /* |
962 | * Free a domain, only used if something went wrong in the | |
963 | * allocation path and we need to free an already allocated page table | |
964 | */ | |
ec487d1a JR |
965 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
966 | { | |
384de729 JR |
967 | int i; |
968 | ||
ec487d1a JR |
969 | if (!dom) |
970 | return; | |
971 | ||
86db2e5d | 972 | free_pagetable(&dom->domain); |
ec487d1a | 973 | |
384de729 JR |
974 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
975 | if (!dom->aperture[i]) | |
976 | continue; | |
977 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
978 | kfree(dom->aperture[i]); | |
979 | } | |
ec487d1a JR |
980 | |
981 | kfree(dom); | |
982 | } | |
983 | ||
431b2a20 JR |
984 | /* |
985 | * Allocates a new protection domain usable for the dma_ops functions. | |
986 | * It also intializes the page table and the address allocator data | |
987 | * structures required for the dma_ops interface | |
988 | */ | |
d9cfed92 | 989 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
990 | { |
991 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
992 | |
993 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
994 | if (!dma_dom) | |
995 | return NULL; | |
996 | ||
997 | spin_lock_init(&dma_dom->domain.lock); | |
998 | ||
999 | dma_dom->domain.id = domain_id_alloc(); | |
1000 | if (dma_dom->domain.id == 0) | |
1001 | goto free_dma_dom; | |
1002 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
1003 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 1004 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1005 | dma_dom->domain.priv = dma_dom; |
1006 | if (!dma_dom->domain.pt_root) | |
1007 | goto free_dma_dom; | |
ec487d1a | 1008 | |
1c655773 | 1009 | dma_dom->need_flush = false; |
bd60b735 | 1010 | dma_dom->target_dev = 0xffff; |
1c655773 | 1011 | |
00cd122a | 1012 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1013 | goto free_dma_dom; |
ec487d1a | 1014 | |
431b2a20 | 1015 | /* |
ec487d1a JR |
1016 | * mark the first page as allocated so we never return 0 as |
1017 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1018 | */ |
384de729 | 1019 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1020 | dma_dom->next_address = 0; |
ec487d1a | 1021 | |
ec487d1a JR |
1022 | |
1023 | return dma_dom; | |
1024 | ||
1025 | free_dma_dom: | |
1026 | dma_ops_domain_free(dma_dom); | |
1027 | ||
1028 | return NULL; | |
1029 | } | |
1030 | ||
5b28df6f JR |
1031 | /* |
1032 | * little helper function to check whether a given protection domain is a | |
1033 | * dma_ops domain | |
1034 | */ | |
1035 | static bool dma_ops_domain(struct protection_domain *domain) | |
1036 | { | |
1037 | return domain->flags & PD_DMA_OPS_MASK; | |
1038 | } | |
1039 | ||
431b2a20 JR |
1040 | /* |
1041 | * Find out the protection domain structure for a given PCI device. This | |
1042 | * will give us the pointer to the page table root for example. | |
1043 | */ | |
b20ac0d4 JR |
1044 | static struct protection_domain *domain_for_device(u16 devid) |
1045 | { | |
1046 | struct protection_domain *dom; | |
1047 | unsigned long flags; | |
1048 | ||
1049 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1050 | dom = amd_iommu_pd_table[devid]; | |
1051 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1052 | ||
1053 | return dom; | |
1054 | } | |
1055 | ||
431b2a20 JR |
1056 | /* |
1057 | * If a device is not yet associated with a domain, this function does | |
1058 | * assigns it visible for the hardware | |
1059 | */ | |
f1179dc0 JR |
1060 | static void attach_device(struct amd_iommu *iommu, |
1061 | struct protection_domain *domain, | |
1062 | u16 devid) | |
b20ac0d4 JR |
1063 | { |
1064 | unsigned long flags; | |
b20ac0d4 JR |
1065 | u64 pte_root = virt_to_phys(domain->pt_root); |
1066 | ||
863c74eb JR |
1067 | domain->dev_cnt += 1; |
1068 | ||
38ddf41b JR |
1069 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1070 | << DEV_ENTRY_MODE_SHIFT; | |
1071 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
1072 | |
1073 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
1074 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
1075 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
1076 | amd_iommu_dev_table[devid].data[2] = domain->id; |
1077 | ||
1078 | amd_iommu_pd_table[devid] = domain; | |
1079 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1080 | ||
1081 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
1082 | } |
1083 | ||
355bf553 JR |
1084 | /* |
1085 | * Removes a device from a protection domain (unlocked) | |
1086 | */ | |
1087 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1088 | { | |
1089 | ||
1090 | /* lock domain */ | |
1091 | spin_lock(&domain->lock); | |
1092 | ||
1093 | /* remove domain from the lookup table */ | |
1094 | amd_iommu_pd_table[devid] = NULL; | |
1095 | ||
1096 | /* remove entry from the device table seen by the hardware */ | |
1097 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1098 | amd_iommu_dev_table[devid].data[1] = 0; | |
1099 | amd_iommu_dev_table[devid].data[2] = 0; | |
1100 | ||
1101 | /* decrease reference counter */ | |
1102 | domain->dev_cnt -= 1; | |
1103 | ||
1104 | /* ready */ | |
1105 | spin_unlock(&domain->lock); | |
1106 | } | |
1107 | ||
1108 | /* | |
1109 | * Removes a device from a protection domain (with devtable_lock held) | |
1110 | */ | |
1111 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1112 | { | |
1113 | unsigned long flags; | |
1114 | ||
1115 | /* lock device table */ | |
1116 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1117 | __detach_device(domain, devid); | |
1118 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1119 | } | |
e275a2a0 JR |
1120 | |
1121 | static int device_change_notifier(struct notifier_block *nb, | |
1122 | unsigned long action, void *data) | |
1123 | { | |
1124 | struct device *dev = data; | |
1125 | struct pci_dev *pdev = to_pci_dev(dev); | |
1126 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1127 | struct protection_domain *domain; | |
1128 | struct dma_ops_domain *dma_domain; | |
1129 | struct amd_iommu *iommu; | |
1ac4cbbc | 1130 | unsigned long flags; |
e275a2a0 JR |
1131 | |
1132 | if (devid > amd_iommu_last_bdf) | |
1133 | goto out; | |
1134 | ||
1135 | devid = amd_iommu_alias_table[devid]; | |
1136 | ||
1137 | iommu = amd_iommu_rlookup_table[devid]; | |
1138 | if (iommu == NULL) | |
1139 | goto out; | |
1140 | ||
1141 | domain = domain_for_device(devid); | |
1142 | ||
1143 | if (domain && !dma_ops_domain(domain)) | |
1144 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1145 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1146 | ||
1147 | switch (action) { | |
c1eee67b | 1148 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1149 | if (!domain) |
1150 | goto out; | |
1151 | detach_device(domain, devid); | |
1ac4cbbc JR |
1152 | break; |
1153 | case BUS_NOTIFY_ADD_DEVICE: | |
1154 | /* allocate a protection domain if a device is added */ | |
1155 | dma_domain = find_protection_domain(devid); | |
1156 | if (dma_domain) | |
1157 | goto out; | |
d9cfed92 | 1158 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1159 | if (!dma_domain) |
1160 | goto out; | |
1161 | dma_domain->target_dev = devid; | |
1162 | ||
1163 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1164 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1165 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1166 | ||
e275a2a0 JR |
1167 | break; |
1168 | default: | |
1169 | goto out; | |
1170 | } | |
1171 | ||
1172 | iommu_queue_inv_dev_entry(iommu, devid); | |
1173 | iommu_completion_wait(iommu); | |
1174 | ||
1175 | out: | |
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | struct notifier_block device_nb = { | |
1180 | .notifier_call = device_change_notifier, | |
1181 | }; | |
355bf553 | 1182 | |
431b2a20 JR |
1183 | /***************************************************************************** |
1184 | * | |
1185 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1186 | * | |
1187 | *****************************************************************************/ | |
1188 | ||
dbcc112e JR |
1189 | /* |
1190 | * This function checks if the driver got a valid device from the caller to | |
1191 | * avoid dereferencing invalid pointers. | |
1192 | */ | |
1193 | static bool check_device(struct device *dev) | |
1194 | { | |
1195 | if (!dev || !dev->dma_mask) | |
1196 | return false; | |
1197 | ||
1198 | return true; | |
1199 | } | |
1200 | ||
bd60b735 JR |
1201 | /* |
1202 | * In this function the list of preallocated protection domains is traversed to | |
1203 | * find the domain for a specific device | |
1204 | */ | |
1205 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1206 | { | |
1207 | struct dma_ops_domain *entry, *ret = NULL; | |
1208 | unsigned long flags; | |
1209 | ||
1210 | if (list_empty(&iommu_pd_list)) | |
1211 | return NULL; | |
1212 | ||
1213 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1214 | ||
1215 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1216 | if (entry->target_dev == devid) { | |
1217 | ret = entry; | |
bd60b735 JR |
1218 | break; |
1219 | } | |
1220 | } | |
1221 | ||
1222 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1223 | ||
1224 | return ret; | |
1225 | } | |
1226 | ||
431b2a20 JR |
1227 | /* |
1228 | * In the dma_ops path we only have the struct device. This function | |
1229 | * finds the corresponding IOMMU, the protection domain and the | |
1230 | * requestor id for a given device. | |
1231 | * If the device is not yet associated with a domain this is also done | |
1232 | * in this function. | |
1233 | */ | |
b20ac0d4 JR |
1234 | static int get_device_resources(struct device *dev, |
1235 | struct amd_iommu **iommu, | |
1236 | struct protection_domain **domain, | |
1237 | u16 *bdf) | |
1238 | { | |
1239 | struct dma_ops_domain *dma_dom; | |
1240 | struct pci_dev *pcidev; | |
1241 | u16 _bdf; | |
1242 | ||
dbcc112e JR |
1243 | *iommu = NULL; |
1244 | *domain = NULL; | |
1245 | *bdf = 0xffff; | |
1246 | ||
1247 | if (dev->bus != &pci_bus_type) | |
1248 | return 0; | |
b20ac0d4 JR |
1249 | |
1250 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1251 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1252 | |
431b2a20 | 1253 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1254 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1255 | return 0; |
b20ac0d4 JR |
1256 | |
1257 | *bdf = amd_iommu_alias_table[_bdf]; | |
1258 | ||
1259 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1260 | if (*iommu == NULL) | |
1261 | return 0; | |
b20ac0d4 JR |
1262 | *domain = domain_for_device(*bdf); |
1263 | if (*domain == NULL) { | |
bd60b735 JR |
1264 | dma_dom = find_protection_domain(*bdf); |
1265 | if (!dma_dom) | |
1266 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1267 | *domain = &dma_dom->domain; |
f1179dc0 | 1268 | attach_device(*iommu, *domain, *bdf); |
b3b99ef8 JR |
1269 | DUMP_printk(KERN_INFO "AMD IOMMU: Using protection domain " |
1270 | "%d for device %s\n", | |
1271 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1272 | } |
1273 | ||
f91ba190 | 1274 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1275 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1276 | |
b20ac0d4 JR |
1277 | return 1; |
1278 | } | |
1279 | ||
8bda3092 JR |
1280 | /* |
1281 | * If the pte_page is not yet allocated this function is called | |
1282 | */ | |
1283 | static u64* alloc_pte(struct protection_domain *dom, | |
1284 | unsigned long address, u64 **pte_page, gfp_t gfp) | |
1285 | { | |
1286 | u64 *pte, *page; | |
1287 | ||
1288 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
1289 | ||
1290 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1291 | page = (u64 *)get_zeroed_page(gfp); | |
1292 | if (!page) | |
1293 | return NULL; | |
1294 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
1295 | } | |
1296 | ||
1297 | pte = IOMMU_PTE_PAGE(*pte); | |
1298 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
1299 | ||
1300 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1301 | page = (u64 *)get_zeroed_page(gfp); | |
1302 | if (!page) | |
1303 | return NULL; | |
1304 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
1305 | } | |
1306 | ||
1307 | pte = IOMMU_PTE_PAGE(*pte); | |
1308 | ||
1309 | if (pte_page) | |
1310 | *pte_page = pte; | |
1311 | ||
1312 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
1313 | ||
1314 | return pte; | |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * This function fetches the PTE for a given address in the aperture | |
1319 | */ | |
1320 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1321 | unsigned long address) | |
1322 | { | |
384de729 | 1323 | struct aperture_range *aperture; |
8bda3092 JR |
1324 | u64 *pte, *pte_page; |
1325 | ||
384de729 JR |
1326 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1327 | if (!aperture) | |
1328 | return NULL; | |
1329 | ||
1330 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 JR |
1331 | if (!pte) { |
1332 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
384de729 JR |
1333 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1334 | } else | |
1335 | pte += IOMMU_PTE_L0_INDEX(address); | |
8bda3092 JR |
1336 | |
1337 | return pte; | |
1338 | } | |
1339 | ||
431b2a20 JR |
1340 | /* |
1341 | * This is the generic map function. It maps one 4kb page at paddr to | |
1342 | * the given address in the DMA address space for the domain. | |
1343 | */ | |
cb76c322 JR |
1344 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1345 | struct dma_ops_domain *dom, | |
1346 | unsigned long address, | |
1347 | phys_addr_t paddr, | |
1348 | int direction) | |
1349 | { | |
1350 | u64 *pte, __pte; | |
1351 | ||
1352 | WARN_ON(address > dom->aperture_size); | |
1353 | ||
1354 | paddr &= PAGE_MASK; | |
1355 | ||
8bda3092 | 1356 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1357 | if (!pte) |
1358 | return bad_dma_address; | |
cb76c322 JR |
1359 | |
1360 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1361 | ||
1362 | if (direction == DMA_TO_DEVICE) | |
1363 | __pte |= IOMMU_PTE_IR; | |
1364 | else if (direction == DMA_FROM_DEVICE) | |
1365 | __pte |= IOMMU_PTE_IW; | |
1366 | else if (direction == DMA_BIDIRECTIONAL) | |
1367 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1368 | ||
1369 | WARN_ON(*pte); | |
1370 | ||
1371 | *pte = __pte; | |
1372 | ||
1373 | return (dma_addr_t)address; | |
1374 | } | |
1375 | ||
431b2a20 JR |
1376 | /* |
1377 | * The generic unmapping function for on page in the DMA address space. | |
1378 | */ | |
cb76c322 JR |
1379 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1380 | struct dma_ops_domain *dom, | |
1381 | unsigned long address) | |
1382 | { | |
384de729 | 1383 | struct aperture_range *aperture; |
cb76c322 JR |
1384 | u64 *pte; |
1385 | ||
1386 | if (address >= dom->aperture_size) | |
1387 | return; | |
1388 | ||
384de729 JR |
1389 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1390 | if (!aperture) | |
1391 | return; | |
1392 | ||
1393 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1394 | if (!pte) | |
1395 | return; | |
cb76c322 | 1396 | |
cb76c322 JR |
1397 | pte += IOMMU_PTE_L0_INDEX(address); |
1398 | ||
1399 | WARN_ON(!*pte); | |
1400 | ||
1401 | *pte = 0ULL; | |
1402 | } | |
1403 | ||
431b2a20 JR |
1404 | /* |
1405 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1406 | * contiguous memory region into DMA address space. It is used by all |
1407 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1408 | * Must be called with the domain lock held. |
1409 | */ | |
cb76c322 JR |
1410 | static dma_addr_t __map_single(struct device *dev, |
1411 | struct amd_iommu *iommu, | |
1412 | struct dma_ops_domain *dma_dom, | |
1413 | phys_addr_t paddr, | |
1414 | size_t size, | |
6d4f343f | 1415 | int dir, |
832a90c3 JR |
1416 | bool align, |
1417 | u64 dma_mask) | |
cb76c322 JR |
1418 | { |
1419 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1420 | dma_addr_t address, start, ret; |
cb76c322 | 1421 | unsigned int pages; |
6d4f343f | 1422 | unsigned long align_mask = 0; |
cb76c322 JR |
1423 | int i; |
1424 | ||
e3c449f5 | 1425 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1426 | paddr &= PAGE_MASK; |
1427 | ||
8ecaf8f1 JR |
1428 | INC_STATS_COUNTER(total_map_requests); |
1429 | ||
c1858976 JR |
1430 | if (pages > 1) |
1431 | INC_STATS_COUNTER(cross_page); | |
1432 | ||
6d4f343f JR |
1433 | if (align) |
1434 | align_mask = (1UL << get_order(size)) - 1; | |
1435 | ||
11b83888 | 1436 | retry: |
832a90c3 JR |
1437 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1438 | dma_mask); | |
11b83888 JR |
1439 | if (unlikely(address == bad_dma_address)) { |
1440 | /* | |
1441 | * setting next_address here will let the address | |
1442 | * allocator only scan the new allocated range in the | |
1443 | * first run. This is a small optimization. | |
1444 | */ | |
1445 | dma_dom->next_address = dma_dom->aperture_size; | |
1446 | ||
1447 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1448 | goto out; | |
1449 | ||
1450 | /* | |
1451 | * aperture was sucessfully enlarged by 128 MB, try | |
1452 | * allocation again | |
1453 | */ | |
1454 | goto retry; | |
1455 | } | |
cb76c322 JR |
1456 | |
1457 | start = address; | |
1458 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1459 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1460 | if (ret == bad_dma_address) | |
1461 | goto out_unmap; | |
1462 | ||
cb76c322 JR |
1463 | paddr += PAGE_SIZE; |
1464 | start += PAGE_SIZE; | |
1465 | } | |
1466 | address += offset; | |
1467 | ||
5774f7c5 JR |
1468 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1469 | ||
afa9fdc2 | 1470 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1471 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1472 | dma_dom->need_flush = false; | |
1473 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1474 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1475 | ||
cb76c322 JR |
1476 | out: |
1477 | return address; | |
53812c11 JR |
1478 | |
1479 | out_unmap: | |
1480 | ||
1481 | for (--i; i >= 0; --i) { | |
1482 | start -= PAGE_SIZE; | |
1483 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1484 | } | |
1485 | ||
1486 | dma_ops_free_addresses(dma_dom, address, pages); | |
1487 | ||
1488 | return bad_dma_address; | |
cb76c322 JR |
1489 | } |
1490 | ||
431b2a20 JR |
1491 | /* |
1492 | * Does the reverse of the __map_single function. Must be called with | |
1493 | * the domain lock held too | |
1494 | */ | |
cb76c322 JR |
1495 | static void __unmap_single(struct amd_iommu *iommu, |
1496 | struct dma_ops_domain *dma_dom, | |
1497 | dma_addr_t dma_addr, | |
1498 | size_t size, | |
1499 | int dir) | |
1500 | { | |
1501 | dma_addr_t i, start; | |
1502 | unsigned int pages; | |
1503 | ||
b8d9905d JR |
1504 | if ((dma_addr == bad_dma_address) || |
1505 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1506 | return; |
1507 | ||
e3c449f5 | 1508 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1509 | dma_addr &= PAGE_MASK; |
1510 | start = dma_addr; | |
1511 | ||
1512 | for (i = 0; i < pages; ++i) { | |
1513 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1514 | start += PAGE_SIZE; | |
1515 | } | |
1516 | ||
5774f7c5 JR |
1517 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1518 | ||
cb76c322 | 1519 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1520 | |
80be308d | 1521 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1522 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1523 | dma_dom->need_flush = false; |
1524 | } | |
cb76c322 JR |
1525 | } |
1526 | ||
431b2a20 JR |
1527 | /* |
1528 | * The exported map_single function for dma_ops. | |
1529 | */ | |
51491367 FT |
1530 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1531 | unsigned long offset, size_t size, | |
1532 | enum dma_data_direction dir, | |
1533 | struct dma_attrs *attrs) | |
4da70b9e JR |
1534 | { |
1535 | unsigned long flags; | |
1536 | struct amd_iommu *iommu; | |
1537 | struct protection_domain *domain; | |
1538 | u16 devid; | |
1539 | dma_addr_t addr; | |
832a90c3 | 1540 | u64 dma_mask; |
51491367 | 1541 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1542 | |
0f2a86f2 JR |
1543 | INC_STATS_COUNTER(cnt_map_single); |
1544 | ||
dbcc112e JR |
1545 | if (!check_device(dev)) |
1546 | return bad_dma_address; | |
1547 | ||
832a90c3 | 1548 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1549 | |
1550 | get_device_resources(dev, &iommu, &domain, &devid); | |
1551 | ||
1552 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1553 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1554 | return (dma_addr_t)paddr; |
1555 | ||
5b28df6f JR |
1556 | if (!dma_ops_domain(domain)) |
1557 | return bad_dma_address; | |
1558 | ||
4da70b9e | 1559 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1560 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1561 | dma_mask); | |
4da70b9e JR |
1562 | if (addr == bad_dma_address) |
1563 | goto out; | |
1564 | ||
09ee17eb | 1565 | iommu_completion_wait(iommu); |
4da70b9e JR |
1566 | |
1567 | out: | |
1568 | spin_unlock_irqrestore(&domain->lock, flags); | |
1569 | ||
1570 | return addr; | |
1571 | } | |
1572 | ||
431b2a20 JR |
1573 | /* |
1574 | * The exported unmap_single function for dma_ops. | |
1575 | */ | |
51491367 FT |
1576 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1577 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1578 | { |
1579 | unsigned long flags; | |
1580 | struct amd_iommu *iommu; | |
1581 | struct protection_domain *domain; | |
1582 | u16 devid; | |
1583 | ||
146a6917 JR |
1584 | INC_STATS_COUNTER(cnt_unmap_single); |
1585 | ||
dbcc112e JR |
1586 | if (!check_device(dev) || |
1587 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1588 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1589 | return; |
1590 | ||
5b28df6f JR |
1591 | if (!dma_ops_domain(domain)) |
1592 | return; | |
1593 | ||
4da70b9e JR |
1594 | spin_lock_irqsave(&domain->lock, flags); |
1595 | ||
1596 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1597 | ||
09ee17eb | 1598 | iommu_completion_wait(iommu); |
4da70b9e JR |
1599 | |
1600 | spin_unlock_irqrestore(&domain->lock, flags); | |
1601 | } | |
1602 | ||
431b2a20 JR |
1603 | /* |
1604 | * This is a special map_sg function which is used if we should map a | |
1605 | * device which is not handled by an AMD IOMMU in the system. | |
1606 | */ | |
65b050ad JR |
1607 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1608 | int nelems, int dir) | |
1609 | { | |
1610 | struct scatterlist *s; | |
1611 | int i; | |
1612 | ||
1613 | for_each_sg(sglist, s, nelems, i) { | |
1614 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1615 | s->dma_length = s->length; | |
1616 | } | |
1617 | ||
1618 | return nelems; | |
1619 | } | |
1620 | ||
431b2a20 JR |
1621 | /* |
1622 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1623 | * lists). | |
1624 | */ | |
65b050ad | 1625 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1626 | int nelems, enum dma_data_direction dir, |
1627 | struct dma_attrs *attrs) | |
65b050ad JR |
1628 | { |
1629 | unsigned long flags; | |
1630 | struct amd_iommu *iommu; | |
1631 | struct protection_domain *domain; | |
1632 | u16 devid; | |
1633 | int i; | |
1634 | struct scatterlist *s; | |
1635 | phys_addr_t paddr; | |
1636 | int mapped_elems = 0; | |
832a90c3 | 1637 | u64 dma_mask; |
65b050ad | 1638 | |
d03f067a JR |
1639 | INC_STATS_COUNTER(cnt_map_sg); |
1640 | ||
dbcc112e JR |
1641 | if (!check_device(dev)) |
1642 | return 0; | |
1643 | ||
832a90c3 | 1644 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1645 | |
1646 | get_device_resources(dev, &iommu, &domain, &devid); | |
1647 | ||
1648 | if (!iommu || !domain) | |
1649 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1650 | ||
5b28df6f JR |
1651 | if (!dma_ops_domain(domain)) |
1652 | return 0; | |
1653 | ||
65b050ad JR |
1654 | spin_lock_irqsave(&domain->lock, flags); |
1655 | ||
1656 | for_each_sg(sglist, s, nelems, i) { | |
1657 | paddr = sg_phys(s); | |
1658 | ||
1659 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1660 | paddr, s->length, dir, false, |
1661 | dma_mask); | |
65b050ad JR |
1662 | |
1663 | if (s->dma_address) { | |
1664 | s->dma_length = s->length; | |
1665 | mapped_elems++; | |
1666 | } else | |
1667 | goto unmap; | |
65b050ad JR |
1668 | } |
1669 | ||
09ee17eb | 1670 | iommu_completion_wait(iommu); |
65b050ad JR |
1671 | |
1672 | out: | |
1673 | spin_unlock_irqrestore(&domain->lock, flags); | |
1674 | ||
1675 | return mapped_elems; | |
1676 | unmap: | |
1677 | for_each_sg(sglist, s, mapped_elems, i) { | |
1678 | if (s->dma_address) | |
1679 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1680 | s->dma_length, dir); | |
1681 | s->dma_address = s->dma_length = 0; | |
1682 | } | |
1683 | ||
1684 | mapped_elems = 0; | |
1685 | ||
1686 | goto out; | |
1687 | } | |
1688 | ||
431b2a20 JR |
1689 | /* |
1690 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1691 | * lists). | |
1692 | */ | |
65b050ad | 1693 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1694 | int nelems, enum dma_data_direction dir, |
1695 | struct dma_attrs *attrs) | |
65b050ad JR |
1696 | { |
1697 | unsigned long flags; | |
1698 | struct amd_iommu *iommu; | |
1699 | struct protection_domain *domain; | |
1700 | struct scatterlist *s; | |
1701 | u16 devid; | |
1702 | int i; | |
1703 | ||
55877a6b JR |
1704 | INC_STATS_COUNTER(cnt_unmap_sg); |
1705 | ||
dbcc112e JR |
1706 | if (!check_device(dev) || |
1707 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1708 | return; |
1709 | ||
5b28df6f JR |
1710 | if (!dma_ops_domain(domain)) |
1711 | return; | |
1712 | ||
65b050ad JR |
1713 | spin_lock_irqsave(&domain->lock, flags); |
1714 | ||
1715 | for_each_sg(sglist, s, nelems, i) { | |
1716 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1717 | s->dma_length, dir); | |
65b050ad JR |
1718 | s->dma_address = s->dma_length = 0; |
1719 | } | |
1720 | ||
09ee17eb | 1721 | iommu_completion_wait(iommu); |
65b050ad JR |
1722 | |
1723 | spin_unlock_irqrestore(&domain->lock, flags); | |
1724 | } | |
1725 | ||
431b2a20 JR |
1726 | /* |
1727 | * The exported alloc_coherent function for dma_ops. | |
1728 | */ | |
5d8b53cf JR |
1729 | static void *alloc_coherent(struct device *dev, size_t size, |
1730 | dma_addr_t *dma_addr, gfp_t flag) | |
1731 | { | |
1732 | unsigned long flags; | |
1733 | void *virt_addr; | |
1734 | struct amd_iommu *iommu; | |
1735 | struct protection_domain *domain; | |
1736 | u16 devid; | |
1737 | phys_addr_t paddr; | |
832a90c3 | 1738 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1739 | |
c8f0fb36 JR |
1740 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1741 | ||
dbcc112e JR |
1742 | if (!check_device(dev)) |
1743 | return NULL; | |
5d8b53cf | 1744 | |
13d9fead FT |
1745 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1746 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1747 | |
c97ac535 | 1748 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1749 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1750 | if (!virt_addr) | |
1751 | return 0; | |
1752 | ||
5d8b53cf JR |
1753 | paddr = virt_to_phys(virt_addr); |
1754 | ||
5d8b53cf JR |
1755 | if (!iommu || !domain) { |
1756 | *dma_addr = (dma_addr_t)paddr; | |
1757 | return virt_addr; | |
1758 | } | |
1759 | ||
5b28df6f JR |
1760 | if (!dma_ops_domain(domain)) |
1761 | goto out_free; | |
1762 | ||
832a90c3 JR |
1763 | if (!dma_mask) |
1764 | dma_mask = *dev->dma_mask; | |
1765 | ||
5d8b53cf JR |
1766 | spin_lock_irqsave(&domain->lock, flags); |
1767 | ||
1768 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1769 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1770 | |
367d04c4 JS |
1771 | if (*dma_addr == bad_dma_address) { |
1772 | spin_unlock_irqrestore(&domain->lock, flags); | |
5b28df6f | 1773 | goto out_free; |
367d04c4 | 1774 | } |
5d8b53cf | 1775 | |
09ee17eb | 1776 | iommu_completion_wait(iommu); |
5d8b53cf | 1777 | |
5d8b53cf JR |
1778 | spin_unlock_irqrestore(&domain->lock, flags); |
1779 | ||
1780 | return virt_addr; | |
5b28df6f JR |
1781 | |
1782 | out_free: | |
1783 | ||
1784 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1785 | ||
1786 | return NULL; | |
5d8b53cf JR |
1787 | } |
1788 | ||
431b2a20 JR |
1789 | /* |
1790 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1791 | */ |
5d8b53cf JR |
1792 | static void free_coherent(struct device *dev, size_t size, |
1793 | void *virt_addr, dma_addr_t dma_addr) | |
1794 | { | |
1795 | unsigned long flags; | |
1796 | struct amd_iommu *iommu; | |
1797 | struct protection_domain *domain; | |
1798 | u16 devid; | |
1799 | ||
5d31ee7e JR |
1800 | INC_STATS_COUNTER(cnt_free_coherent); |
1801 | ||
dbcc112e JR |
1802 | if (!check_device(dev)) |
1803 | return; | |
1804 | ||
5d8b53cf JR |
1805 | get_device_resources(dev, &iommu, &domain, &devid); |
1806 | ||
1807 | if (!iommu || !domain) | |
1808 | goto free_mem; | |
1809 | ||
5b28df6f JR |
1810 | if (!dma_ops_domain(domain)) |
1811 | goto free_mem; | |
1812 | ||
5d8b53cf JR |
1813 | spin_lock_irqsave(&domain->lock, flags); |
1814 | ||
1815 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1816 | |
09ee17eb | 1817 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1818 | |
1819 | spin_unlock_irqrestore(&domain->lock, flags); | |
1820 | ||
1821 | free_mem: | |
1822 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1823 | } | |
1824 | ||
b39ba6ad JR |
1825 | /* |
1826 | * This function is called by the DMA layer to find out if we can handle a | |
1827 | * particular device. It is part of the dma_ops. | |
1828 | */ | |
1829 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1830 | { | |
1831 | u16 bdf; | |
1832 | struct pci_dev *pcidev; | |
1833 | ||
1834 | /* No device or no PCI device */ | |
1835 | if (!dev || dev->bus != &pci_bus_type) | |
1836 | return 0; | |
1837 | ||
1838 | pcidev = to_pci_dev(dev); | |
1839 | ||
1840 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1841 | ||
1842 | /* Out of our scope? */ | |
1843 | if (bdf > amd_iommu_last_bdf) | |
1844 | return 0; | |
1845 | ||
1846 | return 1; | |
1847 | } | |
1848 | ||
c432f3df | 1849 | /* |
431b2a20 JR |
1850 | * The function for pre-allocating protection domains. |
1851 | * | |
c432f3df JR |
1852 | * If the driver core informs the DMA layer if a driver grabs a device |
1853 | * we don't need to preallocate the protection domains anymore. | |
1854 | * For now we have to. | |
1855 | */ | |
0e93dd88 | 1856 | static void prealloc_protection_domains(void) |
c432f3df JR |
1857 | { |
1858 | struct pci_dev *dev = NULL; | |
1859 | struct dma_ops_domain *dma_dom; | |
1860 | struct amd_iommu *iommu; | |
c432f3df JR |
1861 | u16 devid; |
1862 | ||
1863 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1864 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1865 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1866 | continue; |
1867 | devid = amd_iommu_alias_table[devid]; | |
1868 | if (domain_for_device(devid)) | |
1869 | continue; | |
1870 | iommu = amd_iommu_rlookup_table[devid]; | |
1871 | if (!iommu) | |
1872 | continue; | |
d9cfed92 | 1873 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
1874 | if (!dma_dom) |
1875 | continue; | |
1876 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1877 | dma_dom->target_dev = devid; |
1878 | ||
1879 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1880 | } |
1881 | } | |
1882 | ||
160c1d8e | 1883 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1884 | .alloc_coherent = alloc_coherent, |
1885 | .free_coherent = free_coherent, | |
51491367 FT |
1886 | .map_page = map_page, |
1887 | .unmap_page = unmap_page, | |
6631ee9d JR |
1888 | .map_sg = map_sg, |
1889 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1890 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1891 | }; |
1892 | ||
431b2a20 JR |
1893 | /* |
1894 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1895 | */ | |
6631ee9d JR |
1896 | int __init amd_iommu_init_dma_ops(void) |
1897 | { | |
1898 | struct amd_iommu *iommu; | |
6631ee9d JR |
1899 | int ret; |
1900 | ||
431b2a20 JR |
1901 | /* |
1902 | * first allocate a default protection domain for every IOMMU we | |
1903 | * found in the system. Devices not assigned to any other | |
1904 | * protection domain will be assigned to the default one. | |
1905 | */ | |
3bd22172 | 1906 | for_each_iommu(iommu) { |
d9cfed92 | 1907 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
1908 | if (iommu->default_dom == NULL) |
1909 | return -ENOMEM; | |
e2dc14a2 | 1910 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1911 | ret = iommu_init_unity_mappings(iommu); |
1912 | if (ret) | |
1913 | goto free_domains; | |
1914 | } | |
1915 | ||
431b2a20 JR |
1916 | /* |
1917 | * If device isolation is enabled, pre-allocate the protection | |
1918 | * domains for each device. | |
1919 | */ | |
6631ee9d JR |
1920 | if (amd_iommu_isolate) |
1921 | prealloc_protection_domains(); | |
1922 | ||
1923 | iommu_detected = 1; | |
1924 | force_iommu = 1; | |
1925 | bad_dma_address = 0; | |
92af4e29 | 1926 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1927 | gart_iommu_aperture_disabled = 1; |
1928 | gart_iommu_aperture = 0; | |
92af4e29 | 1929 | #endif |
6631ee9d | 1930 | |
431b2a20 | 1931 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1932 | dma_ops = &amd_iommu_dma_ops; |
1933 | ||
26961efe | 1934 | register_iommu(&amd_iommu_ops); |
26961efe | 1935 | |
e275a2a0 JR |
1936 | bus_register_notifier(&pci_bus_type, &device_nb); |
1937 | ||
7f26508b JR |
1938 | amd_iommu_stats_init(); |
1939 | ||
6631ee9d JR |
1940 | return 0; |
1941 | ||
1942 | free_domains: | |
1943 | ||
3bd22172 | 1944 | for_each_iommu(iommu) { |
6631ee9d JR |
1945 | if (iommu->default_dom) |
1946 | dma_ops_domain_free(iommu->default_dom); | |
1947 | } | |
1948 | ||
1949 | return ret; | |
1950 | } | |
6d98cd80 JR |
1951 | |
1952 | /***************************************************************************** | |
1953 | * | |
1954 | * The following functions belong to the exported interface of AMD IOMMU | |
1955 | * | |
1956 | * This interface allows access to lower level functions of the IOMMU | |
1957 | * like protection domain handling and assignement of devices to domains | |
1958 | * which is not possible with the dma_ops interface. | |
1959 | * | |
1960 | *****************************************************************************/ | |
1961 | ||
6d98cd80 JR |
1962 | static void cleanup_domain(struct protection_domain *domain) |
1963 | { | |
1964 | unsigned long flags; | |
1965 | u16 devid; | |
1966 | ||
1967 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1968 | ||
1969 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1970 | if (amd_iommu_pd_table[devid] == domain) | |
1971 | __detach_device(domain, devid); | |
1972 | ||
1973 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1974 | } | |
1975 | ||
c156e347 JR |
1976 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1977 | { | |
1978 | struct protection_domain *domain; | |
1979 | ||
1980 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1981 | if (!domain) | |
1982 | return -ENOMEM; | |
1983 | ||
1984 | spin_lock_init(&domain->lock); | |
1985 | domain->mode = PAGE_MODE_3_LEVEL; | |
1986 | domain->id = domain_id_alloc(); | |
1987 | if (!domain->id) | |
1988 | goto out_free; | |
1989 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1990 | if (!domain->pt_root) | |
1991 | goto out_free; | |
1992 | ||
1993 | dom->priv = domain; | |
1994 | ||
1995 | return 0; | |
1996 | ||
1997 | out_free: | |
1998 | kfree(domain); | |
1999 | ||
2000 | return -ENOMEM; | |
2001 | } | |
2002 | ||
98383fc3 JR |
2003 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2004 | { | |
2005 | struct protection_domain *domain = dom->priv; | |
2006 | ||
2007 | if (!domain) | |
2008 | return; | |
2009 | ||
2010 | if (domain->dev_cnt > 0) | |
2011 | cleanup_domain(domain); | |
2012 | ||
2013 | BUG_ON(domain->dev_cnt != 0); | |
2014 | ||
2015 | free_pagetable(domain); | |
2016 | ||
2017 | domain_id_free(domain->id); | |
2018 | ||
2019 | kfree(domain); | |
2020 | ||
2021 | dom->priv = NULL; | |
2022 | } | |
2023 | ||
684f2888 JR |
2024 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2025 | struct device *dev) | |
2026 | { | |
2027 | struct protection_domain *domain = dom->priv; | |
2028 | struct amd_iommu *iommu; | |
2029 | struct pci_dev *pdev; | |
2030 | u16 devid; | |
2031 | ||
2032 | if (dev->bus != &pci_bus_type) | |
2033 | return; | |
2034 | ||
2035 | pdev = to_pci_dev(dev); | |
2036 | ||
2037 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2038 | ||
2039 | if (devid > 0) | |
2040 | detach_device(domain, devid); | |
2041 | ||
2042 | iommu = amd_iommu_rlookup_table[devid]; | |
2043 | if (!iommu) | |
2044 | return; | |
2045 | ||
2046 | iommu_queue_inv_dev_entry(iommu, devid); | |
2047 | iommu_completion_wait(iommu); | |
2048 | } | |
2049 | ||
01106066 JR |
2050 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2051 | struct device *dev) | |
2052 | { | |
2053 | struct protection_domain *domain = dom->priv; | |
2054 | struct protection_domain *old_domain; | |
2055 | struct amd_iommu *iommu; | |
2056 | struct pci_dev *pdev; | |
2057 | u16 devid; | |
2058 | ||
2059 | if (dev->bus != &pci_bus_type) | |
2060 | return -EINVAL; | |
2061 | ||
2062 | pdev = to_pci_dev(dev); | |
2063 | ||
2064 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2065 | ||
2066 | if (devid >= amd_iommu_last_bdf || | |
2067 | devid != amd_iommu_alias_table[devid]) | |
2068 | return -EINVAL; | |
2069 | ||
2070 | iommu = amd_iommu_rlookup_table[devid]; | |
2071 | if (!iommu) | |
2072 | return -EINVAL; | |
2073 | ||
2074 | old_domain = domain_for_device(devid); | |
2075 | if (old_domain) | |
71ff3bca | 2076 | detach_device(old_domain, devid); |
01106066 JR |
2077 | |
2078 | attach_device(iommu, domain, devid); | |
2079 | ||
2080 | iommu_completion_wait(iommu); | |
2081 | ||
2082 | return 0; | |
2083 | } | |
2084 | ||
c6229ca6 JR |
2085 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2086 | unsigned long iova, phys_addr_t paddr, | |
2087 | size_t size, int iommu_prot) | |
2088 | { | |
2089 | struct protection_domain *domain = dom->priv; | |
2090 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2091 | int prot = 0; | |
2092 | int ret; | |
2093 | ||
2094 | if (iommu_prot & IOMMU_READ) | |
2095 | prot |= IOMMU_PROT_IR; | |
2096 | if (iommu_prot & IOMMU_WRITE) | |
2097 | prot |= IOMMU_PROT_IW; | |
2098 | ||
2099 | iova &= PAGE_MASK; | |
2100 | paddr &= PAGE_MASK; | |
2101 | ||
2102 | for (i = 0; i < npages; ++i) { | |
2103 | ret = iommu_map_page(domain, iova, paddr, prot); | |
2104 | if (ret) | |
2105 | return ret; | |
2106 | ||
2107 | iova += PAGE_SIZE; | |
2108 | paddr += PAGE_SIZE; | |
2109 | } | |
2110 | ||
2111 | return 0; | |
2112 | } | |
2113 | ||
eb74ff6c JR |
2114 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2115 | unsigned long iova, size_t size) | |
2116 | { | |
2117 | ||
2118 | struct protection_domain *domain = dom->priv; | |
2119 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2120 | ||
2121 | iova &= PAGE_MASK; | |
2122 | ||
2123 | for (i = 0; i < npages; ++i) { | |
2124 | iommu_unmap_page(domain, iova); | |
2125 | iova += PAGE_SIZE; | |
2126 | } | |
2127 | ||
2128 | iommu_flush_domain(domain->id); | |
2129 | } | |
2130 | ||
645c4c8d JR |
2131 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2132 | unsigned long iova) | |
2133 | { | |
2134 | struct protection_domain *domain = dom->priv; | |
2135 | unsigned long offset = iova & ~PAGE_MASK; | |
2136 | phys_addr_t paddr; | |
2137 | u64 *pte; | |
2138 | ||
2139 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
2140 | ||
2141 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2142 | return 0; | |
2143 | ||
2144 | pte = IOMMU_PTE_PAGE(*pte); | |
2145 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
2146 | ||
2147 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2148 | return 0; | |
2149 | ||
2150 | pte = IOMMU_PTE_PAGE(*pte); | |
2151 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
2152 | ||
2153 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2154 | return 0; | |
2155 | ||
2156 | paddr = *pte & IOMMU_PAGE_MASK; | |
2157 | paddr |= offset; | |
2158 | ||
2159 | return paddr; | |
2160 | } | |
2161 | ||
dbb9fd86 SY |
2162 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2163 | unsigned long cap) | |
2164 | { | |
2165 | return 0; | |
2166 | } | |
2167 | ||
26961efe JR |
2168 | static struct iommu_ops amd_iommu_ops = { |
2169 | .domain_init = amd_iommu_domain_init, | |
2170 | .domain_destroy = amd_iommu_domain_destroy, | |
2171 | .attach_dev = amd_iommu_attach_device, | |
2172 | .detach_dev = amd_iommu_detach_device, | |
2173 | .map = amd_iommu_map_range, | |
2174 | .unmap = amd_iommu_unmap_range, | |
2175 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2176 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2177 | }; |
2178 |