Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 JR |
57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
58 | ||
bd0e5211 | 59 | |
7f26508b JR |
60 | #ifdef CONFIG_AMD_IOMMU_STATS |
61 | ||
62 | /* | |
63 | * Initialization code for statistics collection | |
64 | */ | |
65 | ||
da49f6df | 66 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 67 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 68 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 69 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 70 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 71 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 72 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 73 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 74 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 75 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 76 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 77 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 78 | |
7f26508b JR |
79 | static struct dentry *stats_dir; |
80 | static struct dentry *de_isolate; | |
81 | static struct dentry *de_fflush; | |
82 | ||
83 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
84 | { | |
85 | if (stats_dir == NULL) | |
86 | return; | |
87 | ||
88 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
89 | &cnt->value); | |
90 | } | |
91 | ||
92 | static void amd_iommu_stats_init(void) | |
93 | { | |
94 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
95 | if (stats_dir == NULL) | |
96 | return; | |
97 | ||
98 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
99 | (u32 *)&amd_iommu_isolate); | |
100 | ||
101 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
102 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
103 | |
104 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 105 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 106 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 107 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 108 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 109 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 110 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 111 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 112 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 113 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 114 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 115 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
116 | } |
117 | ||
118 | #endif | |
119 | ||
431b2a20 | 120 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
121 | static int iommu_has_npcache(struct amd_iommu *iommu) |
122 | { | |
ae9b9403 | 123 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
124 | } |
125 | ||
a80dc3e0 JR |
126 | /**************************************************************************** |
127 | * | |
128 | * Interrupt handling functions | |
129 | * | |
130 | ****************************************************************************/ | |
131 | ||
90008ee4 JR |
132 | static void iommu_print_event(void *__evt) |
133 | { | |
134 | u32 *event = __evt; | |
135 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
136 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
137 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
138 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
139 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
140 | ||
141 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
142 | ||
143 | switch (type) { | |
144 | case EVENT_TYPE_ILL_DEV: | |
145 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
146 | "address=0x%016llx flags=0x%04x]\n", | |
147 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
148 | address, flags); | |
149 | break; | |
150 | case EVENT_TYPE_IO_FAULT: | |
151 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
152 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
153 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
154 | domid, address, flags); | |
155 | break; | |
156 | case EVENT_TYPE_DEV_TAB_ERR: | |
157 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
158 | "address=0x%016llx flags=0x%04x]\n", | |
159 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
160 | address, flags); | |
161 | break; | |
162 | case EVENT_TYPE_PAGE_TAB_ERR: | |
163 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
164 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
165 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
166 | domid, address, flags); | |
167 | break; | |
168 | case EVENT_TYPE_ILL_CMD: | |
169 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
170 | break; | |
171 | case EVENT_TYPE_CMD_HARD_ERR: | |
172 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
173 | "flags=0x%04x]\n", address, flags); | |
174 | break; | |
175 | case EVENT_TYPE_IOTLB_INV_TO: | |
176 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
177 | "address=0x%016llx]\n", | |
178 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
179 | address); | |
180 | break; | |
181 | case EVENT_TYPE_INV_DEV_REQ: | |
182 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
183 | "address=0x%016llx flags=0x%04x]\n", | |
184 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
185 | address, flags); | |
186 | break; | |
187 | default: | |
188 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
189 | } | |
190 | } | |
191 | ||
192 | static void iommu_poll_events(struct amd_iommu *iommu) | |
193 | { | |
194 | u32 head, tail; | |
195 | unsigned long flags; | |
196 | ||
197 | spin_lock_irqsave(&iommu->lock, flags); | |
198 | ||
199 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
200 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
201 | ||
202 | while (head != tail) { | |
203 | iommu_print_event(iommu->evt_buf + head); | |
204 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
205 | } | |
206 | ||
207 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
208 | ||
209 | spin_unlock_irqrestore(&iommu->lock, flags); | |
210 | } | |
211 | ||
a80dc3e0 JR |
212 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
213 | { | |
90008ee4 JR |
214 | struct amd_iommu *iommu; |
215 | ||
216 | list_for_each_entry(iommu, &amd_iommu_list, list) | |
217 | iommu_poll_events(iommu); | |
218 | ||
219 | return IRQ_HANDLED; | |
a80dc3e0 JR |
220 | } |
221 | ||
431b2a20 JR |
222 | /**************************************************************************** |
223 | * | |
224 | * IOMMU command queuing functions | |
225 | * | |
226 | ****************************************************************************/ | |
227 | ||
228 | /* | |
229 | * Writes the command to the IOMMUs command buffer and informs the | |
230 | * hardware about the new command. Must be called with iommu->lock held. | |
231 | */ | |
d6449536 | 232 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
233 | { |
234 | u32 tail, head; | |
235 | u8 *target; | |
236 | ||
237 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 238 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
239 | memcpy_toio(target, cmd, sizeof(*cmd)); |
240 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
241 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
242 | if (tail == head) | |
243 | return -ENOMEM; | |
244 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
431b2a20 JR |
249 | /* |
250 | * General queuing function for commands. Takes iommu->lock and calls | |
251 | * __iommu_queue_command(). | |
252 | */ | |
d6449536 | 253 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
254 | { |
255 | unsigned long flags; | |
256 | int ret; | |
257 | ||
258 | spin_lock_irqsave(&iommu->lock, flags); | |
259 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 260 | if (!ret) |
0cfd7aa9 | 261 | iommu->need_sync = true; |
a19ae1ec JR |
262 | spin_unlock_irqrestore(&iommu->lock, flags); |
263 | ||
264 | return ret; | |
265 | } | |
266 | ||
8d201968 JR |
267 | /* |
268 | * This function waits until an IOMMU has completed a completion | |
269 | * wait command | |
270 | */ | |
271 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
272 | { | |
273 | int ready = 0; | |
274 | unsigned status = 0; | |
275 | unsigned long i = 0; | |
276 | ||
da49f6df JR |
277 | INC_STATS_COUNTER(compl_wait); |
278 | ||
8d201968 JR |
279 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
280 | ++i; | |
281 | /* wait for the bit to become one */ | |
282 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
283 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
284 | } | |
285 | ||
286 | /* set bit back to zero */ | |
287 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
288 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
289 | ||
290 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
291 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
292 | } | |
293 | ||
294 | /* | |
295 | * This function queues a completion wait command into the command | |
296 | * buffer of an IOMMU | |
297 | */ | |
298 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
299 | { | |
300 | struct iommu_cmd cmd; | |
301 | ||
302 | memset(&cmd, 0, sizeof(cmd)); | |
303 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
304 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
305 | ||
306 | return __iommu_queue_command(iommu, &cmd); | |
307 | } | |
308 | ||
431b2a20 JR |
309 | /* |
310 | * This function is called whenever we need to ensure that the IOMMU has | |
311 | * completed execution of all commands we sent. It sends a | |
312 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
313 | * us about that by writing a value to a physical address we pass with | |
314 | * the command. | |
315 | */ | |
a19ae1ec JR |
316 | static int iommu_completion_wait(struct amd_iommu *iommu) |
317 | { | |
8d201968 JR |
318 | int ret = 0; |
319 | unsigned long flags; | |
a19ae1ec | 320 | |
7e4f88da JR |
321 | spin_lock_irqsave(&iommu->lock, flags); |
322 | ||
09ee17eb JR |
323 | if (!iommu->need_sync) |
324 | goto out; | |
325 | ||
8d201968 | 326 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 327 | |
0cfd7aa9 | 328 | iommu->need_sync = false; |
a19ae1ec JR |
329 | |
330 | if (ret) | |
7e4f88da | 331 | goto out; |
a19ae1ec | 332 | |
8d201968 | 333 | __iommu_wait_for_completion(iommu); |
84df8175 | 334 | |
7e4f88da JR |
335 | out: |
336 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
337 | |
338 | return 0; | |
339 | } | |
340 | ||
431b2a20 JR |
341 | /* |
342 | * Command send function for invalidating a device table entry | |
343 | */ | |
a19ae1ec JR |
344 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
345 | { | |
d6449536 | 346 | struct iommu_cmd cmd; |
ee2fa743 | 347 | int ret; |
a19ae1ec JR |
348 | |
349 | BUG_ON(iommu == NULL); | |
350 | ||
351 | memset(&cmd, 0, sizeof(cmd)); | |
352 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
353 | cmd.data[0] = devid; | |
354 | ||
ee2fa743 JR |
355 | ret = iommu_queue_command(iommu, &cmd); |
356 | ||
ee2fa743 | 357 | return ret; |
a19ae1ec JR |
358 | } |
359 | ||
237b6f33 JR |
360 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
361 | u16 domid, int pde, int s) | |
362 | { | |
363 | memset(cmd, 0, sizeof(*cmd)); | |
364 | address &= PAGE_MASK; | |
365 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
366 | cmd->data[1] |= domid; | |
367 | cmd->data[2] = lower_32_bits(address); | |
368 | cmd->data[3] = upper_32_bits(address); | |
369 | if (s) /* size bit - we flush more than one 4kb page */ | |
370 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
371 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
372 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
373 | } | |
374 | ||
431b2a20 JR |
375 | /* |
376 | * Generic command send function for invalidaing TLB entries | |
377 | */ | |
a19ae1ec JR |
378 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
379 | u64 address, u16 domid, int pde, int s) | |
380 | { | |
d6449536 | 381 | struct iommu_cmd cmd; |
ee2fa743 | 382 | int ret; |
a19ae1ec | 383 | |
237b6f33 | 384 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 385 | |
ee2fa743 JR |
386 | ret = iommu_queue_command(iommu, &cmd); |
387 | ||
ee2fa743 | 388 | return ret; |
a19ae1ec JR |
389 | } |
390 | ||
431b2a20 JR |
391 | /* |
392 | * TLB invalidation function which is called from the mapping functions. | |
393 | * It invalidates a single PTE if the range to flush is within a single | |
394 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
395 | */ | |
a19ae1ec JR |
396 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
397 | u64 address, size_t size) | |
398 | { | |
999ba417 | 399 | int s = 0; |
e3c449f5 | 400 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
401 | |
402 | address &= PAGE_MASK; | |
403 | ||
999ba417 JR |
404 | if (pages > 1) { |
405 | /* | |
406 | * If we have to flush more than one page, flush all | |
407 | * TLB entries for this domain | |
408 | */ | |
409 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
410 | s = 1; | |
a19ae1ec JR |
411 | } |
412 | ||
999ba417 JR |
413 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
414 | ||
a19ae1ec JR |
415 | return 0; |
416 | } | |
b6c02715 | 417 | |
1c655773 JR |
418 | /* Flush the whole IO/TLB for a given protection domain */ |
419 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
420 | { | |
421 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
422 | ||
f57d98ae JR |
423 | INC_STATS_COUNTER(domain_flush_single); |
424 | ||
1c655773 JR |
425 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
426 | } | |
427 | ||
43f49609 JR |
428 | /* |
429 | * This function is used to flush the IO/TLB for a given protection domain | |
430 | * on every IOMMU in the system | |
431 | */ | |
432 | static void iommu_flush_domain(u16 domid) | |
433 | { | |
434 | unsigned long flags; | |
435 | struct amd_iommu *iommu; | |
436 | struct iommu_cmd cmd; | |
437 | ||
18811f55 JR |
438 | INC_STATS_COUNTER(domain_flush_all); |
439 | ||
43f49609 JR |
440 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
441 | domid, 1, 1); | |
442 | ||
443 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
444 | spin_lock_irqsave(&iommu->lock, flags); | |
445 | __iommu_queue_command(iommu, &cmd); | |
446 | __iommu_completion_wait(iommu); | |
447 | __iommu_wait_for_completion(iommu); | |
448 | spin_unlock_irqrestore(&iommu->lock, flags); | |
449 | } | |
450 | } | |
43f49609 | 451 | |
431b2a20 JR |
452 | /**************************************************************************** |
453 | * | |
454 | * The functions below are used the create the page table mappings for | |
455 | * unity mapped regions. | |
456 | * | |
457 | ****************************************************************************/ | |
458 | ||
459 | /* | |
460 | * Generic mapping functions. It maps a physical address into a DMA | |
461 | * address space. It allocates the page table pages if necessary. | |
462 | * In the future it can be extended to a generic mapping function | |
463 | * supporting all features of AMD IOMMU page tables like level skipping | |
464 | * and full 64 bit address spaces. | |
465 | */ | |
38e817fe JR |
466 | static int iommu_map_page(struct protection_domain *dom, |
467 | unsigned long bus_addr, | |
468 | unsigned long phys_addr, | |
469 | int prot) | |
bd0e5211 JR |
470 | { |
471 | u64 __pte, *pte, *page; | |
472 | ||
473 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 474 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
475 | |
476 | /* only support 512GB address spaces for now */ | |
477 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
478 | return -EINVAL; | |
479 | ||
480 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
481 | ||
482 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
483 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
484 | if (!page) | |
485 | return -ENOMEM; | |
486 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
487 | } | |
488 | ||
489 | pte = IOMMU_PTE_PAGE(*pte); | |
490 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
491 | ||
492 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
493 | page = (u64 *)get_zeroed_page(GFP_KERNEL); | |
494 | if (!page) | |
495 | return -ENOMEM; | |
496 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
497 | } | |
498 | ||
499 | pte = IOMMU_PTE_PAGE(*pte); | |
500 | pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)]; | |
501 | ||
502 | if (IOMMU_PTE_PRESENT(*pte)) | |
503 | return -EBUSY; | |
504 | ||
505 | __pte = phys_addr | IOMMU_PTE_P; | |
506 | if (prot & IOMMU_PROT_IR) | |
507 | __pte |= IOMMU_PTE_IR; | |
508 | if (prot & IOMMU_PROT_IW) | |
509 | __pte |= IOMMU_PTE_IW; | |
510 | ||
511 | *pte = __pte; | |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
eb74ff6c JR |
516 | static void iommu_unmap_page(struct protection_domain *dom, |
517 | unsigned long bus_addr) | |
518 | { | |
519 | u64 *pte; | |
520 | ||
521 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
522 | ||
523 | if (!IOMMU_PTE_PRESENT(*pte)) | |
524 | return; | |
525 | ||
526 | pte = IOMMU_PTE_PAGE(*pte); | |
527 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
528 | ||
529 | if (!IOMMU_PTE_PRESENT(*pte)) | |
530 | return; | |
531 | ||
532 | pte = IOMMU_PTE_PAGE(*pte); | |
533 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
534 | ||
535 | *pte = 0; | |
536 | } | |
eb74ff6c | 537 | |
431b2a20 JR |
538 | /* |
539 | * This function checks if a specific unity mapping entry is needed for | |
540 | * this specific IOMMU. | |
541 | */ | |
bd0e5211 JR |
542 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
543 | struct unity_map_entry *entry) | |
544 | { | |
545 | u16 bdf, i; | |
546 | ||
547 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
548 | bdf = amd_iommu_alias_table[i]; | |
549 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
550 | return 1; | |
551 | } | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
431b2a20 JR |
556 | /* |
557 | * Init the unity mappings for a specific IOMMU in the system | |
558 | * | |
559 | * Basically iterates over all unity mapping entries and applies them to | |
560 | * the default domain DMA of that IOMMU if necessary. | |
561 | */ | |
bd0e5211 JR |
562 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
563 | { | |
564 | struct unity_map_entry *entry; | |
565 | int ret; | |
566 | ||
567 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
568 | if (!iommu_for_unity_map(iommu, entry)) | |
569 | continue; | |
570 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
571 | if (ret) | |
572 | return ret; | |
573 | } | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
431b2a20 JR |
578 | /* |
579 | * This function actually applies the mapping to the page table of the | |
580 | * dma_ops domain. | |
581 | */ | |
bd0e5211 JR |
582 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
583 | struct unity_map_entry *e) | |
584 | { | |
585 | u64 addr; | |
586 | int ret; | |
587 | ||
588 | for (addr = e->address_start; addr < e->address_end; | |
589 | addr += PAGE_SIZE) { | |
38e817fe | 590 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
591 | if (ret) |
592 | return ret; | |
593 | /* | |
594 | * if unity mapping is in aperture range mark the page | |
595 | * as allocated in the aperture | |
596 | */ | |
597 | if (addr < dma_dom->aperture_size) | |
598 | __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap); | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
431b2a20 JR |
604 | /* |
605 | * Inits the unity mappings required for a specific device | |
606 | */ | |
bd0e5211 JR |
607 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
608 | u16 devid) | |
609 | { | |
610 | struct unity_map_entry *e; | |
611 | int ret; | |
612 | ||
613 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
614 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
615 | continue; | |
616 | ret = dma_ops_unity_map(dma_dom, e); | |
617 | if (ret) | |
618 | return ret; | |
619 | } | |
620 | ||
621 | return 0; | |
622 | } | |
623 | ||
431b2a20 JR |
624 | /**************************************************************************** |
625 | * | |
626 | * The next functions belong to the address allocator for the dma_ops | |
627 | * interface functions. They work like the allocators in the other IOMMU | |
628 | * drivers. Its basically a bitmap which marks the allocated pages in | |
629 | * the aperture. Maybe it could be enhanced in the future to a more | |
630 | * efficient allocator. | |
631 | * | |
632 | ****************************************************************************/ | |
d3086444 | 633 | |
431b2a20 JR |
634 | /* |
635 | * The address allocator core function. | |
636 | * | |
637 | * called with domain->lock held | |
638 | */ | |
d3086444 JR |
639 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
640 | struct dma_ops_domain *dom, | |
6d4f343f | 641 | unsigned int pages, |
832a90c3 JR |
642 | unsigned long align_mask, |
643 | u64 dma_mask) | |
d3086444 | 644 | { |
40becd8d | 645 | unsigned long limit; |
d3086444 | 646 | unsigned long address; |
d3086444 JR |
647 | unsigned long boundary_size; |
648 | ||
649 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
650 | PAGE_SIZE) >> PAGE_SHIFT; | |
40becd8d FT |
651 | limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0, |
652 | dma_mask >> PAGE_SHIFT); | |
d3086444 | 653 | |
1c655773 | 654 | if (dom->next_bit >= limit) { |
d3086444 | 655 | dom->next_bit = 0; |
1c655773 JR |
656 | dom->need_flush = true; |
657 | } | |
d3086444 JR |
658 | |
659 | address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages, | |
6d4f343f | 660 | 0 , boundary_size, align_mask); |
1c655773 | 661 | if (address == -1) { |
d3086444 | 662 | address = iommu_area_alloc(dom->bitmap, limit, 0, pages, |
6d4f343f | 663 | 0, boundary_size, align_mask); |
1c655773 JR |
664 | dom->need_flush = true; |
665 | } | |
d3086444 JR |
666 | |
667 | if (likely(address != -1)) { | |
d3086444 JR |
668 | dom->next_bit = address + pages; |
669 | address <<= PAGE_SHIFT; | |
670 | } else | |
671 | address = bad_dma_address; | |
672 | ||
673 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
674 | ||
675 | return address; | |
676 | } | |
677 | ||
431b2a20 JR |
678 | /* |
679 | * The address free function. | |
680 | * | |
681 | * called with domain->lock held | |
682 | */ | |
d3086444 JR |
683 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
684 | unsigned long address, | |
685 | unsigned int pages) | |
686 | { | |
687 | address >>= PAGE_SHIFT; | |
688 | iommu_area_free(dom->bitmap, address, pages); | |
80be308d | 689 | |
8501c45c | 690 | if (address >= dom->next_bit) |
80be308d | 691 | dom->need_flush = true; |
d3086444 JR |
692 | } |
693 | ||
431b2a20 JR |
694 | /**************************************************************************** |
695 | * | |
696 | * The next functions belong to the domain allocation. A domain is | |
697 | * allocated for every IOMMU as the default domain. If device isolation | |
698 | * is enabled, every device get its own domain. The most important thing | |
699 | * about domains is the page table mapping the DMA address space they | |
700 | * contain. | |
701 | * | |
702 | ****************************************************************************/ | |
703 | ||
ec487d1a JR |
704 | static u16 domain_id_alloc(void) |
705 | { | |
706 | unsigned long flags; | |
707 | int id; | |
708 | ||
709 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
710 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
711 | BUG_ON(id == 0); | |
712 | if (id > 0 && id < MAX_DOMAIN_ID) | |
713 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
714 | else | |
715 | id = 0; | |
716 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
717 | ||
718 | return id; | |
719 | } | |
720 | ||
a2acfb75 JR |
721 | static void domain_id_free(int id) |
722 | { | |
723 | unsigned long flags; | |
724 | ||
725 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
726 | if (id > 0 && id < MAX_DOMAIN_ID) | |
727 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
728 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
729 | } | |
a2acfb75 | 730 | |
431b2a20 JR |
731 | /* |
732 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
733 | * ranges. | |
734 | */ | |
ec487d1a JR |
735 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
736 | unsigned long start_page, | |
737 | unsigned int pages) | |
738 | { | |
739 | unsigned int last_page = dom->aperture_size >> PAGE_SHIFT; | |
740 | ||
741 | if (start_page + pages > last_page) | |
742 | pages = last_page - start_page; | |
743 | ||
d26dbc5c | 744 | iommu_area_reserve(dom->bitmap, start_page, pages); |
ec487d1a JR |
745 | } |
746 | ||
86db2e5d | 747 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
748 | { |
749 | int i, j; | |
750 | u64 *p1, *p2, *p3; | |
751 | ||
86db2e5d | 752 | p1 = domain->pt_root; |
ec487d1a JR |
753 | |
754 | if (!p1) | |
755 | return; | |
756 | ||
757 | for (i = 0; i < 512; ++i) { | |
758 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
759 | continue; | |
760 | ||
761 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 762 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
763 | if (!IOMMU_PTE_PRESENT(p2[j])) |
764 | continue; | |
765 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
766 | free_page((unsigned long)p3); | |
767 | } | |
768 | ||
769 | free_page((unsigned long)p2); | |
770 | } | |
771 | ||
772 | free_page((unsigned long)p1); | |
86db2e5d JR |
773 | |
774 | domain->pt_root = NULL; | |
ec487d1a JR |
775 | } |
776 | ||
431b2a20 JR |
777 | /* |
778 | * Free a domain, only used if something went wrong in the | |
779 | * allocation path and we need to free an already allocated page table | |
780 | */ | |
ec487d1a JR |
781 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
782 | { | |
783 | if (!dom) | |
784 | return; | |
785 | ||
86db2e5d | 786 | free_pagetable(&dom->domain); |
ec487d1a JR |
787 | |
788 | kfree(dom->pte_pages); | |
789 | ||
790 | kfree(dom->bitmap); | |
791 | ||
792 | kfree(dom); | |
793 | } | |
794 | ||
431b2a20 JR |
795 | /* |
796 | * Allocates a new protection domain usable for the dma_ops functions. | |
797 | * It also intializes the page table and the address allocator data | |
798 | * structures required for the dma_ops interface | |
799 | */ | |
ec487d1a JR |
800 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu, |
801 | unsigned order) | |
802 | { | |
803 | struct dma_ops_domain *dma_dom; | |
804 | unsigned i, num_pte_pages; | |
805 | u64 *l2_pde; | |
806 | u64 address; | |
807 | ||
808 | /* | |
809 | * Currently the DMA aperture must be between 32 MB and 1GB in size | |
810 | */ | |
811 | if ((order < 25) || (order > 30)) | |
812 | return NULL; | |
813 | ||
814 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
815 | if (!dma_dom) | |
816 | return NULL; | |
817 | ||
818 | spin_lock_init(&dma_dom->domain.lock); | |
819 | ||
820 | dma_dom->domain.id = domain_id_alloc(); | |
821 | if (dma_dom->domain.id == 0) | |
822 | goto free_dma_dom; | |
823 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
824 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 825 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
826 | dma_dom->domain.priv = dma_dom; |
827 | if (!dma_dom->domain.pt_root) | |
828 | goto free_dma_dom; | |
829 | dma_dom->aperture_size = (1ULL << order); | |
830 | dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8), | |
831 | GFP_KERNEL); | |
832 | if (!dma_dom->bitmap) | |
833 | goto free_dma_dom; | |
834 | /* | |
835 | * mark the first page as allocated so we never return 0 as | |
836 | * a valid dma-address. So we can use 0 as error value | |
837 | */ | |
838 | dma_dom->bitmap[0] = 1; | |
839 | dma_dom->next_bit = 0; | |
840 | ||
1c655773 | 841 | dma_dom->need_flush = false; |
bd60b735 | 842 | dma_dom->target_dev = 0xffff; |
1c655773 | 843 | |
431b2a20 | 844 | /* Intialize the exclusion range if necessary */ |
ec487d1a JR |
845 | if (iommu->exclusion_start && |
846 | iommu->exclusion_start < dma_dom->aperture_size) { | |
847 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
e3c449f5 JR |
848 | int pages = iommu_num_pages(iommu->exclusion_start, |
849 | iommu->exclusion_length, | |
850 | PAGE_SIZE); | |
ec487d1a JR |
851 | dma_ops_reserve_addresses(dma_dom, startpage, pages); |
852 | } | |
853 | ||
431b2a20 JR |
854 | /* |
855 | * At the last step, build the page tables so we don't need to | |
856 | * allocate page table pages in the dma_ops mapping/unmapping | |
857 | * path. | |
858 | */ | |
ec487d1a JR |
859 | num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512); |
860 | dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *), | |
861 | GFP_KERNEL); | |
862 | if (!dma_dom->pte_pages) | |
863 | goto free_dma_dom; | |
864 | ||
865 | l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL); | |
866 | if (l2_pde == NULL) | |
867 | goto free_dma_dom; | |
868 | ||
869 | dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde)); | |
870 | ||
871 | for (i = 0; i < num_pte_pages; ++i) { | |
872 | dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL); | |
873 | if (!dma_dom->pte_pages[i]) | |
874 | goto free_dma_dom; | |
875 | address = virt_to_phys(dma_dom->pte_pages[i]); | |
876 | l2_pde[i] = IOMMU_L1_PDE(address); | |
877 | } | |
878 | ||
879 | return dma_dom; | |
880 | ||
881 | free_dma_dom: | |
882 | dma_ops_domain_free(dma_dom); | |
883 | ||
884 | return NULL; | |
885 | } | |
886 | ||
5b28df6f JR |
887 | /* |
888 | * little helper function to check whether a given protection domain is a | |
889 | * dma_ops domain | |
890 | */ | |
891 | static bool dma_ops_domain(struct protection_domain *domain) | |
892 | { | |
893 | return domain->flags & PD_DMA_OPS_MASK; | |
894 | } | |
895 | ||
431b2a20 JR |
896 | /* |
897 | * Find out the protection domain structure for a given PCI device. This | |
898 | * will give us the pointer to the page table root for example. | |
899 | */ | |
b20ac0d4 JR |
900 | static struct protection_domain *domain_for_device(u16 devid) |
901 | { | |
902 | struct protection_domain *dom; | |
903 | unsigned long flags; | |
904 | ||
905 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
906 | dom = amd_iommu_pd_table[devid]; | |
907 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
908 | ||
909 | return dom; | |
910 | } | |
911 | ||
431b2a20 JR |
912 | /* |
913 | * If a device is not yet associated with a domain, this function does | |
914 | * assigns it visible for the hardware | |
915 | */ | |
f1179dc0 JR |
916 | static void attach_device(struct amd_iommu *iommu, |
917 | struct protection_domain *domain, | |
918 | u16 devid) | |
b20ac0d4 JR |
919 | { |
920 | unsigned long flags; | |
b20ac0d4 JR |
921 | u64 pte_root = virt_to_phys(domain->pt_root); |
922 | ||
863c74eb JR |
923 | domain->dev_cnt += 1; |
924 | ||
38ddf41b JR |
925 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
926 | << DEV_ENTRY_MODE_SHIFT; | |
927 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
928 | |
929 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
930 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
931 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
932 | amd_iommu_dev_table[devid].data[2] = domain->id; |
933 | ||
934 | amd_iommu_pd_table[devid] = domain; | |
935 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
936 | ||
937 | iommu_queue_inv_dev_entry(iommu, devid); | |
b20ac0d4 JR |
938 | } |
939 | ||
355bf553 JR |
940 | /* |
941 | * Removes a device from a protection domain (unlocked) | |
942 | */ | |
943 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
944 | { | |
945 | ||
946 | /* lock domain */ | |
947 | spin_lock(&domain->lock); | |
948 | ||
949 | /* remove domain from the lookup table */ | |
950 | amd_iommu_pd_table[devid] = NULL; | |
951 | ||
952 | /* remove entry from the device table seen by the hardware */ | |
953 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
954 | amd_iommu_dev_table[devid].data[1] = 0; | |
955 | amd_iommu_dev_table[devid].data[2] = 0; | |
956 | ||
957 | /* decrease reference counter */ | |
958 | domain->dev_cnt -= 1; | |
959 | ||
960 | /* ready */ | |
961 | spin_unlock(&domain->lock); | |
962 | } | |
963 | ||
964 | /* | |
965 | * Removes a device from a protection domain (with devtable_lock held) | |
966 | */ | |
967 | static void detach_device(struct protection_domain *domain, u16 devid) | |
968 | { | |
969 | unsigned long flags; | |
970 | ||
971 | /* lock device table */ | |
972 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
973 | __detach_device(domain, devid); | |
974 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
975 | } | |
e275a2a0 JR |
976 | |
977 | static int device_change_notifier(struct notifier_block *nb, | |
978 | unsigned long action, void *data) | |
979 | { | |
980 | struct device *dev = data; | |
981 | struct pci_dev *pdev = to_pci_dev(dev); | |
982 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
983 | struct protection_domain *domain; | |
984 | struct dma_ops_domain *dma_domain; | |
985 | struct amd_iommu *iommu; | |
1ac4cbbc JR |
986 | int order = amd_iommu_aperture_order; |
987 | unsigned long flags; | |
e275a2a0 JR |
988 | |
989 | if (devid > amd_iommu_last_bdf) | |
990 | goto out; | |
991 | ||
992 | devid = amd_iommu_alias_table[devid]; | |
993 | ||
994 | iommu = amd_iommu_rlookup_table[devid]; | |
995 | if (iommu == NULL) | |
996 | goto out; | |
997 | ||
998 | domain = domain_for_device(devid); | |
999 | ||
1000 | if (domain && !dma_ops_domain(domain)) | |
1001 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1002 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1003 | ||
1004 | switch (action) { | |
1005 | case BUS_NOTIFY_BOUND_DRIVER: | |
1006 | if (domain) | |
1007 | goto out; | |
1008 | dma_domain = find_protection_domain(devid); | |
1009 | if (!dma_domain) | |
1010 | dma_domain = iommu->default_dom; | |
1011 | attach_device(iommu, &dma_domain->domain, devid); | |
1012 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " | |
1013 | "device %s\n", dma_domain->domain.id, dev_name(dev)); | |
1014 | break; | |
1015 | case BUS_NOTIFY_UNBIND_DRIVER: | |
1016 | if (!domain) | |
1017 | goto out; | |
1018 | detach_device(domain, devid); | |
1ac4cbbc JR |
1019 | break; |
1020 | case BUS_NOTIFY_ADD_DEVICE: | |
1021 | /* allocate a protection domain if a device is added */ | |
1022 | dma_domain = find_protection_domain(devid); | |
1023 | if (dma_domain) | |
1024 | goto out; | |
1025 | dma_domain = dma_ops_domain_alloc(iommu, order); | |
1026 | if (!dma_domain) | |
1027 | goto out; | |
1028 | dma_domain->target_dev = devid; | |
1029 | ||
1030 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1031 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1032 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1033 | ||
e275a2a0 JR |
1034 | break; |
1035 | default: | |
1036 | goto out; | |
1037 | } | |
1038 | ||
1039 | iommu_queue_inv_dev_entry(iommu, devid); | |
1040 | iommu_completion_wait(iommu); | |
1041 | ||
1042 | out: | |
1043 | return 0; | |
1044 | } | |
1045 | ||
1046 | struct notifier_block device_nb = { | |
1047 | .notifier_call = device_change_notifier, | |
1048 | }; | |
355bf553 | 1049 | |
431b2a20 JR |
1050 | /***************************************************************************** |
1051 | * | |
1052 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1053 | * | |
1054 | *****************************************************************************/ | |
1055 | ||
dbcc112e JR |
1056 | /* |
1057 | * This function checks if the driver got a valid device from the caller to | |
1058 | * avoid dereferencing invalid pointers. | |
1059 | */ | |
1060 | static bool check_device(struct device *dev) | |
1061 | { | |
1062 | if (!dev || !dev->dma_mask) | |
1063 | return false; | |
1064 | ||
1065 | return true; | |
1066 | } | |
1067 | ||
bd60b735 JR |
1068 | /* |
1069 | * In this function the list of preallocated protection domains is traversed to | |
1070 | * find the domain for a specific device | |
1071 | */ | |
1072 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1073 | { | |
1074 | struct dma_ops_domain *entry, *ret = NULL; | |
1075 | unsigned long flags; | |
1076 | ||
1077 | if (list_empty(&iommu_pd_list)) | |
1078 | return NULL; | |
1079 | ||
1080 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1081 | ||
1082 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1083 | if (entry->target_dev == devid) { | |
1084 | ret = entry; | |
bd60b735 JR |
1085 | break; |
1086 | } | |
1087 | } | |
1088 | ||
1089 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1090 | ||
1091 | return ret; | |
1092 | } | |
1093 | ||
431b2a20 JR |
1094 | /* |
1095 | * In the dma_ops path we only have the struct device. This function | |
1096 | * finds the corresponding IOMMU, the protection domain and the | |
1097 | * requestor id for a given device. | |
1098 | * If the device is not yet associated with a domain this is also done | |
1099 | * in this function. | |
1100 | */ | |
b20ac0d4 JR |
1101 | static int get_device_resources(struct device *dev, |
1102 | struct amd_iommu **iommu, | |
1103 | struct protection_domain **domain, | |
1104 | u16 *bdf) | |
1105 | { | |
1106 | struct dma_ops_domain *dma_dom; | |
1107 | struct pci_dev *pcidev; | |
1108 | u16 _bdf; | |
1109 | ||
dbcc112e JR |
1110 | *iommu = NULL; |
1111 | *domain = NULL; | |
1112 | *bdf = 0xffff; | |
1113 | ||
1114 | if (dev->bus != &pci_bus_type) | |
1115 | return 0; | |
b20ac0d4 JR |
1116 | |
1117 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1118 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1119 | |
431b2a20 | 1120 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1121 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1122 | return 0; |
b20ac0d4 JR |
1123 | |
1124 | *bdf = amd_iommu_alias_table[_bdf]; | |
1125 | ||
1126 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1127 | if (*iommu == NULL) | |
1128 | return 0; | |
b20ac0d4 JR |
1129 | *domain = domain_for_device(*bdf); |
1130 | if (*domain == NULL) { | |
bd60b735 JR |
1131 | dma_dom = find_protection_domain(*bdf); |
1132 | if (!dma_dom) | |
1133 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1134 | *domain = &dma_dom->domain; |
f1179dc0 | 1135 | attach_device(*iommu, *domain, *bdf); |
b20ac0d4 | 1136 | printk(KERN_INFO "AMD IOMMU: Using protection domain %d for " |
ab896722 | 1137 | "device %s\n", (*domain)->id, dev_name(dev)); |
b20ac0d4 JR |
1138 | } |
1139 | ||
f91ba190 | 1140 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1141 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1142 | |
b20ac0d4 JR |
1143 | return 1; |
1144 | } | |
1145 | ||
431b2a20 JR |
1146 | /* |
1147 | * This is the generic map function. It maps one 4kb page at paddr to | |
1148 | * the given address in the DMA address space for the domain. | |
1149 | */ | |
cb76c322 JR |
1150 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1151 | struct dma_ops_domain *dom, | |
1152 | unsigned long address, | |
1153 | phys_addr_t paddr, | |
1154 | int direction) | |
1155 | { | |
1156 | u64 *pte, __pte; | |
1157 | ||
1158 | WARN_ON(address > dom->aperture_size); | |
1159 | ||
1160 | paddr &= PAGE_MASK; | |
1161 | ||
1162 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1163 | pte += IOMMU_PTE_L0_INDEX(address); | |
1164 | ||
1165 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1166 | ||
1167 | if (direction == DMA_TO_DEVICE) | |
1168 | __pte |= IOMMU_PTE_IR; | |
1169 | else if (direction == DMA_FROM_DEVICE) | |
1170 | __pte |= IOMMU_PTE_IW; | |
1171 | else if (direction == DMA_BIDIRECTIONAL) | |
1172 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1173 | ||
1174 | WARN_ON(*pte); | |
1175 | ||
1176 | *pte = __pte; | |
1177 | ||
1178 | return (dma_addr_t)address; | |
1179 | } | |
1180 | ||
431b2a20 JR |
1181 | /* |
1182 | * The generic unmapping function for on page in the DMA address space. | |
1183 | */ | |
cb76c322 JR |
1184 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1185 | struct dma_ops_domain *dom, | |
1186 | unsigned long address) | |
1187 | { | |
1188 | u64 *pte; | |
1189 | ||
1190 | if (address >= dom->aperture_size) | |
1191 | return; | |
1192 | ||
8ad909c4 | 1193 | WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size); |
cb76c322 JR |
1194 | |
1195 | pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)]; | |
1196 | pte += IOMMU_PTE_L0_INDEX(address); | |
1197 | ||
1198 | WARN_ON(!*pte); | |
1199 | ||
1200 | *pte = 0ULL; | |
1201 | } | |
1202 | ||
431b2a20 JR |
1203 | /* |
1204 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1205 | * contiguous memory region into DMA address space. It is used by all |
1206 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1207 | * Must be called with the domain lock held. |
1208 | */ | |
cb76c322 JR |
1209 | static dma_addr_t __map_single(struct device *dev, |
1210 | struct amd_iommu *iommu, | |
1211 | struct dma_ops_domain *dma_dom, | |
1212 | phys_addr_t paddr, | |
1213 | size_t size, | |
6d4f343f | 1214 | int dir, |
832a90c3 JR |
1215 | bool align, |
1216 | u64 dma_mask) | |
cb76c322 JR |
1217 | { |
1218 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
1219 | dma_addr_t address, start; | |
1220 | unsigned int pages; | |
6d4f343f | 1221 | unsigned long align_mask = 0; |
cb76c322 JR |
1222 | int i; |
1223 | ||
e3c449f5 | 1224 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1225 | paddr &= PAGE_MASK; |
1226 | ||
8ecaf8f1 JR |
1227 | INC_STATS_COUNTER(total_map_requests); |
1228 | ||
c1858976 JR |
1229 | if (pages > 1) |
1230 | INC_STATS_COUNTER(cross_page); | |
1231 | ||
6d4f343f JR |
1232 | if (align) |
1233 | align_mask = (1UL << get_order(size)) - 1; | |
1234 | ||
832a90c3 JR |
1235 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1236 | dma_mask); | |
cb76c322 JR |
1237 | if (unlikely(address == bad_dma_address)) |
1238 | goto out; | |
1239 | ||
1240 | start = address; | |
1241 | for (i = 0; i < pages; ++i) { | |
1242 | dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); | |
1243 | paddr += PAGE_SIZE; | |
1244 | start += PAGE_SIZE; | |
1245 | } | |
1246 | address += offset; | |
1247 | ||
5774f7c5 JR |
1248 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1249 | ||
afa9fdc2 | 1250 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1251 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1252 | dma_dom->need_flush = false; | |
1253 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1254 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1255 | ||
cb76c322 JR |
1256 | out: |
1257 | return address; | |
1258 | } | |
1259 | ||
431b2a20 JR |
1260 | /* |
1261 | * Does the reverse of the __map_single function. Must be called with | |
1262 | * the domain lock held too | |
1263 | */ | |
cb76c322 JR |
1264 | static void __unmap_single(struct amd_iommu *iommu, |
1265 | struct dma_ops_domain *dma_dom, | |
1266 | dma_addr_t dma_addr, | |
1267 | size_t size, | |
1268 | int dir) | |
1269 | { | |
1270 | dma_addr_t i, start; | |
1271 | unsigned int pages; | |
1272 | ||
b8d9905d JR |
1273 | if ((dma_addr == bad_dma_address) || |
1274 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1275 | return; |
1276 | ||
e3c449f5 | 1277 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1278 | dma_addr &= PAGE_MASK; |
1279 | start = dma_addr; | |
1280 | ||
1281 | for (i = 0; i < pages; ++i) { | |
1282 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1283 | start += PAGE_SIZE; | |
1284 | } | |
1285 | ||
5774f7c5 JR |
1286 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1287 | ||
cb76c322 | 1288 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1289 | |
80be308d | 1290 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1291 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1292 | dma_dom->need_flush = false; |
1293 | } | |
cb76c322 JR |
1294 | } |
1295 | ||
431b2a20 JR |
1296 | /* |
1297 | * The exported map_single function for dma_ops. | |
1298 | */ | |
51491367 FT |
1299 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1300 | unsigned long offset, size_t size, | |
1301 | enum dma_data_direction dir, | |
1302 | struct dma_attrs *attrs) | |
4da70b9e JR |
1303 | { |
1304 | unsigned long flags; | |
1305 | struct amd_iommu *iommu; | |
1306 | struct protection_domain *domain; | |
1307 | u16 devid; | |
1308 | dma_addr_t addr; | |
832a90c3 | 1309 | u64 dma_mask; |
51491367 | 1310 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1311 | |
0f2a86f2 JR |
1312 | INC_STATS_COUNTER(cnt_map_single); |
1313 | ||
dbcc112e JR |
1314 | if (!check_device(dev)) |
1315 | return bad_dma_address; | |
1316 | ||
832a90c3 | 1317 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1318 | |
1319 | get_device_resources(dev, &iommu, &domain, &devid); | |
1320 | ||
1321 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1322 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1323 | return (dma_addr_t)paddr; |
1324 | ||
5b28df6f JR |
1325 | if (!dma_ops_domain(domain)) |
1326 | return bad_dma_address; | |
1327 | ||
4da70b9e | 1328 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1329 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1330 | dma_mask); | |
4da70b9e JR |
1331 | if (addr == bad_dma_address) |
1332 | goto out; | |
1333 | ||
09ee17eb | 1334 | iommu_completion_wait(iommu); |
4da70b9e JR |
1335 | |
1336 | out: | |
1337 | spin_unlock_irqrestore(&domain->lock, flags); | |
1338 | ||
1339 | return addr; | |
1340 | } | |
1341 | ||
431b2a20 JR |
1342 | /* |
1343 | * The exported unmap_single function for dma_ops. | |
1344 | */ | |
51491367 FT |
1345 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1346 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1347 | { |
1348 | unsigned long flags; | |
1349 | struct amd_iommu *iommu; | |
1350 | struct protection_domain *domain; | |
1351 | u16 devid; | |
1352 | ||
146a6917 JR |
1353 | INC_STATS_COUNTER(cnt_unmap_single); |
1354 | ||
dbcc112e JR |
1355 | if (!check_device(dev) || |
1356 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1357 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1358 | return; |
1359 | ||
5b28df6f JR |
1360 | if (!dma_ops_domain(domain)) |
1361 | return; | |
1362 | ||
4da70b9e JR |
1363 | spin_lock_irqsave(&domain->lock, flags); |
1364 | ||
1365 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1366 | ||
09ee17eb | 1367 | iommu_completion_wait(iommu); |
4da70b9e JR |
1368 | |
1369 | spin_unlock_irqrestore(&domain->lock, flags); | |
1370 | } | |
1371 | ||
431b2a20 JR |
1372 | /* |
1373 | * This is a special map_sg function which is used if we should map a | |
1374 | * device which is not handled by an AMD IOMMU in the system. | |
1375 | */ | |
65b050ad JR |
1376 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1377 | int nelems, int dir) | |
1378 | { | |
1379 | struct scatterlist *s; | |
1380 | int i; | |
1381 | ||
1382 | for_each_sg(sglist, s, nelems, i) { | |
1383 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1384 | s->dma_length = s->length; | |
1385 | } | |
1386 | ||
1387 | return nelems; | |
1388 | } | |
1389 | ||
431b2a20 JR |
1390 | /* |
1391 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1392 | * lists). | |
1393 | */ | |
65b050ad | 1394 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1395 | int nelems, enum dma_data_direction dir, |
1396 | struct dma_attrs *attrs) | |
65b050ad JR |
1397 | { |
1398 | unsigned long flags; | |
1399 | struct amd_iommu *iommu; | |
1400 | struct protection_domain *domain; | |
1401 | u16 devid; | |
1402 | int i; | |
1403 | struct scatterlist *s; | |
1404 | phys_addr_t paddr; | |
1405 | int mapped_elems = 0; | |
832a90c3 | 1406 | u64 dma_mask; |
65b050ad | 1407 | |
d03f067a JR |
1408 | INC_STATS_COUNTER(cnt_map_sg); |
1409 | ||
dbcc112e JR |
1410 | if (!check_device(dev)) |
1411 | return 0; | |
1412 | ||
832a90c3 | 1413 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1414 | |
1415 | get_device_resources(dev, &iommu, &domain, &devid); | |
1416 | ||
1417 | if (!iommu || !domain) | |
1418 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1419 | ||
5b28df6f JR |
1420 | if (!dma_ops_domain(domain)) |
1421 | return 0; | |
1422 | ||
65b050ad JR |
1423 | spin_lock_irqsave(&domain->lock, flags); |
1424 | ||
1425 | for_each_sg(sglist, s, nelems, i) { | |
1426 | paddr = sg_phys(s); | |
1427 | ||
1428 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1429 | paddr, s->length, dir, false, |
1430 | dma_mask); | |
65b050ad JR |
1431 | |
1432 | if (s->dma_address) { | |
1433 | s->dma_length = s->length; | |
1434 | mapped_elems++; | |
1435 | } else | |
1436 | goto unmap; | |
65b050ad JR |
1437 | } |
1438 | ||
09ee17eb | 1439 | iommu_completion_wait(iommu); |
65b050ad JR |
1440 | |
1441 | out: | |
1442 | spin_unlock_irqrestore(&domain->lock, flags); | |
1443 | ||
1444 | return mapped_elems; | |
1445 | unmap: | |
1446 | for_each_sg(sglist, s, mapped_elems, i) { | |
1447 | if (s->dma_address) | |
1448 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1449 | s->dma_length, dir); | |
1450 | s->dma_address = s->dma_length = 0; | |
1451 | } | |
1452 | ||
1453 | mapped_elems = 0; | |
1454 | ||
1455 | goto out; | |
1456 | } | |
1457 | ||
431b2a20 JR |
1458 | /* |
1459 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1460 | * lists). | |
1461 | */ | |
65b050ad | 1462 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1463 | int nelems, enum dma_data_direction dir, |
1464 | struct dma_attrs *attrs) | |
65b050ad JR |
1465 | { |
1466 | unsigned long flags; | |
1467 | struct amd_iommu *iommu; | |
1468 | struct protection_domain *domain; | |
1469 | struct scatterlist *s; | |
1470 | u16 devid; | |
1471 | int i; | |
1472 | ||
55877a6b JR |
1473 | INC_STATS_COUNTER(cnt_unmap_sg); |
1474 | ||
dbcc112e JR |
1475 | if (!check_device(dev) || |
1476 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1477 | return; |
1478 | ||
5b28df6f JR |
1479 | if (!dma_ops_domain(domain)) |
1480 | return; | |
1481 | ||
65b050ad JR |
1482 | spin_lock_irqsave(&domain->lock, flags); |
1483 | ||
1484 | for_each_sg(sglist, s, nelems, i) { | |
1485 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1486 | s->dma_length, dir); | |
65b050ad JR |
1487 | s->dma_address = s->dma_length = 0; |
1488 | } | |
1489 | ||
09ee17eb | 1490 | iommu_completion_wait(iommu); |
65b050ad JR |
1491 | |
1492 | spin_unlock_irqrestore(&domain->lock, flags); | |
1493 | } | |
1494 | ||
431b2a20 JR |
1495 | /* |
1496 | * The exported alloc_coherent function for dma_ops. | |
1497 | */ | |
5d8b53cf JR |
1498 | static void *alloc_coherent(struct device *dev, size_t size, |
1499 | dma_addr_t *dma_addr, gfp_t flag) | |
1500 | { | |
1501 | unsigned long flags; | |
1502 | void *virt_addr; | |
1503 | struct amd_iommu *iommu; | |
1504 | struct protection_domain *domain; | |
1505 | u16 devid; | |
1506 | phys_addr_t paddr; | |
832a90c3 | 1507 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1508 | |
c8f0fb36 JR |
1509 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1510 | ||
dbcc112e JR |
1511 | if (!check_device(dev)) |
1512 | return NULL; | |
5d8b53cf | 1513 | |
13d9fead FT |
1514 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1515 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1516 | |
c97ac535 | 1517 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1518 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1519 | if (!virt_addr) | |
1520 | return 0; | |
1521 | ||
5d8b53cf JR |
1522 | paddr = virt_to_phys(virt_addr); |
1523 | ||
5d8b53cf JR |
1524 | if (!iommu || !domain) { |
1525 | *dma_addr = (dma_addr_t)paddr; | |
1526 | return virt_addr; | |
1527 | } | |
1528 | ||
5b28df6f JR |
1529 | if (!dma_ops_domain(domain)) |
1530 | goto out_free; | |
1531 | ||
832a90c3 JR |
1532 | if (!dma_mask) |
1533 | dma_mask = *dev->dma_mask; | |
1534 | ||
5d8b53cf JR |
1535 | spin_lock_irqsave(&domain->lock, flags); |
1536 | ||
1537 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1538 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1539 | |
5b28df6f JR |
1540 | if (*dma_addr == bad_dma_address) |
1541 | goto out_free; | |
5d8b53cf | 1542 | |
09ee17eb | 1543 | iommu_completion_wait(iommu); |
5d8b53cf | 1544 | |
5d8b53cf JR |
1545 | spin_unlock_irqrestore(&domain->lock, flags); |
1546 | ||
1547 | return virt_addr; | |
5b28df6f JR |
1548 | |
1549 | out_free: | |
1550 | ||
1551 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1552 | ||
1553 | return NULL; | |
5d8b53cf JR |
1554 | } |
1555 | ||
431b2a20 JR |
1556 | /* |
1557 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1558 | */ |
5d8b53cf JR |
1559 | static void free_coherent(struct device *dev, size_t size, |
1560 | void *virt_addr, dma_addr_t dma_addr) | |
1561 | { | |
1562 | unsigned long flags; | |
1563 | struct amd_iommu *iommu; | |
1564 | struct protection_domain *domain; | |
1565 | u16 devid; | |
1566 | ||
5d31ee7e JR |
1567 | INC_STATS_COUNTER(cnt_free_coherent); |
1568 | ||
dbcc112e JR |
1569 | if (!check_device(dev)) |
1570 | return; | |
1571 | ||
5d8b53cf JR |
1572 | get_device_resources(dev, &iommu, &domain, &devid); |
1573 | ||
1574 | if (!iommu || !domain) | |
1575 | goto free_mem; | |
1576 | ||
5b28df6f JR |
1577 | if (!dma_ops_domain(domain)) |
1578 | goto free_mem; | |
1579 | ||
5d8b53cf JR |
1580 | spin_lock_irqsave(&domain->lock, flags); |
1581 | ||
1582 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1583 | |
09ee17eb | 1584 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1585 | |
1586 | spin_unlock_irqrestore(&domain->lock, flags); | |
1587 | ||
1588 | free_mem: | |
1589 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1590 | } | |
1591 | ||
b39ba6ad JR |
1592 | /* |
1593 | * This function is called by the DMA layer to find out if we can handle a | |
1594 | * particular device. It is part of the dma_ops. | |
1595 | */ | |
1596 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1597 | { | |
1598 | u16 bdf; | |
1599 | struct pci_dev *pcidev; | |
1600 | ||
1601 | /* No device or no PCI device */ | |
1602 | if (!dev || dev->bus != &pci_bus_type) | |
1603 | return 0; | |
1604 | ||
1605 | pcidev = to_pci_dev(dev); | |
1606 | ||
1607 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1608 | ||
1609 | /* Out of our scope? */ | |
1610 | if (bdf > amd_iommu_last_bdf) | |
1611 | return 0; | |
1612 | ||
1613 | return 1; | |
1614 | } | |
1615 | ||
c432f3df | 1616 | /* |
431b2a20 JR |
1617 | * The function for pre-allocating protection domains. |
1618 | * | |
c432f3df JR |
1619 | * If the driver core informs the DMA layer if a driver grabs a device |
1620 | * we don't need to preallocate the protection domains anymore. | |
1621 | * For now we have to. | |
1622 | */ | |
0e93dd88 | 1623 | static void prealloc_protection_domains(void) |
c432f3df JR |
1624 | { |
1625 | struct pci_dev *dev = NULL; | |
1626 | struct dma_ops_domain *dma_dom; | |
1627 | struct amd_iommu *iommu; | |
1628 | int order = amd_iommu_aperture_order; | |
1629 | u16 devid; | |
1630 | ||
1631 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1632 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1633 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1634 | continue; |
1635 | devid = amd_iommu_alias_table[devid]; | |
1636 | if (domain_for_device(devid)) | |
1637 | continue; | |
1638 | iommu = amd_iommu_rlookup_table[devid]; | |
1639 | if (!iommu) | |
1640 | continue; | |
1641 | dma_dom = dma_ops_domain_alloc(iommu, order); | |
1642 | if (!dma_dom) | |
1643 | continue; | |
1644 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1645 | dma_dom->target_dev = devid; |
1646 | ||
1647 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1648 | } |
1649 | } | |
1650 | ||
160c1d8e | 1651 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1652 | .alloc_coherent = alloc_coherent, |
1653 | .free_coherent = free_coherent, | |
51491367 FT |
1654 | .map_page = map_page, |
1655 | .unmap_page = unmap_page, | |
6631ee9d JR |
1656 | .map_sg = map_sg, |
1657 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1658 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1659 | }; |
1660 | ||
431b2a20 JR |
1661 | /* |
1662 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1663 | */ | |
6631ee9d JR |
1664 | int __init amd_iommu_init_dma_ops(void) |
1665 | { | |
1666 | struct amd_iommu *iommu; | |
1667 | int order = amd_iommu_aperture_order; | |
1668 | int ret; | |
1669 | ||
431b2a20 JR |
1670 | /* |
1671 | * first allocate a default protection domain for every IOMMU we | |
1672 | * found in the system. Devices not assigned to any other | |
1673 | * protection domain will be assigned to the default one. | |
1674 | */ | |
6631ee9d JR |
1675 | list_for_each_entry(iommu, &amd_iommu_list, list) { |
1676 | iommu->default_dom = dma_ops_domain_alloc(iommu, order); | |
1677 | if (iommu->default_dom == NULL) | |
1678 | return -ENOMEM; | |
e2dc14a2 | 1679 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1680 | ret = iommu_init_unity_mappings(iommu); |
1681 | if (ret) | |
1682 | goto free_domains; | |
1683 | } | |
1684 | ||
431b2a20 JR |
1685 | /* |
1686 | * If device isolation is enabled, pre-allocate the protection | |
1687 | * domains for each device. | |
1688 | */ | |
6631ee9d JR |
1689 | if (amd_iommu_isolate) |
1690 | prealloc_protection_domains(); | |
1691 | ||
1692 | iommu_detected = 1; | |
1693 | force_iommu = 1; | |
1694 | bad_dma_address = 0; | |
92af4e29 | 1695 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1696 | gart_iommu_aperture_disabled = 1; |
1697 | gart_iommu_aperture = 0; | |
92af4e29 | 1698 | #endif |
6631ee9d | 1699 | |
431b2a20 | 1700 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1701 | dma_ops = &amd_iommu_dma_ops; |
1702 | ||
26961efe | 1703 | register_iommu(&amd_iommu_ops); |
26961efe | 1704 | |
e275a2a0 JR |
1705 | bus_register_notifier(&pci_bus_type, &device_nb); |
1706 | ||
7f26508b JR |
1707 | amd_iommu_stats_init(); |
1708 | ||
6631ee9d JR |
1709 | return 0; |
1710 | ||
1711 | free_domains: | |
1712 | ||
1713 | list_for_each_entry(iommu, &amd_iommu_list, list) { | |
1714 | if (iommu->default_dom) | |
1715 | dma_ops_domain_free(iommu->default_dom); | |
1716 | } | |
1717 | ||
1718 | return ret; | |
1719 | } | |
6d98cd80 JR |
1720 | |
1721 | /***************************************************************************** | |
1722 | * | |
1723 | * The following functions belong to the exported interface of AMD IOMMU | |
1724 | * | |
1725 | * This interface allows access to lower level functions of the IOMMU | |
1726 | * like protection domain handling and assignement of devices to domains | |
1727 | * which is not possible with the dma_ops interface. | |
1728 | * | |
1729 | *****************************************************************************/ | |
1730 | ||
6d98cd80 JR |
1731 | static void cleanup_domain(struct protection_domain *domain) |
1732 | { | |
1733 | unsigned long flags; | |
1734 | u16 devid; | |
1735 | ||
1736 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1737 | ||
1738 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1739 | if (amd_iommu_pd_table[devid] == domain) | |
1740 | __detach_device(domain, devid); | |
1741 | ||
1742 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1743 | } | |
1744 | ||
c156e347 JR |
1745 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
1746 | { | |
1747 | struct protection_domain *domain; | |
1748 | ||
1749 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
1750 | if (!domain) | |
1751 | return -ENOMEM; | |
1752 | ||
1753 | spin_lock_init(&domain->lock); | |
1754 | domain->mode = PAGE_MODE_3_LEVEL; | |
1755 | domain->id = domain_id_alloc(); | |
1756 | if (!domain->id) | |
1757 | goto out_free; | |
1758 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
1759 | if (!domain->pt_root) | |
1760 | goto out_free; | |
1761 | ||
1762 | dom->priv = domain; | |
1763 | ||
1764 | return 0; | |
1765 | ||
1766 | out_free: | |
1767 | kfree(domain); | |
1768 | ||
1769 | return -ENOMEM; | |
1770 | } | |
1771 | ||
98383fc3 JR |
1772 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
1773 | { | |
1774 | struct protection_domain *domain = dom->priv; | |
1775 | ||
1776 | if (!domain) | |
1777 | return; | |
1778 | ||
1779 | if (domain->dev_cnt > 0) | |
1780 | cleanup_domain(domain); | |
1781 | ||
1782 | BUG_ON(domain->dev_cnt != 0); | |
1783 | ||
1784 | free_pagetable(domain); | |
1785 | ||
1786 | domain_id_free(domain->id); | |
1787 | ||
1788 | kfree(domain); | |
1789 | ||
1790 | dom->priv = NULL; | |
1791 | } | |
1792 | ||
684f2888 JR |
1793 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
1794 | struct device *dev) | |
1795 | { | |
1796 | struct protection_domain *domain = dom->priv; | |
1797 | struct amd_iommu *iommu; | |
1798 | struct pci_dev *pdev; | |
1799 | u16 devid; | |
1800 | ||
1801 | if (dev->bus != &pci_bus_type) | |
1802 | return; | |
1803 | ||
1804 | pdev = to_pci_dev(dev); | |
1805 | ||
1806 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1807 | ||
1808 | if (devid > 0) | |
1809 | detach_device(domain, devid); | |
1810 | ||
1811 | iommu = amd_iommu_rlookup_table[devid]; | |
1812 | if (!iommu) | |
1813 | return; | |
1814 | ||
1815 | iommu_queue_inv_dev_entry(iommu, devid); | |
1816 | iommu_completion_wait(iommu); | |
1817 | } | |
1818 | ||
01106066 JR |
1819 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
1820 | struct device *dev) | |
1821 | { | |
1822 | struct protection_domain *domain = dom->priv; | |
1823 | struct protection_domain *old_domain; | |
1824 | struct amd_iommu *iommu; | |
1825 | struct pci_dev *pdev; | |
1826 | u16 devid; | |
1827 | ||
1828 | if (dev->bus != &pci_bus_type) | |
1829 | return -EINVAL; | |
1830 | ||
1831 | pdev = to_pci_dev(dev); | |
1832 | ||
1833 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1834 | ||
1835 | if (devid >= amd_iommu_last_bdf || | |
1836 | devid != amd_iommu_alias_table[devid]) | |
1837 | return -EINVAL; | |
1838 | ||
1839 | iommu = amd_iommu_rlookup_table[devid]; | |
1840 | if (!iommu) | |
1841 | return -EINVAL; | |
1842 | ||
1843 | old_domain = domain_for_device(devid); | |
1844 | if (old_domain) | |
1845 | return -EBUSY; | |
1846 | ||
1847 | attach_device(iommu, domain, devid); | |
1848 | ||
1849 | iommu_completion_wait(iommu); | |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | ||
c6229ca6 JR |
1854 | static int amd_iommu_map_range(struct iommu_domain *dom, |
1855 | unsigned long iova, phys_addr_t paddr, | |
1856 | size_t size, int iommu_prot) | |
1857 | { | |
1858 | struct protection_domain *domain = dom->priv; | |
1859 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
1860 | int prot = 0; | |
1861 | int ret; | |
1862 | ||
1863 | if (iommu_prot & IOMMU_READ) | |
1864 | prot |= IOMMU_PROT_IR; | |
1865 | if (iommu_prot & IOMMU_WRITE) | |
1866 | prot |= IOMMU_PROT_IW; | |
1867 | ||
1868 | iova &= PAGE_MASK; | |
1869 | paddr &= PAGE_MASK; | |
1870 | ||
1871 | for (i = 0; i < npages; ++i) { | |
1872 | ret = iommu_map_page(domain, iova, paddr, prot); | |
1873 | if (ret) | |
1874 | return ret; | |
1875 | ||
1876 | iova += PAGE_SIZE; | |
1877 | paddr += PAGE_SIZE; | |
1878 | } | |
1879 | ||
1880 | return 0; | |
1881 | } | |
1882 | ||
eb74ff6c JR |
1883 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
1884 | unsigned long iova, size_t size) | |
1885 | { | |
1886 | ||
1887 | struct protection_domain *domain = dom->priv; | |
1888 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
1889 | ||
1890 | iova &= PAGE_MASK; | |
1891 | ||
1892 | for (i = 0; i < npages; ++i) { | |
1893 | iommu_unmap_page(domain, iova); | |
1894 | iova += PAGE_SIZE; | |
1895 | } | |
1896 | ||
1897 | iommu_flush_domain(domain->id); | |
1898 | } | |
1899 | ||
645c4c8d JR |
1900 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
1901 | unsigned long iova) | |
1902 | { | |
1903 | struct protection_domain *domain = dom->priv; | |
1904 | unsigned long offset = iova & ~PAGE_MASK; | |
1905 | phys_addr_t paddr; | |
1906 | u64 *pte; | |
1907 | ||
1908 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
1909 | ||
1910 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1911 | return 0; | |
1912 | ||
1913 | pte = IOMMU_PTE_PAGE(*pte); | |
1914 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
1915 | ||
1916 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1917 | return 0; | |
1918 | ||
1919 | pte = IOMMU_PTE_PAGE(*pte); | |
1920 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
1921 | ||
1922 | if (!IOMMU_PTE_PRESENT(*pte)) | |
1923 | return 0; | |
1924 | ||
1925 | paddr = *pte & IOMMU_PAGE_MASK; | |
1926 | paddr |= offset; | |
1927 | ||
1928 | return paddr; | |
1929 | } | |
1930 | ||
dbb9fd86 SY |
1931 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
1932 | unsigned long cap) | |
1933 | { | |
1934 | return 0; | |
1935 | } | |
1936 | ||
26961efe JR |
1937 | static struct iommu_ops amd_iommu_ops = { |
1938 | .domain_init = amd_iommu_domain_init, | |
1939 | .domain_destroy = amd_iommu_domain_destroy, | |
1940 | .attach_dev = amd_iommu_attach_device, | |
1941 | .detach_dev = amd_iommu_detach_device, | |
1942 | .map = amd_iommu_map_range, | |
1943 | .unmap = amd_iommu_unmap_range, | |
1944 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 1945 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
1946 | }; |
1947 |