Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
a66022c4 | 22 | #include <linux/bitmap.h> |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
6a9401a7 | 31 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
0feae533 JR |
45 | /* |
46 | * Domain for untranslated devices - only allocated | |
47 | * if iommu=pt passed on kernel cmd line. | |
48 | */ | |
49 | static struct protection_domain *pt_domain; | |
50 | ||
26961efe | 51 | static struct iommu_ops amd_iommu_ops; |
26961efe | 52 | |
431b2a20 JR |
53 | /* |
54 | * general struct to manage commands send to an IOMMU | |
55 | */ | |
d6449536 | 56 | struct iommu_cmd { |
b6c02715 JR |
57 | u32 data[4]; |
58 | }; | |
59 | ||
a345b23b | 60 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
04bfdd84 | 61 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 62 | |
15898bbc JR |
63 | /**************************************************************************** |
64 | * | |
65 | * Helper functions | |
66 | * | |
67 | ****************************************************************************/ | |
68 | ||
69 | static inline u16 get_device_id(struct device *dev) | |
70 | { | |
71 | struct pci_dev *pdev = to_pci_dev(dev); | |
72 | ||
73 | return calc_devid(pdev->bus->number, pdev->devfn); | |
74 | } | |
75 | ||
657cbb6b JR |
76 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
77 | { | |
78 | return dev->archdata.iommu; | |
79 | } | |
80 | ||
71c70984 JR |
81 | /* |
82 | * In this function the list of preallocated protection domains is traversed to | |
83 | * find the domain for a specific device | |
84 | */ | |
85 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
86 | { | |
87 | struct dma_ops_domain *entry, *ret = NULL; | |
88 | unsigned long flags; | |
89 | u16 alias = amd_iommu_alias_table[devid]; | |
90 | ||
91 | if (list_empty(&iommu_pd_list)) | |
92 | return NULL; | |
93 | ||
94 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
95 | ||
96 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
97 | if (entry->target_dev == devid || | |
98 | entry->target_dev == alias) { | |
99 | ret = entry; | |
100 | break; | |
101 | } | |
102 | } | |
103 | ||
104 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
105 | ||
106 | return ret; | |
107 | } | |
108 | ||
98fc5a69 JR |
109 | /* |
110 | * This function checks if the driver got a valid device from the caller to | |
111 | * avoid dereferencing invalid pointers. | |
112 | */ | |
113 | static bool check_device(struct device *dev) | |
114 | { | |
115 | u16 devid; | |
116 | ||
117 | if (!dev || !dev->dma_mask) | |
118 | return false; | |
119 | ||
120 | /* No device or no PCI device */ | |
121 | if (!dev || dev->bus != &pci_bus_type) | |
122 | return false; | |
123 | ||
124 | devid = get_device_id(dev); | |
125 | ||
126 | /* Out of our scope? */ | |
127 | if (devid > amd_iommu_last_bdf) | |
128 | return false; | |
129 | ||
130 | if (amd_iommu_rlookup_table[devid] == NULL) | |
131 | return false; | |
132 | ||
133 | return true; | |
134 | } | |
135 | ||
657cbb6b JR |
136 | static int iommu_init_device(struct device *dev) |
137 | { | |
138 | struct iommu_dev_data *dev_data; | |
139 | struct pci_dev *pdev; | |
140 | u16 devid, alias; | |
141 | ||
142 | if (dev->archdata.iommu) | |
143 | return 0; | |
144 | ||
145 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
146 | if (!dev_data) | |
147 | return -ENOMEM; | |
148 | ||
b00d3bcf JR |
149 | dev_data->dev = dev; |
150 | ||
657cbb6b JR |
151 | devid = get_device_id(dev); |
152 | alias = amd_iommu_alias_table[devid]; | |
153 | pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff); | |
154 | if (pdev) | |
155 | dev_data->alias = &pdev->dev; | |
156 | ||
24100055 JR |
157 | atomic_set(&dev_data->bind, 0); |
158 | ||
657cbb6b JR |
159 | dev->archdata.iommu = dev_data; |
160 | ||
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static void iommu_uninit_device(struct device *dev) | |
166 | { | |
167 | kfree(dev->archdata.iommu); | |
168 | } | |
b7cc9554 JR |
169 | |
170 | void __init amd_iommu_uninit_devices(void) | |
171 | { | |
172 | struct pci_dev *pdev = NULL; | |
173 | ||
174 | for_each_pci_dev(pdev) { | |
175 | ||
176 | if (!check_device(&pdev->dev)) | |
177 | continue; | |
178 | ||
179 | iommu_uninit_device(&pdev->dev); | |
180 | } | |
181 | } | |
182 | ||
183 | int __init amd_iommu_init_devices(void) | |
184 | { | |
185 | struct pci_dev *pdev = NULL; | |
186 | int ret = 0; | |
187 | ||
188 | for_each_pci_dev(pdev) { | |
189 | ||
190 | if (!check_device(&pdev->dev)) | |
191 | continue; | |
192 | ||
193 | ret = iommu_init_device(&pdev->dev); | |
194 | if (ret) | |
195 | goto out_free; | |
196 | } | |
197 | ||
198 | return 0; | |
199 | ||
200 | out_free: | |
201 | ||
202 | amd_iommu_uninit_devices(); | |
203 | ||
204 | return ret; | |
205 | } | |
7f26508b JR |
206 | #ifdef CONFIG_AMD_IOMMU_STATS |
207 | ||
208 | /* | |
209 | * Initialization code for statistics collection | |
210 | */ | |
211 | ||
da49f6df | 212 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 213 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 214 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 215 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 216 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 217 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 218 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 219 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 220 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 221 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 222 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 223 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 224 | |
7f26508b | 225 | static struct dentry *stats_dir; |
7f26508b JR |
226 | static struct dentry *de_fflush; |
227 | ||
228 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
229 | { | |
230 | if (stats_dir == NULL) | |
231 | return; | |
232 | ||
233 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
234 | &cnt->value); | |
235 | } | |
236 | ||
237 | static void amd_iommu_stats_init(void) | |
238 | { | |
239 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
240 | if (stats_dir == NULL) | |
241 | return; | |
242 | ||
7f26508b JR |
243 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
244 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
245 | |
246 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 247 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 248 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 249 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 250 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 251 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 252 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 253 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 254 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 255 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 256 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 257 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
258 | } |
259 | ||
260 | #endif | |
261 | ||
a80dc3e0 JR |
262 | /**************************************************************************** |
263 | * | |
264 | * Interrupt handling functions | |
265 | * | |
266 | ****************************************************************************/ | |
267 | ||
e3e59876 JR |
268 | static void dump_dte_entry(u16 devid) |
269 | { | |
270 | int i; | |
271 | ||
272 | for (i = 0; i < 8; ++i) | |
273 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
274 | amd_iommu_dev_table[devid].data[i]); | |
275 | } | |
276 | ||
945b4ac4 JR |
277 | static void dump_command(unsigned long phys_addr) |
278 | { | |
279 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
280 | int i; | |
281 | ||
282 | for (i = 0; i < 4; ++i) | |
283 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
284 | } | |
285 | ||
a345b23b | 286 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
287 | { |
288 | u32 *event = __evt; | |
289 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
290 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
291 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
292 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
293 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
294 | ||
4c6f40d4 | 295 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
296 | |
297 | switch (type) { | |
298 | case EVENT_TYPE_ILL_DEV: | |
299 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
300 | "address=0x%016llx flags=0x%04x]\n", | |
301 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
302 | address, flags); | |
e3e59876 | 303 | dump_dte_entry(devid); |
90008ee4 JR |
304 | break; |
305 | case EVENT_TYPE_IO_FAULT: | |
306 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
307 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
308 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
309 | domid, address, flags); | |
310 | break; | |
311 | case EVENT_TYPE_DEV_TAB_ERR: | |
312 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
313 | "address=0x%016llx flags=0x%04x]\n", | |
314 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
315 | address, flags); | |
316 | break; | |
317 | case EVENT_TYPE_PAGE_TAB_ERR: | |
318 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
319 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
320 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
321 | domid, address, flags); | |
322 | break; | |
323 | case EVENT_TYPE_ILL_CMD: | |
324 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
8eed9833 | 325 | iommu->reset_in_progress = true; |
a345b23b | 326 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 327 | dump_command(address); |
90008ee4 JR |
328 | break; |
329 | case EVENT_TYPE_CMD_HARD_ERR: | |
330 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
331 | "flags=0x%04x]\n", address, flags); | |
332 | break; | |
333 | case EVENT_TYPE_IOTLB_INV_TO: | |
334 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
335 | "address=0x%016llx]\n", | |
336 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
337 | address); | |
338 | break; | |
339 | case EVENT_TYPE_INV_DEV_REQ: | |
340 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
341 | "address=0x%016llx flags=0x%04x]\n", | |
342 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
343 | address, flags); | |
344 | break; | |
345 | default: | |
346 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
347 | } | |
348 | } | |
349 | ||
350 | static void iommu_poll_events(struct amd_iommu *iommu) | |
351 | { | |
352 | u32 head, tail; | |
353 | unsigned long flags; | |
354 | ||
355 | spin_lock_irqsave(&iommu->lock, flags); | |
356 | ||
357 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
358 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
359 | ||
360 | while (head != tail) { | |
a345b23b | 361 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
362 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
363 | } | |
364 | ||
365 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
366 | ||
367 | spin_unlock_irqrestore(&iommu->lock, flags); | |
368 | } | |
369 | ||
a80dc3e0 JR |
370 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
371 | { | |
90008ee4 JR |
372 | struct amd_iommu *iommu; |
373 | ||
3bd22172 | 374 | for_each_iommu(iommu) |
90008ee4 JR |
375 | iommu_poll_events(iommu); |
376 | ||
377 | return IRQ_HANDLED; | |
a80dc3e0 JR |
378 | } |
379 | ||
431b2a20 JR |
380 | /**************************************************************************** |
381 | * | |
382 | * IOMMU command queuing functions | |
383 | * | |
384 | ****************************************************************************/ | |
385 | ||
386 | /* | |
387 | * Writes the command to the IOMMUs command buffer and informs the | |
388 | * hardware about the new command. Must be called with iommu->lock held. | |
389 | */ | |
d6449536 | 390 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
391 | { |
392 | u32 tail, head; | |
393 | u8 *target; | |
394 | ||
395 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 396 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
397 | memcpy_toio(target, cmd, sizeof(*cmd)); |
398 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
399 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
400 | if (tail == head) | |
401 | return -ENOMEM; | |
402 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
431b2a20 JR |
407 | /* |
408 | * General queuing function for commands. Takes iommu->lock and calls | |
409 | * __iommu_queue_command(). | |
410 | */ | |
d6449536 | 411 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
412 | { |
413 | unsigned long flags; | |
414 | int ret; | |
415 | ||
416 | spin_lock_irqsave(&iommu->lock, flags); | |
417 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 418 | if (!ret) |
0cfd7aa9 | 419 | iommu->need_sync = true; |
a19ae1ec JR |
420 | spin_unlock_irqrestore(&iommu->lock, flags); |
421 | ||
422 | return ret; | |
423 | } | |
424 | ||
8d201968 JR |
425 | /* |
426 | * This function waits until an IOMMU has completed a completion | |
427 | * wait command | |
428 | */ | |
429 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
430 | { | |
431 | int ready = 0; | |
432 | unsigned status = 0; | |
433 | unsigned long i = 0; | |
434 | ||
da49f6df JR |
435 | INC_STATS_COUNTER(compl_wait); |
436 | ||
8d201968 JR |
437 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
438 | ++i; | |
439 | /* wait for the bit to become one */ | |
440 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
441 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
442 | } | |
443 | ||
444 | /* set bit back to zero */ | |
445 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
446 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
447 | ||
8eed9833 JR |
448 | if (unlikely(i == EXIT_LOOP_COUNT)) |
449 | iommu->reset_in_progress = true; | |
8d201968 JR |
450 | } |
451 | ||
452 | /* | |
453 | * This function queues a completion wait command into the command | |
454 | * buffer of an IOMMU | |
455 | */ | |
456 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
457 | { | |
458 | struct iommu_cmd cmd; | |
459 | ||
460 | memset(&cmd, 0, sizeof(cmd)); | |
461 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
462 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
463 | ||
464 | return __iommu_queue_command(iommu, &cmd); | |
465 | } | |
466 | ||
431b2a20 JR |
467 | /* |
468 | * This function is called whenever we need to ensure that the IOMMU has | |
469 | * completed execution of all commands we sent. It sends a | |
470 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
471 | * us about that by writing a value to a physical address we pass with | |
472 | * the command. | |
473 | */ | |
a19ae1ec JR |
474 | static int iommu_completion_wait(struct amd_iommu *iommu) |
475 | { | |
8d201968 JR |
476 | int ret = 0; |
477 | unsigned long flags; | |
a19ae1ec | 478 | |
7e4f88da JR |
479 | spin_lock_irqsave(&iommu->lock, flags); |
480 | ||
09ee17eb JR |
481 | if (!iommu->need_sync) |
482 | goto out; | |
483 | ||
8d201968 | 484 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 485 | |
0cfd7aa9 | 486 | iommu->need_sync = false; |
a19ae1ec JR |
487 | |
488 | if (ret) | |
7e4f88da | 489 | goto out; |
a19ae1ec | 490 | |
8d201968 | 491 | __iommu_wait_for_completion(iommu); |
84df8175 | 492 | |
7e4f88da JR |
493 | out: |
494 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec | 495 | |
8eed9833 JR |
496 | if (iommu->reset_in_progress) |
497 | reset_iommu_command_buffer(iommu); | |
498 | ||
a19ae1ec JR |
499 | return 0; |
500 | } | |
501 | ||
0518a3a4 JR |
502 | static void iommu_flush_complete(struct protection_domain *domain) |
503 | { | |
504 | int i; | |
505 | ||
506 | for (i = 0; i < amd_iommus_present; ++i) { | |
507 | if (!domain->dev_iommu[i]) | |
508 | continue; | |
509 | ||
510 | /* | |
511 | * Devices of this domain are behind this IOMMU | |
512 | * We need to wait for completion of all commands. | |
513 | */ | |
514 | iommu_completion_wait(amd_iommus[i]); | |
515 | } | |
516 | } | |
517 | ||
431b2a20 JR |
518 | /* |
519 | * Command send function for invalidating a device table entry | |
520 | */ | |
3fa43655 JR |
521 | static int iommu_flush_device(struct device *dev) |
522 | { | |
523 | struct amd_iommu *iommu; | |
b00d3bcf | 524 | struct iommu_cmd cmd; |
3fa43655 JR |
525 | u16 devid; |
526 | ||
527 | devid = get_device_id(dev); | |
528 | iommu = amd_iommu_rlookup_table[devid]; | |
529 | ||
b00d3bcf JR |
530 | /* Build command */ |
531 | memset(&cmd, 0, sizeof(cmd)); | |
532 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
533 | cmd.data[0] = devid; | |
534 | ||
535 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
536 | } |
537 | ||
237b6f33 JR |
538 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
539 | u16 domid, int pde, int s) | |
540 | { | |
541 | memset(cmd, 0, sizeof(*cmd)); | |
542 | address &= PAGE_MASK; | |
543 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
544 | cmd->data[1] |= domid; | |
545 | cmd->data[2] = lower_32_bits(address); | |
546 | cmd->data[3] = upper_32_bits(address); | |
547 | if (s) /* size bit - we flush more than one 4kb page */ | |
548 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
549 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
550 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
551 | } | |
552 | ||
431b2a20 JR |
553 | /* |
554 | * Generic command send function for invalidaing TLB entries | |
555 | */ | |
a19ae1ec JR |
556 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
557 | u64 address, u16 domid, int pde, int s) | |
558 | { | |
d6449536 | 559 | struct iommu_cmd cmd; |
ee2fa743 | 560 | int ret; |
a19ae1ec | 561 | |
237b6f33 | 562 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 563 | |
ee2fa743 JR |
564 | ret = iommu_queue_command(iommu, &cmd); |
565 | ||
ee2fa743 | 566 | return ret; |
a19ae1ec JR |
567 | } |
568 | ||
431b2a20 JR |
569 | /* |
570 | * TLB invalidation function which is called from the mapping functions. | |
571 | * It invalidates a single PTE if the range to flush is within a single | |
572 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
573 | */ | |
6de8ad9b JR |
574 | static void __iommu_flush_pages(struct protection_domain *domain, |
575 | u64 address, size_t size, int pde) | |
a19ae1ec | 576 | { |
6de8ad9b | 577 | int s = 0, i; |
dcd1e92e | 578 | unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
579 | |
580 | address &= PAGE_MASK; | |
581 | ||
999ba417 JR |
582 | if (pages > 1) { |
583 | /* | |
584 | * If we have to flush more than one page, flush all | |
585 | * TLB entries for this domain | |
586 | */ | |
587 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
588 | s = 1; | |
a19ae1ec JR |
589 | } |
590 | ||
999ba417 | 591 | |
6de8ad9b JR |
592 | for (i = 0; i < amd_iommus_present; ++i) { |
593 | if (!domain->dev_iommu[i]) | |
594 | continue; | |
595 | ||
596 | /* | |
597 | * Devices of this domain are behind this IOMMU | |
598 | * We need a TLB flush | |
599 | */ | |
600 | iommu_queue_inv_iommu_pages(amd_iommus[i], address, | |
601 | domain->id, pde, s); | |
602 | } | |
603 | ||
604 | return; | |
605 | } | |
606 | ||
607 | static void iommu_flush_pages(struct protection_domain *domain, | |
608 | u64 address, size_t size) | |
609 | { | |
610 | __iommu_flush_pages(domain, address, size, 0); | |
a19ae1ec | 611 | } |
b6c02715 | 612 | |
1c655773 | 613 | /* Flush the whole IO/TLB for a given protection domain */ |
dcd1e92e | 614 | static void iommu_flush_tlb(struct protection_domain *domain) |
1c655773 | 615 | { |
dcd1e92e | 616 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
617 | } |
618 | ||
42a49f96 | 619 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
dcd1e92e | 620 | static void iommu_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 621 | { |
dcd1e92e | 622 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
623 | } |
624 | ||
b00d3bcf | 625 | |
43f49609 | 626 | /* |
b00d3bcf | 627 | * This function flushes the DTEs for all devices in domain |
43f49609 | 628 | */ |
b00d3bcf JR |
629 | static void iommu_flush_domain_devices(struct protection_domain *domain) |
630 | { | |
631 | struct iommu_dev_data *dev_data; | |
632 | unsigned long flags; | |
633 | ||
634 | spin_lock_irqsave(&domain->lock, flags); | |
635 | ||
636 | list_for_each_entry(dev_data, &domain->dev_list, list) | |
637 | iommu_flush_device(dev_data->dev); | |
638 | ||
639 | spin_unlock_irqrestore(&domain->lock, flags); | |
640 | } | |
641 | ||
642 | static void iommu_flush_all_domain_devices(void) | |
43f49609 | 643 | { |
09b42804 | 644 | struct protection_domain *domain; |
e394d72a | 645 | unsigned long flags; |
18811f55 | 646 | |
09b42804 | 647 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); |
bfd1be18 | 648 | |
09b42804 | 649 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
b00d3bcf | 650 | iommu_flush_domain_devices(domain); |
09b42804 | 651 | iommu_flush_complete(domain); |
bfd1be18 | 652 | } |
e394d72a | 653 | |
09b42804 | 654 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); |
e394d72a JR |
655 | } |
656 | ||
b00d3bcf JR |
657 | void amd_iommu_flush_all_devices(void) |
658 | { | |
659 | iommu_flush_all_domain_devices(); | |
660 | } | |
661 | ||
09b42804 JR |
662 | /* |
663 | * This function uses heavy locking and may disable irqs for some time. But | |
664 | * this is no issue because it is only called during resume. | |
665 | */ | |
bfd1be18 | 666 | void amd_iommu_flush_all_domains(void) |
e394d72a | 667 | { |
e3306664 | 668 | struct protection_domain *domain; |
09b42804 JR |
669 | unsigned long flags; |
670 | ||
671 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
e394d72a | 672 | |
e3306664 | 673 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
09b42804 | 674 | spin_lock(&domain->lock); |
e3306664 JR |
675 | iommu_flush_tlb_pde(domain); |
676 | iommu_flush_complete(domain); | |
09b42804 | 677 | spin_unlock(&domain->lock); |
e3306664 | 678 | } |
09b42804 JR |
679 | |
680 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
bfd1be18 JR |
681 | } |
682 | ||
a345b23b JR |
683 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
684 | { | |
685 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
686 | ||
b26e81b8 JR |
687 | if (iommu->reset_in_progress) |
688 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
689 | ||
a345b23b | 690 | amd_iommu_reset_cmd_buffer(iommu); |
b00d3bcf JR |
691 | amd_iommu_flush_all_devices(); |
692 | amd_iommu_flush_all_domains(); | |
b26e81b8 JR |
693 | |
694 | iommu->reset_in_progress = false; | |
a345b23b JR |
695 | } |
696 | ||
431b2a20 JR |
697 | /**************************************************************************** |
698 | * | |
699 | * The functions below are used the create the page table mappings for | |
700 | * unity mapped regions. | |
701 | * | |
702 | ****************************************************************************/ | |
703 | ||
308973d3 JR |
704 | /* |
705 | * This function is used to add another level to an IO page table. Adding | |
706 | * another level increases the size of the address space by 9 bits to a size up | |
707 | * to 64 bits. | |
708 | */ | |
709 | static bool increase_address_space(struct protection_domain *domain, | |
710 | gfp_t gfp) | |
711 | { | |
712 | u64 *pte; | |
713 | ||
714 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
715 | /* address space already 64 bit large */ | |
716 | return false; | |
717 | ||
718 | pte = (void *)get_zeroed_page(gfp); | |
719 | if (!pte) | |
720 | return false; | |
721 | ||
722 | *pte = PM_LEVEL_PDE(domain->mode, | |
723 | virt_to_phys(domain->pt_root)); | |
724 | domain->pt_root = pte; | |
725 | domain->mode += 1; | |
726 | domain->updated = true; | |
727 | ||
728 | return true; | |
729 | } | |
730 | ||
731 | static u64 *alloc_pte(struct protection_domain *domain, | |
732 | unsigned long address, | |
733 | int end_lvl, | |
734 | u64 **pte_page, | |
735 | gfp_t gfp) | |
736 | { | |
737 | u64 *pte, *page; | |
738 | int level; | |
739 | ||
740 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
741 | increase_address_space(domain, gfp); | |
742 | ||
743 | level = domain->mode - 1; | |
744 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
745 | ||
746 | while (level > end_lvl) { | |
747 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
748 | page = (u64 *)get_zeroed_page(gfp); | |
749 | if (!page) | |
750 | return NULL; | |
751 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
752 | } | |
753 | ||
754 | level -= 1; | |
755 | ||
756 | pte = IOMMU_PTE_PAGE(*pte); | |
757 | ||
758 | if (pte_page && level == end_lvl) | |
759 | *pte_page = pte; | |
760 | ||
761 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
762 | } | |
763 | ||
764 | return pte; | |
765 | } | |
766 | ||
767 | /* | |
768 | * This function checks if there is a PTE for a given dma address. If | |
769 | * there is one, it returns the pointer to it. | |
770 | */ | |
771 | static u64 *fetch_pte(struct protection_domain *domain, | |
772 | unsigned long address, int map_size) | |
773 | { | |
774 | int level; | |
775 | u64 *pte; | |
776 | ||
777 | level = domain->mode - 1; | |
778 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
779 | ||
780 | while (level > map_size) { | |
781 | if (!IOMMU_PTE_PRESENT(*pte)) | |
782 | return NULL; | |
783 | ||
784 | level -= 1; | |
785 | ||
786 | pte = IOMMU_PTE_PAGE(*pte); | |
787 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
788 | ||
789 | if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) { | |
790 | pte = NULL; | |
791 | break; | |
792 | } | |
793 | } | |
794 | ||
795 | return pte; | |
796 | } | |
797 | ||
431b2a20 JR |
798 | /* |
799 | * Generic mapping functions. It maps a physical address into a DMA | |
800 | * address space. It allocates the page table pages if necessary. | |
801 | * In the future it can be extended to a generic mapping function | |
802 | * supporting all features of AMD IOMMU page tables like level skipping | |
803 | * and full 64 bit address spaces. | |
804 | */ | |
38e817fe JR |
805 | static int iommu_map_page(struct protection_domain *dom, |
806 | unsigned long bus_addr, | |
807 | unsigned long phys_addr, | |
abdc5eb3 JR |
808 | int prot, |
809 | int map_size) | |
bd0e5211 | 810 | { |
8bda3092 | 811 | u64 __pte, *pte; |
bd0e5211 JR |
812 | |
813 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 814 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 | 815 | |
abdc5eb3 JR |
816 | BUG_ON(!PM_ALIGNED(map_size, bus_addr)); |
817 | BUG_ON(!PM_ALIGNED(map_size, phys_addr)); | |
818 | ||
bad1cac2 | 819 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
820 | return -EINVAL; |
821 | ||
abdc5eb3 | 822 | pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL); |
bd0e5211 JR |
823 | |
824 | if (IOMMU_PTE_PRESENT(*pte)) | |
825 | return -EBUSY; | |
826 | ||
827 | __pte = phys_addr | IOMMU_PTE_P; | |
828 | if (prot & IOMMU_PROT_IR) | |
829 | __pte |= IOMMU_PTE_IR; | |
830 | if (prot & IOMMU_PROT_IW) | |
831 | __pte |= IOMMU_PTE_IW; | |
832 | ||
833 | *pte = __pte; | |
834 | ||
04bfdd84 JR |
835 | update_domain(dom); |
836 | ||
bd0e5211 JR |
837 | return 0; |
838 | } | |
839 | ||
eb74ff6c | 840 | static void iommu_unmap_page(struct protection_domain *dom, |
a6b256b4 | 841 | unsigned long bus_addr, int map_size) |
eb74ff6c | 842 | { |
a6b256b4 | 843 | u64 *pte = fetch_pte(dom, bus_addr, map_size); |
eb74ff6c | 844 | |
38a76eee JR |
845 | if (pte) |
846 | *pte = 0; | |
eb74ff6c | 847 | } |
eb74ff6c | 848 | |
431b2a20 JR |
849 | /* |
850 | * This function checks if a specific unity mapping entry is needed for | |
851 | * this specific IOMMU. | |
852 | */ | |
bd0e5211 JR |
853 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
854 | struct unity_map_entry *entry) | |
855 | { | |
856 | u16 bdf, i; | |
857 | ||
858 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
859 | bdf = amd_iommu_alias_table[i]; | |
860 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
861 | return 1; | |
862 | } | |
863 | ||
864 | return 0; | |
865 | } | |
866 | ||
431b2a20 JR |
867 | /* |
868 | * This function actually applies the mapping to the page table of the | |
869 | * dma_ops domain. | |
870 | */ | |
bd0e5211 JR |
871 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
872 | struct unity_map_entry *e) | |
873 | { | |
874 | u64 addr; | |
875 | int ret; | |
876 | ||
877 | for (addr = e->address_start; addr < e->address_end; | |
878 | addr += PAGE_SIZE) { | |
abdc5eb3 JR |
879 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
880 | PM_MAP_4k); | |
bd0e5211 JR |
881 | if (ret) |
882 | return ret; | |
883 | /* | |
884 | * if unity mapping is in aperture range mark the page | |
885 | * as allocated in the aperture | |
886 | */ | |
887 | if (addr < dma_dom->aperture_size) | |
c3239567 | 888 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 889 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
890 | } |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
171e7b37 JR |
895 | /* |
896 | * Init the unity mappings for a specific IOMMU in the system | |
897 | * | |
898 | * Basically iterates over all unity mapping entries and applies them to | |
899 | * the default domain DMA of that IOMMU if necessary. | |
900 | */ | |
901 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
902 | { | |
903 | struct unity_map_entry *entry; | |
904 | int ret; | |
905 | ||
906 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
907 | if (!iommu_for_unity_map(iommu, entry)) | |
908 | continue; | |
909 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
910 | if (ret) | |
911 | return ret; | |
912 | } | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
431b2a20 JR |
917 | /* |
918 | * Inits the unity mappings required for a specific device | |
919 | */ | |
bd0e5211 JR |
920 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
921 | u16 devid) | |
922 | { | |
923 | struct unity_map_entry *e; | |
924 | int ret; | |
925 | ||
926 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
927 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
928 | continue; | |
929 | ret = dma_ops_unity_map(dma_dom, e); | |
930 | if (ret) | |
931 | return ret; | |
932 | } | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
431b2a20 JR |
937 | /**************************************************************************** |
938 | * | |
939 | * The next functions belong to the address allocator for the dma_ops | |
940 | * interface functions. They work like the allocators in the other IOMMU | |
941 | * drivers. Its basically a bitmap which marks the allocated pages in | |
942 | * the aperture. Maybe it could be enhanced in the future to a more | |
943 | * efficient allocator. | |
944 | * | |
945 | ****************************************************************************/ | |
d3086444 | 946 | |
431b2a20 | 947 | /* |
384de729 | 948 | * The address allocator core functions. |
431b2a20 JR |
949 | * |
950 | * called with domain->lock held | |
951 | */ | |
384de729 | 952 | |
171e7b37 JR |
953 | /* |
954 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
955 | * ranges. | |
956 | */ | |
957 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
958 | unsigned long start_page, | |
959 | unsigned int pages) | |
960 | { | |
961 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
962 | ||
963 | if (start_page + pages > last_page) | |
964 | pages = last_page - start_page; | |
965 | ||
966 | for (i = start_page; i < start_page + pages; ++i) { | |
967 | int index = i / APERTURE_RANGE_PAGES; | |
968 | int page = i % APERTURE_RANGE_PAGES; | |
969 | __set_bit(page, dom->aperture[index]->bitmap); | |
970 | } | |
971 | } | |
972 | ||
9cabe89b JR |
973 | /* |
974 | * This function is used to add a new aperture range to an existing | |
975 | * aperture in case of dma_ops domain allocation or address allocation | |
976 | * failure. | |
977 | */ | |
576175c2 | 978 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
979 | bool populate, gfp_t gfp) |
980 | { | |
981 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 982 | struct amd_iommu *iommu; |
00cd122a | 983 | int i; |
9cabe89b | 984 | |
f5e9705c JR |
985 | #ifdef CONFIG_IOMMU_STRESS |
986 | populate = false; | |
987 | #endif | |
988 | ||
9cabe89b JR |
989 | if (index >= APERTURE_MAX_RANGES) |
990 | return -ENOMEM; | |
991 | ||
992 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
993 | if (!dma_dom->aperture[index]) | |
994 | return -ENOMEM; | |
995 | ||
996 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
997 | if (!dma_dom->aperture[index]->bitmap) | |
998 | goto out_free; | |
999 | ||
1000 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1001 | ||
1002 | if (populate) { | |
1003 | unsigned long address = dma_dom->aperture_size; | |
1004 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1005 | u64 *pte, *pte_page; | |
1006 | ||
1007 | for (i = 0; i < num_ptes; ++i) { | |
abdc5eb3 | 1008 | pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k, |
9cabe89b JR |
1009 | &pte_page, gfp); |
1010 | if (!pte) | |
1011 | goto out_free; | |
1012 | ||
1013 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1014 | ||
1015 | address += APERTURE_RANGE_SIZE / 64; | |
1016 | } | |
1017 | } | |
1018 | ||
1019 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1020 | ||
00cd122a | 1021 | /* Intialize the exclusion range if necessary */ |
576175c2 JR |
1022 | for_each_iommu(iommu) { |
1023 | if (iommu->exclusion_start && | |
1024 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1025 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1026 | unsigned long startpage; | |
1027 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1028 | iommu->exclusion_length, | |
1029 | PAGE_SIZE); | |
1030 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1031 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1032 | } | |
00cd122a JR |
1033 | } |
1034 | ||
1035 | /* | |
1036 | * Check for areas already mapped as present in the new aperture | |
1037 | * range and mark those pages as reserved in the allocator. Such | |
1038 | * mappings may already exist as a result of requested unity | |
1039 | * mappings for devices. | |
1040 | */ | |
1041 | for (i = dma_dom->aperture[index]->offset; | |
1042 | i < dma_dom->aperture_size; | |
1043 | i += PAGE_SIZE) { | |
a6b256b4 | 1044 | u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k); |
00cd122a JR |
1045 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1046 | continue; | |
1047 | ||
1048 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1049 | } | |
1050 | ||
04bfdd84 JR |
1051 | update_domain(&dma_dom->domain); |
1052 | ||
9cabe89b JR |
1053 | return 0; |
1054 | ||
1055 | out_free: | |
04bfdd84 JR |
1056 | update_domain(&dma_dom->domain); |
1057 | ||
9cabe89b JR |
1058 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1059 | ||
1060 | kfree(dma_dom->aperture[index]); | |
1061 | dma_dom->aperture[index] = NULL; | |
1062 | ||
1063 | return -ENOMEM; | |
1064 | } | |
1065 | ||
384de729 JR |
1066 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1067 | struct dma_ops_domain *dom, | |
1068 | unsigned int pages, | |
1069 | unsigned long align_mask, | |
1070 | u64 dma_mask, | |
1071 | unsigned long start) | |
1072 | { | |
803b8cb4 | 1073 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1074 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1075 | int i = start >> APERTURE_RANGE_SHIFT; | |
1076 | unsigned long boundary_size; | |
1077 | unsigned long address = -1; | |
1078 | unsigned long limit; | |
1079 | ||
803b8cb4 JR |
1080 | next_bit >>= PAGE_SHIFT; |
1081 | ||
384de729 JR |
1082 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1083 | PAGE_SIZE) >> PAGE_SHIFT; | |
1084 | ||
1085 | for (;i < max_index; ++i) { | |
1086 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1087 | ||
1088 | if (dom->aperture[i]->offset >= dma_mask) | |
1089 | break; | |
1090 | ||
1091 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1092 | dma_mask >> PAGE_SHIFT); | |
1093 | ||
1094 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1095 | limit, next_bit, pages, 0, | |
1096 | boundary_size, align_mask); | |
1097 | if (address != -1) { | |
1098 | address = dom->aperture[i]->offset + | |
1099 | (address << PAGE_SHIFT); | |
803b8cb4 | 1100 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1101 | break; |
1102 | } | |
1103 | ||
1104 | next_bit = 0; | |
1105 | } | |
1106 | ||
1107 | return address; | |
1108 | } | |
1109 | ||
d3086444 JR |
1110 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1111 | struct dma_ops_domain *dom, | |
6d4f343f | 1112 | unsigned int pages, |
832a90c3 JR |
1113 | unsigned long align_mask, |
1114 | u64 dma_mask) | |
d3086444 | 1115 | { |
d3086444 | 1116 | unsigned long address; |
d3086444 | 1117 | |
fe16f088 JR |
1118 | #ifdef CONFIG_IOMMU_STRESS |
1119 | dom->next_address = 0; | |
1120 | dom->need_flush = true; | |
1121 | #endif | |
d3086444 | 1122 | |
384de729 | 1123 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1124 | dma_mask, dom->next_address); |
d3086444 | 1125 | |
1c655773 | 1126 | if (address == -1) { |
803b8cb4 | 1127 | dom->next_address = 0; |
384de729 JR |
1128 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1129 | dma_mask, 0); | |
1c655773 JR |
1130 | dom->need_flush = true; |
1131 | } | |
d3086444 | 1132 | |
384de729 | 1133 | if (unlikely(address == -1)) |
8fd524b3 | 1134 | address = DMA_ERROR_CODE; |
d3086444 JR |
1135 | |
1136 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1137 | ||
1138 | return address; | |
1139 | } | |
1140 | ||
431b2a20 JR |
1141 | /* |
1142 | * The address free function. | |
1143 | * | |
1144 | * called with domain->lock held | |
1145 | */ | |
d3086444 JR |
1146 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1147 | unsigned long address, | |
1148 | unsigned int pages) | |
1149 | { | |
384de729 JR |
1150 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1151 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1152 | |
384de729 JR |
1153 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1154 | ||
47bccd6b JR |
1155 | #ifdef CONFIG_IOMMU_STRESS |
1156 | if (i < 4) | |
1157 | return; | |
1158 | #endif | |
80be308d | 1159 | |
803b8cb4 | 1160 | if (address >= dom->next_address) |
80be308d | 1161 | dom->need_flush = true; |
384de729 JR |
1162 | |
1163 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1164 | |
a66022c4 | 1165 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1166 | |
d3086444 JR |
1167 | } |
1168 | ||
431b2a20 JR |
1169 | /**************************************************************************** |
1170 | * | |
1171 | * The next functions belong to the domain allocation. A domain is | |
1172 | * allocated for every IOMMU as the default domain. If device isolation | |
1173 | * is enabled, every device get its own domain. The most important thing | |
1174 | * about domains is the page table mapping the DMA address space they | |
1175 | * contain. | |
1176 | * | |
1177 | ****************************************************************************/ | |
1178 | ||
aeb26f55 JR |
1179 | /* |
1180 | * This function adds a protection domain to the global protection domain list | |
1181 | */ | |
1182 | static void add_domain_to_list(struct protection_domain *domain) | |
1183 | { | |
1184 | unsigned long flags; | |
1185 | ||
1186 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1187 | list_add(&domain->list, &amd_iommu_pd_list); | |
1188 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1189 | } | |
1190 | ||
1191 | /* | |
1192 | * This function removes a protection domain to the global | |
1193 | * protection domain list | |
1194 | */ | |
1195 | static void del_domain_from_list(struct protection_domain *domain) | |
1196 | { | |
1197 | unsigned long flags; | |
1198 | ||
1199 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1200 | list_del(&domain->list); | |
1201 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1202 | } | |
1203 | ||
ec487d1a JR |
1204 | static u16 domain_id_alloc(void) |
1205 | { | |
1206 | unsigned long flags; | |
1207 | int id; | |
1208 | ||
1209 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1210 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1211 | BUG_ON(id == 0); | |
1212 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1213 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1214 | else | |
1215 | id = 0; | |
1216 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1217 | ||
1218 | return id; | |
1219 | } | |
1220 | ||
a2acfb75 JR |
1221 | static void domain_id_free(int id) |
1222 | { | |
1223 | unsigned long flags; | |
1224 | ||
1225 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1226 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1227 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1228 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1229 | } | |
a2acfb75 | 1230 | |
86db2e5d | 1231 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1232 | { |
1233 | int i, j; | |
1234 | u64 *p1, *p2, *p3; | |
1235 | ||
86db2e5d | 1236 | p1 = domain->pt_root; |
ec487d1a JR |
1237 | |
1238 | if (!p1) | |
1239 | return; | |
1240 | ||
1241 | for (i = 0; i < 512; ++i) { | |
1242 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1243 | continue; | |
1244 | ||
1245 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1246 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1247 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1248 | continue; | |
1249 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1250 | free_page((unsigned long)p3); | |
1251 | } | |
1252 | ||
1253 | free_page((unsigned long)p2); | |
1254 | } | |
1255 | ||
1256 | free_page((unsigned long)p1); | |
86db2e5d JR |
1257 | |
1258 | domain->pt_root = NULL; | |
ec487d1a JR |
1259 | } |
1260 | ||
431b2a20 JR |
1261 | /* |
1262 | * Free a domain, only used if something went wrong in the | |
1263 | * allocation path and we need to free an already allocated page table | |
1264 | */ | |
ec487d1a JR |
1265 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1266 | { | |
384de729 JR |
1267 | int i; |
1268 | ||
ec487d1a JR |
1269 | if (!dom) |
1270 | return; | |
1271 | ||
aeb26f55 JR |
1272 | del_domain_from_list(&dom->domain); |
1273 | ||
86db2e5d | 1274 | free_pagetable(&dom->domain); |
ec487d1a | 1275 | |
384de729 JR |
1276 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1277 | if (!dom->aperture[i]) | |
1278 | continue; | |
1279 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1280 | kfree(dom->aperture[i]); | |
1281 | } | |
ec487d1a JR |
1282 | |
1283 | kfree(dom); | |
1284 | } | |
1285 | ||
431b2a20 JR |
1286 | /* |
1287 | * Allocates a new protection domain usable for the dma_ops functions. | |
1288 | * It also intializes the page table and the address allocator data | |
1289 | * structures required for the dma_ops interface | |
1290 | */ | |
87a64d52 | 1291 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1292 | { |
1293 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1294 | |
1295 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1296 | if (!dma_dom) | |
1297 | return NULL; | |
1298 | ||
1299 | spin_lock_init(&dma_dom->domain.lock); | |
1300 | ||
1301 | dma_dom->domain.id = domain_id_alloc(); | |
1302 | if (dma_dom->domain.id == 0) | |
1303 | goto free_dma_dom; | |
7c392cbe | 1304 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1305 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1306 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1307 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1308 | dma_dom->domain.priv = dma_dom; |
1309 | if (!dma_dom->domain.pt_root) | |
1310 | goto free_dma_dom; | |
ec487d1a | 1311 | |
1c655773 | 1312 | dma_dom->need_flush = false; |
bd60b735 | 1313 | dma_dom->target_dev = 0xffff; |
1c655773 | 1314 | |
aeb26f55 JR |
1315 | add_domain_to_list(&dma_dom->domain); |
1316 | ||
576175c2 | 1317 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1318 | goto free_dma_dom; |
ec487d1a | 1319 | |
431b2a20 | 1320 | /* |
ec487d1a JR |
1321 | * mark the first page as allocated so we never return 0 as |
1322 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1323 | */ |
384de729 | 1324 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1325 | dma_dom->next_address = 0; |
ec487d1a | 1326 | |
ec487d1a JR |
1327 | |
1328 | return dma_dom; | |
1329 | ||
1330 | free_dma_dom: | |
1331 | dma_ops_domain_free(dma_dom); | |
1332 | ||
1333 | return NULL; | |
1334 | } | |
1335 | ||
5b28df6f JR |
1336 | /* |
1337 | * little helper function to check whether a given protection domain is a | |
1338 | * dma_ops domain | |
1339 | */ | |
1340 | static bool dma_ops_domain(struct protection_domain *domain) | |
1341 | { | |
1342 | return domain->flags & PD_DMA_OPS_MASK; | |
1343 | } | |
1344 | ||
407d733e | 1345 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1346 | { |
b20ac0d4 | 1347 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1348 | |
38ddf41b JR |
1349 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1350 | << DEV_ENTRY_MODE_SHIFT; | |
1351 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1352 | |
b20ac0d4 | 1353 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1354 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1355 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1356 | } |
1357 | ||
1358 | static void clear_dte_entry(u16 devid) | |
1359 | { | |
15898bbc JR |
1360 | /* remove entry from the device table seen by the hardware */ |
1361 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1362 | amd_iommu_dev_table[devid].data[1] = 0; | |
1363 | amd_iommu_dev_table[devid].data[2] = 0; | |
1364 | ||
1365 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1366 | } |
1367 | ||
1368 | static void do_attach(struct device *dev, struct protection_domain *domain) | |
1369 | { | |
1370 | struct iommu_dev_data *dev_data; | |
1371 | struct amd_iommu *iommu; | |
1372 | u16 devid; | |
1373 | ||
1374 | devid = get_device_id(dev); | |
1375 | iommu = amd_iommu_rlookup_table[devid]; | |
1376 | dev_data = get_dev_data(dev); | |
1377 | ||
1378 | /* Update data structures */ | |
1379 | dev_data->domain = domain; | |
1380 | list_add(&dev_data->list, &domain->dev_list); | |
1381 | set_dte_entry(devid, domain); | |
1382 | ||
1383 | /* Do reference counting */ | |
1384 | domain->dev_iommu[iommu->index] += 1; | |
1385 | domain->dev_cnt += 1; | |
1386 | ||
1387 | /* Flush the DTE entry */ | |
3fa43655 | 1388 | iommu_flush_device(dev); |
7f760ddd JR |
1389 | } |
1390 | ||
1391 | static void do_detach(struct device *dev) | |
1392 | { | |
1393 | struct iommu_dev_data *dev_data; | |
1394 | struct amd_iommu *iommu; | |
1395 | u16 devid; | |
1396 | ||
1397 | devid = get_device_id(dev); | |
1398 | iommu = amd_iommu_rlookup_table[devid]; | |
1399 | dev_data = get_dev_data(dev); | |
15898bbc JR |
1400 | |
1401 | /* decrease reference counters */ | |
7f760ddd JR |
1402 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1403 | dev_data->domain->dev_cnt -= 1; | |
1404 | ||
1405 | /* Update data structures */ | |
1406 | dev_data->domain = NULL; | |
1407 | list_del(&dev_data->list); | |
1408 | clear_dte_entry(devid); | |
15898bbc | 1409 | |
7f760ddd | 1410 | /* Flush the DTE entry */ |
3fa43655 | 1411 | iommu_flush_device(dev); |
2b681faf JR |
1412 | } |
1413 | ||
1414 | /* | |
1415 | * If a device is not yet associated with a domain, this function does | |
1416 | * assigns it visible for the hardware | |
1417 | */ | |
15898bbc JR |
1418 | static int __attach_device(struct device *dev, |
1419 | struct protection_domain *domain) | |
2b681faf | 1420 | { |
657cbb6b | 1421 | struct iommu_dev_data *dev_data, *alias_data; |
657cbb6b | 1422 | |
657cbb6b JR |
1423 | dev_data = get_dev_data(dev); |
1424 | alias_data = get_dev_data(dev_data->alias); | |
7f760ddd | 1425 | |
657cbb6b JR |
1426 | if (!alias_data) |
1427 | return -EINVAL; | |
15898bbc | 1428 | |
2b681faf JR |
1429 | /* lock domain */ |
1430 | spin_lock(&domain->lock); | |
1431 | ||
15898bbc | 1432 | /* Some sanity checks */ |
657cbb6b JR |
1433 | if (alias_data->domain != NULL && |
1434 | alias_data->domain != domain) | |
15898bbc | 1435 | return -EBUSY; |
eba6ac60 | 1436 | |
657cbb6b JR |
1437 | if (dev_data->domain != NULL && |
1438 | dev_data->domain != domain) | |
15898bbc JR |
1439 | return -EBUSY; |
1440 | ||
1441 | /* Do real assignment */ | |
7f760ddd JR |
1442 | if (dev_data->alias != dev) { |
1443 | alias_data = get_dev_data(dev_data->alias); | |
1444 | if (alias_data->domain == NULL) | |
1445 | do_attach(dev_data->alias, domain); | |
24100055 JR |
1446 | |
1447 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1448 | } |
15898bbc | 1449 | |
7f760ddd JR |
1450 | if (dev_data->domain == NULL) |
1451 | do_attach(dev, domain); | |
eba6ac60 | 1452 | |
24100055 JR |
1453 | atomic_inc(&dev_data->bind); |
1454 | ||
eba6ac60 JR |
1455 | /* ready */ |
1456 | spin_unlock(&domain->lock); | |
15898bbc JR |
1457 | |
1458 | return 0; | |
0feae533 | 1459 | } |
b20ac0d4 | 1460 | |
407d733e JR |
1461 | /* |
1462 | * If a device is not yet associated with a domain, this function does | |
1463 | * assigns it visible for the hardware | |
1464 | */ | |
15898bbc JR |
1465 | static int attach_device(struct device *dev, |
1466 | struct protection_domain *domain) | |
0feae533 | 1467 | { |
eba6ac60 | 1468 | unsigned long flags; |
15898bbc | 1469 | int ret; |
eba6ac60 JR |
1470 | |
1471 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1472 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1473 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1474 | ||
0feae533 JR |
1475 | /* |
1476 | * We might boot into a crash-kernel here. The crashed kernel | |
1477 | * left the caches in the IOMMU dirty. So we have to flush | |
1478 | * here to evict all dirty stuff. | |
1479 | */ | |
dcd1e92e | 1480 | iommu_flush_tlb_pde(domain); |
15898bbc JR |
1481 | |
1482 | return ret; | |
b20ac0d4 JR |
1483 | } |
1484 | ||
355bf553 JR |
1485 | /* |
1486 | * Removes a device from a protection domain (unlocked) | |
1487 | */ | |
15898bbc | 1488 | static void __detach_device(struct device *dev) |
355bf553 | 1489 | { |
657cbb6b | 1490 | struct iommu_dev_data *dev_data = get_dev_data(dev); |
24100055 | 1491 | struct iommu_dev_data *alias_data; |
7c392cbe | 1492 | unsigned long flags; |
c4596114 | 1493 | |
7f760ddd | 1494 | BUG_ON(!dev_data->domain); |
355bf553 | 1495 | |
7f760ddd | 1496 | spin_lock_irqsave(&dev_data->domain->lock, flags); |
24100055 | 1497 | |
7f760ddd | 1498 | if (dev_data->alias != dev) { |
24100055 | 1499 | alias_data = get_dev_data(dev_data->alias); |
7f760ddd JR |
1500 | if (atomic_dec_and_test(&alias_data->bind)) |
1501 | do_detach(dev_data->alias); | |
24100055 JR |
1502 | } |
1503 | ||
7f760ddd JR |
1504 | if (atomic_dec_and_test(&dev_data->bind)) |
1505 | do_detach(dev); | |
1506 | ||
1507 | spin_unlock_irqrestore(&dev_data->domain->lock, flags); | |
21129f78 JR |
1508 | |
1509 | /* | |
1510 | * If we run in passthrough mode the device must be assigned to the | |
1511 | * passthrough domain if it is detached from any other domain | |
1512 | */ | |
24100055 | 1513 | if (iommu_pass_through && dev_data->domain == NULL) |
15898bbc | 1514 | __attach_device(dev, pt_domain); |
355bf553 JR |
1515 | } |
1516 | ||
1517 | /* | |
1518 | * Removes a device from a protection domain (with devtable_lock held) | |
1519 | */ | |
15898bbc | 1520 | static void detach_device(struct device *dev) |
355bf553 JR |
1521 | { |
1522 | unsigned long flags; | |
1523 | ||
1524 | /* lock device table */ | |
1525 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1526 | __detach_device(dev); |
355bf553 JR |
1527 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1528 | } | |
e275a2a0 | 1529 | |
15898bbc JR |
1530 | /* |
1531 | * Find out the protection domain structure for a given PCI device. This | |
1532 | * will give us the pointer to the page table root for example. | |
1533 | */ | |
1534 | static struct protection_domain *domain_for_device(struct device *dev) | |
1535 | { | |
1536 | struct protection_domain *dom; | |
657cbb6b | 1537 | struct iommu_dev_data *dev_data, *alias_data; |
15898bbc JR |
1538 | unsigned long flags; |
1539 | u16 devid, alias; | |
1540 | ||
657cbb6b JR |
1541 | devid = get_device_id(dev); |
1542 | alias = amd_iommu_alias_table[devid]; | |
1543 | dev_data = get_dev_data(dev); | |
1544 | alias_data = get_dev_data(dev_data->alias); | |
1545 | if (!alias_data) | |
1546 | return NULL; | |
15898bbc JR |
1547 | |
1548 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
657cbb6b | 1549 | dom = dev_data->domain; |
15898bbc | 1550 | if (dom == NULL && |
657cbb6b JR |
1551 | alias_data->domain != NULL) { |
1552 | __attach_device(dev, alias_data->domain); | |
1553 | dom = alias_data->domain; | |
15898bbc JR |
1554 | } |
1555 | ||
1556 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1557 | ||
1558 | return dom; | |
1559 | } | |
1560 | ||
e275a2a0 JR |
1561 | static int device_change_notifier(struct notifier_block *nb, |
1562 | unsigned long action, void *data) | |
1563 | { | |
1564 | struct device *dev = data; | |
98fc5a69 | 1565 | u16 devid; |
e275a2a0 JR |
1566 | struct protection_domain *domain; |
1567 | struct dma_ops_domain *dma_domain; | |
1568 | struct amd_iommu *iommu; | |
1ac4cbbc | 1569 | unsigned long flags; |
e275a2a0 | 1570 | |
98fc5a69 JR |
1571 | if (!check_device(dev)) |
1572 | return 0; | |
e275a2a0 | 1573 | |
98fc5a69 JR |
1574 | devid = get_device_id(dev); |
1575 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1576 | |
1577 | switch (action) { | |
c1eee67b | 1578 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1579 | |
1580 | domain = domain_for_device(dev); | |
1581 | ||
e275a2a0 JR |
1582 | if (!domain) |
1583 | goto out; | |
a1ca331c JR |
1584 | if (iommu_pass_through) |
1585 | break; | |
15898bbc | 1586 | detach_device(dev); |
1ac4cbbc JR |
1587 | break; |
1588 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1589 | |
1590 | iommu_init_device(dev); | |
1591 | ||
1592 | domain = domain_for_device(dev); | |
1593 | ||
1ac4cbbc JR |
1594 | /* allocate a protection domain if a device is added */ |
1595 | dma_domain = find_protection_domain(devid); | |
1596 | if (dma_domain) | |
1597 | goto out; | |
87a64d52 | 1598 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1599 | if (!dma_domain) |
1600 | goto out; | |
1601 | dma_domain->target_dev = devid; | |
1602 | ||
1603 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1604 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1605 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1606 | ||
e275a2a0 | 1607 | break; |
657cbb6b JR |
1608 | case BUS_NOTIFY_DEL_DEVICE: |
1609 | ||
1610 | iommu_uninit_device(dev); | |
1611 | ||
e275a2a0 JR |
1612 | default: |
1613 | goto out; | |
1614 | } | |
1615 | ||
3fa43655 | 1616 | iommu_flush_device(dev); |
e275a2a0 JR |
1617 | iommu_completion_wait(iommu); |
1618 | ||
1619 | out: | |
1620 | return 0; | |
1621 | } | |
1622 | ||
b25ae679 | 1623 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1624 | .notifier_call = device_change_notifier, |
1625 | }; | |
355bf553 | 1626 | |
8638c491 JR |
1627 | void amd_iommu_init_notifier(void) |
1628 | { | |
1629 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1630 | } | |
1631 | ||
431b2a20 JR |
1632 | /***************************************************************************** |
1633 | * | |
1634 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1635 | * | |
1636 | *****************************************************************************/ | |
1637 | ||
1638 | /* | |
1639 | * In the dma_ops path we only have the struct device. This function | |
1640 | * finds the corresponding IOMMU, the protection domain and the | |
1641 | * requestor id for a given device. | |
1642 | * If the device is not yet associated with a domain this is also done | |
1643 | * in this function. | |
1644 | */ | |
94f6d190 | 1645 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1646 | { |
94f6d190 | 1647 | struct protection_domain *domain; |
b20ac0d4 | 1648 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1649 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1650 | |
f99c0f1c | 1651 | if (!check_device(dev)) |
94f6d190 | 1652 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1653 | |
94f6d190 JR |
1654 | domain = domain_for_device(dev); |
1655 | if (domain != NULL && !dma_ops_domain(domain)) | |
1656 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1657 | |
94f6d190 JR |
1658 | if (domain != NULL) |
1659 | return domain; | |
b20ac0d4 | 1660 | |
15898bbc | 1661 | /* Device not bount yet - bind it */ |
94f6d190 | 1662 | dma_dom = find_protection_domain(devid); |
15898bbc | 1663 | if (!dma_dom) |
94f6d190 JR |
1664 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1665 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1666 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1667 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1668 | |
94f6d190 | 1669 | return &dma_dom->domain; |
b20ac0d4 JR |
1670 | } |
1671 | ||
04bfdd84 JR |
1672 | static void update_device_table(struct protection_domain *domain) |
1673 | { | |
492667da | 1674 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1675 | |
492667da JR |
1676 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
1677 | u16 devid = get_device_id(dev_data->dev); | |
1678 | set_dte_entry(devid, domain); | |
04bfdd84 JR |
1679 | } |
1680 | } | |
1681 | ||
1682 | static void update_domain(struct protection_domain *domain) | |
1683 | { | |
1684 | if (!domain->updated) | |
1685 | return; | |
1686 | ||
1687 | update_device_table(domain); | |
b00d3bcf | 1688 | iommu_flush_domain_devices(domain); |
601367d7 | 1689 | iommu_flush_tlb_pde(domain); |
04bfdd84 JR |
1690 | |
1691 | domain->updated = false; | |
1692 | } | |
1693 | ||
8bda3092 JR |
1694 | /* |
1695 | * This function fetches the PTE for a given address in the aperture | |
1696 | */ | |
1697 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1698 | unsigned long address) | |
1699 | { | |
384de729 | 1700 | struct aperture_range *aperture; |
8bda3092 JR |
1701 | u64 *pte, *pte_page; |
1702 | ||
384de729 JR |
1703 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1704 | if (!aperture) | |
1705 | return NULL; | |
1706 | ||
1707 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1708 | if (!pte) { |
abdc5eb3 JR |
1709 | pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page, |
1710 | GFP_ATOMIC); | |
384de729 JR |
1711 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1712 | } else | |
8c8c143c | 1713 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1714 | |
04bfdd84 | 1715 | update_domain(&dom->domain); |
8bda3092 JR |
1716 | |
1717 | return pte; | |
1718 | } | |
1719 | ||
431b2a20 JR |
1720 | /* |
1721 | * This is the generic map function. It maps one 4kb page at paddr to | |
1722 | * the given address in the DMA address space for the domain. | |
1723 | */ | |
680525e0 | 1724 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1725 | unsigned long address, |
1726 | phys_addr_t paddr, | |
1727 | int direction) | |
1728 | { | |
1729 | u64 *pte, __pte; | |
1730 | ||
1731 | WARN_ON(address > dom->aperture_size); | |
1732 | ||
1733 | paddr &= PAGE_MASK; | |
1734 | ||
8bda3092 | 1735 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1736 | if (!pte) |
8fd524b3 | 1737 | return DMA_ERROR_CODE; |
cb76c322 JR |
1738 | |
1739 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1740 | ||
1741 | if (direction == DMA_TO_DEVICE) | |
1742 | __pte |= IOMMU_PTE_IR; | |
1743 | else if (direction == DMA_FROM_DEVICE) | |
1744 | __pte |= IOMMU_PTE_IW; | |
1745 | else if (direction == DMA_BIDIRECTIONAL) | |
1746 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1747 | ||
1748 | WARN_ON(*pte); | |
1749 | ||
1750 | *pte = __pte; | |
1751 | ||
1752 | return (dma_addr_t)address; | |
1753 | } | |
1754 | ||
431b2a20 JR |
1755 | /* |
1756 | * The generic unmapping function for on page in the DMA address space. | |
1757 | */ | |
680525e0 | 1758 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1759 | unsigned long address) |
1760 | { | |
384de729 | 1761 | struct aperture_range *aperture; |
cb76c322 JR |
1762 | u64 *pte; |
1763 | ||
1764 | if (address >= dom->aperture_size) | |
1765 | return; | |
1766 | ||
384de729 JR |
1767 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1768 | if (!aperture) | |
1769 | return; | |
1770 | ||
1771 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1772 | if (!pte) | |
1773 | return; | |
cb76c322 | 1774 | |
8c8c143c | 1775 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1776 | |
1777 | WARN_ON(!*pte); | |
1778 | ||
1779 | *pte = 0ULL; | |
1780 | } | |
1781 | ||
431b2a20 JR |
1782 | /* |
1783 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1784 | * contiguous memory region into DMA address space. It is used by all |
1785 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1786 | * Must be called with the domain lock held. |
1787 | */ | |
cb76c322 | 1788 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1789 | struct dma_ops_domain *dma_dom, |
1790 | phys_addr_t paddr, | |
1791 | size_t size, | |
6d4f343f | 1792 | int dir, |
832a90c3 JR |
1793 | bool align, |
1794 | u64 dma_mask) | |
cb76c322 JR |
1795 | { |
1796 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1797 | dma_addr_t address, start, ret; |
cb76c322 | 1798 | unsigned int pages; |
6d4f343f | 1799 | unsigned long align_mask = 0; |
cb76c322 JR |
1800 | int i; |
1801 | ||
e3c449f5 | 1802 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1803 | paddr &= PAGE_MASK; |
1804 | ||
8ecaf8f1 JR |
1805 | INC_STATS_COUNTER(total_map_requests); |
1806 | ||
c1858976 JR |
1807 | if (pages > 1) |
1808 | INC_STATS_COUNTER(cross_page); | |
1809 | ||
6d4f343f JR |
1810 | if (align) |
1811 | align_mask = (1UL << get_order(size)) - 1; | |
1812 | ||
11b83888 | 1813 | retry: |
832a90c3 JR |
1814 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1815 | dma_mask); | |
8fd524b3 | 1816 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1817 | /* |
1818 | * setting next_address here will let the address | |
1819 | * allocator only scan the new allocated range in the | |
1820 | * first run. This is a small optimization. | |
1821 | */ | |
1822 | dma_dom->next_address = dma_dom->aperture_size; | |
1823 | ||
576175c2 | 1824 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1825 | goto out; |
1826 | ||
1827 | /* | |
af901ca1 | 1828 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
1829 | * allocation again |
1830 | */ | |
1831 | goto retry; | |
1832 | } | |
cb76c322 JR |
1833 | |
1834 | start = address; | |
1835 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1836 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 1837 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1838 | goto out_unmap; |
1839 | ||
cb76c322 JR |
1840 | paddr += PAGE_SIZE; |
1841 | start += PAGE_SIZE; | |
1842 | } | |
1843 | address += offset; | |
1844 | ||
5774f7c5 JR |
1845 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1846 | ||
afa9fdc2 | 1847 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
dcd1e92e | 1848 | iommu_flush_tlb(&dma_dom->domain); |
1c655773 | 1849 | dma_dom->need_flush = false; |
318afd41 | 1850 | } else if (unlikely(amd_iommu_np_cache)) |
6de8ad9b | 1851 | iommu_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1852 | |
cb76c322 JR |
1853 | out: |
1854 | return address; | |
53812c11 JR |
1855 | |
1856 | out_unmap: | |
1857 | ||
1858 | for (--i; i >= 0; --i) { | |
1859 | start -= PAGE_SIZE; | |
680525e0 | 1860 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
1861 | } |
1862 | ||
1863 | dma_ops_free_addresses(dma_dom, address, pages); | |
1864 | ||
8fd524b3 | 1865 | return DMA_ERROR_CODE; |
cb76c322 JR |
1866 | } |
1867 | ||
431b2a20 JR |
1868 | /* |
1869 | * Does the reverse of the __map_single function. Must be called with | |
1870 | * the domain lock held too | |
1871 | */ | |
cd8c82e8 | 1872 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
1873 | dma_addr_t dma_addr, |
1874 | size_t size, | |
1875 | int dir) | |
1876 | { | |
1877 | dma_addr_t i, start; | |
1878 | unsigned int pages; | |
1879 | ||
8fd524b3 | 1880 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1881 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1882 | return; |
1883 | ||
e3c449f5 | 1884 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1885 | dma_addr &= PAGE_MASK; |
1886 | start = dma_addr; | |
1887 | ||
1888 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1889 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
1890 | start += PAGE_SIZE; |
1891 | } | |
1892 | ||
5774f7c5 JR |
1893 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1894 | ||
cb76c322 | 1895 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1896 | |
80be308d | 1897 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
6de8ad9b | 1898 | iommu_flush_pages(&dma_dom->domain, dma_addr, size); |
80be308d JR |
1899 | dma_dom->need_flush = false; |
1900 | } | |
cb76c322 JR |
1901 | } |
1902 | ||
431b2a20 JR |
1903 | /* |
1904 | * The exported map_single function for dma_ops. | |
1905 | */ | |
51491367 FT |
1906 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1907 | unsigned long offset, size_t size, | |
1908 | enum dma_data_direction dir, | |
1909 | struct dma_attrs *attrs) | |
4da70b9e JR |
1910 | { |
1911 | unsigned long flags; | |
4da70b9e | 1912 | struct protection_domain *domain; |
4da70b9e | 1913 | dma_addr_t addr; |
832a90c3 | 1914 | u64 dma_mask; |
51491367 | 1915 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1916 | |
0f2a86f2 JR |
1917 | INC_STATS_COUNTER(cnt_map_single); |
1918 | ||
94f6d190 JR |
1919 | domain = get_domain(dev); |
1920 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 1921 | return (dma_addr_t)paddr; |
94f6d190 JR |
1922 | else if (IS_ERR(domain)) |
1923 | return DMA_ERROR_CODE; | |
4da70b9e | 1924 | |
f99c0f1c JR |
1925 | dma_mask = *dev->dma_mask; |
1926 | ||
4da70b9e | 1927 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 1928 | |
cd8c82e8 | 1929 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 1930 | dma_mask); |
8fd524b3 | 1931 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
1932 | goto out; |
1933 | ||
0518a3a4 | 1934 | iommu_flush_complete(domain); |
4da70b9e JR |
1935 | |
1936 | out: | |
1937 | spin_unlock_irqrestore(&domain->lock, flags); | |
1938 | ||
1939 | return addr; | |
1940 | } | |
1941 | ||
431b2a20 JR |
1942 | /* |
1943 | * The exported unmap_single function for dma_ops. | |
1944 | */ | |
51491367 FT |
1945 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1946 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1947 | { |
1948 | unsigned long flags; | |
4da70b9e | 1949 | struct protection_domain *domain; |
4da70b9e | 1950 | |
146a6917 JR |
1951 | INC_STATS_COUNTER(cnt_unmap_single); |
1952 | ||
94f6d190 JR |
1953 | domain = get_domain(dev); |
1954 | if (IS_ERR(domain)) | |
5b28df6f JR |
1955 | return; |
1956 | ||
4da70b9e JR |
1957 | spin_lock_irqsave(&domain->lock, flags); |
1958 | ||
cd8c82e8 | 1959 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 1960 | |
0518a3a4 | 1961 | iommu_flush_complete(domain); |
4da70b9e JR |
1962 | |
1963 | spin_unlock_irqrestore(&domain->lock, flags); | |
1964 | } | |
1965 | ||
431b2a20 JR |
1966 | /* |
1967 | * This is a special map_sg function which is used if we should map a | |
1968 | * device which is not handled by an AMD IOMMU in the system. | |
1969 | */ | |
65b050ad JR |
1970 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1971 | int nelems, int dir) | |
1972 | { | |
1973 | struct scatterlist *s; | |
1974 | int i; | |
1975 | ||
1976 | for_each_sg(sglist, s, nelems, i) { | |
1977 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1978 | s->dma_length = s->length; | |
1979 | } | |
1980 | ||
1981 | return nelems; | |
1982 | } | |
1983 | ||
431b2a20 JR |
1984 | /* |
1985 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1986 | * lists). | |
1987 | */ | |
65b050ad | 1988 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1989 | int nelems, enum dma_data_direction dir, |
1990 | struct dma_attrs *attrs) | |
65b050ad JR |
1991 | { |
1992 | unsigned long flags; | |
65b050ad | 1993 | struct protection_domain *domain; |
65b050ad JR |
1994 | int i; |
1995 | struct scatterlist *s; | |
1996 | phys_addr_t paddr; | |
1997 | int mapped_elems = 0; | |
832a90c3 | 1998 | u64 dma_mask; |
65b050ad | 1999 | |
d03f067a JR |
2000 | INC_STATS_COUNTER(cnt_map_sg); |
2001 | ||
94f6d190 JR |
2002 | domain = get_domain(dev); |
2003 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2004 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2005 | else if (IS_ERR(domain)) |
2006 | return 0; | |
dbcc112e | 2007 | |
832a90c3 | 2008 | dma_mask = *dev->dma_mask; |
65b050ad | 2009 | |
65b050ad JR |
2010 | spin_lock_irqsave(&domain->lock, flags); |
2011 | ||
2012 | for_each_sg(sglist, s, nelems, i) { | |
2013 | paddr = sg_phys(s); | |
2014 | ||
cd8c82e8 | 2015 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2016 | paddr, s->length, dir, false, |
2017 | dma_mask); | |
65b050ad JR |
2018 | |
2019 | if (s->dma_address) { | |
2020 | s->dma_length = s->length; | |
2021 | mapped_elems++; | |
2022 | } else | |
2023 | goto unmap; | |
65b050ad JR |
2024 | } |
2025 | ||
0518a3a4 | 2026 | iommu_flush_complete(domain); |
65b050ad JR |
2027 | |
2028 | out: | |
2029 | spin_unlock_irqrestore(&domain->lock, flags); | |
2030 | ||
2031 | return mapped_elems; | |
2032 | unmap: | |
2033 | for_each_sg(sglist, s, mapped_elems, i) { | |
2034 | if (s->dma_address) | |
cd8c82e8 | 2035 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2036 | s->dma_length, dir); |
2037 | s->dma_address = s->dma_length = 0; | |
2038 | } | |
2039 | ||
2040 | mapped_elems = 0; | |
2041 | ||
2042 | goto out; | |
2043 | } | |
2044 | ||
431b2a20 JR |
2045 | /* |
2046 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2047 | * lists). | |
2048 | */ | |
65b050ad | 2049 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2050 | int nelems, enum dma_data_direction dir, |
2051 | struct dma_attrs *attrs) | |
65b050ad JR |
2052 | { |
2053 | unsigned long flags; | |
65b050ad JR |
2054 | struct protection_domain *domain; |
2055 | struct scatterlist *s; | |
65b050ad JR |
2056 | int i; |
2057 | ||
55877a6b JR |
2058 | INC_STATS_COUNTER(cnt_unmap_sg); |
2059 | ||
94f6d190 JR |
2060 | domain = get_domain(dev); |
2061 | if (IS_ERR(domain)) | |
5b28df6f JR |
2062 | return; |
2063 | ||
65b050ad JR |
2064 | spin_lock_irqsave(&domain->lock, flags); |
2065 | ||
2066 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2067 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2068 | s->dma_length, dir); |
65b050ad JR |
2069 | s->dma_address = s->dma_length = 0; |
2070 | } | |
2071 | ||
0518a3a4 | 2072 | iommu_flush_complete(domain); |
65b050ad JR |
2073 | |
2074 | spin_unlock_irqrestore(&domain->lock, flags); | |
2075 | } | |
2076 | ||
431b2a20 JR |
2077 | /* |
2078 | * The exported alloc_coherent function for dma_ops. | |
2079 | */ | |
5d8b53cf JR |
2080 | static void *alloc_coherent(struct device *dev, size_t size, |
2081 | dma_addr_t *dma_addr, gfp_t flag) | |
2082 | { | |
2083 | unsigned long flags; | |
2084 | void *virt_addr; | |
5d8b53cf | 2085 | struct protection_domain *domain; |
5d8b53cf | 2086 | phys_addr_t paddr; |
832a90c3 | 2087 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2088 | |
c8f0fb36 JR |
2089 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2090 | ||
94f6d190 JR |
2091 | domain = get_domain(dev); |
2092 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2093 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2094 | *dma_addr = __pa(virt_addr); | |
2095 | return virt_addr; | |
94f6d190 JR |
2096 | } else if (IS_ERR(domain)) |
2097 | return NULL; | |
5d8b53cf | 2098 | |
f99c0f1c JR |
2099 | dma_mask = dev->coherent_dma_mask; |
2100 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2101 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2102 | |
2103 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2104 | if (!virt_addr) | |
b25ae679 | 2105 | return NULL; |
5d8b53cf | 2106 | |
5d8b53cf JR |
2107 | paddr = virt_to_phys(virt_addr); |
2108 | ||
832a90c3 JR |
2109 | if (!dma_mask) |
2110 | dma_mask = *dev->dma_mask; | |
2111 | ||
5d8b53cf JR |
2112 | spin_lock_irqsave(&domain->lock, flags); |
2113 | ||
cd8c82e8 | 2114 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2115 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2116 | |
8fd524b3 | 2117 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2118 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2119 | goto out_free; |
367d04c4 | 2120 | } |
5d8b53cf | 2121 | |
0518a3a4 | 2122 | iommu_flush_complete(domain); |
5d8b53cf | 2123 | |
5d8b53cf JR |
2124 | spin_unlock_irqrestore(&domain->lock, flags); |
2125 | ||
2126 | return virt_addr; | |
5b28df6f JR |
2127 | |
2128 | out_free: | |
2129 | ||
2130 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2131 | ||
2132 | return NULL; | |
5d8b53cf JR |
2133 | } |
2134 | ||
431b2a20 JR |
2135 | /* |
2136 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2137 | */ |
5d8b53cf JR |
2138 | static void free_coherent(struct device *dev, size_t size, |
2139 | void *virt_addr, dma_addr_t dma_addr) | |
2140 | { | |
2141 | unsigned long flags; | |
5d8b53cf | 2142 | struct protection_domain *domain; |
5d8b53cf | 2143 | |
5d31ee7e JR |
2144 | INC_STATS_COUNTER(cnt_free_coherent); |
2145 | ||
94f6d190 JR |
2146 | domain = get_domain(dev); |
2147 | if (IS_ERR(domain)) | |
5b28df6f JR |
2148 | goto free_mem; |
2149 | ||
5d8b53cf JR |
2150 | spin_lock_irqsave(&domain->lock, flags); |
2151 | ||
cd8c82e8 | 2152 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2153 | |
0518a3a4 | 2154 | iommu_flush_complete(domain); |
5d8b53cf JR |
2155 | |
2156 | spin_unlock_irqrestore(&domain->lock, flags); | |
2157 | ||
2158 | free_mem: | |
2159 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2160 | } | |
2161 | ||
b39ba6ad JR |
2162 | /* |
2163 | * This function is called by the DMA layer to find out if we can handle a | |
2164 | * particular device. It is part of the dma_ops. | |
2165 | */ | |
2166 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2167 | { | |
420aef8a | 2168 | return check_device(dev); |
b39ba6ad JR |
2169 | } |
2170 | ||
c432f3df | 2171 | /* |
431b2a20 JR |
2172 | * The function for pre-allocating protection domains. |
2173 | * | |
c432f3df JR |
2174 | * If the driver core informs the DMA layer if a driver grabs a device |
2175 | * we don't need to preallocate the protection domains anymore. | |
2176 | * For now we have to. | |
2177 | */ | |
0e93dd88 | 2178 | static void prealloc_protection_domains(void) |
c432f3df JR |
2179 | { |
2180 | struct pci_dev *dev = NULL; | |
2181 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2182 | u16 devid; |
c432f3df JR |
2183 | |
2184 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
98fc5a69 JR |
2185 | |
2186 | /* Do we handle this device? */ | |
2187 | if (!check_device(&dev->dev)) | |
c432f3df | 2188 | continue; |
98fc5a69 JR |
2189 | |
2190 | /* Is there already any domain for it? */ | |
15898bbc | 2191 | if (domain_for_device(&dev->dev)) |
c432f3df | 2192 | continue; |
98fc5a69 JR |
2193 | |
2194 | devid = get_device_id(&dev->dev); | |
2195 | ||
87a64d52 | 2196 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2197 | if (!dma_dom) |
2198 | continue; | |
2199 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2200 | dma_dom->target_dev = devid; |
2201 | ||
15898bbc | 2202 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2203 | |
bd60b735 | 2204 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2205 | } |
2206 | } | |
2207 | ||
160c1d8e | 2208 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2209 | .alloc_coherent = alloc_coherent, |
2210 | .free_coherent = free_coherent, | |
51491367 FT |
2211 | .map_page = map_page, |
2212 | .unmap_page = unmap_page, | |
6631ee9d JR |
2213 | .map_sg = map_sg, |
2214 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2215 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2216 | }; |
2217 | ||
431b2a20 JR |
2218 | /* |
2219 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2220 | */ | |
6631ee9d JR |
2221 | int __init amd_iommu_init_dma_ops(void) |
2222 | { | |
2223 | struct amd_iommu *iommu; | |
6631ee9d JR |
2224 | int ret; |
2225 | ||
431b2a20 JR |
2226 | /* |
2227 | * first allocate a default protection domain for every IOMMU we | |
2228 | * found in the system. Devices not assigned to any other | |
2229 | * protection domain will be assigned to the default one. | |
2230 | */ | |
3bd22172 | 2231 | for_each_iommu(iommu) { |
87a64d52 | 2232 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2233 | if (iommu->default_dom == NULL) |
2234 | return -ENOMEM; | |
e2dc14a2 | 2235 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2236 | ret = iommu_init_unity_mappings(iommu); |
2237 | if (ret) | |
2238 | goto free_domains; | |
2239 | } | |
2240 | ||
431b2a20 | 2241 | /* |
8793abeb | 2242 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2243 | */ |
8793abeb | 2244 | prealloc_protection_domains(); |
6631ee9d JR |
2245 | |
2246 | iommu_detected = 1; | |
75f1cdf1 | 2247 | swiotlb = 0; |
92af4e29 | 2248 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
2249 | gart_iommu_aperture_disabled = 1; |
2250 | gart_iommu_aperture = 0; | |
92af4e29 | 2251 | #endif |
6631ee9d | 2252 | |
431b2a20 | 2253 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2254 | dma_ops = &amd_iommu_dma_ops; |
2255 | ||
26961efe | 2256 | register_iommu(&amd_iommu_ops); |
26961efe | 2257 | |
7f26508b JR |
2258 | amd_iommu_stats_init(); |
2259 | ||
6631ee9d JR |
2260 | return 0; |
2261 | ||
2262 | free_domains: | |
2263 | ||
3bd22172 | 2264 | for_each_iommu(iommu) { |
6631ee9d JR |
2265 | if (iommu->default_dom) |
2266 | dma_ops_domain_free(iommu->default_dom); | |
2267 | } | |
2268 | ||
2269 | return ret; | |
2270 | } | |
6d98cd80 JR |
2271 | |
2272 | /***************************************************************************** | |
2273 | * | |
2274 | * The following functions belong to the exported interface of AMD IOMMU | |
2275 | * | |
2276 | * This interface allows access to lower level functions of the IOMMU | |
2277 | * like protection domain handling and assignement of devices to domains | |
2278 | * which is not possible with the dma_ops interface. | |
2279 | * | |
2280 | *****************************************************************************/ | |
2281 | ||
6d98cd80 JR |
2282 | static void cleanup_domain(struct protection_domain *domain) |
2283 | { | |
492667da | 2284 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2285 | unsigned long flags; |
6d98cd80 JR |
2286 | |
2287 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2288 | ||
492667da JR |
2289 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
2290 | struct device *dev = dev_data->dev; | |
2291 | ||
2292 | do_detach(dev); | |
2293 | atomic_set(&dev_data->bind, 0); | |
2294 | } | |
6d98cd80 JR |
2295 | |
2296 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2297 | } | |
2298 | ||
2650815f JR |
2299 | static void protection_domain_free(struct protection_domain *domain) |
2300 | { | |
2301 | if (!domain) | |
2302 | return; | |
2303 | ||
aeb26f55 JR |
2304 | del_domain_from_list(domain); |
2305 | ||
2650815f JR |
2306 | if (domain->id) |
2307 | domain_id_free(domain->id); | |
2308 | ||
2309 | kfree(domain); | |
2310 | } | |
2311 | ||
2312 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2313 | { |
2314 | struct protection_domain *domain; | |
2315 | ||
2316 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2317 | if (!domain) | |
2650815f | 2318 | return NULL; |
c156e347 JR |
2319 | |
2320 | spin_lock_init(&domain->lock); | |
c156e347 JR |
2321 | domain->id = domain_id_alloc(); |
2322 | if (!domain->id) | |
2650815f | 2323 | goto out_err; |
7c392cbe | 2324 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2325 | |
aeb26f55 JR |
2326 | add_domain_to_list(domain); |
2327 | ||
2650815f JR |
2328 | return domain; |
2329 | ||
2330 | out_err: | |
2331 | kfree(domain); | |
2332 | ||
2333 | return NULL; | |
2334 | } | |
2335 | ||
2336 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2337 | { | |
2338 | struct protection_domain *domain; | |
2339 | ||
2340 | domain = protection_domain_alloc(); | |
2341 | if (!domain) | |
c156e347 | 2342 | goto out_free; |
2650815f JR |
2343 | |
2344 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2345 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2346 | if (!domain->pt_root) | |
2347 | goto out_free; | |
2348 | ||
2349 | dom->priv = domain; | |
2350 | ||
2351 | return 0; | |
2352 | ||
2353 | out_free: | |
2650815f | 2354 | protection_domain_free(domain); |
c156e347 JR |
2355 | |
2356 | return -ENOMEM; | |
2357 | } | |
2358 | ||
98383fc3 JR |
2359 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2360 | { | |
2361 | struct protection_domain *domain = dom->priv; | |
2362 | ||
2363 | if (!domain) | |
2364 | return; | |
2365 | ||
2366 | if (domain->dev_cnt > 0) | |
2367 | cleanup_domain(domain); | |
2368 | ||
2369 | BUG_ON(domain->dev_cnt != 0); | |
2370 | ||
2371 | free_pagetable(domain); | |
2372 | ||
2373 | domain_id_free(domain->id); | |
2374 | ||
2375 | kfree(domain); | |
2376 | ||
2377 | dom->priv = NULL; | |
2378 | } | |
2379 | ||
684f2888 JR |
2380 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2381 | struct device *dev) | |
2382 | { | |
657cbb6b | 2383 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2384 | struct amd_iommu *iommu; |
684f2888 JR |
2385 | u16 devid; |
2386 | ||
98fc5a69 | 2387 | if (!check_device(dev)) |
684f2888 JR |
2388 | return; |
2389 | ||
98fc5a69 | 2390 | devid = get_device_id(dev); |
684f2888 | 2391 | |
657cbb6b | 2392 | if (dev_data->domain != NULL) |
15898bbc | 2393 | detach_device(dev); |
684f2888 JR |
2394 | |
2395 | iommu = amd_iommu_rlookup_table[devid]; | |
2396 | if (!iommu) | |
2397 | return; | |
2398 | ||
3fa43655 | 2399 | iommu_flush_device(dev); |
684f2888 JR |
2400 | iommu_completion_wait(iommu); |
2401 | } | |
2402 | ||
01106066 JR |
2403 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2404 | struct device *dev) | |
2405 | { | |
2406 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2407 | struct iommu_dev_data *dev_data; |
01106066 | 2408 | struct amd_iommu *iommu; |
15898bbc | 2409 | int ret; |
01106066 JR |
2410 | u16 devid; |
2411 | ||
98fc5a69 | 2412 | if (!check_device(dev)) |
01106066 JR |
2413 | return -EINVAL; |
2414 | ||
657cbb6b JR |
2415 | dev_data = dev->archdata.iommu; |
2416 | ||
98fc5a69 | 2417 | devid = get_device_id(dev); |
01106066 JR |
2418 | |
2419 | iommu = amd_iommu_rlookup_table[devid]; | |
2420 | if (!iommu) | |
2421 | return -EINVAL; | |
2422 | ||
657cbb6b | 2423 | if (dev_data->domain) |
15898bbc | 2424 | detach_device(dev); |
01106066 | 2425 | |
15898bbc | 2426 | ret = attach_device(dev, domain); |
01106066 JR |
2427 | |
2428 | iommu_completion_wait(iommu); | |
2429 | ||
15898bbc | 2430 | return ret; |
01106066 JR |
2431 | } |
2432 | ||
c6229ca6 JR |
2433 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2434 | unsigned long iova, phys_addr_t paddr, | |
2435 | size_t size, int iommu_prot) | |
2436 | { | |
2437 | struct protection_domain *domain = dom->priv; | |
2438 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2439 | int prot = 0; | |
2440 | int ret; | |
2441 | ||
2442 | if (iommu_prot & IOMMU_READ) | |
2443 | prot |= IOMMU_PROT_IR; | |
2444 | if (iommu_prot & IOMMU_WRITE) | |
2445 | prot |= IOMMU_PROT_IW; | |
2446 | ||
2447 | iova &= PAGE_MASK; | |
2448 | paddr &= PAGE_MASK; | |
2449 | ||
2450 | for (i = 0; i < npages; ++i) { | |
abdc5eb3 | 2451 | ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k); |
c6229ca6 JR |
2452 | if (ret) |
2453 | return ret; | |
2454 | ||
2455 | iova += PAGE_SIZE; | |
2456 | paddr += PAGE_SIZE; | |
2457 | } | |
2458 | ||
2459 | return 0; | |
2460 | } | |
2461 | ||
eb74ff6c JR |
2462 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2463 | unsigned long iova, size_t size) | |
2464 | { | |
2465 | ||
2466 | struct protection_domain *domain = dom->priv; | |
2467 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2468 | ||
2469 | iova &= PAGE_MASK; | |
2470 | ||
2471 | for (i = 0; i < npages; ++i) { | |
a6b256b4 | 2472 | iommu_unmap_page(domain, iova, PM_MAP_4k); |
eb74ff6c JR |
2473 | iova += PAGE_SIZE; |
2474 | } | |
2475 | ||
601367d7 | 2476 | iommu_flush_tlb_pde(domain); |
eb74ff6c JR |
2477 | } |
2478 | ||
645c4c8d JR |
2479 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2480 | unsigned long iova) | |
2481 | { | |
2482 | struct protection_domain *domain = dom->priv; | |
2483 | unsigned long offset = iova & ~PAGE_MASK; | |
2484 | phys_addr_t paddr; | |
2485 | u64 *pte; | |
2486 | ||
a6b256b4 | 2487 | pte = fetch_pte(domain, iova, PM_MAP_4k); |
645c4c8d | 2488 | |
a6d41a40 | 2489 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2490 | return 0; |
2491 | ||
2492 | paddr = *pte & IOMMU_PAGE_MASK; | |
2493 | paddr |= offset; | |
2494 | ||
2495 | return paddr; | |
2496 | } | |
2497 | ||
dbb9fd86 SY |
2498 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2499 | unsigned long cap) | |
2500 | { | |
2501 | return 0; | |
2502 | } | |
2503 | ||
26961efe JR |
2504 | static struct iommu_ops amd_iommu_ops = { |
2505 | .domain_init = amd_iommu_domain_init, | |
2506 | .domain_destroy = amd_iommu_domain_destroy, | |
2507 | .attach_dev = amd_iommu_attach_device, | |
2508 | .detach_dev = amd_iommu_detach_device, | |
2509 | .map = amd_iommu_map_range, | |
2510 | .unmap = amd_iommu_unmap_range, | |
2511 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2512 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2513 | }; |
2514 | ||
0feae533 JR |
2515 | /***************************************************************************** |
2516 | * | |
2517 | * The next functions do a basic initialization of IOMMU for pass through | |
2518 | * mode | |
2519 | * | |
2520 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2521 | * DMA-API translation. | |
2522 | * | |
2523 | *****************************************************************************/ | |
2524 | ||
2525 | int __init amd_iommu_init_passthrough(void) | |
2526 | { | |
15898bbc | 2527 | struct amd_iommu *iommu; |
0feae533 | 2528 | struct pci_dev *dev = NULL; |
15898bbc | 2529 | u16 devid; |
0feae533 | 2530 | |
af901ca1 | 2531 | /* allocate passthrough domain */ |
0feae533 JR |
2532 | pt_domain = protection_domain_alloc(); |
2533 | if (!pt_domain) | |
2534 | return -ENOMEM; | |
2535 | ||
2536 | pt_domain->mode |= PAGE_MODE_NONE; | |
2537 | ||
2538 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
0feae533 | 2539 | |
98fc5a69 | 2540 | if (!check_device(&dev->dev)) |
0feae533 JR |
2541 | continue; |
2542 | ||
98fc5a69 JR |
2543 | devid = get_device_id(&dev->dev); |
2544 | ||
15898bbc | 2545 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2546 | if (!iommu) |
2547 | continue; | |
2548 | ||
15898bbc | 2549 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2550 | } |
2551 | ||
2552 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2553 | ||
2554 | return 0; | |
2555 | } |