[linux-2.6-block.git] / arch / x86 / include / uapi / asm / hyperv.h

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _ASM_X86_HYPERV_H
#define _ASM_X86_HYPERV_H

#include <linux/types.h>

/*
 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
 */
#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS	0x40000000
#define HYPERV_CPUID_INTERFACE			0x40000001
#define HYPERV_CPUID_VERSION			0x40000002
#define HYPERV_CPUID_FEATURES			0x40000003
#define HYPERV_CPUID_ENLIGHTMENT_INFO		0x40000004
#define HYPERV_CPUID_IMPLEMENT_LIMITS		0x40000005

#define HYPERV_HYPERVISOR_PRESENT_BIT		0x80000000
#define HYPERV_CPUID_MIN			0x40000005
#define HYPERV_CPUID_MAX			0x4000ffff

/*
 * Feature identification. EAX indicates which features are available
 * to the partition based upon the current partition privileges.
 */

/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
#define HV_X64_MSR_VP_RUNTIME_AVAILABLE		(1 << 0)
/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE	(1 << 1)
/* Partition reference TSC MSR is available */
#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE              (1 << 9)

/* A partition's reference time stamp counter (TSC) page */
#define HV_X64_MSR_REFERENCE_TSC		0x40000021

/*
 * There is a single feature flag that signifies if the partition has access
 * to MSRs with local APIC and TSC frequencies.
 */
#define HV_X64_ACCESS_FREQUENCY_MSRS		(1 << 11)

/* AccessReenlightenmentControls privilege */
#define HV_X64_ACCESS_REENLIGHTENMENT		BIT(13)

/*
 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
 */
#define HV_X64_MSR_SYNIC_AVAILABLE		(1 << 2)
/*
 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
 * HV_X64_MSR_STIMER3_COUNT) available
 */
#define HV_X64_MSR_SYNTIMER_AVAILABLE		(1 << 3)
/*
 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
 * are available
 */
#define HV_X64_MSR_APIC_ACCESS_AVAILABLE	(1 << 4)
/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
#define HV_X64_MSR_HYPERCALL_AVAILABLE		(1 << 5)
/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
#define HV_X64_MSR_VP_INDEX_AVAILABLE		(1 << 6)
/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
#define HV_X64_MSR_RESET_AVAILABLE		(1 << 7)
 /*
  * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
  * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
  * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
  */
#define HV_X64_MSR_STAT_PAGES_AVAILABLE		(1 << 8)

/* Frequency MSRs available */
#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE	(1 << 8)

/* Crash MSR available */
#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)

/*
 * Feature identification: EBX indicates which flags were specified at
 * partition creation. The format is the same as the partition creation
 * flag structure defined in section Partition Creation Flags.
 */
#define HV_X64_CREATE_PARTITIONS		(1 << 0)
#define HV_X64_ACCESS_PARTITION_ID		(1 << 1)
#define HV_X64_ACCESS_MEMORY_POOL		(1 << 2)
#define HV_X64_ADJUST_MESSAGE_BUFFERS		(1 << 3)
#define HV_X64_POST_MESSAGES			(1 << 4)
#define HV_X64_SIGNAL_EVENTS			(1 << 5)
#define HV_X64_CREATE_PORT			(1 << 6)
#define HV_X64_CONNECT_PORT			(1 << 7)
#define HV_X64_ACCESS_STATS			(1 << 8)
#define HV_X64_DEBUGGING			(1 << 11)
#define HV_X64_CPU_POWER_MANAGEMENT		(1 << 12)
#define HV_X64_CONFIGURE_PROFILER		(1 << 13)

/*
 * Feature identification. EDX indicates which miscellaneous features
 * are available to the partition.
 */
/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
#define HV_X64_MWAIT_AVAILABLE				(1 << 0)
/* Guest debugging support is available */
#define HV_X64_GUEST_DEBUGGING_AVAILABLE		(1 << 1)
/* Performance Monitor support is available*/
#define HV_X64_PERF_MONITOR_AVAILABLE			(1 << 2)
/* Support for physical CPU dynamic partitioning events is available*/
#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE	(1 << 3)
/*
 * Support for passing hypercall input parameter block via XMM
 * registers is available
 */
#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE		(1 << 4)
/* Support for a virtual guest idle state is available */
#define HV_X64_GUEST_IDLE_STATE_AVAILABLE		(1 << 5)
/* Guest crash data handler available */
#define HV_X64_GUEST_CRASH_MSR_AVAILABLE		(1 << 10)

/*
 * Implementation recommendations. Indicates which behaviors the hypervisor
 * recommends the OS implement for optimal performance.
 */
 /*
  * Recommend using hypercall for address space switches rather
  * than MOV to CR3 instruction
  */
#define HV_X64_AS_SWITCH_RECOMMENDED		(1 << 0)
/* Recommend using hypercall for local TLB flushes rather
 * than INVLPG or MOV to CR3 instructions */
#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED	(1 << 1)
/*
 * Recommend using hypercall for remote TLB flushes rather
 * than inter-processor interrupts
 */
#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED	(1 << 2)
/*
 * Recommend using MSRs for accessing APIC registers
 * EOI, ICR and TPR rather than their memory-mapped counterparts
 */
#define HV_X64_APIC_ACCESS_RECOMMENDED		(1 << 3)
/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
#define HV_X64_SYSTEM_RESET_RECOMMENDED		(1 << 4)
/*
 * Recommend using relaxed timing for this partition. If used,
 * the VM should disable any watchdog timeouts that rely on the
 * timely delivery of external interrupts
 */
#define HV_X64_RELAXED_TIMING_RECOMMENDED	(1 << 5)

/*
 * Virtual APIC support
 */
#define HV_X64_DEPRECATING_AEOI_RECOMMENDED	(1 << 9)

/* Recommend using the newer ExProcessorMasks interface */
#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED	(1 << 11)

/*
 * Crash notification flag.
 */
#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)

/* MSR used to identify the guest OS. */
#define HV_X64_MSR_GUEST_OS_ID			0x40000000

/* MSR used to setup pages used to communicate with the hypervisor. */
#define HV_X64_MSR_HYPERCALL			0x40000001

/* MSR used to provide vcpu index */
#define HV_X64_MSR_VP_INDEX			0x40000002

/* MSR used to reset the guest OS. */
#define HV_X64_MSR_RESET			0x40000003

/* MSR used to provide vcpu runtime in 100ns units */
#define HV_X64_MSR_VP_RUNTIME			0x40000010

/* MSR used to read the per-partition time reference counter */
#define HV_X64_MSR_TIME_REF_COUNT		0x40000020

/* MSR used to retrieve the TSC frequency */
#define HV_X64_MSR_TSC_FREQUENCY		0x40000022

/* MSR used to retrieve the local APIC timer frequency */
#define HV_X64_MSR_APIC_FREQUENCY		0x40000023

/* Define the virtual APIC registers */
#define HV_X64_MSR_EOI				0x40000070
#define HV_X64_MSR_ICR				0x40000071
#define HV_X64_MSR_TPR				0x40000072
#define HV_X64_MSR_APIC_ASSIST_PAGE		0x40000073

/* Define synthetic interrupt controller model specific registers. */
#define HV_X64_MSR_SCONTROL			0x40000080
#define HV_X64_MSR_SVERSION			0x40000081
#define HV_X64_MSR_SIEFP			0x40000082
#define HV_X64_MSR_SIMP				0x40000083
#define HV_X64_MSR_EOM				0x40000084
#define HV_X64_MSR_SINT0			0x40000090
#define HV_X64_MSR_SINT1			0x40000091
#define HV_X64_MSR_SINT2			0x40000092
#define HV_X64_MSR_SINT3			0x40000093
#define HV_X64_MSR_SINT4			0x40000094
#define HV_X64_MSR_SINT5			0x40000095
#define HV_X64_MSR_SINT6			0x40000096
#define HV_X64_MSR_SINT7			0x40000097
#define HV_X64_MSR_SINT8			0x40000098
#define HV_X64_MSR_SINT9			0x40000099
#define HV_X64_MSR_SINT10			0x4000009A
#define HV_X64_MSR_SINT11			0x4000009B
#define HV_X64_MSR_SINT12			0x4000009C
#define HV_X64_MSR_SINT13			0x4000009D
#define HV_X64_MSR_SINT14			0x4000009E
#define HV_X64_MSR_SINT15			0x4000009F

/*
 * Synthetic Timer MSRs. Four timers per vcpu.
 */
#define HV_X64_MSR_STIMER0_CONFIG		0x400000B0
#define HV_X64_MSR_STIMER0_COUNT		0x400000B1
#define HV_X64_MSR_STIMER1_CONFIG		0x400000B2
#define HV_X64_MSR_STIMER1_COUNT		0x400000B3
#define HV_X64_MSR_STIMER2_CONFIG		0x400000B4
#define HV_X64_MSR_STIMER2_COUNT		0x400000B5
#define HV_X64_MSR_STIMER3_CONFIG		0x400000B6
#define HV_X64_MSR_STIMER3_COUNT		0x400000B7

/* Hyper-V guest crash notification MSR's */
#define HV_X64_MSR_CRASH_P0			0x40000100
#define HV_X64_MSR_CRASH_P1			0x40000101
#define HV_X64_MSR_CRASH_P2			0x40000102
#define HV_X64_MSR_CRASH_P3			0x40000103
#define HV_X64_MSR_CRASH_P4			0x40000104
#define HV_X64_MSR_CRASH_CTL			0x40000105
#define HV_X64_MSR_CRASH_CTL_NOTIFY		(1ULL << 63)
#define HV_X64_MSR_CRASH_PARAMS		\
		(1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))

/* TSC emulation after migration */
#define HV_X64_MSR_REENLIGHTENMENT_CONTROL	0x40000106

struct hv_reenlightenment_control {
	__u64 vector:8;
	__u64 reserved1:8;
	__u64 enabled:1;
	__u64 reserved2:15;
	__u64 target_vp:32;
};

#define HV_X64_MSR_TSC_EMULATION_CONTROL	0x40000107
#define HV_X64_MSR_TSC_EMULATION_STATUS		0x40000108

struct hv_tsc_emulation_control {
	__u64 enabled:1;
	__u64 reserved:63;
};

struct hv_tsc_emulation_status {
	__u64 inprogress:1;
	__u64 reserved:63;
};

#define HV_X64_MSR_HYPERCALL_ENABLE		0x00000001
#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT	12
#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK	\
		(~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))

/* Declare the various hypercall operations. */
#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE	0x0002
#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST	0x0003
#define HVCALL_NOTIFY_LONG_SPIN_WAIT		0x0008
#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX  0x0013
#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX   0x0014
#define HVCALL_POST_MESSAGE			0x005c
#define HVCALL_SIGNAL_EVENT			0x005d

#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE		0x00000001
#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT	12
#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK	\
		(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))

#define HV_X64_MSR_TSC_REFERENCE_ENABLE		0x00000001
#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT	12

#define HV_PROCESSOR_POWER_STATE_C0		0
#define HV_PROCESSOR_POWER_STATE_C1		1
#define HV_PROCESSOR_POWER_STATE_C2		2
#define HV_PROCESSOR_POWER_STATE_C3		3

#define HV_FLUSH_ALL_PROCESSORS			BIT(0)
#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES	BIT(1)
#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY	BIT(2)
#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT	BIT(3)

enum HV_GENERIC_SET_FORMAT {
	HV_GENERIC_SET_SPARCE_4K,
	HV_GENERIC_SET_ALL,
};

/* hypercall status code */
#define HV_STATUS_SUCCESS			0
#define HV_STATUS_INVALID_HYPERCALL_CODE	2
#define HV_STATUS_INVALID_HYPERCALL_INPUT	3
#define HV_STATUS_INVALID_ALIGNMENT		4
#define HV_STATUS_INSUFFICIENT_MEMORY		11
#define HV_STATUS_INVALID_CONNECTION_ID		18
#define HV_STATUS_INSUFFICIENT_BUFFERS		19

typedef struct _HV_REFERENCE_TSC_PAGE {
	__u32 tsc_sequence;
	__u32 res1;
	__u64 tsc_scale;
	__s64 tsc_offset;
} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;

/* Define the number of synthetic interrupt sources. */
#define HV_SYNIC_SINT_COUNT		(16)
/* Define the expected SynIC version. */
#define HV_SYNIC_VERSION_1		(0x1)

#define HV_SYNIC_CONTROL_ENABLE		(1ULL << 0)
#define HV_SYNIC_SIMP_ENABLE		(1ULL << 0)
#define HV_SYNIC_SIEFP_ENABLE		(1ULL << 0)
#define HV_SYNIC_SINT_MASKED		(1ULL << 16)
#define HV_SYNIC_SINT_AUTO_EOI		(1ULL << 17)
#define HV_SYNIC_SINT_VECTOR_MASK	(0xFF)

#define HV_SYNIC_STIMER_COUNT		(4)

/* Define synthetic interrupt controller message constants. */
#define HV_MESSAGE_SIZE			(256)
#define HV_MESSAGE_PAYLOAD_BYTE_COUNT	(240)
#define HV_MESSAGE_PAYLOAD_QWORD_COUNT	(30)

/* Define hypervisor message types. */
enum hv_message_type {
	HVMSG_NONE			= 0x00000000,

	/* Memory access messages. */
	HVMSG_UNMAPPED_GPA		= 0x80000000,
	HVMSG_GPA_INTERCEPT		= 0x80000001,

	/* Timer notification messages. */
	HVMSG_TIMER_EXPIRED			= 0x80000010,

	/* Error messages. */
	HVMSG_INVALID_VP_REGISTER_VALUE	= 0x80000020,
	HVMSG_UNRECOVERABLE_EXCEPTION	= 0x80000021,
	HVMSG_UNSUPPORTED_FEATURE		= 0x80000022,

	/* Trace buffer complete messages. */
	HVMSG_EVENTLOG_BUFFERCOMPLETE	= 0x80000040,

	/* Platform-specific processor intercept messages. */
	HVMSG_X64_IOPORT_INTERCEPT		= 0x80010000,
	HVMSG_X64_MSR_INTERCEPT		= 0x80010001,
	HVMSG_X64_CPUID_INTERCEPT		= 0x80010002,
	HVMSG_X64_EXCEPTION_INTERCEPT	= 0x80010003,
	HVMSG_X64_APIC_EOI			= 0x80010004,
	HVMSG_X64_LEGACY_FP_ERROR		= 0x80010005
};

/* Define synthetic interrupt controller message flags. */
union hv_message_flags {
	__u8 asu8;
	struct {
		__u8 msg_pending:1;
		__u8 reserved:7;
	};
};

/* Define port identifier type. */
union hv_port_id {
	__u32 asu32;
	struct {
		__u32 id:24;
		__u32 reserved:8;
	} u;
};

/* Define synthetic interrupt controller message header. */
struct hv_message_header {
	__u32 message_type;
	__u8 payload_size;
	union hv_message_flags message_flags;
	__u8 reserved[2];
	union {
		__u64 sender;
		union hv_port_id port;
	};
};

/* Define synthetic interrupt controller message format. */
struct hv_message {
	struct hv_message_header header;
	union {
		__u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
	} u;
};

/* Define the synthetic interrupt message page layout. */
struct hv_message_page {
	struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
};

/* Define timer message payload structure. */
struct hv_timer_message_payload {
	__u32 timer_index;
	__u32 reserved;
	__u64 expiration_time;	/* When the timer expired */
	__u64 delivery_time;	/* When the message was delivered */
};

#define HV_STIMER_ENABLE		(1ULL << 0)
#define HV_STIMER_PERIODIC		(1ULL << 1)
#define HV_STIMER_LAZY			(1ULL << 2)
#define HV_STIMER_AUTOENABLE		(1ULL << 3)
#define HV_STIMER_SINT(config)		(__u8)(((config) >> 16) & 0x0F)

#endif
Commit	Line	Data
6f52b16c	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
e08cae41 PA	2	#ifndef _ASM_X86_HYPERV_H
e08cae41 PA	3	#define _ASM_X86_HYPERV_H
1d5103c1 GN	4
	5	#include <linux/types.h>
	6
	7	/*
	8	* The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
	9	* is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
	10	*/
	11	#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
	12	#define HYPERV_CPUID_INTERFACE 0x40000001
	13	#define HYPERV_CPUID_VERSION 0x40000002
	14	#define HYPERV_CPUID_FEATURES 0x40000003
	15	#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
	16	#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
	17
a2a47c6c KS	18	#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000
a2a47c6c KS	19	#define HYPERV_CPUID_MIN 0x40000005
e08cae41	20	#define HYPERV_CPUID_MAX 0x4000ffff
a2a47c6c	21
1d5103c1 GN	22	/*
	23	* Feature identification. EAX indicates which features are available
	24	* to the partition based upon the current partition privileges.
	25	*/
	26
	27	/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
	28	#define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0)
	29	/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
	30	#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1)
ca9357bd S	31	/* Partition reference TSC MSR is available */
ca9357bd S	32	#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE (1 << 9)
9e7827b5	33
e984097b VR	34	/* A partition's reference time stamp counter (TSC) page */
	35	#define HV_X64_MSR_REFERENCE_TSC 0x40000021
	36
9e7827b5	37	/*
2cf02842 VK	38	* There is a single feature flag that signifies if the partition has access
2cf02842 VK	39	* to MSRs with local APIC and TSC frequencies.
9e7827b5	40	*/
2cf02842	41	#define HV_X64_ACCESS_FREQUENCY_MSRS (1 << 11)
9e7827b5	42
93286261 VK	43	/* AccessReenlightenmentControls privilege */
	44	#define HV_X64_ACCESS_REENLIGHTENMENT BIT(13)
	45
1d5103c1 GN	46	/*
	47	* Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
	48	* and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
	49	*/
	50	#define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2)
	51	/*
	52	* Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
	53	* HV_X64_MSR_STIMER3_COUNT) available
	54	*/
	55	#define HV_X64_MSR_SYNTIMER_AVAILABLE (1 << 3)
	56	/*
	57	* APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
	58	* are available
	59	*/
	60	#define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4)
	61	/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
	62	#define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5)
	63	/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
	64	#define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6)
	65	/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
	66	#define HV_X64_MSR_RESET_AVAILABLE (1 << 7)
	67	/*
	68	* Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
	69	* HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
	70	* HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
	71	*/
	72	#define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8)
	73
2cf02842 VK	74	/* Frequency MSRs available */
	75	#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE (1 << 8)
	76
d058fa7e S	77	/* Crash MSR available */
	78	#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
	79
1d5103c1 GN	80	/*
	81	* Feature identification: EBX indicates which flags were specified at
	82	* partition creation. The format is the same as the partition creation
	83	* flag structure defined in section Partition Creation Flags.
	84	*/
	85	#define HV_X64_CREATE_PARTITIONS (1 << 0)
	86	#define HV_X64_ACCESS_PARTITION_ID (1 << 1)
	87	#define HV_X64_ACCESS_MEMORY_POOL (1 << 2)
	88	#define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3)
	89	#define HV_X64_POST_MESSAGES (1 << 4)
	90	#define HV_X64_SIGNAL_EVENTS (1 << 5)
	91	#define HV_X64_CREATE_PORT (1 << 6)
	92	#define HV_X64_CONNECT_PORT (1 << 7)
	93	#define HV_X64_ACCESS_STATS (1 << 8)
	94	#define HV_X64_DEBUGGING (1 << 11)
	95	#define HV_X64_CPU_POWER_MANAGEMENT (1 << 12)
	96	#define HV_X64_CONFIGURE_PROFILER (1 << 13)
	97
	98	/*
	99	* Feature identification. EDX indicates which miscellaneous features
	100	* are available to the partition.
	101	*/
	102	/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
	103	#define HV_X64_MWAIT_AVAILABLE (1 << 0)
	104	/* Guest debugging support is available */
	105	#define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1)
	106	/* Performance Monitor support is available*/
	107	#define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2)
	108	/* Support for physical CPU dynamic partitioning events is available*/
	109	#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3)
	110	/*
	111	* Support for passing hypercall input parameter block via XMM
	112	* registers is available
	113	*/
	114	#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4)
	115	/* Support for a virtual guest idle state is available */
	116	#define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5)
5d75a747 PB	117	/* Guest crash data handler available */
5d75a747 PB	118	#define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
1d5103c1 GN	119
	120	/*
	121	* Implementation recommendations. Indicates which behaviors the hypervisor
	122	* recommends the OS implement for optimal performance.
	123	*/
	124	/*
	125	* Recommend using hypercall for address space switches rather
	126	* than MOV to CR3 instruction
	127	*/
4539673a	128	#define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0)
1d5103c1 GN	129	/* Recommend using hypercall for local TLB flushes rather
	130	* than INVLPG or MOV to CR3 instructions */
	131	#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1)
	132	/*
	133	* Recommend using hypercall for remote TLB flushes rather
	134	* than inter-processor interrupts
	135	*/
	136	#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2)
	137	/*
	138	* Recommend using MSRs for accessing APIC registers
	139	* EOI, ICR and TPR rather than their memory-mapped counterparts
	140	*/
	141	#define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3)
	142	/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
	143	#define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4)
	144	/*
	145	* Recommend using relaxed timing for this partition. If used,
	146	* the VM should disable any watchdog timeouts that rely on the
	147	* timely delivery of external interrupts
	148	*/
	149	#define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5)
	150
6c248aad S	151	/*
	152	* Virtual APIC support
	153	*/
	154	#define HV_X64_DEPRECATING_AEOI_RECOMMENDED (1 << 9)
	155
628f54cc VK	156	/* Recommend using the newer ExProcessorMasks interface */
	157	#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11)
	158
d058fa7e S	159	/*
	160	* Crash notification flag.
	161	*/
	162	#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
	163
1d5103c1 GN	164	/* MSR used to identify the guest OS. */
	165	#define HV_X64_MSR_GUEST_OS_ID 0x40000000
	166
	167	/* MSR used to setup pages used to communicate with the hypervisor. */
	168	#define HV_X64_MSR_HYPERCALL 0x40000001
	169
	170	/* MSR used to provide vcpu index */
	171	#define HV_X64_MSR_VP_INDEX 0x40000002
	172
e516cebb AS	173	/* MSR used to reset the guest OS. */
	174	#define HV_X64_MSR_RESET 0x40000003
	175
9eec50b8 AS	176	/* MSR used to provide vcpu runtime in 100ns units */
	177	#define HV_X64_MSR_VP_RUNTIME 0x40000010
	178
a2a47c6c KS	179	/* MSR used to read the per-partition time reference counter */
	180	#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
	181
9e7827b5 S	182	/* MSR used to retrieve the TSC frequency */
	183	#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
	184
	185	/* MSR used to retrieve the local APIC timer frequency */
	186	#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
	187
1d5103c1 GN	188	/* Define the virtual APIC registers */
	189	#define HV_X64_MSR_EOI 0x40000070
	190	#define HV_X64_MSR_ICR 0x40000071
	191	#define HV_X64_MSR_TPR 0x40000072
	192	#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
	193
	194	/* Define synthetic interrupt controller model specific registers. */
	195	#define HV_X64_MSR_SCONTROL 0x40000080
	196	#define HV_X64_MSR_SVERSION 0x40000081
	197	#define HV_X64_MSR_SIEFP 0x40000082
	198	#define HV_X64_MSR_SIMP 0x40000083
	199	#define HV_X64_MSR_EOM 0x40000084
	200	#define HV_X64_MSR_SINT0 0x40000090
	201	#define HV_X64_MSR_SINT1 0x40000091
	202	#define HV_X64_MSR_SINT2 0x40000092
	203	#define HV_X64_MSR_SINT3 0x40000093
	204	#define HV_X64_MSR_SINT4 0x40000094
	205	#define HV_X64_MSR_SINT5 0x40000095
	206	#define HV_X64_MSR_SINT6 0x40000096
	207	#define HV_X64_MSR_SINT7 0x40000097
	208	#define HV_X64_MSR_SINT8 0x40000098
	209	#define HV_X64_MSR_SINT9 0x40000099
	210	#define HV_X64_MSR_SINT10 0x4000009A
	211	#define HV_X64_MSR_SINT11 0x4000009B
	212	#define HV_X64_MSR_SINT12 0x4000009C
	213	#define HV_X64_MSR_SINT13 0x4000009D
	214	#define HV_X64_MSR_SINT14 0x4000009E
	215	#define HV_X64_MSR_SINT15 0x4000009F
	216
4061ed9e S	217	/*
	218	* Synthetic Timer MSRs. Four timers per vcpu.
	219	*/
	220	#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
	221	#define HV_X64_MSR_STIMER0_COUNT 0x400000B1
	222	#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
	223	#define HV_X64_MSR_STIMER1_COUNT 0x400000B3
	224	#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
	225	#define HV_X64_MSR_STIMER2_COUNT 0x400000B5
	226	#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
	227	#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
1d5103c1	228
a88464a8 AS	229	/* Hyper-V guest crash notification MSR's */
	230	#define HV_X64_MSR_CRASH_P0 0x40000100
	231	#define HV_X64_MSR_CRASH_P1 0x40000101
	232	#define HV_X64_MSR_CRASH_P2 0x40000102
	233	#define HV_X64_MSR_CRASH_P3 0x40000103
	234	#define HV_X64_MSR_CRASH_P4 0x40000104
	235	#define HV_X64_MSR_CRASH_CTL 0x40000105
	236	#define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63)
	237	#define HV_X64_MSR_CRASH_PARAMS \
	238	(1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
	239
93286261 VK	240	/* TSC emulation after migration */
	241	#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
	242
	243	struct hv_reenlightenment_control {
89426646 KA	244	__u64 vector:8;
	245	__u64 reserved1:8;
	246	__u64 enabled:1;
	247	__u64 reserved2:15;
	248	__u64 target_vp:32;
93286261 VK	249	};
	250
	251	#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
	252	#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
	253
	254	struct hv_tsc_emulation_control {
89426646 KA	255	__u64 enabled:1;
89426646 KA	256	__u64 reserved:63;
93286261 VK	257	};
	258
	259	struct hv_tsc_emulation_status {
89426646 KA	260	__u64 inprogress:1;
89426646 KA	261	__u64 reserved:63;
93286261 VK	262	};
93286261 VK	263
1d5103c1 GN	264	#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
	265	#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
	266	#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
	267	(~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
	268
	269	/* Declare the various hypercall operations. */
2ffd9e33 VK	270	#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002
2ffd9e33 VK	271	#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003
8ed6d767	272	#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
628f54cc VK	273	#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013
628f54cc VK	274	#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014
18f09861 AS	275	#define HVCALL_POST_MESSAGE 0x005c
18f09861 AS	276	#define HVCALL_SIGNAL_EVENT 0x005d
1d5103c1 GN	277
	278	#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE 0x00000001
	279	#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT 12
	280	#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK \
	281	(~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
	282
e984097b VR	283	#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001
	284	#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
	285
1d5103c1 GN	286	#define HV_PROCESSOR_POWER_STATE_C0 0
	287	#define HV_PROCESSOR_POWER_STATE_C1 1
	288	#define HV_PROCESSOR_POWER_STATE_C2 2
	289	#define HV_PROCESSOR_POWER_STATE_C3 3
	290
2ffd9e33 VK	291	#define HV_FLUSH_ALL_PROCESSORS BIT(0)
	292	#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1)
	293	#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2)
	294	#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3)
	295
628f54cc VK	296	enum HV_GENERIC_SET_FORMAT {
	297	HV_GENERIC_SET_SPARCE_4K,
	298	HV_GENERIC_SET_ALL,
	299	};
	300
1d5103c1 GN	301	/* hypercall status code */
	302	#define HV_STATUS_SUCCESS 0
	303	#define HV_STATUS_INVALID_HYPERCALL_CODE 2
	304	#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
	305	#define HV_STATUS_INVALID_ALIGNMENT 4
89f9f679 DC	306	#define HV_STATUS_INSUFFICIENT_MEMORY 11
89f9f679 DC	307	#define HV_STATUS_INVALID_CONNECTION_ID 18
5289d3d1	308	#define HV_STATUS_INSUFFICIENT_BUFFERS 19
1d5103c1	309
e984097b VR	310	typedef struct _HV_REFERENCE_TSC_PAGE {
	311	__u32 tsc_sequence;
	312	__u32 res1;
	313	__u64 tsc_scale;
	314	__s64 tsc_offset;
	315	} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
	316
c75efa97 AS	317	/* Define the number of synthetic interrupt sources. */
	318	#define HV_SYNIC_SINT_COUNT (16)
	319	/* Define the expected SynIC version. */
	320	#define HV_SYNIC_VERSION_1 (0x1)
	321
	322	#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0)
	323	#define HV_SYNIC_SIMP_ENABLE (1ULL << 0)
	324	#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0)
	325	#define HV_SYNIC_SINT_MASKED (1ULL << 16)
	326	#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17)
	327	#define HV_SYNIC_SINT_VECTOR_MASK (0xFF)
	328
4f39bcfd AS	329	#define HV_SYNIC_STIMER_COUNT (4)
4f39bcfd AS	330
5b423efe AS	331	/* Define synthetic interrupt controller message constants. */
	332	#define HV_MESSAGE_SIZE (256)
	333	#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
	334	#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
	335
	336	/* Define hypervisor message types. */
	337	enum hv_message_type {
	338	HVMSG_NONE = 0x00000000,
	339
	340	/* Memory access messages. */
	341	HVMSG_UNMAPPED_GPA = 0x80000000,
	342	HVMSG_GPA_INTERCEPT = 0x80000001,
	343
	344	/* Timer notification messages. */
	345	HVMSG_TIMER_EXPIRED = 0x80000010,
	346
	347	/* Error messages. */
	348	HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
	349	HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
	350	HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
	351
	352	/* Trace buffer complete messages. */
	353	HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
	354
	355	/* Platform-specific processor intercept messages. */
	356	HVMSG_X64_IOPORT_INTERCEPT = 0x80010000,
	357	HVMSG_X64_MSR_INTERCEPT = 0x80010001,
	358	HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
	359	HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
	360	HVMSG_X64_APIC_EOI = 0x80010004,
	361	HVMSG_X64_LEGACY_FP_ERROR = 0x80010005
	362	};
	363
	364	/* Define synthetic interrupt controller message flags. */
	365	union hv_message_flags {
	366	__u8 asu8;
	367	struct {
	368	__u8 msg_pending:1;
	369	__u8 reserved:7;
	370	};
	371	};
	372
	373	/* Define port identifier type. */
	374	union hv_port_id {
	375	__u32 asu32;
	376	struct {
	377	__u32 id:24;
	378	__u32 reserved:8;
	379	} u;
	380	};
	381
	382	/* Define synthetic interrupt controller message header. */
	383	struct hv_message_header {
	384	__u32 message_type;
	385	__u8 payload_size;
	386	union hv_message_flags message_flags;
	387	__u8 reserved[2];
	388	union {
	389	__u64 sender;
	390	union hv_port_id port;
	391	};
	392	};
	393
	394	/* Define synthetic interrupt controller message format. */
395	struct hv_message {
396	struct hv_message_header header;
397	union {
398	__u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
399	} u;
400	};
401
402	/* Define the synthetic interrupt message page layout. */
403	struct hv_message_page {
404	struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
405	};
406
c71acc4c AS	407	/* Define timer message payload structure. */
	408	struct hv_timer_message_payload {
	409	__u32 timer_index;
	410	__u32 reserved;
	411	__u64 expiration_time; /* When the timer expired */
	412	__u64 delivery_time; /* When the message was delivered */
	413	};
	414
1f4b34f8 AS	415	#define HV_STIMER_ENABLE (1ULL << 0)
	416	#define HV_STIMER_PERIODIC (1ULL << 1)
	417	#define HV_STIMER_LAZY (1ULL << 2)
	418	#define HV_STIMER_AUTOENABLE (1ULL << 3)
	419	#define HV_STIMER_SINT(config) (__u8)(((config) >> 16) & 0x0F)
	420
1d5103c1	421	#endif