Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
57844a8f TG |
2 | #ifndef _ASM_X86_PLATFORM_H |
3 | #define _ASM_X86_PLATFORM_H | |
4 | ||
f6a9f8a4 | 5 | struct ghcb; |
52fdb568 | 6 | struct mpc_bus; |
fd6c6661 | 7 | struct mpc_cpu; |
f6a9f8a4 | 8 | struct pt_regs; |
72302142 | 9 | struct mpc_table; |
64be4c1c | 10 | struct cpuinfo_x86; |
6b15ffa0 | 11 | struct irq_domain; |
fd6c6661 | 12 | |
f4848472 TG |
13 | /** |
14 | * struct x86_init_mpparse - platform specific mpparse ops | |
de934103 | 15 | * @setup_ioapic_ids: platform specific ioapic id override |
e061c7ae | 16 | * @find_mptable: Find MPTABLE early to reserve the memory region |
fc60fd00 TG |
17 | * @early_parse_smp_cfg: Parse the SMP configuration data early before initmem_init() |
18 | * @parse_smp_cfg: Parse the SMP configuration data | |
f4848472 TG |
19 | */ |
20 | struct x86_init_mpparse { | |
de934103 | 21 | void (*setup_ioapic_ids)(void); |
e061c7ae | 22 | void (*find_mptable)(void); |
fc60fd00 TG |
23 | void (*early_parse_smp_cfg)(void); |
24 | void (*parse_smp_cfg)(void); | |
f4848472 TG |
25 | }; |
26 | ||
f7cf5a5b TG |
27 | /** |
28 | * struct x86_init_resources - platform specific resource related ops | |
29 | * @probe_roms: probe BIOS roms | |
8fee697d TG |
30 | * @reserve_resources: reserve the standard resources for the |
31 | * platform | |
6b18ae3e | 32 | * @memory_setup: platform specific memory setup |
0f4a1e80 | 33 | * @dmi_setup: platform specific DMI setup |
f7cf5a5b TG |
34 | */ |
35 | struct x86_init_resources { | |
36 | void (*probe_roms)(void); | |
8fee697d | 37 | void (*reserve_resources)(void); |
6b18ae3e | 38 | char *(*memory_setup)(void); |
0f4a1e80 | 39 | void (*dmi_setup)(void); |
f7cf5a5b TG |
40 | }; |
41 | ||
d9112f43 TG |
42 | /** |
43 | * struct x86_init_irqs - platform specific interrupt setup | |
44 | * @pre_vector_init: init code to run before interrupt vectors | |
45 | * are set up. | |
66bcaf0b | 46 | * @intr_init: interrupt init code |
97992387 | 47 | * @intr_mode_select: interrupt delivery mode selection |
34fba3e6 | 48 | * @intr_mode_init: interrupt delivery mode setup |
6b15ffa0 | 49 | * @create_pci_msi_domain: Create the PCI/MSI interrupt domain |
d9112f43 TG |
50 | */ |
51 | struct x86_init_irqs { | |
52 | void (*pre_vector_init)(void); | |
66bcaf0b | 53 | void (*intr_init)(void); |
97992387 | 54 | void (*intr_mode_select)(void); |
34fba3e6 | 55 | void (*intr_mode_init)(void); |
6b15ffa0 | 56 | struct irq_domain *(*create_pci_msi_domain)(void); |
d9112f43 TG |
57 | }; |
58 | ||
42bbdb43 TG |
59 | /** |
60 | * struct x86_init_oem - oem platform specific customizing functions | |
22d3c0d6 | 61 | * @arch_setup: platform specific architecture setup |
6f30c1ac | 62 | * @banner: print a platform specific banner |
42bbdb43 TG |
63 | */ |
64 | struct x86_init_oem { | |
65 | void (*arch_setup)(void); | |
6f30c1ac | 66 | void (*banner)(void); |
42bbdb43 TG |
67 | }; |
68 | ||
030cb6c0 TG |
69 | /** |
70 | * struct x86_init_paging - platform specific paging functions | |
64282278 AR |
71 | * @pagetable_init: platform specific paging initialization call to setup |
72 | * the kernel pagetables and prepare accessors functions. | |
73 | * Callback must call paging_init(). Called once after the | |
74 | * direct mapping for phys memory is available. | |
030cb6c0 TG |
75 | */ |
76 | struct x86_init_paging { | |
7737b215 | 77 | void (*pagetable_init)(void); |
030cb6c0 TG |
78 | }; |
79 | ||
736decac TG |
80 | /** |
81 | * struct x86_init_timers - platform specific timer setup | |
82 | * @setup_perpcu_clockev: set up the per cpu clock event device for the | |
83 | * boot cpu | |
845b3944 | 84 | * @timer_init: initialize the platform timer (default PIT/HPET) |
6b617e22 | 85 | * @wallclock_init: init the wallclock device |
736decac TG |
86 | */ |
87 | struct x86_init_timers { | |
88 | void (*setup_percpu_clockev)(void); | |
845b3944 | 89 | void (*timer_init)(void); |
6b617e22 | 90 | void (*wallclock_init)(void); |
736decac TG |
91 | }; |
92 | ||
d07c1be0 FT |
93 | /** |
94 | * struct x86_init_iommu - platform specific iommu setup | |
95 | * @iommu_init: platform specific iommu setup | |
96 | */ | |
97 | struct x86_init_iommu { | |
98 | int (*iommu_init)(void); | |
99 | }; | |
100 | ||
4fb6088a TG |
101 | /** |
102 | * struct x86_init_pci - platform specific pci init functions | |
103 | * @arch_init: platform specific pci arch init call | |
104 | * @init: platform specific pci subsystem init | |
ab3b3793 | 105 | * @init_irq: platform specific pci irq init |
9325a28c | 106 | * @fixup_irqs: platform specific pci irq fixup |
b72d0db9 TG |
107 | */ |
108 | struct x86_init_pci { | |
4fb6088a | 109 | int (*arch_init)(void); |
b72d0db9 | 110 | int (*init)(void); |
ab3b3793 | 111 | void (*init_irq)(void); |
9325a28c | 112 | void (*fixup_irqs)(void); |
b72d0db9 TG |
113 | }; |
114 | ||
f72e38e8 JG |
115 | /** |
116 | * struct x86_hyper_init - x86 hypervisor init functions | |
117 | * @init_platform: platform setup | |
f3614646 | 118 | * @guest_late_init: guest late init |
f72e38e8 | 119 | * @x2apic_available: X2APIC detection |
ab0f59c6 | 120 | * @msi_ext_dest_id: MSI supports 15-bit APIC IDs |
f72e38e8 | 121 | * @init_mem_mapping: setup early mappings during init_mem_mapping() |
6f84f8d1 | 122 | * @init_after_bootmem: guest init after boot allocator is finished |
f72e38e8 JG |
123 | */ |
124 | struct x86_hyper_init { | |
125 | void (*init_platform)(void); | |
f3614646 | 126 | void (*guest_late_init)(void); |
f72e38e8 | 127 | bool (*x2apic_available)(void); |
ab0f59c6 | 128 | bool (*msi_ext_dest_id)(void); |
f72e38e8 | 129 | void (*init_mem_mapping)(void); |
6f84f8d1 | 130 | void (*init_after_bootmem)(void); |
f72e38e8 JG |
131 | }; |
132 | ||
038bac2b JG |
133 | /** |
134 | * struct x86_init_acpi - x86 ACPI init functions | |
41fa1ee9 | 135 | * @set_root_poitner: set RSDP address |
038bac2b | 136 | * @get_root_pointer: get RSDP address |
81b53e5f | 137 | * @reduced_hw_early_init: hardware reduced platform early init |
038bac2b JG |
138 | */ |
139 | struct x86_init_acpi { | |
41fa1ee9 | 140 | void (*set_root_pointer)(u64 addr); |
038bac2b | 141 | u64 (*get_root_pointer)(void); |
81b53e5f | 142 | void (*reduced_hw_early_init)(void); |
038bac2b JG |
143 | }; |
144 | ||
1e8c5971 BS |
145 | /** |
146 | * struct x86_guest - Functions used by misc guest incarnations like SEV, TDX, etc. | |
147 | * | |
148 | * @enc_status_change_prepare Notify HV before the encryption status of a range is changed | |
149 | * @enc_status_change_finish Notify HV after the encryption status of a range is changed | |
150 | * @enc_tlb_flush_required Returns true if a TLB flush is needed before changing page encryption status | |
151 | * @enc_cache_flush_required Returns true if a cache flush is needed before changing page encryption status | |
22daa422 KS |
152 | * @enc_kexec_begin Begin the two-step process of converting shared memory back |
153 | * to private. It stops the new conversions from being started | |
154 | * and waits in-flight conversions to finish, if possible. | |
155 | * @enc_kexec_finish Finish the two-step process of converting shared memory to | |
156 | * private. All memory is private after the call when | |
157 | * the function returns. | |
158 | * It is called on only one CPU while the others are shut down | |
159 | * and with interrupts disabled. | |
1e8c5971 BS |
160 | */ |
161 | struct x86_guest { | |
99c5c4c6 KS |
162 | int (*enc_status_change_prepare)(unsigned long vaddr, int npages, bool enc); |
163 | int (*enc_status_change_finish)(unsigned long vaddr, int npages, bool enc); | |
1e8c5971 BS |
164 | bool (*enc_tlb_flush_required)(bool enc); |
165 | bool (*enc_cache_flush_required)(void); | |
22daa422 KS |
166 | void (*enc_kexec_begin)(void); |
167 | void (*enc_kexec_finish)(void); | |
1e8c5971 BS |
168 | }; |
169 | ||
57844a8f TG |
170 | /** |
171 | * struct x86_init_ops - functions for platform specific setup | |
172 | * | |
173 | */ | |
174 | struct x86_init_ops { | |
f4848472 TG |
175 | struct x86_init_resources resources; |
176 | struct x86_init_mpparse mpparse; | |
d9112f43 | 177 | struct x86_init_irqs irqs; |
42bbdb43 | 178 | struct x86_init_oem oem; |
030cb6c0 | 179 | struct x86_init_paging paging; |
736decac | 180 | struct x86_init_timers timers; |
d07c1be0 | 181 | struct x86_init_iommu iommu; |
b72d0db9 | 182 | struct x86_init_pci pci; |
f72e38e8 | 183 | struct x86_hyper_init hyper; |
038bac2b | 184 | struct x86_init_acpi acpi; |
736decac TG |
185 | }; |
186 | ||
187 | /** | |
188 | * struct x86_cpuinit_ops - platform specific cpu hotplug setups | |
189 | * @setup_percpu_clockev: set up the per cpu clock event device | |
df156f90 | 190 | * @early_percpu_clock_init: early init of the per cpu clock event device |
02fb601d | 191 | * @fixup_cpu_id: fixup function for cpuinfo_x86::topo.pkg_id |
ff3cfcb0 | 192 | * @parallel_bringup: Parallel bringup control |
736decac TG |
193 | */ |
194 | struct x86_cpuinit_ops { | |
195 | void (*setup_percpu_clockev)(void); | |
df156f90 | 196 | void (*early_percpu_clock_init)(void); |
64be4c1c | 197 | void (*fixup_cpu_id)(struct cpuinfo_x86 *c, int node); |
ff3cfcb0 | 198 | bool parallel_bringup; |
57844a8f TG |
199 | }; |
200 | ||
e27c4929 | 201 | struct timespec64; |
3565184e | 202 | |
80dfd83d LR |
203 | /** |
204 | * struct x86_legacy_devices - legacy x86 devices | |
205 | * | |
206 | * @pnpbios: this platform can have a PNPBIOS. If this is disabled the platform | |
207 | * is known to never have a PNPBIOS. | |
208 | * | |
209 | * These are devices known to require LPC or ISA bus. The definition of legacy | |
210 | * devices adheres to the ACPI 5.2.9.3 IA-PC Boot Architecture flag | |
211 | * ACPI_FADT_LEGACY_DEVICES. These devices consist of user visible devices on | |
212 | * the LPC or ISA bus. User visible devices are devices that have end-user | |
213 | * accessible connectors (for example, LPT parallel port). Legacy devices on | |
214 | * the LPC bus consist for example of serial and parallel ports, PS/2 keyboard | |
215 | * / mouse, and the floppy disk controller. A system that lacks all known | |
216 | * legacy devices can assume all devices can be detected exclusively via | |
217 | * standard device enumeration mechanisms including the ACPI namespace. | |
218 | * | |
219 | * A system which has does not have ACPI_FADT_LEGACY_DEVICES enabled must not | |
220 | * have any of the legacy devices enumerated below present. | |
221 | */ | |
222 | struct x86_legacy_devices { | |
223 | int pnpbios; | |
224 | }; | |
225 | ||
93ffa9a4 DT |
226 | /** |
227 | * enum x86_legacy_i8042_state - i8042 keyboard controller state | |
228 | * @X86_LEGACY_I8042_PLATFORM_ABSENT: the controller is always absent on | |
229 | * given platform/subarch. | |
230 | * @X86_LEGACY_I8042_FIRMWARE_ABSENT: firmware reports that the controller | |
231 | * is absent. | |
232 | * @X86_LEGACY_i8042_EXPECTED_PRESENT: the controller is likely to be | |
233 | * present, the i8042 driver should probe for controller existence. | |
234 | */ | |
235 | enum x86_legacy_i8042_state { | |
236 | X86_LEGACY_I8042_PLATFORM_ABSENT, | |
237 | X86_LEGACY_I8042_FIRMWARE_ABSENT, | |
238 | X86_LEGACY_I8042_EXPECTED_PRESENT, | |
239 | }; | |
240 | ||
8d152e7a LR |
241 | /** |
242 | * struct x86_legacy_features - legacy x86 features | |
243 | * | |
93ffa9a4 DT |
244 | * @i8042: indicated if we expect the device to have i8042 controller |
245 | * present. | |
8d152e7a | 246 | * @rtc: this device has a CMOS real-time clock present |
30f02739 AL |
247 | * @reserve_bios_regions: boot code will search for the EBDA address and the |
248 | * start of the 640k - 1M BIOS region. If false, the platform must | |
249 | * ensure that its memory map correctly reserves sub-1MB regions as needed. | |
80dfd83d LR |
250 | * @devices: legacy x86 devices, refer to struct x86_legacy_devices |
251 | * documentation for further details. | |
8d152e7a LR |
252 | */ |
253 | struct x86_legacy_features { | |
93ffa9a4 | 254 | enum x86_legacy_i8042_state i8042; |
8d152e7a | 255 | int rtc; |
e348caef | 256 | int warm_reset; |
6d730525 | 257 | int no_vga; |
edce2121 | 258 | int reserve_bios_regions; |
80dfd83d | 259 | struct x86_legacy_devices devices; |
8d152e7a LR |
260 | }; |
261 | ||
f72e38e8 JG |
262 | /** |
263 | * struct x86_hyper_runtime - x86 hypervisor specific runtime callbacks | |
264 | * | |
f6a9f8a4 JR |
265 | * @pin_vcpu: pin current vcpu to specified physical |
266 | * cpu (run rarely) | |
267 | * @sev_es_hcall_prepare: Load additional hypervisor-specific | |
268 | * state into the GHCB when doing a VMMCALL under | |
269 | * SEV-ES. Called from the #VC exception handler. | |
270 | * @sev_es_hcall_finish: Copies state from the GHCB back into the | |
271 | * processor (or pt_regs). Also runs checks on the | |
272 | * state returned from the hypervisor after a | |
273 | * VMMCALL under SEV-ES. Needs to return 'false' | |
274 | * if the checks fail. Called from the #VC | |
275 | * exception handler. | |
88e378d4 MK |
276 | * @is_private_mmio: For CoCo VMs, must map MMIO address as private. |
277 | * Used when device is emulated by a paravisor | |
278 | * layer in the VM context. | |
f72e38e8 JG |
279 | */ |
280 | struct x86_hyper_runtime { | |
281 | void (*pin_vcpu)(int cpu); | |
f6a9f8a4 JR |
282 | void (*sev_es_hcall_prepare)(struct ghcb *ghcb, struct pt_regs *regs); |
283 | bool (*sev_es_hcall_finish)(struct ghcb *ghcb, struct pt_regs *regs); | |
88e378d4 | 284 | bool (*is_private_mmio)(u64 addr); |
f72e38e8 JG |
285 | }; |
286 | ||
2d826404 TG |
287 | /** |
288 | * struct x86_platform_ops - platform specific runtime functions | |
aa297292 LB |
289 | * @calibrate_cpu: calibrate CPU |
290 | * @calibrate_tsc: calibrate TSC, if different from CPU | |
7bd867df FT |
291 | * @get_wallclock: get time from HW clock like RTC etc. |
292 | * @set_wallclock: set time back to HW clock | |
eb41c8be | 293 | * @is_untracked_pat_range exclude from PAT logic |
78c06176 | 294 | * @nmi_init enable NMI on cpus |
b74f05d6 MT |
295 | * @save_sched_clock_state: save state for sched_clock() on suspend |
296 | * @restore_sched_clock_state: restore state for sched_clock() on resume | |
22d3c0d6 | 297 | * @apic_post_init: adjust apic if needed |
8d152e7a LR |
298 | * @legacy: legacy features |
299 | * @set_legacy_features: override legacy features. Use of this callback | |
300 | * is highly discouraged. You should only need | |
301 | * this if your hardware platform requires further | |
22d3c0d6 | 302 | * custom fine tuning far beyond what may be |
8d152e7a LR |
303 | * possible in x86_early_init_platform_quirks() by |
304 | * only using the current x86_hardware_subarch | |
305 | * semantics. | |
f1e52500 JG |
306 | * @realmode_reserve: reserve memory for realmode trampoline |
307 | * @realmode_init: initialize realmode trampoline | |
f72e38e8 | 308 | * @hyper: x86 hypervisor specific runtime callbacks |
2d826404 TG |
309 | */ |
310 | struct x86_platform_ops { | |
aa297292 | 311 | unsigned long (*calibrate_cpu)(void); |
2d826404 | 312 | unsigned long (*calibrate_tsc)(void); |
e27c4929 AB |
313 | void (*get_wallclock)(struct timespec64 *ts); |
314 | int (*set_wallclock)(const struct timespec64 *ts); | |
338bac52 | 315 | void (*iommu_shutdown)(void); |
eb41c8be | 316 | bool (*is_untracked_pat_range)(u64 start, u64 end); |
78c06176 | 317 | void (*nmi_init)(void); |
064a59b6 | 318 | unsigned char (*get_nmi_reason)(void); |
b74f05d6 MT |
319 | void (*save_sched_clock_state)(void); |
320 | void (*restore_sched_clock_state)(void); | |
7db971b2 | 321 | void (*apic_post_init)(void); |
8d152e7a LR |
322 | struct x86_legacy_features legacy; |
323 | void (*set_legacy_features)(void); | |
f1e52500 JG |
324 | void (*realmode_reserve)(void); |
325 | void (*realmode_init)(void); | |
f72e38e8 | 326 | struct x86_hyper_runtime hyper; |
1e8c5971 | 327 | struct x86_guest guest; |
2d826404 TG |
328 | }; |
329 | ||
51b146c5 BH |
330 | struct x86_apic_ops { |
331 | unsigned int (*io_apic_read) (unsigned int apic, unsigned int reg); | |
332 | void (*restore)(void); | |
4a8e2a31 KRW |
333 | }; |
334 | ||
57844a8f | 335 | extern struct x86_init_ops x86_init; |
736decac | 336 | extern struct x86_cpuinit_ops x86_cpuinit; |
2d826404 | 337 | extern struct x86_platform_ops x86_platform; |
294ee6f8 | 338 | extern struct x86_msi_ops x86_msi; |
51b146c5 | 339 | extern struct x86_apic_ops x86_apic_ops; |
8d152e7a LR |
340 | |
341 | extern void x86_early_init_platform_quirks(void); | |
57844a8f | 342 | extern void x86_init_noop(void); |
f4848472 | 343 | extern void x86_init_uint_noop(unsigned int unused); |
bef6e0ae ZD |
344 | extern bool bool_x86_init_noop(void); |
345 | extern void x86_op_int_noop(int cpu); | |
f79b1c57 | 346 | extern bool x86_pnpbios_disabled(void); |
d21a19e1 SS |
347 | extern int set_rtc_noop(const struct timespec64 *now); |
348 | extern void get_rtc_noop(struct timespec64 *now); | |
57844a8f TG |
349 | |
350 | #endif |