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0d3e865b JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV MMR definitions | |
7 | * | |
1d44e828 | 8 | * Copyright (C) 2007-2011 Silicon Graphics, Inc. All rights reserved. |
0d3e865b JS |
9 | */ |
10 | ||
05e4d316 PA |
11 | #ifndef _ASM_X86_UV_UV_MMRS_H |
12 | #define _ASM_X86_UV_UV_MMRS_H | |
0d3e865b | 13 | |
2a919596 JS |
14 | /* |
15 | * This file contains MMR definitions for both UV1 & UV2 hubs. | |
16 | * | |
17 | * In general, MMR addresses and structures are identical on both hubs. | |
18 | * These MMRs are identified as: | |
19 | * #define UVH_xxx <address> | |
20 | * union uvh_xxx { | |
21 | * unsigned long v; | |
22 | * struct uvh_int_cmpd_s { | |
23 | * } s; | |
24 | * }; | |
25 | * | |
26 | * If the MMR exists on both hub type but has different addresses or | |
27 | * contents, the MMR definition is similar to: | |
28 | * #define UV1H_xxx <uv1 address> | |
29 | * #define UV2H_xxx <uv2address> | |
30 | * #define UVH_xxx (is_uv1_hub() ? UV1H_xxx : UV2H_xxx) | |
31 | * union uvh_xxx { | |
32 | * unsigned long v; | |
33 | * struct uv1h_int_cmpd_s { (Common fields only) | |
34 | * } s; | |
35 | * struct uv1h_int_cmpd_s { (Full UV1 definition) | |
36 | * } s1; | |
37 | * struct uv2h_int_cmpd_s { (Full UV2 definition) | |
38 | * } s2; | |
39 | * }; | |
40 | * | |
41 | * Only essential difference are enumerated. For example, if the address is | |
42 | * the same for both UV1 & UV2, only a single #define is generated. Likewise, | |
43 | * if the contents is the same for both hubs, only the "s" structure is | |
44 | * generated. | |
45 | * | |
46 | * If the MMR exists on ONLY 1 type of hub, no generic definition is | |
47 | * generated: | |
48 | * #define UVnH_xxx <uvn address> | |
49 | * union uvnh_xxx { | |
50 | * unsigned long v; | |
51 | * struct uvh_int_cmpd_s { | |
52 | * } sn; | |
53 | * }; | |
54 | */ | |
55 | ||
9f5314fb | 56 | #define UV_MMR_ENABLE (1UL << 63) |
0d3e865b | 57 | |
2a919596 JS |
58 | #define UV1_HUB_PART_NUMBER 0x88a5 |
59 | #define UV2_HUB_PART_NUMBER 0x8eb8 | |
b495e039 | 60 | #define UV2_HUB_PART_NUMBER_X 0x1111 |
2a919596 JS |
61 | |
62 | /* Compat: if this #define is present, UV headers support UV2 */ | |
63 | #define UV2_HUB_IS_SUPPORTED 1 | |
64 | ||
6f4edd69 JS |
65 | /* ========================================================================= */ |
66 | /* UVH_BAU_DATA_BROADCAST */ | |
67 | /* ========================================================================= */ | |
55ba4120 JS |
68 | #define UVH_BAU_DATA_BROADCAST 0x61688UL |
69 | #define UVH_BAU_DATA_BROADCAST_32 0x440 | |
6f4edd69 | 70 | |
55ba4120 JS |
71 | #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 |
72 | #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL | |
6f4edd69 JS |
73 | |
74 | union uvh_bau_data_broadcast_u { | |
55ba4120 JS |
75 | unsigned long v; |
76 | struct uvh_bau_data_broadcast_s { | |
77 | unsigned long enable:1; /* RW */ | |
78 | unsigned long rsvd_1_63:63; | |
79 | } s; | |
6f4edd69 JS |
80 | }; |
81 | ||
9f5314fb JS |
82 | /* ========================================================================= */ |
83 | /* UVH_BAU_DATA_CONFIG */ | |
84 | /* ========================================================================= */ | |
55ba4120 JS |
85 | #define UVH_BAU_DATA_CONFIG 0x61680UL |
86 | #define UVH_BAU_DATA_CONFIG_32 0x438 | |
87 | ||
88 | #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 | |
89 | #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 | |
90 | #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 | |
91 | #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 | |
92 | #define UVH_BAU_DATA_CONFIG_P_SHFT 13 | |
93 | #define UVH_BAU_DATA_CONFIG_T_SHFT 15 | |
94 | #define UVH_BAU_DATA_CONFIG_M_SHFT 16 | |
95 | #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 | |
96 | #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
97 | #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL | |
98 | #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
99 | #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL | |
100 | #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL | |
101 | #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL | |
102 | #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL | |
103 | #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
9f5314fb JS |
104 | |
105 | union uvh_bau_data_config_u { | |
55ba4120 JS |
106 | unsigned long v; |
107 | struct uvh_bau_data_config_s { | |
108 | unsigned long vector_:8; /* RW */ | |
109 | unsigned long dm:3; /* RW */ | |
110 | unsigned long destmode:1; /* RW */ | |
111 | unsigned long status:1; /* RO */ | |
112 | unsigned long p:1; /* RO */ | |
113 | unsigned long rsvd_14:1; | |
114 | unsigned long t:1; /* RO */ | |
115 | unsigned long m:1; /* RW */ | |
116 | unsigned long rsvd_17_31:15; | |
117 | unsigned long apic_id:32; /* RW */ | |
118 | } s; | |
9f5314fb | 119 | }; |
0d3e865b | 120 | |
5d061e39 DS |
121 | /* ========================================================================= */ |
122 | /* UVH_EVENT_OCCURRED0 */ | |
123 | /* ========================================================================= */ | |
55ba4120 JS |
124 | #define UVH_EVENT_OCCURRED0 0x70000UL |
125 | #define UVH_EVENT_OCCURRED0_32 0x5e8 | |
126 | ||
127 | #define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 | |
128 | #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 | |
129 | #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 | |
130 | #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3 | |
131 | #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4 | |
132 | #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5 | |
133 | #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6 | |
134 | #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 | |
135 | #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 | |
136 | #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 | |
137 | #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 | |
138 | #define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 | |
139 | #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 | |
140 | #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 | |
141 | #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 | |
142 | #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 | |
143 | #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 | |
144 | #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 | |
145 | #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 | |
146 | #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 | |
147 | #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 | |
148 | #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 | |
149 | #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 | |
150 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 | |
151 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 | |
152 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 | |
153 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 | |
154 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 | |
155 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 | |
156 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 | |
157 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 | |
158 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 | |
159 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 | |
160 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 | |
161 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 | |
162 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 | |
163 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 | |
164 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 | |
165 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 | |
166 | #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 | |
167 | #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 | |
168 | #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 | |
169 | #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 | |
170 | #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43 | |
171 | #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 | |
172 | #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45 | |
173 | #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 | |
174 | #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 | |
175 | #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 | |
176 | #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 | |
177 | #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 | |
178 | #define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51 | |
179 | #define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52 | |
180 | #define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53 | |
181 | #define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54 | |
182 | #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55 | |
183 | #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 | |
184 | #define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL | |
185 | #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL | |
186 | #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL | |
187 | #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL | |
188 | #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL | |
189 | #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL | |
190 | #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL | |
191 | #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL | |
192 | #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL | |
193 | #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL | |
194 | #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL | |
195 | #define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL | |
196 | #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL | |
197 | #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL | |
198 | #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL | |
199 | #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL | |
200 | #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL | |
201 | #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL | |
202 | #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL | |
203 | #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL | |
204 | #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL | |
205 | #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL | |
206 | #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL | |
207 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL | |
208 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL | |
209 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL | |
210 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL | |
211 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL | |
212 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL | |
213 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL | |
214 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL | |
215 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL | |
216 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL | |
217 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL | |
218 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL | |
219 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL | |
220 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL | |
221 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL | |
222 | #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL | |
223 | #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL | |
224 | #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL | |
225 | #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL | |
226 | #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL | |
227 | #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL | |
228 | #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL | |
229 | #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL | |
230 | #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL | |
231 | #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL | |
232 | #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL | |
233 | #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL | |
234 | #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL | |
235 | #define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL | |
236 | #define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL | |
237 | #define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL | |
238 | #define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL | |
239 | #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL | |
240 | #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL | |
241 | ||
242 | #define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 | |
243 | #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 | |
244 | #define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2 | |
245 | #define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 | |
246 | #define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 | |
247 | #define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 | |
248 | #define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 | |
249 | #define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 | |
250 | #define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 | |
251 | #define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 | |
252 | #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 | |
253 | #define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 | |
254 | #define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 | |
255 | #define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 | |
256 | #define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 | |
257 | #define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 | |
258 | #define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 | |
259 | #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 | |
260 | #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 | |
261 | #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 | |
262 | #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 | |
263 | #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 | |
264 | #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 | |
265 | #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 | |
266 | #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 | |
267 | #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 | |
268 | #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 | |
269 | #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 | |
270 | #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 | |
271 | #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 | |
272 | #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 | |
273 | #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 | |
274 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 | |
275 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 | |
276 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 | |
277 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 | |
278 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 | |
279 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 | |
280 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 | |
281 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 | |
282 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 | |
283 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 | |
284 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 | |
285 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 | |
286 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 | |
287 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 | |
288 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 | |
289 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 | |
290 | #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 | |
291 | #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 | |
292 | #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 | |
293 | #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 | |
294 | #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 | |
295 | #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53 | |
296 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 | |
297 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 | |
298 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 | |
299 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 | |
300 | #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 | |
301 | #define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL | |
302 | #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL | |
303 | #define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL | |
304 | #define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL | |
305 | #define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL | |
306 | #define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL | |
307 | #define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL | |
308 | #define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL | |
309 | #define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL | |
310 | #define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL | |
311 | #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL | |
312 | #define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL | |
313 | #define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL | |
314 | #define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL | |
315 | #define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL | |
316 | #define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL | |
317 | #define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL | |
318 | #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL | |
319 | #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL | |
320 | #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL | |
321 | #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL | |
322 | #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL | |
323 | #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL | |
324 | #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL | |
325 | #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL | |
326 | #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL | |
327 | #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL | |
328 | #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL | |
329 | #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL | |
330 | #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL | |
331 | #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL | |
332 | #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL | |
333 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL | |
334 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL | |
335 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL | |
336 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL | |
337 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL | |
338 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL | |
339 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL | |
340 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL | |
341 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL | |
342 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL | |
343 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL | |
344 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL | |
345 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL | |
346 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL | |
347 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL | |
348 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL | |
349 | #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL | |
350 | #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL | |
351 | #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL | |
352 | #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL | |
353 | #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL | |
354 | #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL | |
355 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL | |
356 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL | |
357 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL | |
358 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL | |
359 | #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL | |
2a919596 | 360 | |
5d061e39 | 361 | union uvh_event_occurred0_u { |
55ba4120 JS |
362 | unsigned long v; |
363 | struct uv1h_event_occurred0_s { | |
364 | unsigned long lb_hcerr:1; /* RW, W1C */ | |
365 | unsigned long gr0_hcerr:1; /* RW, W1C */ | |
366 | unsigned long gr1_hcerr:1; /* RW, W1C */ | |
367 | unsigned long lh_hcerr:1; /* RW, W1C */ | |
368 | unsigned long rh_hcerr:1; /* RW, W1C */ | |
369 | unsigned long xn_hcerr:1; /* RW, W1C */ | |
370 | unsigned long si_hcerr:1; /* RW, W1C */ | |
371 | unsigned long lb_aoerr0:1; /* RW, W1C */ | |
372 | unsigned long gr0_aoerr0:1; /* RW, W1C */ | |
373 | unsigned long gr1_aoerr0:1; /* RW, W1C */ | |
374 | unsigned long lh_aoerr0:1; /* RW, W1C */ | |
375 | unsigned long rh_aoerr0:1; /* RW, W1C */ | |
376 | unsigned long xn_aoerr0:1; /* RW, W1C */ | |
377 | unsigned long si_aoerr0:1; /* RW, W1C */ | |
378 | unsigned long lb_aoerr1:1; /* RW, W1C */ | |
379 | unsigned long gr0_aoerr1:1; /* RW, W1C */ | |
380 | unsigned long gr1_aoerr1:1; /* RW, W1C */ | |
381 | unsigned long lh_aoerr1:1; /* RW, W1C */ | |
382 | unsigned long rh_aoerr1:1; /* RW, W1C */ | |
383 | unsigned long xn_aoerr1:1; /* RW, W1C */ | |
384 | unsigned long si_aoerr1:1; /* RW, W1C */ | |
385 | unsigned long rh_vpi_int:1; /* RW, W1C */ | |
386 | unsigned long system_shutdown_int:1; /* RW, W1C */ | |
387 | unsigned long lb_irq_int_0:1; /* RW, W1C */ | |
388 | unsigned long lb_irq_int_1:1; /* RW, W1C */ | |
389 | unsigned long lb_irq_int_2:1; /* RW, W1C */ | |
390 | unsigned long lb_irq_int_3:1; /* RW, W1C */ | |
391 | unsigned long lb_irq_int_4:1; /* RW, W1C */ | |
392 | unsigned long lb_irq_int_5:1; /* RW, W1C */ | |
393 | unsigned long lb_irq_int_6:1; /* RW, W1C */ | |
394 | unsigned long lb_irq_int_7:1; /* RW, W1C */ | |
395 | unsigned long lb_irq_int_8:1; /* RW, W1C */ | |
396 | unsigned long lb_irq_int_9:1; /* RW, W1C */ | |
397 | unsigned long lb_irq_int_10:1; /* RW, W1C */ | |
398 | unsigned long lb_irq_int_11:1; /* RW, W1C */ | |
399 | unsigned long lb_irq_int_12:1; /* RW, W1C */ | |
400 | unsigned long lb_irq_int_13:1; /* RW, W1C */ | |
401 | unsigned long lb_irq_int_14:1; /* RW, W1C */ | |
402 | unsigned long lb_irq_int_15:1; /* RW, W1C */ | |
403 | unsigned long l1_nmi_int:1; /* RW, W1C */ | |
404 | unsigned long stop_clock:1; /* RW, W1C */ | |
405 | unsigned long asic_to_l1:1; /* RW, W1C */ | |
406 | unsigned long l1_to_asic:1; /* RW, W1C */ | |
407 | unsigned long ltc_int:1; /* RW, W1C */ | |
408 | unsigned long la_seq_trigger:1; /* RW, W1C */ | |
409 | unsigned long ipi_int:1; /* RW, W1C */ | |
410 | unsigned long extio_int0:1; /* RW, W1C */ | |
411 | unsigned long extio_int1:1; /* RW, W1C */ | |
412 | unsigned long extio_int2:1; /* RW, W1C */ | |
413 | unsigned long extio_int3:1; /* RW, W1C */ | |
414 | unsigned long profile_int:1; /* RW, W1C */ | |
415 | unsigned long rtc0:1; /* RW, W1C */ | |
416 | unsigned long rtc1:1; /* RW, W1C */ | |
417 | unsigned long rtc2:1; /* RW, W1C */ | |
418 | unsigned long rtc3:1; /* RW, W1C */ | |
419 | unsigned long bau_data:1; /* RW, W1C */ | |
420 | unsigned long power_management_req:1; /* RW, W1C */ | |
421 | unsigned long rsvd_57_63:7; | |
422 | } s1; | |
423 | struct uv2h_event_occurred0_s { | |
424 | unsigned long lb_hcerr:1; /* RW */ | |
425 | unsigned long qp_hcerr:1; /* RW */ | |
426 | unsigned long rh_hcerr:1; /* RW */ | |
427 | unsigned long lh0_hcerr:1; /* RW */ | |
428 | unsigned long lh1_hcerr:1; /* RW */ | |
429 | unsigned long gr0_hcerr:1; /* RW */ | |
430 | unsigned long gr1_hcerr:1; /* RW */ | |
431 | unsigned long ni0_hcerr:1; /* RW */ | |
432 | unsigned long ni1_hcerr:1; /* RW */ | |
433 | unsigned long lb_aoerr0:1; /* RW */ | |
434 | unsigned long qp_aoerr0:1; /* RW */ | |
435 | unsigned long rh_aoerr0:1; /* RW */ | |
436 | unsigned long lh0_aoerr0:1; /* RW */ | |
437 | unsigned long lh1_aoerr0:1; /* RW */ | |
438 | unsigned long gr0_aoerr0:1; /* RW */ | |
439 | unsigned long gr1_aoerr0:1; /* RW */ | |
440 | unsigned long xb_aoerr0:1; /* RW */ | |
441 | unsigned long rt_aoerr0:1; /* RW */ | |
442 | unsigned long ni0_aoerr0:1; /* RW */ | |
443 | unsigned long ni1_aoerr0:1; /* RW */ | |
444 | unsigned long lb_aoerr1:1; /* RW */ | |
445 | unsigned long qp_aoerr1:1; /* RW */ | |
446 | unsigned long rh_aoerr1:1; /* RW */ | |
447 | unsigned long lh0_aoerr1:1; /* RW */ | |
448 | unsigned long lh1_aoerr1:1; /* RW */ | |
449 | unsigned long gr0_aoerr1:1; /* RW */ | |
450 | unsigned long gr1_aoerr1:1; /* RW */ | |
451 | unsigned long xb_aoerr1:1; /* RW */ | |
452 | unsigned long rt_aoerr1:1; /* RW */ | |
453 | unsigned long ni0_aoerr1:1; /* RW */ | |
454 | unsigned long ni1_aoerr1:1; /* RW */ | |
455 | unsigned long system_shutdown_int:1; /* RW */ | |
456 | unsigned long lb_irq_int_0:1; /* RW */ | |
457 | unsigned long lb_irq_int_1:1; /* RW */ | |
458 | unsigned long lb_irq_int_2:1; /* RW */ | |
459 | unsigned long lb_irq_int_3:1; /* RW */ | |
460 | unsigned long lb_irq_int_4:1; /* RW */ | |
461 | unsigned long lb_irq_int_5:1; /* RW */ | |
462 | unsigned long lb_irq_int_6:1; /* RW */ | |
463 | unsigned long lb_irq_int_7:1; /* RW */ | |
464 | unsigned long lb_irq_int_8:1; /* RW */ | |
465 | unsigned long lb_irq_int_9:1; /* RW */ | |
466 | unsigned long lb_irq_int_10:1; /* RW */ | |
467 | unsigned long lb_irq_int_11:1; /* RW */ | |
468 | unsigned long lb_irq_int_12:1; /* RW */ | |
469 | unsigned long lb_irq_int_13:1; /* RW */ | |
470 | unsigned long lb_irq_int_14:1; /* RW */ | |
471 | unsigned long lb_irq_int_15:1; /* RW */ | |
472 | unsigned long l1_nmi_int:1; /* RW */ | |
473 | unsigned long stop_clock:1; /* RW */ | |
474 | unsigned long asic_to_l1:1; /* RW */ | |
475 | unsigned long l1_to_asic:1; /* RW */ | |
476 | unsigned long la_seq_trigger:1; /* RW */ | |
477 | unsigned long ipi_int:1; /* RW */ | |
478 | unsigned long extio_int0:1; /* RW */ | |
479 | unsigned long extio_int1:1; /* RW */ | |
480 | unsigned long extio_int2:1; /* RW */ | |
481 | unsigned long extio_int3:1; /* RW */ | |
482 | unsigned long profile_int:1; /* RW */ | |
483 | unsigned long rsvd_59_63:5; | |
484 | } s2; | |
5d061e39 DS |
485 | }; |
486 | ||
487 | /* ========================================================================= */ | |
488 | /* UVH_EVENT_OCCURRED0_ALIAS */ | |
489 | /* ========================================================================= */ | |
55ba4120 JS |
490 | #define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL |
491 | #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 | |
5d061e39 | 492 | |
a4c31557 JS |
493 | /* ========================================================================= */ |
494 | /* UVH_GR0_TLB_INT0_CONFIG */ | |
495 | /* ========================================================================= */ | |
55ba4120 JS |
496 | #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL |
497 | ||
498 | #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 | |
499 | #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 | |
500 | #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | |
501 | #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 | |
502 | #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13 | |
503 | #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15 | |
504 | #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16 | |
505 | #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | |
506 | #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
507 | #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | |
508 | #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
509 | #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | |
510 | #define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | |
511 | #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | |
512 | #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | |
513 | #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
a4c31557 JS |
514 | |
515 | union uvh_gr0_tlb_int0_config_u { | |
55ba4120 JS |
516 | unsigned long v; |
517 | struct uvh_gr0_tlb_int0_config_s { | |
518 | unsigned long vector_:8; /* RW */ | |
519 | unsigned long dm:3; /* RW */ | |
520 | unsigned long destmode:1; /* RW */ | |
521 | unsigned long status:1; /* RO */ | |
522 | unsigned long p:1; /* RO */ | |
523 | unsigned long rsvd_14:1; | |
524 | unsigned long t:1; /* RO */ | |
525 | unsigned long m:1; /* RW */ | |
526 | unsigned long rsvd_17_31:15; | |
527 | unsigned long apic_id:32; /* RW */ | |
528 | } s; | |
a4c31557 JS |
529 | }; |
530 | ||
531 | /* ========================================================================= */ | |
532 | /* UVH_GR0_TLB_INT1_CONFIG */ | |
533 | /* ========================================================================= */ | |
55ba4120 JS |
534 | #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL |
535 | ||
536 | #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 | |
537 | #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 | |
538 | #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | |
539 | #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 | |
540 | #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13 | |
541 | #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15 | |
542 | #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16 | |
543 | #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | |
544 | #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
545 | #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | |
546 | #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
547 | #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | |
548 | #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | |
549 | #define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | |
550 | #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | |
551 | #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
a4c31557 JS |
552 | |
553 | union uvh_gr0_tlb_int1_config_u { | |
55ba4120 JS |
554 | unsigned long v; |
555 | struct uvh_gr0_tlb_int1_config_s { | |
556 | unsigned long vector_:8; /* RW */ | |
557 | unsigned long dm:3; /* RW */ | |
558 | unsigned long destmode:1; /* RW */ | |
559 | unsigned long status:1; /* RO */ | |
560 | unsigned long p:1; /* RO */ | |
561 | unsigned long rsvd_14:1; | |
562 | unsigned long t:1; /* RO */ | |
563 | unsigned long m:1; /* RW */ | |
564 | unsigned long rsvd_17_31:15; | |
565 | unsigned long apic_id:32; /* RW */ | |
566 | } s; | |
567 | }; | |
568 | ||
569 | /* ========================================================================= */ | |
570 | /* UVH_GR0_TLB_MMR_CONTROL */ | |
571 | /* ========================================================================= */ | |
572 | #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL | |
573 | #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL | |
574 | #define UVH_GR0_TLB_MMR_CONTROL (is_uv1_hub() ? \ | |
575 | UV1H_GR0_TLB_MMR_CONTROL : \ | |
576 | UV2H_GR0_TLB_MMR_CONTROL) | |
577 | ||
578 | #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 | |
579 | #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | |
580 | #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | |
581 | #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 | |
582 | #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 | |
583 | #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 | |
584 | #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL | |
585 | #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL | |
586 | #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL | |
587 | #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL | |
588 | #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL | |
589 | #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL | |
590 | ||
591 | #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 | |
592 | #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | |
593 | #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | |
594 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 | |
595 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 | |
596 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 | |
597 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 | |
598 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 | |
599 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54 | |
600 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56 | |
601 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60 | |
602 | #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL | |
603 | #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL | |
604 | #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL | |
605 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL | |
606 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL | |
607 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL | |
608 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL | |
609 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL | |
610 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL | |
611 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL | |
612 | #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL | |
613 | ||
614 | #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 | |
615 | #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | |
616 | #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | |
617 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 | |
618 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 | |
619 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 | |
620 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 | |
621 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 | |
622 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 | |
623 | #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL | |
624 | #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL | |
625 | #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL | |
626 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL | |
627 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL | |
628 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL | |
629 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL | |
630 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL | |
631 | #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL | |
632 | ||
633 | union uvh_gr0_tlb_mmr_control_u { | |
634 | unsigned long v; | |
635 | struct uvh_gr0_tlb_mmr_control_s { | |
636 | unsigned long index:12; /* RW */ | |
637 | unsigned long mem_sel:2; /* RW */ | |
638 | unsigned long rsvd_14_15:2; | |
639 | unsigned long auto_valid_en:1; /* RW */ | |
640 | unsigned long rsvd_17_19:3; | |
641 | unsigned long mmr_hash_index_en:1; /* RW */ | |
642 | unsigned long rsvd_21_29:9; | |
643 | unsigned long mmr_write:1; /* WP */ | |
644 | unsigned long mmr_read:1; /* WP */ | |
645 | unsigned long rsvd_32_63:32; | |
646 | } s; | |
647 | struct uv1h_gr0_tlb_mmr_control_s { | |
648 | unsigned long index:12; /* RW */ | |
649 | unsigned long mem_sel:2; /* RW */ | |
650 | unsigned long rsvd_14_15:2; | |
651 | unsigned long auto_valid_en:1; /* RW */ | |
652 | unsigned long rsvd_17_19:3; | |
653 | unsigned long mmr_hash_index_en:1; /* RW */ | |
654 | unsigned long rsvd_21_29:9; | |
655 | unsigned long mmr_write:1; /* WP */ | |
656 | unsigned long mmr_read:1; /* WP */ | |
657 | unsigned long rsvd_32_47:16; | |
658 | unsigned long mmr_inj_con:1; /* RW */ | |
659 | unsigned long rsvd_49_51:3; | |
660 | unsigned long mmr_inj_tlbram:1; /* RW */ | |
661 | unsigned long rsvd_53:1; | |
662 | unsigned long mmr_inj_tlbpgsize:1; /* RW */ | |
663 | unsigned long rsvd_55:1; | |
664 | unsigned long mmr_inj_tlbrreg:1; /* RW */ | |
665 | unsigned long rsvd_57_59:3; | |
666 | unsigned long mmr_inj_tlblruv:1; /* RW */ | |
667 | unsigned long rsvd_61_63:3; | |
668 | } s1; | |
669 | struct uv2h_gr0_tlb_mmr_control_s { | |
670 | unsigned long index:12; /* RW */ | |
671 | unsigned long mem_sel:2; /* RW */ | |
672 | unsigned long rsvd_14_15:2; | |
673 | unsigned long auto_valid_en:1; /* RW */ | |
674 | unsigned long rsvd_17_19:3; | |
675 | unsigned long mmr_hash_index_en:1; /* RW */ | |
676 | unsigned long rsvd_21_29:9; | |
677 | unsigned long mmr_write:1; /* WP */ | |
678 | unsigned long mmr_read:1; /* WP */ | |
679 | unsigned long mmr_op_done:1; /* RW */ | |
680 | unsigned long rsvd_33_47:15; | |
681 | unsigned long mmr_inj_con:1; /* RW */ | |
682 | unsigned long rsvd_49_51:3; | |
683 | unsigned long mmr_inj_tlbram:1; /* RW */ | |
684 | unsigned long rsvd_53_63:11; | |
685 | } s2; | |
686 | }; | |
687 | ||
688 | /* ========================================================================= */ | |
689 | /* UVH_GR0_TLB_MMR_READ_DATA_HI */ | |
690 | /* ========================================================================= */ | |
691 | #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL | |
692 | #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL | |
693 | #define UVH_GR0_TLB_MMR_READ_DATA_HI (is_uv1_hub() ? \ | |
694 | UV1H_GR0_TLB_MMR_READ_DATA_HI : \ | |
695 | UV2H_GR0_TLB_MMR_READ_DATA_HI) | |
696 | ||
697 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | |
698 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | |
699 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 | |
700 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 | |
701 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL | |
702 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL | |
703 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | |
704 | #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | |
705 | ||
706 | union uvh_gr0_tlb_mmr_read_data_hi_u { | |
707 | unsigned long v; | |
708 | struct uvh_gr0_tlb_mmr_read_data_hi_s { | |
709 | unsigned long pfn:41; /* RO */ | |
710 | unsigned long gaa:2; /* RO */ | |
711 | unsigned long dirty:1; /* RO */ | |
712 | unsigned long larger:1; /* RO */ | |
713 | unsigned long rsvd_45_63:19; | |
714 | } s; | |
715 | }; | |
716 | ||
717 | /* ========================================================================= */ | |
718 | /* UVH_GR0_TLB_MMR_READ_DATA_LO */ | |
719 | /* ========================================================================= */ | |
720 | #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL | |
721 | #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL | |
722 | #define UVH_GR0_TLB_MMR_READ_DATA_LO (is_uv1_hub() ? \ | |
723 | UV1H_GR0_TLB_MMR_READ_DATA_LO : \ | |
724 | UV2H_GR0_TLB_MMR_READ_DATA_LO) | |
725 | ||
726 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | |
727 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | |
728 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 | |
729 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL | |
730 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | |
731 | #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | |
732 | ||
733 | union uvh_gr0_tlb_mmr_read_data_lo_u { | |
734 | unsigned long v; | |
735 | struct uvh_gr0_tlb_mmr_read_data_lo_s { | |
736 | unsigned long vpn:39; /* RO */ | |
737 | unsigned long asid:24; /* RO */ | |
738 | unsigned long valid:1; /* RO */ | |
739 | } s; | |
a4c31557 JS |
740 | }; |
741 | ||
742 | /* ========================================================================= */ | |
743 | /* UVH_GR1_TLB_INT0_CONFIG */ | |
744 | /* ========================================================================= */ | |
55ba4120 JS |
745 | #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL |
746 | ||
747 | #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 | |
748 | #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 | |
749 | #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 | |
750 | #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 | |
751 | #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13 | |
752 | #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15 | |
753 | #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16 | |
754 | #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 | |
755 | #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
756 | #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL | |
757 | #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
758 | #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL | |
759 | #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL | |
760 | #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL | |
761 | #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL | |
762 | #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
a4c31557 JS |
763 | |
764 | union uvh_gr1_tlb_int0_config_u { | |
55ba4120 JS |
765 | unsigned long v; |
766 | struct uvh_gr1_tlb_int0_config_s { | |
767 | unsigned long vector_:8; /* RW */ | |
768 | unsigned long dm:3; /* RW */ | |
769 | unsigned long destmode:1; /* RW */ | |
770 | unsigned long status:1; /* RO */ | |
771 | unsigned long p:1; /* RO */ | |
772 | unsigned long rsvd_14:1; | |
773 | unsigned long t:1; /* RO */ | |
774 | unsigned long m:1; /* RW */ | |
775 | unsigned long rsvd_17_31:15; | |
776 | unsigned long apic_id:32; /* RW */ | |
777 | } s; | |
a4c31557 JS |
778 | }; |
779 | ||
780 | /* ========================================================================= */ | |
781 | /* UVH_GR1_TLB_INT1_CONFIG */ | |
782 | /* ========================================================================= */ | |
55ba4120 JS |
783 | #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL |
784 | ||
785 | #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 | |
786 | #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 | |
787 | #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 | |
788 | #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 | |
789 | #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13 | |
790 | #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15 | |
791 | #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16 | |
792 | #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 | |
793 | #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
794 | #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL | |
795 | #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
796 | #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL | |
797 | #define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL | |
798 | #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL | |
799 | #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL | |
800 | #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
a4c31557 JS |
801 | |
802 | union uvh_gr1_tlb_int1_config_u { | |
55ba4120 JS |
803 | unsigned long v; |
804 | struct uvh_gr1_tlb_int1_config_s { | |
805 | unsigned long vector_:8; /* RW */ | |
806 | unsigned long dm:3; /* RW */ | |
807 | unsigned long destmode:1; /* RW */ | |
808 | unsigned long status:1; /* RO */ | |
809 | unsigned long p:1; /* RO */ | |
810 | unsigned long rsvd_14:1; | |
811 | unsigned long t:1; /* RO */ | |
812 | unsigned long m:1; /* RW */ | |
813 | unsigned long rsvd_17_31:15; | |
814 | unsigned long apic_id:32; /* RW */ | |
815 | } s; | |
816 | }; | |
817 | ||
818 | /* ========================================================================= */ | |
819 | /* UVH_GR1_TLB_MMR_CONTROL */ | |
820 | /* ========================================================================= */ | |
821 | #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL | |
822 | #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL | |
823 | #define UVH_GR1_TLB_MMR_CONTROL (is_uv1_hub() ? \ | |
824 | UV1H_GR1_TLB_MMR_CONTROL : \ | |
825 | UV2H_GR1_TLB_MMR_CONTROL) | |
826 | ||
827 | #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 | |
828 | #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | |
829 | #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | |
830 | #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 | |
831 | #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 | |
832 | #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 | |
833 | #define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL | |
834 | #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL | |
835 | #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL | |
836 | #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL | |
837 | #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL | |
838 | #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL | |
839 | ||
840 | #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 | |
841 | #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | |
842 | #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | |
843 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 | |
844 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 | |
845 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 | |
846 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 | |
847 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 | |
848 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54 | |
849 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56 | |
850 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60 | |
851 | #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL | |
852 | #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL | |
853 | #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL | |
854 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL | |
855 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL | |
856 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL | |
857 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL | |
858 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL | |
859 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL | |
860 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL | |
861 | #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL | |
862 | ||
863 | #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 | |
864 | #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 | |
865 | #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 | |
866 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 | |
867 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 | |
868 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 | |
869 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 | |
870 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 | |
871 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 | |
872 | #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL | |
873 | #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL | |
874 | #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL | |
875 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL | |
876 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL | |
877 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL | |
878 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL | |
879 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL | |
880 | #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL | |
881 | ||
882 | union uvh_gr1_tlb_mmr_control_u { | |
883 | unsigned long v; | |
884 | struct uvh_gr1_tlb_mmr_control_s { | |
885 | unsigned long index:12; /* RW */ | |
886 | unsigned long mem_sel:2; /* RW */ | |
887 | unsigned long rsvd_14_15:2; | |
888 | unsigned long auto_valid_en:1; /* RW */ | |
889 | unsigned long rsvd_17_19:3; | |
890 | unsigned long mmr_hash_index_en:1; /* RW */ | |
891 | unsigned long rsvd_21_29:9; | |
892 | unsigned long mmr_write:1; /* WP */ | |
893 | unsigned long mmr_read:1; /* WP */ | |
894 | unsigned long rsvd_32_63:32; | |
895 | } s; | |
896 | struct uv1h_gr1_tlb_mmr_control_s { | |
897 | unsigned long index:12; /* RW */ | |
898 | unsigned long mem_sel:2; /* RW */ | |
899 | unsigned long rsvd_14_15:2; | |
900 | unsigned long auto_valid_en:1; /* RW */ | |
901 | unsigned long rsvd_17_19:3; | |
902 | unsigned long mmr_hash_index_en:1; /* RW */ | |
903 | unsigned long rsvd_21_29:9; | |
904 | unsigned long mmr_write:1; /* WP */ | |
905 | unsigned long mmr_read:1; /* WP */ | |
906 | unsigned long rsvd_32_47:16; | |
907 | unsigned long mmr_inj_con:1; /* RW */ | |
908 | unsigned long rsvd_49_51:3; | |
909 | unsigned long mmr_inj_tlbram:1; /* RW */ | |
910 | unsigned long rsvd_53:1; | |
911 | unsigned long mmr_inj_tlbpgsize:1; /* RW */ | |
912 | unsigned long rsvd_55:1; | |
913 | unsigned long mmr_inj_tlbrreg:1; /* RW */ | |
914 | unsigned long rsvd_57_59:3; | |
915 | unsigned long mmr_inj_tlblruv:1; /* RW */ | |
916 | unsigned long rsvd_61_63:3; | |
917 | } s1; | |
918 | struct uv2h_gr1_tlb_mmr_control_s { | |
919 | unsigned long index:12; /* RW */ | |
920 | unsigned long mem_sel:2; /* RW */ | |
921 | unsigned long rsvd_14_15:2; | |
922 | unsigned long auto_valid_en:1; /* RW */ | |
923 | unsigned long rsvd_17_19:3; | |
924 | unsigned long mmr_hash_index_en:1; /* RW */ | |
925 | unsigned long rsvd_21_29:9; | |
926 | unsigned long mmr_write:1; /* WP */ | |
927 | unsigned long mmr_read:1; /* WP */ | |
928 | unsigned long mmr_op_done:1; /* RW */ | |
929 | unsigned long rsvd_33_47:15; | |
930 | unsigned long mmr_inj_con:1; /* RW */ | |
931 | unsigned long rsvd_49_51:3; | |
932 | unsigned long mmr_inj_tlbram:1; /* RW */ | |
933 | unsigned long rsvd_53_63:11; | |
934 | } s2; | |
935 | }; | |
936 | ||
937 | /* ========================================================================= */ | |
938 | /* UVH_GR1_TLB_MMR_READ_DATA_HI */ | |
939 | /* ========================================================================= */ | |
940 | #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL | |
941 | #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL | |
942 | #define UVH_GR1_TLB_MMR_READ_DATA_HI (is_uv1_hub() ? \ | |
943 | UV1H_GR1_TLB_MMR_READ_DATA_HI : \ | |
944 | UV2H_GR1_TLB_MMR_READ_DATA_HI) | |
945 | ||
946 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 | |
947 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 | |
948 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 | |
949 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 | |
950 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL | |
951 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL | |
952 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL | |
953 | #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL | |
954 | ||
955 | union uvh_gr1_tlb_mmr_read_data_hi_u { | |
956 | unsigned long v; | |
957 | struct uvh_gr1_tlb_mmr_read_data_hi_s { | |
958 | unsigned long pfn:41; /* RO */ | |
959 | unsigned long gaa:2; /* RO */ | |
960 | unsigned long dirty:1; /* RO */ | |
961 | unsigned long larger:1; /* RO */ | |
962 | unsigned long rsvd_45_63:19; | |
963 | } s; | |
964 | }; | |
965 | ||
966 | /* ========================================================================= */ | |
967 | /* UVH_GR1_TLB_MMR_READ_DATA_LO */ | |
968 | /* ========================================================================= */ | |
969 | #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL | |
970 | #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL | |
971 | #define UVH_GR1_TLB_MMR_READ_DATA_LO (is_uv1_hub() ? \ | |
972 | UV1H_GR1_TLB_MMR_READ_DATA_LO : \ | |
973 | UV2H_GR1_TLB_MMR_READ_DATA_LO) | |
974 | ||
975 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 | |
976 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 | |
977 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 | |
978 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL | |
979 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL | |
980 | #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL | |
981 | ||
982 | union uvh_gr1_tlb_mmr_read_data_lo_u { | |
983 | unsigned long v; | |
984 | struct uvh_gr1_tlb_mmr_read_data_lo_s { | |
985 | unsigned long vpn:39; /* RO */ | |
986 | unsigned long asid:24; /* RO */ | |
987 | unsigned long valid:1; /* RO */ | |
988 | } s; | |
a4c31557 JS |
989 | }; |
990 | ||
5d061e39 DS |
991 | /* ========================================================================= */ |
992 | /* UVH_INT_CMPB */ | |
993 | /* ========================================================================= */ | |
55ba4120 | 994 | #define UVH_INT_CMPB 0x22080UL |
5d061e39 | 995 | |
55ba4120 JS |
996 | #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 |
997 | #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL | |
5d061e39 DS |
998 | |
999 | union uvh_int_cmpb_u { | |
55ba4120 JS |
1000 | unsigned long v; |
1001 | struct uvh_int_cmpb_s { | |
1002 | unsigned long real_time_cmpb:56; /* RW */ | |
1003 | unsigned long rsvd_56_63:8; | |
1004 | } s; | |
5d061e39 DS |
1005 | }; |
1006 | ||
1007 | /* ========================================================================= */ | |
1008 | /* UVH_INT_CMPC */ | |
1009 | /* ========================================================================= */ | |
55ba4120 | 1010 | #define UVH_INT_CMPC 0x22100UL |
5d061e39 | 1011 | |
55ba4120 JS |
1012 | #define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 |
1013 | #define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL | |
5d061e39 DS |
1014 | |
1015 | union uvh_int_cmpc_u { | |
55ba4120 JS |
1016 | unsigned long v; |
1017 | struct uvh_int_cmpc_s { | |
1018 | unsigned long real_time_cmpc:56; /* RW */ | |
1019 | unsigned long rsvd_56_63:8; | |
1020 | } s; | |
5d061e39 DS |
1021 | }; |
1022 | ||
1023 | /* ========================================================================= */ | |
1024 | /* UVH_INT_CMPD */ | |
1025 | /* ========================================================================= */ | |
55ba4120 | 1026 | #define UVH_INT_CMPD 0x22180UL |
5d061e39 | 1027 | |
55ba4120 JS |
1028 | #define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 |
1029 | #define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL | |
5d061e39 DS |
1030 | |
1031 | union uvh_int_cmpd_u { | |
55ba4120 JS |
1032 | unsigned long v; |
1033 | struct uvh_int_cmpd_s { | |
1034 | unsigned long real_time_cmpd:56; /* RW */ | |
1035 | unsigned long rsvd_56_63:8; | |
1036 | } s; | |
5d061e39 DS |
1037 | }; |
1038 | ||
0d3e865b JS |
1039 | /* ========================================================================= */ |
1040 | /* UVH_IPI_INT */ | |
1041 | /* ========================================================================= */ | |
55ba4120 JS |
1042 | #define UVH_IPI_INT 0x60500UL |
1043 | #define UVH_IPI_INT_32 0x348 | |
0d3e865b | 1044 | |
55ba4120 JS |
1045 | #define UVH_IPI_INT_VECTOR_SHFT 0 |
1046 | #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 | |
1047 | #define UVH_IPI_INT_DESTMODE_SHFT 11 | |
1048 | #define UVH_IPI_INT_APIC_ID_SHFT 16 | |
1049 | #define UVH_IPI_INT_SEND_SHFT 63 | |
1050 | #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL | |
1051 | #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL | |
1052 | #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL | |
1053 | #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL | |
1054 | #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL | |
0d3e865b JS |
1055 | |
1056 | union uvh_ipi_int_u { | |
55ba4120 JS |
1057 | unsigned long v; |
1058 | struct uvh_ipi_int_s { | |
1059 | unsigned long vector_:8; /* RW */ | |
1060 | unsigned long delivery_mode:3; /* RW */ | |
1061 | unsigned long destmode:1; /* RW */ | |
1062 | unsigned long rsvd_12_15:4; | |
1063 | unsigned long apic_id:32; /* RW */ | |
1064 | unsigned long rsvd_48_62:15; | |
1065 | unsigned long send:1; /* WP */ | |
1066 | } s; | |
0d3e865b JS |
1067 | }; |
1068 | ||
1069 | /* ========================================================================= */ | |
1070 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ | |
1071 | /* ========================================================================= */ | |
55ba4120 JS |
1072 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL |
1073 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 | |
0d3e865b JS |
1074 | |
1075 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 | |
0d3e865b | 1076 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 |
55ba4120 | 1077 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL |
0d3e865b JS |
1078 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL |
1079 | ||
1080 | union uvh_lb_bau_intd_payload_queue_first_u { | |
55ba4120 JS |
1081 | unsigned long v; |
1082 | struct uvh_lb_bau_intd_payload_queue_first_s { | |
1083 | unsigned long rsvd_0_3:4; | |
1084 | unsigned long address:39; /* RW */ | |
1085 | unsigned long rsvd_43_48:6; | |
1086 | unsigned long node_id:14; /* RW */ | |
1087 | unsigned long rsvd_63:1; | |
1088 | } s; | |
0d3e865b JS |
1089 | }; |
1090 | ||
1091 | /* ========================================================================= */ | |
1092 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ | |
1093 | /* ========================================================================= */ | |
55ba4120 JS |
1094 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL |
1095 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 | |
0d3e865b | 1096 | |
55ba4120 JS |
1097 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 |
1098 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL | |
0d3e865b JS |
1099 | |
1100 | union uvh_lb_bau_intd_payload_queue_last_u { | |
55ba4120 JS |
1101 | unsigned long v; |
1102 | struct uvh_lb_bau_intd_payload_queue_last_s { | |
1103 | unsigned long rsvd_0_3:4; | |
1104 | unsigned long address:39; /* RW */ | |
1105 | unsigned long rsvd_43_63:21; | |
1106 | } s; | |
0d3e865b JS |
1107 | }; |
1108 | ||
1109 | /* ========================================================================= */ | |
1110 | /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ | |
1111 | /* ========================================================================= */ | |
55ba4120 JS |
1112 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL |
1113 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 | |
0d3e865b | 1114 | |
55ba4120 JS |
1115 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 |
1116 | #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL | |
0d3e865b JS |
1117 | |
1118 | union uvh_lb_bau_intd_payload_queue_tail_u { | |
55ba4120 JS |
1119 | unsigned long v; |
1120 | struct uvh_lb_bau_intd_payload_queue_tail_s { | |
1121 | unsigned long rsvd_0_3:4; | |
1122 | unsigned long address:39; /* RW */ | |
1123 | unsigned long rsvd_43_63:21; | |
1124 | } s; | |
0d3e865b JS |
1125 | }; |
1126 | ||
1127 | /* ========================================================================= */ | |
1128 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ | |
1129 | /* ========================================================================= */ | |
55ba4120 JS |
1130 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL |
1131 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 | |
0d3e865b JS |
1132 | |
1133 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 | |
0d3e865b | 1134 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 |
0d3e865b | 1135 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 |
0d3e865b | 1136 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 |
0d3e865b | 1137 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 |
0d3e865b | 1138 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 |
0d3e865b | 1139 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 |
0d3e865b | 1140 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 |
0d3e865b | 1141 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 |
0d3e865b | 1142 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 |
0d3e865b | 1143 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 |
0d3e865b | 1144 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 |
0d3e865b | 1145 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 |
0d3e865b | 1146 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 |
0d3e865b | 1147 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 |
0d3e865b | 1148 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 |
55ba4120 JS |
1149 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL |
1150 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL | |
1151 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL | |
1152 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL | |
1153 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL | |
1154 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL | |
1155 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL | |
1156 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL | |
1157 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL | |
1158 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL | |
1159 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL | |
1160 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL | |
1161 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL | |
1162 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL | |
1163 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL | |
0d3e865b | 1164 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL |
2a919596 | 1165 | |
0d3e865b | 1166 | union uvh_lb_bau_intd_software_acknowledge_u { |
55ba4120 JS |
1167 | unsigned long v; |
1168 | struct uvh_lb_bau_intd_software_acknowledge_s { | |
1169 | unsigned long pending_0:1; /* RW, W1C */ | |
1170 | unsigned long pending_1:1; /* RW, W1C */ | |
1171 | unsigned long pending_2:1; /* RW, W1C */ | |
1172 | unsigned long pending_3:1; /* RW, W1C */ | |
1173 | unsigned long pending_4:1; /* RW, W1C */ | |
1174 | unsigned long pending_5:1; /* RW, W1C */ | |
1175 | unsigned long pending_6:1; /* RW, W1C */ | |
1176 | unsigned long pending_7:1; /* RW, W1C */ | |
1177 | unsigned long timeout_0:1; /* RW, W1C */ | |
1178 | unsigned long timeout_1:1; /* RW, W1C */ | |
1179 | unsigned long timeout_2:1; /* RW, W1C */ | |
1180 | unsigned long timeout_3:1; /* RW, W1C */ | |
1181 | unsigned long timeout_4:1; /* RW, W1C */ | |
1182 | unsigned long timeout_5:1; /* RW, W1C */ | |
1183 | unsigned long timeout_6:1; /* RW, W1C */ | |
1184 | unsigned long timeout_7:1; /* RW, W1C */ | |
1185 | unsigned long rsvd_16_63:48; | |
1186 | } s; | |
0d3e865b JS |
1187 | }; |
1188 | ||
1189 | /* ========================================================================= */ | |
1190 | /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ | |
1191 | /* ========================================================================= */ | |
55ba4120 JS |
1192 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL |
1193 | #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 | |
0d3e865b | 1194 | |
6f4edd69 JS |
1195 | /* ========================================================================= */ |
1196 | /* UVH_LB_BAU_MISC_CONTROL */ | |
1197 | /* ========================================================================= */ | |
55ba4120 JS |
1198 | #define UVH_LB_BAU_MISC_CONTROL 0x320170UL |
1199 | #define UVH_LB_BAU_MISC_CONTROL_32 0xa10 | |
1200 | ||
1201 | #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 | |
1202 | #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 | |
1203 | #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 | |
1204 | #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 | |
2a919596 | 1205 | #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 |
6f4edd69 | 1206 | #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 |
6f4edd69 | 1207 | #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 |
6f4edd69 | 1208 | #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 |
6f4edd69 | 1209 | #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 |
6f4edd69 | 1210 | #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 |
6f4edd69 | 1211 | #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 |
6f4edd69 | 1212 | #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 |
6f4edd69 | 1213 | #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 |
6f4edd69 | 1214 | #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 |
6f4edd69 | 1215 | #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 |
55ba4120 JS |
1216 | #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL |
1217 | #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL | |
1218 | #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL | |
1219 | #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL | |
1220 | #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL | |
1221 | #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL | |
1222 | #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL | |
1223 | #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL | |
1224 | #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL | |
1225 | #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL | |
1226 | #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL | |
1227 | #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL | |
1228 | #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL | |
1229 | #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL | |
6f4edd69 | 1230 | #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL |
2a919596 | 1231 | |
55ba4120 JS |
1232 | #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 |
1233 | #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 | |
1234 | #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 | |
1235 | #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 | |
2a919596 | 1236 | #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 |
2a919596 | 1237 | #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 |
2a919596 | 1238 | #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 |
2a919596 | 1239 | #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 |
2a919596 | 1240 | #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 |
2a919596 | 1241 | #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 |
2a919596 | 1242 | #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 |
2a919596 | 1243 | #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 |
2a919596 | 1244 | #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 |
2a919596 | 1245 | #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 |
2a919596 | 1246 | #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 |
55ba4120 JS |
1247 | #define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 |
1248 | #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL | |
1249 | #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL | |
1250 | #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL | |
1251 | #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL | |
1252 | #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL | |
1253 | #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL | |
1254 | #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL | |
1255 | #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL | |
1256 | #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL | |
1257 | #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL | |
1258 | #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL | |
1259 | #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL | |
1260 | #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL | |
1261 | #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL | |
2a919596 | 1262 | #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL |
55ba4120 JS |
1263 | #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL |
1264 | ||
1265 | #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 | |
1266 | #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 | |
1267 | #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 | |
1268 | #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 | |
2a919596 | 1269 | #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 |
2a919596 | 1270 | #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 |
2a919596 | 1271 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 |
2a919596 | 1272 | #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 |
2a919596 | 1273 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 |
2a919596 | 1274 | #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 |
2a919596 | 1275 | #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 |
2a919596 | 1276 | #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 |
2a919596 | 1277 | #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 |
2a919596 | 1278 | #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 |
2a919596 | 1279 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 |
2a919596 | 1280 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 |
55ba4120 | 1281 | #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 |
2a919596 | 1282 | #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 |
2a919596 | 1283 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 |
2a919596 | 1284 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 |
2a919596 | 1285 | #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 |
2a919596 | 1286 | #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 |
55ba4120 JS |
1287 | #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 |
1288 | #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL | |
1289 | #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL | |
1290 | #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL | |
1291 | #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL | |
1292 | #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL | |
1293 | #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL | |
1294 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL | |
1295 | #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL | |
1296 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL | |
1297 | #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL | |
1298 | #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL | |
1299 | #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL | |
1300 | #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL | |
1301 | #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL | |
1302 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL | |
1303 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL | |
1304 | #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL | |
1305 | #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL | |
1306 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL | |
1307 | #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL | |
1308 | #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL | |
2a919596 | 1309 | #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL |
55ba4120 | 1310 | #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL |
6f4edd69 JS |
1311 | |
1312 | union uvh_lb_bau_misc_control_u { | |
55ba4120 JS |
1313 | unsigned long v; |
1314 | struct uvh_lb_bau_misc_control_s { | |
1315 | unsigned long rejection_delay:8; /* RW */ | |
1316 | unsigned long apic_mode:1; /* RW */ | |
1317 | unsigned long force_broadcast:1; /* RW */ | |
1318 | unsigned long force_lock_nop:1; /* RW */ | |
1319 | unsigned long qpi_agent_presence_vector:3; /* RW */ | |
1320 | unsigned long descriptor_fetch_mode:1; /* RW */ | |
1321 | unsigned long enable_intd_soft_ack_mode:1; /* RW */ | |
1322 | unsigned long intd_soft_ack_timeout_period:4; /* RW */ | |
1323 | unsigned long enable_dual_mapping_mode:1; /* RW */ | |
1324 | unsigned long vga_io_port_decode_enable:1; /* RW */ | |
1325 | unsigned long vga_io_port_16_bit_decode:1; /* RW */ | |
1326 | unsigned long suppress_dest_registration:1; /* RW */ | |
1327 | unsigned long programmed_initial_priority:3; /* RW */ | |
1328 | unsigned long use_incoming_priority:1; /* RW */ | |
1329 | unsigned long enable_programmed_initial_priority:1;/* RW */ | |
1330 | unsigned long rsvd_29_63:35; | |
1331 | } s; | |
1332 | struct uv1h_lb_bau_misc_control_s { | |
1333 | unsigned long rejection_delay:8; /* RW */ | |
1334 | unsigned long apic_mode:1; /* RW */ | |
1335 | unsigned long force_broadcast:1; /* RW */ | |
1336 | unsigned long force_lock_nop:1; /* RW */ | |
1337 | unsigned long qpi_agent_presence_vector:3; /* RW */ | |
1338 | unsigned long descriptor_fetch_mode:1; /* RW */ | |
1339 | unsigned long enable_intd_soft_ack_mode:1; /* RW */ | |
1340 | unsigned long intd_soft_ack_timeout_period:4; /* RW */ | |
1341 | unsigned long enable_dual_mapping_mode:1; /* RW */ | |
1342 | unsigned long vga_io_port_decode_enable:1; /* RW */ | |
1343 | unsigned long vga_io_port_16_bit_decode:1; /* RW */ | |
1344 | unsigned long suppress_dest_registration:1; /* RW */ | |
1345 | unsigned long programmed_initial_priority:3; /* RW */ | |
1346 | unsigned long use_incoming_priority:1; /* RW */ | |
1347 | unsigned long enable_programmed_initial_priority:1;/* RW */ | |
1348 | unsigned long rsvd_29_47:19; | |
1349 | unsigned long fun:16; /* RW */ | |
1350 | } s1; | |
1351 | struct uv2h_lb_bau_misc_control_s { | |
1352 | unsigned long rejection_delay:8; /* RW */ | |
1353 | unsigned long apic_mode:1; /* RW */ | |
1354 | unsigned long force_broadcast:1; /* RW */ | |
1355 | unsigned long force_lock_nop:1; /* RW */ | |
1356 | unsigned long qpi_agent_presence_vector:3; /* RW */ | |
1357 | unsigned long descriptor_fetch_mode:1; /* RW */ | |
1358 | unsigned long enable_intd_soft_ack_mode:1; /* RW */ | |
1359 | unsigned long intd_soft_ack_timeout_period:4; /* RW */ | |
1360 | unsigned long enable_dual_mapping_mode:1; /* RW */ | |
1361 | unsigned long vga_io_port_decode_enable:1; /* RW */ | |
1362 | unsigned long vga_io_port_16_bit_decode:1; /* RW */ | |
1363 | unsigned long suppress_dest_registration:1; /* RW */ | |
1364 | unsigned long programmed_initial_priority:3; /* RW */ | |
1365 | unsigned long use_incoming_priority:1; /* RW */ | |
1366 | unsigned long enable_programmed_initial_priority:1;/* RW */ | |
1367 | unsigned long enable_automatic_apic_mode_selection:1;/* RW */ | |
1368 | unsigned long apic_mode_status:1; /* RO */ | |
1369 | unsigned long suppress_interrupts_to_self:1; /* RW */ | |
1370 | unsigned long enable_lock_based_system_flush:1;/* RW */ | |
1371 | unsigned long enable_extended_sb_status:1; /* RW */ | |
1372 | unsigned long suppress_int_prio_udt_to_self:1;/* RW */ | |
1373 | unsigned long use_legacy_descriptor_formats:1;/* RW */ | |
1374 | unsigned long rsvd_36_47:12; | |
1375 | unsigned long fun:16; /* RW */ | |
1376 | } s2; | |
6f4edd69 JS |
1377 | }; |
1378 | ||
0d3e865b JS |
1379 | /* ========================================================================= */ |
1380 | /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ | |
1381 | /* ========================================================================= */ | |
55ba4120 JS |
1382 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL |
1383 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 | |
0d3e865b | 1384 | |
55ba4120 JS |
1385 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 |
1386 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 | |
1387 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 | |
1388 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL | |
1389 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL | |
1390 | #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL | |
0d3e865b JS |
1391 | |
1392 | union uvh_lb_bau_sb_activation_control_u { | |
55ba4120 JS |
1393 | unsigned long v; |
1394 | struct uvh_lb_bau_sb_activation_control_s { | |
1395 | unsigned long index:6; /* RW */ | |
1396 | unsigned long rsvd_6_61:56; | |
1397 | unsigned long push:1; /* WP */ | |
1398 | unsigned long init:1; /* WP */ | |
1399 | } s; | |
0d3e865b JS |
1400 | }; |
1401 | ||
1402 | /* ========================================================================= */ | |
1403 | /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ | |
1404 | /* ========================================================================= */ | |
55ba4120 JS |
1405 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL |
1406 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 | |
0d3e865b | 1407 | |
55ba4120 JS |
1408 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 |
1409 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL | |
0d3e865b JS |
1410 | |
1411 | union uvh_lb_bau_sb_activation_status_0_u { | |
55ba4120 JS |
1412 | unsigned long v; |
1413 | struct uvh_lb_bau_sb_activation_status_0_s { | |
1414 | unsigned long status:64; /* RW */ | |
1415 | } s; | |
0d3e865b JS |
1416 | }; |
1417 | ||
1418 | /* ========================================================================= */ | |
1419 | /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ | |
1420 | /* ========================================================================= */ | |
55ba4120 JS |
1421 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL |
1422 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 | |
0d3e865b | 1423 | |
55ba4120 JS |
1424 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 |
1425 | #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL | |
0d3e865b JS |
1426 | |
1427 | union uvh_lb_bau_sb_activation_status_1_u { | |
55ba4120 JS |
1428 | unsigned long v; |
1429 | struct uvh_lb_bau_sb_activation_status_1_s { | |
1430 | unsigned long status:64; /* RW */ | |
1431 | } s; | |
0d3e865b JS |
1432 | }; |
1433 | ||
1434 | /* ========================================================================= */ | |
1435 | /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ | |
1436 | /* ========================================================================= */ | |
55ba4120 JS |
1437 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL |
1438 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 | |
0d3e865b | 1439 | |
55ba4120 JS |
1440 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 |
1441 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 | |
1442 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL | |
1443 | #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL | |
0d3e865b JS |
1444 | |
1445 | union uvh_lb_bau_sb_descriptor_base_u { | |
55ba4120 JS |
1446 | unsigned long v; |
1447 | struct uvh_lb_bau_sb_descriptor_base_s { | |
1448 | unsigned long rsvd_0_11:12; | |
1449 | unsigned long page_address:31; /* RW */ | |
1450 | unsigned long rsvd_43_48:6; | |
1451 | unsigned long node_id:14; /* RW */ | |
1452 | unsigned long rsvd_63:1; | |
1453 | } s; | |
0d3e865b JS |
1454 | }; |
1455 | ||
1456 | /* ========================================================================= */ | |
1457 | /* UVH_NODE_ID */ | |
1458 | /* ========================================================================= */ | |
55ba4120 JS |
1459 | #define UVH_NODE_ID 0x0UL |
1460 | ||
1461 | #define UVH_NODE_ID_FORCE1_SHFT 0 | |
1462 | #define UVH_NODE_ID_MANUFACTURER_SHFT 1 | |
1463 | #define UVH_NODE_ID_PART_NUMBER_SHFT 12 | |
1464 | #define UVH_NODE_ID_REVISION_SHFT 28 | |
1465 | #define UVH_NODE_ID_NODE_ID_SHFT 32 | |
1466 | #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL | |
1467 | #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL | |
1468 | #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL | |
1469 | #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL | |
1470 | #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL | |
1471 | ||
1472 | #define UV1H_NODE_ID_FORCE1_SHFT 0 | |
1473 | #define UV1H_NODE_ID_MANUFACTURER_SHFT 1 | |
1474 | #define UV1H_NODE_ID_PART_NUMBER_SHFT 12 | |
1475 | #define UV1H_NODE_ID_REVISION_SHFT 28 | |
1476 | #define UV1H_NODE_ID_NODE_ID_SHFT 32 | |
1477 | #define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48 | |
1478 | #define UV1H_NODE_ID_NI_PORT_SHFT 56 | |
1479 | #define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL | |
1480 | #define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL | |
1481 | #define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL | |
1482 | #define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL | |
1483 | #define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL | |
1484 | #define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL | |
1485 | #define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL | |
1486 | ||
1487 | #define UV2H_NODE_ID_FORCE1_SHFT 0 | |
1488 | #define UV2H_NODE_ID_MANUFACTURER_SHFT 1 | |
1489 | #define UV2H_NODE_ID_PART_NUMBER_SHFT 12 | |
1490 | #define UV2H_NODE_ID_REVISION_SHFT 28 | |
1491 | #define UV2H_NODE_ID_NODE_ID_SHFT 32 | |
1492 | #define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50 | |
1493 | #define UV2H_NODE_ID_NI_PORT_SHFT 57 | |
1494 | #define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL | |
1495 | #define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL | |
1496 | #define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL | |
1497 | #define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL | |
1498 | #define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL | |
1499 | #define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL | |
1500 | #define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL | |
0d3e865b JS |
1501 | |
1502 | union uvh_node_id_u { | |
55ba4120 JS |
1503 | unsigned long v; |
1504 | struct uvh_node_id_s { | |
1505 | unsigned long force1:1; /* RO */ | |
1506 | unsigned long manufacturer:11; /* RO */ | |
1507 | unsigned long part_number:16; /* RO */ | |
1508 | unsigned long revision:4; /* RO */ | |
1509 | unsigned long node_id:15; /* RW */ | |
1510 | unsigned long rsvd_47_63:17; | |
1511 | } s; | |
1512 | struct uv1h_node_id_s { | |
1513 | unsigned long force1:1; /* RO */ | |
1514 | unsigned long manufacturer:11; /* RO */ | |
1515 | unsigned long part_number:16; /* RO */ | |
1516 | unsigned long revision:4; /* RO */ | |
1517 | unsigned long node_id:15; /* RW */ | |
1518 | unsigned long rsvd_47:1; | |
1519 | unsigned long nodes_per_bit:7; /* RW */ | |
1520 | unsigned long rsvd_55:1; | |
1521 | unsigned long ni_port:4; /* RO */ | |
1522 | unsigned long rsvd_60_63:4; | |
1523 | } s1; | |
1524 | struct uv2h_node_id_s { | |
1525 | unsigned long force1:1; /* RO */ | |
1526 | unsigned long manufacturer:11; /* RO */ | |
1527 | unsigned long part_number:16; /* RO */ | |
1528 | unsigned long revision:4; /* RO */ | |
1529 | unsigned long node_id:15; /* RW */ | |
1530 | unsigned long rsvd_47_49:3; | |
1531 | unsigned long nodes_per_bit:7; /* RO */ | |
1532 | unsigned long ni_port:5; /* RO */ | |
1533 | unsigned long rsvd_62_63:2; | |
1534 | } s2; | |
0d3e865b JS |
1535 | }; |
1536 | ||
9f5314fb JS |
1537 | /* ========================================================================= */ |
1538 | /* UVH_NODE_PRESENT_TABLE */ | |
1539 | /* ========================================================================= */ | |
55ba4120 JS |
1540 | #define UVH_NODE_PRESENT_TABLE 0x1400UL |
1541 | #define UVH_NODE_PRESENT_TABLE_DEPTH 16 | |
9f5314fb | 1542 | |
55ba4120 JS |
1543 | #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 |
1544 | #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL | |
9f5314fb JS |
1545 | |
1546 | union uvh_node_present_table_u { | |
55ba4120 JS |
1547 | unsigned long v; |
1548 | struct uvh_node_present_table_s { | |
1549 | unsigned long nodes:64; /* RW */ | |
1550 | } s; | |
9f5314fb JS |
1551 | }; |
1552 | ||
62b0cfc2 JS |
1553 | /* ========================================================================= */ |
1554 | /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ | |
1555 | /* ========================================================================= */ | |
55ba4120 | 1556 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL |
62b0cfc2 JS |
1557 | |
1558 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 | |
62b0cfc2 | 1559 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 |
62b0cfc2 | 1560 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 |
55ba4120 JS |
1561 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL |
1562 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL | |
62b0cfc2 JS |
1563 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL |
1564 | ||
1565 | union uvh_rh_gam_alias210_overlay_config_0_mmr_u { | |
55ba4120 JS |
1566 | unsigned long v; |
1567 | struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { | |
1568 | unsigned long rsvd_0_23:24; | |
1569 | unsigned long base:8; /* RW */ | |
1570 | unsigned long rsvd_32_47:16; | |
1571 | unsigned long m_alias:5; /* RW */ | |
1572 | unsigned long rsvd_53_62:10; | |
1573 | unsigned long enable:1; /* RW */ | |
1574 | } s; | |
62b0cfc2 JS |
1575 | }; |
1576 | ||
1577 | /* ========================================================================= */ | |
1578 | /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ | |
1579 | /* ========================================================================= */ | |
55ba4120 | 1580 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL |
62b0cfc2 JS |
1581 | |
1582 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 | |
62b0cfc2 | 1583 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 |
62b0cfc2 | 1584 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 |
55ba4120 JS |
1585 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL |
1586 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL | |
62b0cfc2 JS |
1587 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL |
1588 | ||
1589 | union uvh_rh_gam_alias210_overlay_config_1_mmr_u { | |
55ba4120 JS |
1590 | unsigned long v; |
1591 | struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { | |
1592 | unsigned long rsvd_0_23:24; | |
1593 | unsigned long base:8; /* RW */ | |
1594 | unsigned long rsvd_32_47:16; | |
1595 | unsigned long m_alias:5; /* RW */ | |
1596 | unsigned long rsvd_53_62:10; | |
1597 | unsigned long enable:1; /* RW */ | |
1598 | } s; | |
62b0cfc2 JS |
1599 | }; |
1600 | ||
1601 | /* ========================================================================= */ | |
1602 | /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ | |
1603 | /* ========================================================================= */ | |
55ba4120 | 1604 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL |
62b0cfc2 JS |
1605 | |
1606 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 | |
62b0cfc2 | 1607 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 |
62b0cfc2 | 1608 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 |
55ba4120 JS |
1609 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL |
1610 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL | |
62b0cfc2 JS |
1611 | #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL |
1612 | ||
1613 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u { | |
55ba4120 JS |
1614 | unsigned long v; |
1615 | struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { | |
1616 | unsigned long rsvd_0_23:24; | |
1617 | unsigned long base:8; /* RW */ | |
1618 | unsigned long rsvd_32_47:16; | |
1619 | unsigned long m_alias:5; /* RW */ | |
1620 | unsigned long rsvd_53_62:10; | |
1621 | unsigned long enable:1; /* RW */ | |
1622 | } s; | |
62b0cfc2 JS |
1623 | }; |
1624 | ||
9f5314fb JS |
1625 | /* ========================================================================= */ |
1626 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ | |
1627 | /* ========================================================================= */ | |
55ba4120 | 1628 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL |
9f5314fb JS |
1629 | |
1630 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 | |
1631 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL | |
1632 | ||
1633 | union uvh_rh_gam_alias210_redirect_config_0_mmr_u { | |
55ba4120 JS |
1634 | unsigned long v; |
1635 | struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { | |
1636 | unsigned long rsvd_0_23:24; | |
1637 | unsigned long dest_base:22; /* RW */ | |
1638 | unsigned long rsvd_46_63:18; | |
1639 | } s; | |
9f5314fb JS |
1640 | }; |
1641 | ||
1642 | /* ========================================================================= */ | |
1643 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ | |
1644 | /* ========================================================================= */ | |
55ba4120 | 1645 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL |
9f5314fb JS |
1646 | |
1647 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 | |
1648 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL | |
1649 | ||
1650 | union uvh_rh_gam_alias210_redirect_config_1_mmr_u { | |
55ba4120 JS |
1651 | unsigned long v; |
1652 | struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { | |
1653 | unsigned long rsvd_0_23:24; | |
1654 | unsigned long dest_base:22; /* RW */ | |
1655 | unsigned long rsvd_46_63:18; | |
1656 | } s; | |
9f5314fb JS |
1657 | }; |
1658 | ||
1659 | /* ========================================================================= */ | |
1660 | /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ | |
1661 | /* ========================================================================= */ | |
55ba4120 | 1662 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL |
9f5314fb JS |
1663 | |
1664 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 | |
1665 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL | |
1666 | ||
1667 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u { | |
55ba4120 JS |
1668 | unsigned long v; |
1669 | struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { | |
1670 | unsigned long rsvd_0_23:24; | |
1671 | unsigned long dest_base:22; /* RW */ | |
1672 | unsigned long rsvd_46_63:18; | |
1673 | } s; | |
9f5314fb JS |
1674 | }; |
1675 | ||
62b0cfc2 JS |
1676 | /* ========================================================================= */ |
1677 | /* UVH_RH_GAM_CONFIG_MMR */ | |
1678 | /* ========================================================================= */ | |
55ba4120 | 1679 | #define UVH_RH_GAM_CONFIG_MMR 0x1600000UL |
62b0cfc2 | 1680 | |
55ba4120 JS |
1681 | #define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 |
1682 | #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 | |
1683 | #define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL | |
1684 | #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL | |
2a919596 | 1685 | |
55ba4120 JS |
1686 | #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 |
1687 | #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 | |
1688 | #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12 | |
1689 | #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL | |
1690 | #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL | |
1691 | #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL | |
2a919596 | 1692 | |
55ba4120 JS |
1693 | #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 |
1694 | #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 | |
1695 | #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL | |
1696 | #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL | |
62b0cfc2 JS |
1697 | |
1698 | union uvh_rh_gam_config_mmr_u { | |
55ba4120 JS |
1699 | unsigned long v; |
1700 | struct uvh_rh_gam_config_mmr_s { | |
1701 | unsigned long m_skt:6; /* RW */ | |
1702 | unsigned long n_skt:4; /* RW */ | |
1703 | unsigned long rsvd_10_63:54; | |
1704 | } s; | |
1705 | struct uv1h_rh_gam_config_mmr_s { | |
1706 | unsigned long m_skt:6; /* RW */ | |
1707 | unsigned long n_skt:4; /* RW */ | |
1708 | unsigned long rsvd_10_11:2; | |
1709 | unsigned long mmiol_cfg:1; /* RW */ | |
1710 | unsigned long rsvd_13_63:51; | |
1711 | } s1; | |
1712 | struct uv2h_rh_gam_config_mmr_s { | |
1713 | unsigned long m_skt:6; /* RW */ | |
1714 | unsigned long n_skt:4; /* RW */ | |
1715 | unsigned long rsvd_10_63:54; | |
1716 | } s2; | |
62b0cfc2 JS |
1717 | }; |
1718 | ||
0d3e865b JS |
1719 | /* ========================================================================= */ |
1720 | /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ | |
1721 | /* ========================================================================= */ | |
55ba4120 | 1722 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL |
0d3e865b | 1723 | |
55ba4120 JS |
1724 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 |
1725 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL | |
2a919596 | 1726 | |
55ba4120 JS |
1727 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 |
1728 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 | |
1729 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 | |
1730 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | |
1731 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL | |
1732 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL | |
1733 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL | |
1734 | #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | |
2a919596 | 1735 | |
55ba4120 JS |
1736 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 |
1737 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 | |
1738 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | |
1739 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL | |
1740 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL | |
1741 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | |
0d3e865b JS |
1742 | |
1743 | union uvh_rh_gam_gru_overlay_config_mmr_u { | |
55ba4120 JS |
1744 | unsigned long v; |
1745 | struct uvh_rh_gam_gru_overlay_config_mmr_s { | |
1746 | unsigned long rsvd_0_27:28; | |
1747 | unsigned long base:18; /* RW */ | |
1748 | unsigned long rsvd_46_62:17; | |
1749 | unsigned long enable:1; /* RW */ | |
1750 | } s; | |
1751 | struct uv1h_rh_gam_gru_overlay_config_mmr_s { | |
1752 | unsigned long rsvd_0_27:28; | |
1753 | unsigned long base:18; /* RW */ | |
1754 | unsigned long rsvd_46_47:2; | |
1755 | unsigned long gr4:1; /* RW */ | |
1756 | unsigned long rsvd_49_51:3; | |
1757 | unsigned long n_gru:4; /* RW */ | |
1758 | unsigned long rsvd_56_62:7; | |
1759 | unsigned long enable:1; /* RW */ | |
1760 | } s1; | |
1761 | struct uv2h_rh_gam_gru_overlay_config_mmr_s { | |
1762 | unsigned long rsvd_0_27:28; | |
1763 | unsigned long base:18; /* RW */ | |
1764 | unsigned long rsvd_46_51:6; | |
1765 | unsigned long n_gru:4; /* RW */ | |
1766 | unsigned long rsvd_56_62:7; | |
1767 | unsigned long enable:1; /* RW */ | |
1768 | } s2; | |
0d3e865b JS |
1769 | }; |
1770 | ||
83f5d894 JS |
1771 | /* ========================================================================= */ |
1772 | /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */ | |
1773 | /* ========================================================================= */ | |
55ba4120 | 1774 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL |
83f5d894 | 1775 | |
55ba4120 JS |
1776 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 |
1777 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 | |
1778 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 | |
2a919596 | 1779 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 |
55ba4120 JS |
1780 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL |
1781 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL | |
1782 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL | |
2a919596 JS |
1783 | #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL |
1784 | ||
55ba4120 JS |
1785 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27 |
1786 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 | |
1787 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 | |
2a919596 | 1788 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 |
55ba4120 JS |
1789 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL |
1790 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL | |
1791 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL | |
2a919596 | 1792 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL |
5d061e39 DS |
1793 | |
1794 | union uvh_rh_gam_mmioh_overlay_config_mmr_u { | |
55ba4120 JS |
1795 | unsigned long v; |
1796 | struct uv1h_rh_gam_mmioh_overlay_config_mmr_s { | |
1797 | unsigned long rsvd_0_29:30; | |
1798 | unsigned long base:16; /* RW */ | |
1799 | unsigned long m_io:6; /* RW */ | |
1800 | unsigned long n_io:4; /* RW */ | |
1801 | unsigned long rsvd_56_62:7; | |
1802 | unsigned long enable:1; /* RW */ | |
1803 | } s1; | |
1804 | struct uv2h_rh_gam_mmioh_overlay_config_mmr_s { | |
1805 | unsigned long rsvd_0_26:27; | |
1806 | unsigned long base:19; /* RW */ | |
1807 | unsigned long m_io:6; /* RW */ | |
1808 | unsigned long n_io:4; /* RW */ | |
1809 | unsigned long rsvd_56_62:7; | |
1810 | unsigned long enable:1; /* RW */ | |
1811 | } s2; | |
5d061e39 DS |
1812 | }; |
1813 | ||
0d3e865b JS |
1814 | /* ========================================================================= */ |
1815 | /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ | |
1816 | /* ========================================================================= */ | |
55ba4120 | 1817 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL |
0d3e865b | 1818 | |
55ba4120 JS |
1819 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 |
1820 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL | |
2a919596 | 1821 | |
55ba4120 | 1822 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 |
2a919596 | 1823 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 |
55ba4120 JS |
1824 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 |
1825 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL | |
2a919596 | 1826 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL |
55ba4120 | 1827 | #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL |
2a919596 | 1828 | |
55ba4120 JS |
1829 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 |
1830 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 | |
1831 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL | |
1832 | #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL | |
0d3e865b JS |
1833 | |
1834 | union uvh_rh_gam_mmr_overlay_config_mmr_u { | |
55ba4120 JS |
1835 | unsigned long v; |
1836 | struct uvh_rh_gam_mmr_overlay_config_mmr_s { | |
1837 | unsigned long rsvd_0_25:26; | |
1838 | unsigned long base:20; /* RW */ | |
1839 | unsigned long rsvd_46_62:17; | |
1840 | unsigned long enable:1; /* RW */ | |
1841 | } s; | |
1842 | struct uv1h_rh_gam_mmr_overlay_config_mmr_s { | |
1843 | unsigned long rsvd_0_25:26; | |
1844 | unsigned long base:20; /* RW */ | |
1845 | unsigned long dual_hub:1; /* RW */ | |
1846 | unsigned long rsvd_47_62:16; | |
1847 | unsigned long enable:1; /* RW */ | |
1848 | } s1; | |
1849 | struct uv2h_rh_gam_mmr_overlay_config_mmr_s { | |
1850 | unsigned long rsvd_0_25:26; | |
1851 | unsigned long base:20; /* RW */ | |
1852 | unsigned long rsvd_46_62:17; | |
1853 | unsigned long enable:1; /* RW */ | |
1854 | } s2; | |
0d3e865b JS |
1855 | }; |
1856 | ||
1857 | /* ========================================================================= */ | |
1858 | /* UVH_RTC */ | |
1859 | /* ========================================================================= */ | |
55ba4120 | 1860 | #define UVH_RTC 0x340000UL |
0d3e865b | 1861 | |
55ba4120 JS |
1862 | #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 |
1863 | #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL | |
0d3e865b JS |
1864 | |
1865 | union uvh_rtc_u { | |
55ba4120 JS |
1866 | unsigned long v; |
1867 | struct uvh_rtc_s { | |
1868 | unsigned long real_time_clock:56; /* RW */ | |
1869 | unsigned long rsvd_56_63:8; | |
1870 | } s; | |
0d3e865b JS |
1871 | }; |
1872 | ||
5d061e39 DS |
1873 | /* ========================================================================= */ |
1874 | /* UVH_RTC1_INT_CONFIG */ | |
1875 | /* ========================================================================= */ | |
55ba4120 JS |
1876 | #define UVH_RTC1_INT_CONFIG 0x615c0UL |
1877 | ||
1878 | #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 | |
1879 | #define UVH_RTC1_INT_CONFIG_DM_SHFT 8 | |
1880 | #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 | |
1881 | #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 | |
1882 | #define UVH_RTC1_INT_CONFIG_P_SHFT 13 | |
1883 | #define UVH_RTC1_INT_CONFIG_T_SHFT 15 | |
1884 | #define UVH_RTC1_INT_CONFIG_M_SHFT 16 | |
1885 | #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 | |
1886 | #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL | |
1887 | #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL | |
1888 | #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL | |
1889 | #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL | |
1890 | #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL | |
1891 | #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL | |
1892 | #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL | |
1893 | #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL | |
5d061e39 DS |
1894 | |
1895 | union uvh_rtc1_int_config_u { | |
55ba4120 JS |
1896 | unsigned long v; |
1897 | struct uvh_rtc1_int_config_s { | |
1898 | unsigned long vector_:8; /* RW */ | |
1899 | unsigned long dm:3; /* RW */ | |
1900 | unsigned long destmode:1; /* RW */ | |
1901 | unsigned long status:1; /* RO */ | |
1902 | unsigned long p:1; /* RO */ | |
1903 | unsigned long rsvd_14:1; | |
1904 | unsigned long t:1; /* RO */ | |
1905 | unsigned long m:1; /* RW */ | |
1906 | unsigned long rsvd_17_31:15; | |
1907 | unsigned long apic_id:32; /* RW */ | |
1908 | } s; | |
5d061e39 DS |
1909 | }; |
1910 | ||
1d44e828 JS |
1911 | /* ========================================================================= */ |
1912 | /* UVH_SCRATCH5 */ | |
1913 | /* ========================================================================= */ | |
55ba4120 JS |
1914 | #define UVH_SCRATCH5 0x2d0200UL |
1915 | #define UVH_SCRATCH5_32 0x778 | |
1d44e828 | 1916 | |
55ba4120 JS |
1917 | #define UVH_SCRATCH5_SCRATCH5_SHFT 0 |
1918 | #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL | |
2a919596 | 1919 | |
1d44e828 | 1920 | union uvh_scratch5_u { |
55ba4120 JS |
1921 | unsigned long v; |
1922 | struct uvh_scratch5_s { | |
1923 | unsigned long scratch5:64; /* RW, W1CS */ | |
1924 | } s; | |
1d44e828 | 1925 | }; |
0d3e865b | 1926 | |
2a919596 JS |
1927 | /* ========================================================================= */ |
1928 | /* UV2H_EVENT_OCCURRED2 */ | |
1929 | /* ========================================================================= */ | |
55ba4120 JS |
1930 | #define UV2H_EVENT_OCCURRED2 0x70100UL |
1931 | #define UV2H_EVENT_OCCURRED2_32 0xb68 | |
1932 | ||
1933 | #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 | |
1934 | #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 | |
1935 | #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2 | |
1936 | #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3 | |
1937 | #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4 | |
1938 | #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5 | |
1939 | #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6 | |
1940 | #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7 | |
1941 | #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8 | |
1942 | #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9 | |
1943 | #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10 | |
1944 | #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11 | |
1945 | #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12 | |
1946 | #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13 | |
1947 | #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14 | |
1948 | #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15 | |
1949 | #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16 | |
1950 | #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17 | |
1951 | #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18 | |
1952 | #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19 | |
1953 | #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20 | |
1954 | #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21 | |
1955 | #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22 | |
1956 | #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23 | |
1957 | #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24 | |
1958 | #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25 | |
1959 | #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26 | |
1960 | #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27 | |
1961 | #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28 | |
1962 | #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29 | |
1963 | #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30 | |
1964 | #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31 | |
1965 | #define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL | |
1966 | #define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL | |
1967 | #define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL | |
1968 | #define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL | |
1969 | #define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL | |
1970 | #define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL | |
1971 | #define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL | |
1972 | #define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL | |
1973 | #define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL | |
1974 | #define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL | |
1975 | #define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL | |
1976 | #define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL | |
1977 | #define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL | |
1978 | #define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL | |
1979 | #define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL | |
1980 | #define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL | |
1981 | #define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL | |
1982 | #define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL | |
1983 | #define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL | |
1984 | #define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL | |
1985 | #define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL | |
1986 | #define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL | |
1987 | #define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL | |
1988 | #define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL | |
1989 | #define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL | |
1990 | #define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL | |
1991 | #define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL | |
1992 | #define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL | |
1993 | #define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL | |
1994 | #define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL | |
1995 | #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL | |
1996 | #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL | |
2a919596 JS |
1997 | |
1998 | union uv2h_event_occurred2_u { | |
55ba4120 JS |
1999 | unsigned long v; |
2000 | struct uv2h_event_occurred2_s { | |
2001 | unsigned long rtc_0:1; /* RW */ | |
2002 | unsigned long rtc_1:1; /* RW */ | |
2003 | unsigned long rtc_2:1; /* RW */ | |
2004 | unsigned long rtc_3:1; /* RW */ | |
2005 | unsigned long rtc_4:1; /* RW */ | |
2006 | unsigned long rtc_5:1; /* RW */ | |
2007 | unsigned long rtc_6:1; /* RW */ | |
2008 | unsigned long rtc_7:1; /* RW */ | |
2009 | unsigned long rtc_8:1; /* RW */ | |
2010 | unsigned long rtc_9:1; /* RW */ | |
2011 | unsigned long rtc_10:1; /* RW */ | |
2012 | unsigned long rtc_11:1; /* RW */ | |
2013 | unsigned long rtc_12:1; /* RW */ | |
2014 | unsigned long rtc_13:1; /* RW */ | |
2015 | unsigned long rtc_14:1; /* RW */ | |
2016 | unsigned long rtc_15:1; /* RW */ | |
2017 | unsigned long rtc_16:1; /* RW */ | |
2018 | unsigned long rtc_17:1; /* RW */ | |
2019 | unsigned long rtc_18:1; /* RW */ | |
2020 | unsigned long rtc_19:1; /* RW */ | |
2021 | unsigned long rtc_20:1; /* RW */ | |
2022 | unsigned long rtc_21:1; /* RW */ | |
2023 | unsigned long rtc_22:1; /* RW */ | |
2024 | unsigned long rtc_23:1; /* RW */ | |
2025 | unsigned long rtc_24:1; /* RW */ | |
2026 | unsigned long rtc_25:1; /* RW */ | |
2027 | unsigned long rtc_26:1; /* RW */ | |
2028 | unsigned long rtc_27:1; /* RW */ | |
2029 | unsigned long rtc_28:1; /* RW */ | |
2030 | unsigned long rtc_29:1; /* RW */ | |
2031 | unsigned long rtc_30:1; /* RW */ | |
2032 | unsigned long rtc_31:1; /* RW */ | |
2033 | unsigned long rsvd_32_63:32; | |
2034 | } s1; | |
2a919596 JS |
2035 | }; |
2036 | ||
2037 | /* ========================================================================= */ | |
2038 | /* UV2H_EVENT_OCCURRED2_ALIAS */ | |
2039 | /* ========================================================================= */ | |
55ba4120 JS |
2040 | #define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL |
2041 | #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70 | |
2a919596 JS |
2042 | |
2043 | /* ========================================================================= */ | |
2044 | /* UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 */ | |
2045 | /* ========================================================================= */ | |
55ba4120 JS |
2046 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL |
2047 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 | |
2a919596 JS |
2048 | |
2049 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 | |
2050 | #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL | |
2051 | ||
2052 | union uv2h_lb_bau_sb_activation_status_2_u { | |
55ba4120 JS |
2053 | unsigned long v; |
2054 | struct uv2h_lb_bau_sb_activation_status_2_s { | |
2055 | unsigned long aux_error:64; /* RW */ | |
2056 | } s1; | |
2a919596 JS |
2057 | }; |
2058 | ||
2059 | /* ========================================================================= */ | |
2060 | /* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */ | |
2061 | /* ========================================================================= */ | |
55ba4120 JS |
2062 | #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL |
2063 | #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0 | |
2a919596 JS |
2064 | |
2065 | #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0 | |
2066 | #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL | |
2067 | ||
2068 | union uv1h_lb_target_physical_apic_id_mask_u { | |
55ba4120 JS |
2069 | unsigned long v; |
2070 | struct uv1h_lb_target_physical_apic_id_mask_s { | |
2071 | unsigned long bit_enables:32; /* RW */ | |
2072 | unsigned long rsvd_32_63:32; | |
2073 | } s1; | |
2a919596 JS |
2074 | }; |
2075 | ||
2076 | ||
55ba4120 | 2077 | #endif /* _ASM_X86_UV_UV_MMRS_H */ |