Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2272b0e0 | 2 | /* |
2f0798a3 | 3 | * x86 TSC related functions |
2272b0e0 | 4 | */ |
1965aae3 PA |
5 | #ifndef _ASM_X86_TSC_H |
6 | #define _ASM_X86_TSC_H | |
2272b0e0 AS |
7 | |
8 | #include <asm/processor.h> | |
9 | ||
2f0798a3 TG |
10 | #define NS_SCALE 10 /* 2^10, carefully chosen */ |
11 | #define US_SCALE 32 /* 2^32, arbitralrily chosen */ | |
12 | ||
2272b0e0 AS |
13 | /* |
14 | * Standard way to access the cycle counter. | |
15 | */ | |
16 | typedef unsigned long long cycles_t; | |
17 | ||
18 | extern unsigned int cpu_khz; | |
19 | extern unsigned int tsc_khz; | |
73018a66 GOC |
20 | |
21 | extern void disable_TSC(void); | |
2272b0e0 AS |
22 | |
23 | static inline cycles_t get_cycles(void) | |
24 | { | |
2272b0e0 | 25 | #ifndef CONFIG_X86_TSC |
59e21e3d | 26 | if (!boot_cpu_has(X86_FEATURE_TSC)) |
2272b0e0 AS |
27 | return 0; |
28 | #endif | |
2272b0e0 | 29 | |
4ea1636b | 30 | return rdtsc(); |
6d63de8d | 31 | } |
4e87173e | 32 | |
a5a1d1c2 | 33 | extern struct system_counterval_t convert_art_to_tsc(u64 art); |
f9677e0f | 34 | |
2272b0e0 | 35 | extern void tsc_init(void); |
5a90cf20 | 36 | extern void mark_tsc_unstable(char *reason); |
2272b0e0 | 37 | extern int unsynchronized_tsc(void); |
2d826404 | 38 | extern int check_tsc_unstable(void); |
aa297292 | 39 | extern unsigned long native_calibrate_cpu(void); |
2d826404 | 40 | extern unsigned long native_calibrate_tsc(void); |
a94cab23 | 41 | extern unsigned long long native_sched_clock_from_tsc(u64 tsc); |
2272b0e0 | 42 | |
28a00184 SS |
43 | extern int tsc_clocksource_reliable; |
44 | ||
2272b0e0 AS |
45 | /* |
46 | * Boot-time check whether the TSCs are synchronized across | |
47 | * all CPUs/cores: | |
48 | */ | |
8b223bc7 | 49 | #ifdef CONFIG_X86_TSC |
5bae1562 | 50 | extern bool tsc_store_and_check_tsc_adjust(bool bootcpu); |
6a369583 | 51 | extern void tsc_verify_tsc_adjust(bool resume); |
b8365543 TG |
52 | extern void check_tsc_sync_source(int cpu); |
53 | extern void check_tsc_sync_target(void); | |
8b223bc7 | 54 | #else |
5bae1562 | 55 | static inline bool tsc_store_and_check_tsc_adjust(bool bootcpu) { return false; } |
6a369583 | 56 | static inline void tsc_verify_tsc_adjust(bool resume) { } |
b8365543 TG |
57 | static inline void check_tsc_sync_source(int cpu) { } |
58 | static inline void check_tsc_sync_target(void) { } | |
8b223bc7 TG |
59 | #endif |
60 | ||
80ca9c98 | 61 | extern int notsc_setup(char *); |
b74f05d6 MT |
62 | extern void tsc_save_sched_clock_state(void); |
63 | extern void tsc_restore_sched_clock_state(void); | |
d371698e | 64 | |
02c0cd2d | 65 | unsigned long cpu_khz_from_msr(void); |
7da7c156 | 66 | |
1965aae3 | 67 | #endif /* _ASM_X86_TSC_H */ |