[linux-block.git] / arch / x86 / include / asm / svm.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SVM_H
#define __SVM_H

#include <uapi/asm/svm.h>
#include <uapi/asm/kvm.h>

/*
 * 32-bit intercept words in the VMCB Control Area, starting
 * at Byte offset 000h.
 */

enum intercept_words {
	INTERCEPT_CR = 0,
	INTERCEPT_DR,
	INTERCEPT_EXCEPTION,
	INTERCEPT_WORD3,
	INTERCEPT_WORD4,
	INTERCEPT_WORD5,
	MAX_INTERCEPT,
};

enum {
	/* Byte offset 000h (word 0) */
	INTERCEPT_CR0_READ = 0,
	INTERCEPT_CR3_READ = 3,
	INTERCEPT_CR4_READ = 4,
	INTERCEPT_CR8_READ = 8,
	INTERCEPT_CR0_WRITE = 16,
	INTERCEPT_CR3_WRITE = 16 + 3,
	INTERCEPT_CR4_WRITE = 16 + 4,
	INTERCEPT_CR8_WRITE = 16 + 8,
	/* Byte offset 004h (word 1) */
	INTERCEPT_DR0_READ = 32,
	INTERCEPT_DR1_READ,
	INTERCEPT_DR2_READ,
	INTERCEPT_DR3_READ,
	INTERCEPT_DR4_READ,
	INTERCEPT_DR5_READ,
	INTERCEPT_DR6_READ,
	INTERCEPT_DR7_READ,
	INTERCEPT_DR0_WRITE = 48,
	INTERCEPT_DR1_WRITE,
	INTERCEPT_DR2_WRITE,
	INTERCEPT_DR3_WRITE,
	INTERCEPT_DR4_WRITE,
	INTERCEPT_DR5_WRITE,
	INTERCEPT_DR6_WRITE,
	INTERCEPT_DR7_WRITE,
	/* Byte offset 008h (word 2) */
	INTERCEPT_EXCEPTION_OFFSET = 64,
	/* Byte offset 00Ch (word 3) */
	INTERCEPT_INTR = 96,
	INTERCEPT_NMI,
	INTERCEPT_SMI,
	INTERCEPT_INIT,
	INTERCEPT_VINTR,
	INTERCEPT_SELECTIVE_CR0,
	INTERCEPT_STORE_IDTR,
	INTERCEPT_STORE_GDTR,
	INTERCEPT_STORE_LDTR,
	INTERCEPT_STORE_TR,
	INTERCEPT_LOAD_IDTR,
	INTERCEPT_LOAD_GDTR,
	INTERCEPT_LOAD_LDTR,
	INTERCEPT_LOAD_TR,
	INTERCEPT_RDTSC,
	INTERCEPT_RDPMC,
	INTERCEPT_PUSHF,
	INTERCEPT_POPF,
	INTERCEPT_CPUID,
	INTERCEPT_RSM,
	INTERCEPT_IRET,
	INTERCEPT_INTn,
	INTERCEPT_INVD,
	INTERCEPT_PAUSE,
	INTERCEPT_HLT,
	INTERCEPT_INVLPG,
	INTERCEPT_INVLPGA,
	INTERCEPT_IOIO_PROT,
	INTERCEPT_MSR_PROT,
	INTERCEPT_TASK_SWITCH,
	INTERCEPT_FERR_FREEZE,
	INTERCEPT_SHUTDOWN,
	/* Byte offset 010h (word 4) */
	INTERCEPT_VMRUN = 128,
	INTERCEPT_VMMCALL,
	INTERCEPT_VMLOAD,
	INTERCEPT_VMSAVE,
	INTERCEPT_STGI,
	INTERCEPT_CLGI,
	INTERCEPT_SKINIT,
	INTERCEPT_RDTSCP,
	INTERCEPT_ICEBP,
	INTERCEPT_WBINVD,
	INTERCEPT_MONITOR,
	INTERCEPT_MWAIT,
	INTERCEPT_MWAIT_COND,
	INTERCEPT_XSETBV,
	INTERCEPT_RDPRU,
	TRAP_EFER_WRITE,
	TRAP_CR0_WRITE,
	TRAP_CR1_WRITE,
	TRAP_CR2_WRITE,
	TRAP_CR3_WRITE,
	TRAP_CR4_WRITE,
	TRAP_CR5_WRITE,
	TRAP_CR6_WRITE,
	TRAP_CR7_WRITE,
	TRAP_CR8_WRITE,
	/* Byte offset 014h (word 5) */
	INTERCEPT_INVLPGB = 160,
	INTERCEPT_INVLPGB_ILLEGAL,
	INTERCEPT_INVPCID,
	INTERCEPT_MCOMMIT,
	INTERCEPT_TLBSYNC,
};


struct __attribute__ ((__packed__)) vmcb_control_area {
	u32 intercepts[MAX_INTERCEPT];
	u32 reserved_1[15 - MAX_INTERCEPT];
	u16 pause_filter_thresh;
	u16 pause_filter_count;
	u64 iopm_base_pa;
	u64 msrpm_base_pa;
	u64 tsc_offset;
	u32 asid;
	u8 tlb_ctl;
	u8 reserved_2[3];
	u32 int_ctl;
	u32 int_vector;
	u32 int_state;
	u8 reserved_3[4];
	u32 exit_code;
	u32 exit_code_hi;
	u64 exit_info_1;
	u64 exit_info_2;
	u32 exit_int_info;
	u32 exit_int_info_err;
	u64 nested_ctl;
	u64 avic_vapic_bar;
	u64 ghcb_gpa;
	u32 event_inj;
	u32 event_inj_err;
	u64 nested_cr3;
	u64 virt_ext;
	u32 clean;
	u32 reserved_5;
	u64 next_rip;
	u8 insn_len;
	u8 insn_bytes[15];
	u64 avic_backing_page;	/* Offset 0xe0 */
	u8 reserved_6[8];	/* Offset 0xe8 */
	u64 avic_logical_id;	/* Offset 0xf0 */
	u64 avic_physical_id;	/* Offset 0xf8 */
	u8 reserved_7[8];
	u64 vmsa_pa;		/* Used for an SEV-ES guest */
	u8 reserved_8[720];
	/*
	 * Offset 0x3e0, 32 bytes reserved
	 * for use by hypervisor/software.
	 */
	u8 reserved_sw[32];
};


#define TLB_CONTROL_DO_NOTHING 0
#define TLB_CONTROL_FLUSH_ALL_ASID 1
#define TLB_CONTROL_FLUSH_ASID 3
#define TLB_CONTROL_FLUSH_ASID_LOCAL 7

#define V_TPR_MASK 0x0f

#define V_IRQ_SHIFT 8
#define V_IRQ_MASK (1 << V_IRQ_SHIFT)

#define V_GIF_SHIFT 9
#define V_GIF_MASK (1 << V_GIF_SHIFT)

#define V_INTR_PRIO_SHIFT 16
#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)

#define V_IGN_TPR_SHIFT 20
#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)

#define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)

#define V_INTR_MASKING_SHIFT 24
#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)

#define V_GIF_ENABLE_SHIFT 25
#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)

#define AVIC_ENABLE_SHIFT 31
#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)

#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)

#define SVM_INTERRUPT_SHADOW_MASK	BIT_ULL(0)
#define SVM_GUEST_INTERRUPT_MASK	BIT_ULL(1)

#define SVM_IOIO_STR_SHIFT 2
#define SVM_IOIO_REP_SHIFT 3
#define SVM_IOIO_SIZE_SHIFT 4
#define SVM_IOIO_ASIZE_SHIFT 7

#define SVM_IOIO_TYPE_MASK 1
#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)

#define SVM_VM_CR_VALID_MASK	0x001fULL
#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
#define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL

#define SVM_NESTED_CTL_NP_ENABLE	BIT(0)
#define SVM_NESTED_CTL_SEV_ENABLE	BIT(1)
#define SVM_NESTED_CTL_SEV_ES_ENABLE	BIT(2)


#define SVM_TSC_RATIO_RSVD	0xffffff0000000000ULL
#define SVM_TSC_RATIO_MIN	0x0000000000000001ULL
#define SVM_TSC_RATIO_MAX	0x000000ffffffffffULL
#define SVM_TSC_RATIO_DEFAULT	0x0100000000ULL


/* AVIC */
#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK	(0xFFULL)
#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT			31
#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK		(1 << 31)

#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK	GENMASK_ULL(11, 0)
#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK	(0xFFFFFFFFFFULL << 12)
#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK		(1ULL << 62)
#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK		(1ULL << 63)
#define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK		(0xFFULL)

#define AVIC_DOORBELL_PHYSICAL_ID_MASK			GENMASK_ULL(11, 0)

#define VMCB_AVIC_APIC_BAR_MASK				0xFFFFFFFFFF000ULL

#define AVIC_UNACCEL_ACCESS_WRITE_MASK		1
#define AVIC_UNACCEL_ACCESS_OFFSET_MASK		0xFF0
#define AVIC_UNACCEL_ACCESS_VECTOR_MASK		0xFFFFFFFF

enum avic_ipi_failure_cause {
	AVIC_IPI_FAILURE_INVALID_INT_TYPE,
	AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
	AVIC_IPI_FAILURE_INVALID_TARGET,
	AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
};


/*
 * 0xff is broadcast, so the max index allowed for physical APIC ID
 * table is 0xfe.  APIC IDs above 0xff are reserved.
 */
#define AVIC_MAX_PHYSICAL_ID_COUNT	0xff

#define AVIC_HPA_MASK	~((0xFFFULL << 52) | 0xFFF)
#define VMCB_AVIC_APIC_BAR_MASK		0xFFFFFFFFFF000ULL


struct vmcb_seg {
	u16 selector;
	u16 attrib;
	u32 limit;
	u64 base;
} __packed;

/* Save area definition for legacy and SEV-MEM guests */
struct vmcb_save_area {
	struct vmcb_seg es;
	struct vmcb_seg cs;
	struct vmcb_seg ss;
	struct vmcb_seg ds;
	struct vmcb_seg fs;
	struct vmcb_seg gs;
	struct vmcb_seg gdtr;
	struct vmcb_seg ldtr;
	struct vmcb_seg idtr;
	struct vmcb_seg tr;
	u8 reserved_1[42];
	u8 vmpl;
	u8 cpl;
	u8 reserved_2[4];
	u64 efer;
	u8 reserved_3[112];
	u64 cr4;
	u64 cr3;
	u64 cr0;
	u64 dr7;
	u64 dr6;
	u64 rflags;
	u64 rip;
	u8 reserved_4[88];
	u64 rsp;
	u64 s_cet;
	u64 ssp;
	u64 isst_addr;
	u64 rax;
	u64 star;
	u64 lstar;
	u64 cstar;
	u64 sfmask;
	u64 kernel_gs_base;
	u64 sysenter_cs;
	u64 sysenter_esp;
	u64 sysenter_eip;
	u64 cr2;
	u8 reserved_5[32];
	u64 g_pat;
	u64 dbgctl;
	u64 br_from;
	u64 br_to;
	u64 last_excp_from;
	u64 last_excp_to;
	u8 reserved_6[72];
	u32 spec_ctrl;		/* Guest version of SPEC_CTRL at 0x2E0 */
} __packed;

/* Save area definition for SEV-ES and SEV-SNP guests */
struct sev_es_save_area {
	struct vmcb_seg es;
	struct vmcb_seg cs;
	struct vmcb_seg ss;
	struct vmcb_seg ds;
	struct vmcb_seg fs;
	struct vmcb_seg gs;
	struct vmcb_seg gdtr;
	struct vmcb_seg ldtr;
	struct vmcb_seg idtr;
	struct vmcb_seg tr;
	u64 vmpl0_ssp;
	u64 vmpl1_ssp;
	u64 vmpl2_ssp;
	u64 vmpl3_ssp;
	u64 u_cet;
	u8 reserved_1[2];
	u8 vmpl;
	u8 cpl;
	u8 reserved_2[4];
	u64 efer;
	u8 reserved_3[104];
	u64 xss;
	u64 cr4;
	u64 cr3;
	u64 cr0;
	u64 dr7;
	u64 dr6;
	u64 rflags;
	u64 rip;
	u64 dr0;
	u64 dr1;
	u64 dr2;
	u64 dr3;
	u64 dr0_addr_mask;
	u64 dr1_addr_mask;
	u64 dr2_addr_mask;
	u64 dr3_addr_mask;
	u8 reserved_4[24];
	u64 rsp;
	u64 s_cet;
	u64 ssp;
	u64 isst_addr;
	u64 rax;
	u64 star;
	u64 lstar;
	u64 cstar;
	u64 sfmask;
	u64 kernel_gs_base;
	u64 sysenter_cs;
	u64 sysenter_esp;
	u64 sysenter_eip;
	u64 cr2;
	u8 reserved_5[32];
	u64 g_pat;
	u64 dbgctl;
	u64 br_from;
	u64 br_to;
	u64 last_excp_from;
	u64 last_excp_to;
	u8 reserved_7[80];
	u32 pkru;
	u8 reserved_8[20];
	u64 reserved_9;		/* rax already available at 0x01f8 */
	u64 rcx;
	u64 rdx;
	u64 rbx;
	u64 reserved_10;	/* rsp already available at 0x01d8 */
	u64 rbp;
	u64 rsi;
	u64 rdi;
	u64 r8;
	u64 r9;
	u64 r10;
	u64 r11;
	u64 r12;
	u64 r13;
	u64 r14;
	u64 r15;
	u8 reserved_11[16];
	u64 guest_exit_info_1;
	u64 guest_exit_info_2;
	u64 guest_exit_int_info;
	u64 guest_nrip;
	u64 sev_features;
	u64 vintr_ctrl;
	u64 guest_exit_code;
	u64 virtual_tom;
	u64 tlb_id;
	u64 pcpu_id;
	u64 event_inj;
	u64 xcr0;
	u8 reserved_12[16];

	/* Floating point area */
	u64 x87_dp;
	u32 mxcsr;
	u16 x87_ftw;
	u16 x87_fsw;
	u16 x87_fcw;
	u16 x87_fop;
	u16 x87_ds;
	u16 x87_cs;
	u64 x87_rip;
	u8 fpreg_x87[80];
	u8 fpreg_xmm[256];
	u8 fpreg_ymm[256];
} __packed;

struct ghcb_save_area {
	u8 reserved_1[203];
	u8 cpl;
	u8 reserved_2[116];
	u64 xss;
	u8 reserved_3[24];
	u64 dr7;
	u8 reserved_4[16];
	u64 rip;
	u8 reserved_5[88];
	u64 rsp;
	u8 reserved_6[24];
	u64 rax;
	u8 reserved_7[264];
	u64 rcx;
	u64 rdx;
	u64 rbx;
	u8 reserved_8[8];
	u64 rbp;
	u64 rsi;
	u64 rdi;
	u64 r8;
	u64 r9;
	u64 r10;
	u64 r11;
	u64 r12;
	u64 r13;
	u64 r14;
	u64 r15;
	u8 reserved_9[16];
	u64 sw_exit_code;
	u64 sw_exit_info_1;
	u64 sw_exit_info_2;
	u64 sw_scratch;
	u8 reserved_10[56];
	u64 xcr0;
	u8 valid_bitmap[16];
	u64 x87_state_gpa;
} __packed;

#define GHCB_SHARED_BUF_SIZE	2032

struct ghcb {
	struct ghcb_save_area save;
	u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];

	u8 shared_buffer[GHCB_SHARED_BUF_SIZE];

	u8 reserved_1[10];
	u16 protocol_version;	/* negotiated SEV-ES/GHCB protocol version */
	u32 ghcb_usage;
} __packed;


#define EXPECTED_VMCB_SAVE_AREA_SIZE		740
#define EXPECTED_GHCB_SAVE_AREA_SIZE		1032
#define EXPECTED_SEV_ES_SAVE_AREA_SIZE		1648
#define EXPECTED_VMCB_CONTROL_AREA_SIZE		1024
#define EXPECTED_GHCB_SIZE			PAGE_SIZE

static inline void __unused_size_checks(void)
{
	BUILD_BUG_ON(sizeof(struct vmcb_save_area)	!= EXPECTED_VMCB_SAVE_AREA_SIZE);
	BUILD_BUG_ON(sizeof(struct ghcb_save_area)	!= EXPECTED_GHCB_SAVE_AREA_SIZE);
	BUILD_BUG_ON(sizeof(struct sev_es_save_area)	!= EXPECTED_SEV_ES_SAVE_AREA_SIZE);
	BUILD_BUG_ON(sizeof(struct vmcb_control_area)	!= EXPECTED_VMCB_CONTROL_AREA_SIZE);
	BUILD_BUG_ON(sizeof(struct ghcb)		!= EXPECTED_GHCB_SIZE);
}

struct vmcb {
	struct vmcb_control_area control;
	struct vmcb_save_area save;
} __packed;

#define SVM_CPUID_FUNC 0x8000000a

#define SVM_VM_CR_SVM_DISABLE 4

#define SVM_SELECTOR_S_SHIFT 4
#define SVM_SELECTOR_DPL_SHIFT 5
#define SVM_SELECTOR_P_SHIFT 7
#define SVM_SELECTOR_AVL_SHIFT 8
#define SVM_SELECTOR_L_SHIFT 9
#define SVM_SELECTOR_DB_SHIFT 10
#define SVM_SELECTOR_G_SHIFT 11

#define SVM_SELECTOR_TYPE_MASK (0xf)
#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)

#define SVM_SELECTOR_WRITE_MASK (1 << 1)
#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
#define SVM_SELECTOR_CODE_MASK (1 << 3)

#define SVM_EVTINJ_VEC_MASK 0xff

#define SVM_EVTINJ_TYPE_SHIFT 8
#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)

#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)

#define SVM_EVTINJ_VALID (1 << 31)
#define SVM_EVTINJ_VALID_ERR (1 << 11)

#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK

#define	SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
#define	SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
#define	SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
#define	SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT

#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR

#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44

#define SVM_EXITINFO_REG_MASK 0x0F

#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)

/* GHCB Accessor functions */

#define GHCB_BITMAP_IDX(field)							\
	(offsetof(struct ghcb_save_area, field) / sizeof(u64))

#define DEFINE_GHCB_ACCESSORS(field)						\
	static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
	{									\
		return test_bit(GHCB_BITMAP_IDX(field),				\
				(unsigned long *)&ghcb->save.valid_bitmap);	\
	}									\
										\
	static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb)		\
	{									\
		return ghcb->save.field;					\
	}									\
										\
	static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
	{									\
		return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0;	\
	}									\
										\
	static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
	{									\
		__set_bit(GHCB_BITMAP_IDX(field),				\
			  (unsigned long *)&ghcb->save.valid_bitmap);		\
		ghcb->save.field = value;					\
	}

DEFINE_GHCB_ACCESSORS(cpl)
DEFINE_GHCB_ACCESSORS(rip)
DEFINE_GHCB_ACCESSORS(rsp)
DEFINE_GHCB_ACCESSORS(rax)
DEFINE_GHCB_ACCESSORS(rcx)
DEFINE_GHCB_ACCESSORS(rdx)
DEFINE_GHCB_ACCESSORS(rbx)
DEFINE_GHCB_ACCESSORS(rbp)
DEFINE_GHCB_ACCESSORS(rsi)
DEFINE_GHCB_ACCESSORS(rdi)
DEFINE_GHCB_ACCESSORS(r8)
DEFINE_GHCB_ACCESSORS(r9)
DEFINE_GHCB_ACCESSORS(r10)
DEFINE_GHCB_ACCESSORS(r11)
DEFINE_GHCB_ACCESSORS(r12)
DEFINE_GHCB_ACCESSORS(r13)
DEFINE_GHCB_ACCESSORS(r14)
DEFINE_GHCB_ACCESSORS(r15)
DEFINE_GHCB_ACCESSORS(sw_exit_code)
DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
DEFINE_GHCB_ACCESSORS(sw_scratch)
DEFINE_GHCB_ACCESSORS(xcr0)

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
6aa8b732 AK	2	#ifndef __SVM_H
	3	#define __SVM_H
	4
af170c50	5	#include <uapi/asm/svm.h>
9780d51d	6	#include <uapi/asm/kvm.h>
af170c50	7
c45ad722 BM	8	/*
	9	* 32-bit intercept words in the VMCB Control Area, starting
	10	* at Byte offset 000h.
	11	*/
	12
	13	enum intercept_words {
03bfeeb9	14	INTERCEPT_CR = 0,
30abaa88	15	INTERCEPT_DR,
9780d51d	16	INTERCEPT_EXCEPTION,
c62e2e94 BM	17	INTERCEPT_WORD3,
c62e2e94 BM	18	INTERCEPT_WORD4,
4c44e8d6	19	INTERCEPT_WORD5,
c45ad722 BM	20	MAX_INTERCEPT,
c45ad722 BM	21	};
26bf264e	22
03bfeeb9 BM	23	enum {
	24	/* Byte offset 000h (word 0) */
	25	INTERCEPT_CR0_READ = 0,
	26	INTERCEPT_CR3_READ = 3,
	27	INTERCEPT_CR4_READ = 4,
	28	INTERCEPT_CR8_READ = 8,
	29	INTERCEPT_CR0_WRITE = 16,
	30	INTERCEPT_CR3_WRITE = 16 + 3,
	31	INTERCEPT_CR4_WRITE = 16 + 4,
	32	INTERCEPT_CR8_WRITE = 16 + 8,
30abaa88 BM	33	/* Byte offset 004h (word 1) */
	34	INTERCEPT_DR0_READ = 32,
	35	INTERCEPT_DR1_READ,
	36	INTERCEPT_DR2_READ,
	37	INTERCEPT_DR3_READ,
	38	INTERCEPT_DR4_READ,
	39	INTERCEPT_DR5_READ,
	40	INTERCEPT_DR6_READ,
	41	INTERCEPT_DR7_READ,
	42	INTERCEPT_DR0_WRITE = 48,
	43	INTERCEPT_DR1_WRITE,
	44	INTERCEPT_DR2_WRITE,
	45	INTERCEPT_DR3_WRITE,
	46	INTERCEPT_DR4_WRITE,
	47	INTERCEPT_DR5_WRITE,
	48	INTERCEPT_DR6_WRITE,
	49	INTERCEPT_DR7_WRITE,
9780d51d BM	50	/* Byte offset 008h (word 2) */
9780d51d BM	51	INTERCEPT_EXCEPTION_OFFSET = 64,
c62e2e94 BM	52	/* Byte offset 00Ch (word 3) */
c62e2e94 BM	53	INTERCEPT_INTR = 96,
6aa8b732 AK	54	INTERCEPT_NMI,
	55	INTERCEPT_SMI,
	56	INTERCEPT_INIT,
	57	INTERCEPT_VINTR,
	58	INTERCEPT_SELECTIVE_CR0,
	59	INTERCEPT_STORE_IDTR,
	60	INTERCEPT_STORE_GDTR,
	61	INTERCEPT_STORE_LDTR,
	62	INTERCEPT_STORE_TR,
	63	INTERCEPT_LOAD_IDTR,
	64	INTERCEPT_LOAD_GDTR,
	65	INTERCEPT_LOAD_LDTR,
	66	INTERCEPT_LOAD_TR,
	67	INTERCEPT_RDTSC,
	68	INTERCEPT_RDPMC,
	69	INTERCEPT_PUSHF,
	70	INTERCEPT_POPF,
	71	INTERCEPT_CPUID,
	72	INTERCEPT_RSM,
	73	INTERCEPT_IRET,
	74	INTERCEPT_INTn,
	75	INTERCEPT_INVD,
	76	INTERCEPT_PAUSE,
	77	INTERCEPT_HLT,
	78	INTERCEPT_INVLPG,
	79	INTERCEPT_INVLPGA,
	80	INTERCEPT_IOIO_PROT,
	81	INTERCEPT_MSR_PROT,
	82	INTERCEPT_TASK_SWITCH,
	83	INTERCEPT_FERR_FREEZE,
	84	INTERCEPT_SHUTDOWN,
c62e2e94 BM	85	/* Byte offset 010h (word 4) */
c62e2e94 BM	86	INTERCEPT_VMRUN = 128,
6aa8b732 AK	87	INTERCEPT_VMMCALL,
	88	INTERCEPT_VMLOAD,
	89	INTERCEPT_VMSAVE,
	90	INTERCEPT_STGI,
	91	INTERCEPT_CLGI,
	92	INTERCEPT_SKINIT,
	93	INTERCEPT_RDTSCP,
	94	INTERCEPT_ICEBP,
	95	INTERCEPT_WBINVD,
916ce236 JR	96	INTERCEPT_MONITOR,
	97	INTERCEPT_MWAIT,
	98	INTERCEPT_MWAIT_COND,
81dd35d4	99	INTERCEPT_XSETBV,
0cb8410b	100	INTERCEPT_RDPRU,
376c6d28 TL	101	TRAP_EFER_WRITE,
	102	TRAP_CR0_WRITE,
	103	TRAP_CR1_WRITE,
	104	TRAP_CR2_WRITE,
	105	TRAP_CR3_WRITE,
	106	TRAP_CR4_WRITE,
	107	TRAP_CR5_WRITE,
	108	TRAP_CR6_WRITE,
	109	TRAP_CR7_WRITE,
	110	TRAP_CR8_WRITE,
4c44e8d6 BM	111	/* Byte offset 014h (word 5) */
	112	INTERCEPT_INVLPGB = 160,
	113	INTERCEPT_INVLPGB_ILLEGAL,
	114	INTERCEPT_INVPCID,
	115	INTERCEPT_MCOMMIT,
	116	INTERCEPT_TLBSYNC,
6aa8b732 AK	117	};
	118
	119
	120	struct __attribute__ ((__packed__)) vmcb_control_area {
c45ad722	121	u32 intercepts[MAX_INTERCEPT];
c62e2e94	122	u32 reserved_1[15 - MAX_INTERCEPT];
1d8fb44a	123	u16 pause_filter_thresh;
565d0998	124	u16 pause_filter_count;
6aa8b732 AK	125	u64 iopm_base_pa;
	126	u64 msrpm_base_pa;
	127	u64 tsc_offset;
	128	u32 asid;
	129	u8 tlb_ctl;
	130	u8 reserved_2[3];
	131	u32 int_ctl;
	132	u32 int_vector;
	133	u32 int_state;
	134	u8 reserved_3[4];
	135	u32 exit_code;
	136	u32 exit_code_hi;
	137	u64 exit_info_1;
	138	u64 exit_info_2;
	139	u32 exit_int_info;
	140	u32 exit_int_info_err;
	141	u64 nested_ctl;
3d5615e5	142	u64 avic_vapic_bar;
291bd20d	143	u64 ghcb_gpa;
6aa8b732 AK	144	u32 event_inj;
	145	u32 event_inj_err;
	146	u64 nested_cr3;
0dc92119	147	u64 virt_ext;
8d28fec4 RJ	148	u32 clean;
8d28fec4 RJ	149	u32 reserved_5;
6bc31bdc	150	u64 next_rip;
dc25e89e AP	151	u8 insn_len;
dc25e89e AP	152	u8 insn_bytes[15];
3d5615e5 SS	153	u64 avic_backing_page; /* Offset 0xe0 */
	154	u8 reserved_6[8]; /* Offset 0xe8 */
	155	u64 avic_logical_id; /* Offset 0xf0 */
	156	u64 avic_physical_id; /* Offset 0xf8 */
376c6d28 TL	157	u8 reserved_7[8];
376c6d28 TL	158	u64 vmsa_pa; /* Used for an SEV-ES guest */
59d21d67 VP	159	u8 reserved_8[720];
	160	/*
	161	* Offset 0x3e0, 32 bytes reserved
	162	* for use by hypervisor/software.
	163	*/
	164	u8 reserved_sw[32];
6aa8b732 AK	165	};
	166
	167
	168	#define TLB_CONTROL_DO_NOTHING 0
	169	#define TLB_CONTROL_FLUSH_ALL_ASID 1
38e5e92f JR	170	#define TLB_CONTROL_FLUSH_ASID 3
38e5e92f JR	171	#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
6aa8b732 AK	172
	173	#define V_TPR_MASK 0x0f
	174
	175	#define V_IRQ_SHIFT 8
	176	#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
	177
640bd6e5 JN	178	#define V_GIF_SHIFT 9
	179	#define V_GIF_MASK (1 << V_GIF_SHIFT)
	180
6aa8b732 AK	181	#define V_INTR_PRIO_SHIFT 16
	182	#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
	183
	184	#define V_IGN_TPR_SHIFT 20
	185	#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
	186
0f923e07 ML	187	#define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK \| V_INTR_PRIO_MASK \| V_IGN_TPR_MASK)
0f923e07 ML	188
6aa8b732 AK	189	#define V_INTR_MASKING_SHIFT 24
	190	#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
	191
640bd6e5 JN	192	#define V_GIF_ENABLE_SHIFT 25
	193	#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
	194
44a95dae SS	195	#define AVIC_ENABLE_SHIFT 31
	196	#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
	197
8a77e909	198	#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
89c8a498	199	#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
8a77e909	200
f1c6366e TL	201	#define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
f1c6366e TL	202	#define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
6aa8b732 AK	203
	204	#define SVM_IOIO_STR_SHIFT 2
	205	#define SVM_IOIO_REP_SHIFT 3
	206	#define SVM_IOIO_SIZE_SHIFT 4
	207	#define SVM_IOIO_ASIZE_SHIFT 7
	208
	209	#define SVM_IOIO_TYPE_MASK 1
	210	#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
	211	#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
	212	#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
	213	#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
	214
4a810181 JR	215	#define SVM_VM_CR_VALID_MASK 0x001fULL
	216	#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
	217	#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
	218
cea3a19b	219	#define SVM_NESTED_CTL_NP_ENABLE BIT(0)
ba7c3398	220	#define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
376c6d28	221	#define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
cea3a19b	222
39150352	223
bb2aa78e ML	224	#define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL
	225	#define SVM_TSC_RATIO_MIN 0x0000000000000001ULL
	226	#define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL
	227	#define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL
	228
	229
39150352	230	/* AVIC */
0dacc3df	231	#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL)
39150352 ML	232	#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
	233	#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
	234
4a204f78	235	#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
39150352 ML	236	#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
	237	#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
	238	#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
0dacc3df	239	#define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL)
39150352	240
0dacc3df ML	241	#define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
	242
	243	#define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
39150352 ML	244
	245	#define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
	246	#define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
	247	#define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
	248
	249	enum avic_ipi_failure_cause {
	250	AVIC_IPI_FAILURE_INVALID_INT_TYPE,
	251	AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
	252	AVIC_IPI_FAILURE_INVALID_TARGET,
	253	AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
	254	};
	255
	256
	257	/*
	258	* 0xff is broadcast, so the max index allowed for physical APIC ID
	259	* table is 0xfe. APIC IDs above 0xff are reserved.
	260	*/
	261	#define AVIC_MAX_PHYSICAL_ID_COUNT 0xff
	262
	263	#define AVIC_HPA_MASK ~((0xFFFULL << 52) \| 0xFFF)
	264	#define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
	265
	266
976bc5e2	267	struct vmcb_seg {
6aa8b732 AK	268	u16 selector;
	269	u16 attrib;
	270	u32 limit;
	271	u64 base;
976bc5e2	272	} __packed;
6aa8b732	273
3dd2775b	274	/* Save area definition for legacy and SEV-MEM guests */
976bc5e2	275	struct vmcb_save_area {
6aa8b732 AK	276	struct vmcb_seg es;
	277	struct vmcb_seg cs;
	278	struct vmcb_seg ss;
	279	struct vmcb_seg ds;
	280	struct vmcb_seg fs;
	281	struct vmcb_seg gs;
	282	struct vmcb_seg gdtr;
	283	struct vmcb_seg ldtr;
	284	struct vmcb_seg idtr;
	285	struct vmcb_seg tr;
046f773b BS	286	u8 reserved_1[42];
046f773b BS	287	u8 vmpl;
6aa8b732 AK	288	u8 cpl;
	289	u8 reserved_2[4];
	290	u64 efer;
3dd2775b TL	291	u8 reserved_3[112];
	292	u64 cr4;
	293	u64 cr3;
	294	u64 cr0;
	295	u64 dr7;
	296	u64 dr6;
	297	u64 rflags;
	298	u64 rip;
	299	u8 reserved_4[88];
	300	u64 rsp;
	301	u64 s_cet;
	302	u64 ssp;
	303	u64 isst_addr;
	304	u64 rax;
	305	u64 star;
	306	u64 lstar;
	307	u64 cstar;
	308	u64 sfmask;
	309	u64 kernel_gs_base;
	310	u64 sysenter_cs;
	311	u64 sysenter_esp;
	312	u64 sysenter_eip;
	313	u64 cr2;
	314	u8 reserved_5[32];
	315	u64 g_pat;
	316	u64 dbgctl;
	317	u64 br_from;
	318	u64 br_to;
	319	u64 last_excp_from;
	320	u64 last_excp_to;
	321	u8 reserved_6[72];
	322	u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */
	323	} __packed;
	324
	325	/* Save area definition for SEV-ES and SEV-SNP guests */
	326	struct sev_es_save_area {
	327	struct vmcb_seg es;
	328	struct vmcb_seg cs;
	329	struct vmcb_seg ss;
	330	struct vmcb_seg ds;
	331	struct vmcb_seg fs;
	332	struct vmcb_seg gs;
	333	struct vmcb_seg gdtr;
	334	struct vmcb_seg ldtr;
	335	struct vmcb_seg idtr;
	336	struct vmcb_seg tr;
6d3b3d34 TL	337	u64 vmpl0_ssp;
	338	u64 vmpl1_ssp;
	339	u64 vmpl2_ssp;
	340	u64 vmpl3_ssp;
	341	u64 u_cet;
	342	u8 reserved_1[2];
	343	u8 vmpl;
3dd2775b TL	344	u8 cpl;
	345	u8 reserved_2[4];
	346	u64 efer;
86137773	347	u8 reserved_3[104];
3dd2775b	348	u64 xss;
6aa8b732 AK	349	u64 cr4;
	350	u64 cr3;
	351	u64 cr0;
	352	u64 dr7;
	353	u64 dr6;
	354	u64 rflags;
	355	u64 rip;
6d3b3d34 TL	356	u64 dr0;
	357	u64 dr1;
	358	u64 dr2;
	359	u64 dr3;
	360	u64 dr0_addr_mask;
	361	u64 dr1_addr_mask;
	362	u64 dr2_addr_mask;
	363	u64 dr3_addr_mask;
	364	u8 reserved_4[24];
6aa8b732	365	u64 rsp;
6d3b3d34 TL	366	u64 s_cet;
	367	u64 ssp;
	368	u64 isst_addr;
6aa8b732 AK	369	u64 rax;
	370	u64 star;
	371	u64 lstar;
	372	u64 cstar;
	373	u64 sfmask;
	374	u64 kernel_gs_base;
	375	u64 sysenter_cs;
	376	u64 sysenter_esp;
	377	u64 sysenter_eip;
	378	u64 cr2;
6d3b3d34	379	u8 reserved_5[32];
6aa8b732 AK	380	u64 g_pat;
	381	u64 dbgctl;
	382	u64 br_from;
	383	u64 br_to;
	384	u64 last_excp_from;
	385	u64 last_excp_to;
3dd2775b	386	u8 reserved_7[80];
86137773	387	u32 pkru;
6d3b3d34 TL	388	u8 reserved_8[20];
6d3b3d34 TL	389	u64 reserved_9; /* rax already available at 0x01f8 */
d07f46f9 TL	390	u64 rcx;
	391	u64 rdx;
	392	u64 rbx;
6d3b3d34	393	u64 reserved_10; /* rsp already available at 0x01d8 */
d07f46f9 TL	394	u64 rbp;
	395	u64 rsi;
	396	u64 rdi;
	397	u64 r8;
	398	u64 r9;
	399	u64 r10;
	400	u64 r11;
	401	u64 r12;
	402	u64 r13;
	403	u64 r14;
	404	u64 r15;
6d3b3d34 TL	405	u8 reserved_11[16];
	406	u64 guest_exit_info_1;
	407	u64 guest_exit_info_2;
	408	u64 guest_exit_int_info;
	409	u64 guest_nrip;
046f773b	410	u64 sev_features;
6d3b3d34 TL	411	u64 vintr_ctrl;
	412	u64 guest_exit_code;
	413	u64 virtual_tom;
	414	u64 tlb_id;
	415	u64 pcpu_id;
	416	u64 event_inj;
d07f46f9	417	u64 xcr0;
6d3b3d34 TL	418	u8 reserved_12[16];
	419
	420	/* Floating point area */
	421	u64 x87_dp;
	422	u32 mxcsr;
	423	u16 x87_ftw;
	424	u16 x87_fsw;
	425	u16 x87_fcw;
	426	u16 x87_fop;
	427	u16 x87_ds;
	428	u16 x87_cs;
	429	u64 x87_rip;
	430	u8 fpreg_x87[80];
	431	u8 fpreg_xmm[256];
	432	u8 fpreg_ymm[256];
976bc5e2	433	} __packed;
6aa8b732	434
a4690359 TL	435	struct ghcb_save_area {
	436	u8 reserved_1[203];
	437	u8 cpl;
	438	u8 reserved_2[116];
	439	u64 xss;
	440	u8 reserved_3[24];
	441	u64 dr7;
	442	u8 reserved_4[16];
	443	u64 rip;
	444	u8 reserved_5[88];
	445	u64 rsp;
	446	u8 reserved_6[24];
	447	u64 rax;
	448	u8 reserved_7[264];
	449	u64 rcx;
	450	u64 rdx;
	451	u64 rbx;
	452	u8 reserved_8[8];
	453	u64 rbp;
	454	u64 rsi;
	455	u64 rdi;
	456	u64 r8;
	457	u64 r9;
	458	u64 r10;
	459	u64 r11;
	460	u64 r12;
	461	u64 r13;
	462	u64 r14;
	463	u64 r15;
	464	u8 reserved_9[16];
	465	u64 sw_exit_code;
	466	u64 sw_exit_info_1;
	467	u64 sw_exit_info_2;
	468	u64 sw_scratch;
	469	u8 reserved_10[56];
	470	u64 xcr0;
	471	u8 valid_bitmap[16];
	472	u64 x87_state_gpa;
	473	} __packed;
	474
3dd2775b TL	475	#define GHCB_SHARED_BUF_SIZE 2032
3dd2775b TL	476
d07f46f9	477	struct ghcb {
a4690359 TL	478	struct ghcb_save_area save;
a4690359 TL	479	u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];
d07f46f9	480
3dd2775b	481	u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
d07f46f9 TL	482
	483	u8 reserved_1[10];
	484	u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
	485	u32 ghcb_usage;
	486	} __packed;
	487
	488
3dd2775b	489	#define EXPECTED_VMCB_SAVE_AREA_SIZE 740
a4690359	490	#define EXPECTED_GHCB_SAVE_AREA_SIZE 1032
6d3b3d34	491	#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648
59d21d67	492	#define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
d07f46f9	493	#define EXPECTED_GHCB_SIZE PAGE_SIZE
7923ef4f PB	494
	495	static inline void __unused_size_checks(void)
	496	{
d07f46f9	497	BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
a4690359	498	BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE);
3dd2775b	499	BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
d07f46f9 TL	500	BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
d07f46f9 TL	501	BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
7923ef4f PB	502	}
7923ef4f PB	503
976bc5e2	504	struct vmcb {
6aa8b732 AK	505	struct vmcb_control_area control;
6aa8b732 AK	506	struct vmcb_save_area save;
976bc5e2	507	} __packed;
6aa8b732	508
6aa8b732 AK	509	#define SVM_CPUID_FUNC 0x8000000a
6aa8b732 AK	510
6031a61c JR	511	#define SVM_VM_CR_SVM_DISABLE 4
6031a61c JR	512
6aa8b732 AK	513	#define SVM_SELECTOR_S_SHIFT 4
	514	#define SVM_SELECTOR_DPL_SHIFT 5
	515	#define SVM_SELECTOR_P_SHIFT 7
	516	#define SVM_SELECTOR_AVL_SHIFT 8
	517	#define SVM_SELECTOR_L_SHIFT 9
	518	#define SVM_SELECTOR_DB_SHIFT 10
	519	#define SVM_SELECTOR_G_SHIFT 11
	520
	521	#define SVM_SELECTOR_TYPE_MASK (0xf)
	522	#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
	523	#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
	524	#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
	525	#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
	526	#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
	527	#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
	528	#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
	529
	530	#define SVM_SELECTOR_WRITE_MASK (1 << 1)
	531	#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
	532	#define SVM_SELECTOR_CODE_MASK (1 << 3)
	533
6aa8b732 AK	534	#define SVM_EVTINJ_VEC_MASK 0xff
	535
	536	#define SVM_EVTINJ_TYPE_SHIFT 8
	537	#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
	538
	539	#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
	540	#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
	541	#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
	542	#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
	543
	544	#define SVM_EVTINJ_VALID (1 << 31)
	545	#define SVM_EVTINJ_VALID_ERR (1 << 11)
	546
	547	#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
64a7ec06	548	#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
6aa8b732 AK	549
	550	#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
	551	#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
	552	#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
	553	#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
	554
	555	#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
	556	#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
	557
37817f29 IE	558	#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
37817f29 IE	559	#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
e269fb21	560	#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
37817f29	561
7ff76d58 AP	562	#define SVM_EXITINFO_REG_MASK 0x0F
7ff76d58 AP	563
dc77270f	564	#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS \| X86_CR0_MP)
6aa8b732	565
3702c2f4 JR	566	/* GHCB Accessor functions */
	567
	568	#define GHCB_BITMAP_IDX(field) \
a4690359	569	(offsetof(struct ghcb_save_area, field) / sizeof(u64))
3702c2f4 JR	570
3702c2f4 JR	571	#define DEFINE_GHCB_ACCESSORS(field) \
6b91ec4a	572	static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
3702c2f4 JR	573	{ \
	574	return test_bit(GHCB_BITMAP_IDX(field), \
	575	(unsigned long *)&ghcb->save.valid_bitmap); \
	576	} \
	577	\
6b91ec4a	578	static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb) \
0f60bde1 TL	579	{ \
	580	return ghcb->save.field; \
	581	} \
	582	\
6b91ec4a	583	static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
0f60bde1 TL	584	{ \
	585	return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
	586	} \
	587	\
6b91ec4a	588	static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
3702c2f4 JR	589	{ \
	590	__set_bit(GHCB_BITMAP_IDX(field), \
	591	(unsigned long *)&ghcb->save.valid_bitmap); \
	592	ghcb->save.field = value; \
	593	}
	594
	595	DEFINE_GHCB_ACCESSORS(cpl)
	596	DEFINE_GHCB_ACCESSORS(rip)
	597	DEFINE_GHCB_ACCESSORS(rsp)
	598	DEFINE_GHCB_ACCESSORS(rax)
	599	DEFINE_GHCB_ACCESSORS(rcx)
	600	DEFINE_GHCB_ACCESSORS(rdx)
	601	DEFINE_GHCB_ACCESSORS(rbx)
	602	DEFINE_GHCB_ACCESSORS(rbp)
	603	DEFINE_GHCB_ACCESSORS(rsi)
	604	DEFINE_GHCB_ACCESSORS(rdi)
	605	DEFINE_GHCB_ACCESSORS(r8)
	606	DEFINE_GHCB_ACCESSORS(r9)
	607	DEFINE_GHCB_ACCESSORS(r10)
	608	DEFINE_GHCB_ACCESSORS(r11)
	609	DEFINE_GHCB_ACCESSORS(r12)
	610	DEFINE_GHCB_ACCESSORS(r13)
	611	DEFINE_GHCB_ACCESSORS(r14)
	612	DEFINE_GHCB_ACCESSORS(r15)
	613	DEFINE_GHCB_ACCESSORS(sw_exit_code)
	614	DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
	615	DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
	616	DEFINE_GHCB_ACCESSORS(sw_scratch)
	617	DEFINE_GHCB_ACCESSORS(xcr0)
	618
6aa8b732	619	#endif