[linux-block.git] / arch / x86 / include / asm / svm.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SVM_H
#define __SVM_H

#include <uapi/asm/svm.h>


enum {
	INTERCEPT_INTR,
	INTERCEPT_NMI,
	INTERCEPT_SMI,
	INTERCEPT_INIT,
	INTERCEPT_VINTR,
	INTERCEPT_SELECTIVE_CR0,
	INTERCEPT_STORE_IDTR,
	INTERCEPT_STORE_GDTR,
	INTERCEPT_STORE_LDTR,
	INTERCEPT_STORE_TR,
	INTERCEPT_LOAD_IDTR,
	INTERCEPT_LOAD_GDTR,
	INTERCEPT_LOAD_LDTR,
	INTERCEPT_LOAD_TR,
	INTERCEPT_RDTSC,
	INTERCEPT_RDPMC,
	INTERCEPT_PUSHF,
	INTERCEPT_POPF,
	INTERCEPT_CPUID,
	INTERCEPT_RSM,
	INTERCEPT_IRET,
	INTERCEPT_INTn,
	INTERCEPT_INVD,
	INTERCEPT_PAUSE,
	INTERCEPT_HLT,
	INTERCEPT_INVLPG,
	INTERCEPT_INVLPGA,
	INTERCEPT_IOIO_PROT,
	INTERCEPT_MSR_PROT,
	INTERCEPT_TASK_SWITCH,
	INTERCEPT_FERR_FREEZE,
	INTERCEPT_SHUTDOWN,
	INTERCEPT_VMRUN,
	INTERCEPT_VMMCALL,
	INTERCEPT_VMLOAD,
	INTERCEPT_VMSAVE,
	INTERCEPT_STGI,
	INTERCEPT_CLGI,
	INTERCEPT_SKINIT,
	INTERCEPT_RDTSCP,
	INTERCEPT_ICEBP,
	INTERCEPT_WBINVD,
	INTERCEPT_MONITOR,
	INTERCEPT_MWAIT,
	INTERCEPT_MWAIT_COND,
	INTERCEPT_XSETBV,
};


struct __attribute__ ((__packed__)) vmcb_control_area {
	u32 intercept_cr;
	u32 intercept_dr;
	u32 intercept_exceptions;
	u64 intercept;
	u8 reserved_1[42];
	u16 pause_filter_count;
	u64 iopm_base_pa;
	u64 msrpm_base_pa;
	u64 tsc_offset;
	u32 asid;
	u8 tlb_ctl;
	u8 reserved_2[3];
	u32 int_ctl;
	u32 int_vector;
	u32 int_state;
	u8 reserved_3[4];
	u32 exit_code;
	u32 exit_code_hi;
	u64 exit_info_1;
	u64 exit_info_2;
	u32 exit_int_info;
	u32 exit_int_info_err;
	u64 nested_ctl;
	u64 avic_vapic_bar;
	u8 reserved_4[8];
	u32 event_inj;
	u32 event_inj_err;
	u64 nested_cr3;
	u64 virt_ext;
	u32 clean;
	u32 reserved_5;
	u64 next_rip;
	u8 insn_len;
	u8 insn_bytes[15];
	u64 avic_backing_page;	/* Offset 0xe0 */
	u8 reserved_6[8];	/* Offset 0xe8 */
	u64 avic_logical_id;	/* Offset 0xf0 */
	u64 avic_physical_id;	/* Offset 0xf8 */
	u8 reserved_7[768];
};


#define TLB_CONTROL_DO_NOTHING 0
#define TLB_CONTROL_FLUSH_ALL_ASID 1
#define TLB_CONTROL_FLUSH_ASID 3
#define TLB_CONTROL_FLUSH_ASID_LOCAL 7

#define V_TPR_MASK 0x0f

#define V_IRQ_SHIFT 8
#define V_IRQ_MASK (1 << V_IRQ_SHIFT)

#define V_GIF_SHIFT 9
#define V_GIF_MASK (1 << V_GIF_SHIFT)

#define V_INTR_PRIO_SHIFT 16
#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)

#define V_IGN_TPR_SHIFT 20
#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)

#define V_INTR_MASKING_SHIFT 24
#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)

#define V_GIF_ENABLE_SHIFT 25
#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)

#define AVIC_ENABLE_SHIFT 31
#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)

#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)

#define SVM_INTERRUPT_SHADOW_MASK 1

#define SVM_IOIO_STR_SHIFT 2
#define SVM_IOIO_REP_SHIFT 3
#define SVM_IOIO_SIZE_SHIFT 4
#define SVM_IOIO_ASIZE_SHIFT 7

#define SVM_IOIO_TYPE_MASK 1
#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)

#define SVM_VM_CR_VALID_MASK	0x001fULL
#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
#define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL

struct __attribute__ ((__packed__)) vmcb_seg {
	u16 selector;
	u16 attrib;
	u32 limit;
	u64 base;
};

struct __attribute__ ((__packed__)) vmcb_save_area {
	struct vmcb_seg es;
	struct vmcb_seg cs;
	struct vmcb_seg ss;
	struct vmcb_seg ds;
	struct vmcb_seg fs;
	struct vmcb_seg gs;
	struct vmcb_seg gdtr;
	struct vmcb_seg ldtr;
	struct vmcb_seg idtr;
	struct vmcb_seg tr;
	u8 reserved_1[43];
	u8 cpl;
	u8 reserved_2[4];
	u64 efer;
	u8 reserved_3[112];
	u64 cr4;
	u64 cr3;
	u64 cr0;
	u64 dr7;
	u64 dr6;
	u64 rflags;
	u64 rip;
	u8 reserved_4[88];
	u64 rsp;
	u8 reserved_5[24];
	u64 rax;
	u64 star;
	u64 lstar;
	u64 cstar;
	u64 sfmask;
	u64 kernel_gs_base;
	u64 sysenter_cs;
	u64 sysenter_esp;
	u64 sysenter_eip;
	u64 cr2;
	u8 reserved_6[32];
	u64 g_pat;
	u64 dbgctl;
	u64 br_from;
	u64 br_to;
	u64 last_excp_from;
	u64 last_excp_to;
};

struct __attribute__ ((__packed__)) vmcb {
	struct vmcb_control_area control;
	struct vmcb_save_area save;
};

#define SVM_CPUID_FUNC 0x8000000a

#define SVM_VM_CR_SVM_DISABLE 4

#define SVM_SELECTOR_S_SHIFT 4
#define SVM_SELECTOR_DPL_SHIFT 5
#define SVM_SELECTOR_P_SHIFT 7
#define SVM_SELECTOR_AVL_SHIFT 8
#define SVM_SELECTOR_L_SHIFT 9
#define SVM_SELECTOR_DB_SHIFT 10
#define SVM_SELECTOR_G_SHIFT 11

#define SVM_SELECTOR_TYPE_MASK (0xf)
#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)

#define SVM_SELECTOR_WRITE_MASK (1 << 1)
#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
#define SVM_SELECTOR_CODE_MASK (1 << 3)

#define INTERCEPT_CR0_READ	0
#define INTERCEPT_CR3_READ	3
#define INTERCEPT_CR4_READ	4
#define INTERCEPT_CR8_READ	8
#define INTERCEPT_CR0_WRITE	(16 + 0)
#define INTERCEPT_CR3_WRITE	(16 + 3)
#define INTERCEPT_CR4_WRITE	(16 + 4)
#define INTERCEPT_CR8_WRITE	(16 + 8)

#define INTERCEPT_DR0_READ	0
#define INTERCEPT_DR1_READ	1
#define INTERCEPT_DR2_READ	2
#define INTERCEPT_DR3_READ	3
#define INTERCEPT_DR4_READ	4
#define INTERCEPT_DR5_READ	5
#define INTERCEPT_DR6_READ	6
#define INTERCEPT_DR7_READ	7
#define INTERCEPT_DR0_WRITE	(16 + 0)
#define INTERCEPT_DR1_WRITE	(16 + 1)
#define INTERCEPT_DR2_WRITE	(16 + 2)
#define INTERCEPT_DR3_WRITE	(16 + 3)
#define INTERCEPT_DR4_WRITE	(16 + 4)
#define INTERCEPT_DR5_WRITE	(16 + 5)
#define INTERCEPT_DR6_WRITE	(16 + 6)
#define INTERCEPT_DR7_WRITE	(16 + 7)

#define SVM_EVTINJ_VEC_MASK 0xff

#define SVM_EVTINJ_TYPE_SHIFT 8
#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)

#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)

#define SVM_EVTINJ_VALID (1 << 31)
#define SVM_EVTINJ_VALID_ERR (1 << 11)

#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK

#define	SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
#define	SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
#define	SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
#define	SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT

#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR

#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44

#define SVM_EXITINFO_REG_MASK 0x0F

#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)

#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
#define SVM_VMRUN  ".byte 0x0f, 0x01, 0xd8"
#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
#define SVM_CLGI   ".byte 0x0f, 0x01, 0xdd"
#define SVM_STGI   ".byte 0x0f, 0x01, 0xdc"
#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
6aa8b732 AK	2	#ifndef __SVM_H
	3	#define __SVM_H
	4
af170c50 DH	5	#include <uapi/asm/svm.h>
af170c50 DH	6
26bf264e	7
6aa8b732 AK	8	enum {
	9	INTERCEPT_INTR,
	10	INTERCEPT_NMI,
	11	INTERCEPT_SMI,
	12	INTERCEPT_INIT,
	13	INTERCEPT_VINTR,
	14	INTERCEPT_SELECTIVE_CR0,
	15	INTERCEPT_STORE_IDTR,
	16	INTERCEPT_STORE_GDTR,
	17	INTERCEPT_STORE_LDTR,
	18	INTERCEPT_STORE_TR,
	19	INTERCEPT_LOAD_IDTR,
	20	INTERCEPT_LOAD_GDTR,
	21	INTERCEPT_LOAD_LDTR,
	22	INTERCEPT_LOAD_TR,
	23	INTERCEPT_RDTSC,
	24	INTERCEPT_RDPMC,
	25	INTERCEPT_PUSHF,
	26	INTERCEPT_POPF,
	27	INTERCEPT_CPUID,
	28	INTERCEPT_RSM,
	29	INTERCEPT_IRET,
	30	INTERCEPT_INTn,
	31	INTERCEPT_INVD,
	32	INTERCEPT_PAUSE,
	33	INTERCEPT_HLT,
	34	INTERCEPT_INVLPG,
	35	INTERCEPT_INVLPGA,
	36	INTERCEPT_IOIO_PROT,
	37	INTERCEPT_MSR_PROT,
	38	INTERCEPT_TASK_SWITCH,
	39	INTERCEPT_FERR_FREEZE,
	40	INTERCEPT_SHUTDOWN,
	41	INTERCEPT_VMRUN,
	42	INTERCEPT_VMMCALL,
	43	INTERCEPT_VMLOAD,
	44	INTERCEPT_VMSAVE,
	45	INTERCEPT_STGI,
	46	INTERCEPT_CLGI,
	47	INTERCEPT_SKINIT,
	48	INTERCEPT_RDTSCP,
	49	INTERCEPT_ICEBP,
	50	INTERCEPT_WBINVD,
916ce236 JR	51	INTERCEPT_MONITOR,
	52	INTERCEPT_MWAIT,
	53	INTERCEPT_MWAIT_COND,
81dd35d4	54	INTERCEPT_XSETBV,
6aa8b732 AK	55	};
	56
	57
	58	struct __attribute__ ((__packed__)) vmcb_control_area {
4ee546b4	59	u32 intercept_cr;
3aed041a	60	u32 intercept_dr;
6aa8b732 AK	61	u32 intercept_exceptions;
6aa8b732 AK	62	u64 intercept;
565d0998 ML	63	u8 reserved_1[42];
565d0998 ML	64	u16 pause_filter_count;
6aa8b732 AK	65	u64 iopm_base_pa;
	66	u64 msrpm_base_pa;
	67	u64 tsc_offset;
	68	u32 asid;
	69	u8 tlb_ctl;
	70	u8 reserved_2[3];
	71	u32 int_ctl;
	72	u32 int_vector;
	73	u32 int_state;
	74	u8 reserved_3[4];
	75	u32 exit_code;
	76	u32 exit_code_hi;
	77	u64 exit_info_1;
	78	u64 exit_info_2;
	79	u32 exit_int_info;
	80	u32 exit_int_info_err;
	81	u64 nested_ctl;
3d5615e5 SS	82	u64 avic_vapic_bar;
3d5615e5 SS	83	u8 reserved_4[8];
6aa8b732 AK	84	u32 event_inj;
	85	u32 event_inj_err;
	86	u64 nested_cr3;
0dc92119	87	u64 virt_ext;
8d28fec4 RJ	88	u32 clean;
8d28fec4 RJ	89	u32 reserved_5;
6bc31bdc	90	u64 next_rip;
dc25e89e AP	91	u8 insn_len;
dc25e89e AP	92	u8 insn_bytes[15];
3d5615e5 SS	93	u64 avic_backing_page; /* Offset 0xe0 */
	94	u8 reserved_6[8]; /* Offset 0xe8 */
	95	u64 avic_logical_id; /* Offset 0xf0 */
	96	u64 avic_physical_id; /* Offset 0xf8 */
	97	u8 reserved_7[768];
6aa8b732 AK	98	};
	99
	100
	101	#define TLB_CONTROL_DO_NOTHING 0
	102	#define TLB_CONTROL_FLUSH_ALL_ASID 1
38e5e92f JR	103	#define TLB_CONTROL_FLUSH_ASID 3
38e5e92f JR	104	#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
6aa8b732 AK	105
	106	#define V_TPR_MASK 0x0f
	107
	108	#define V_IRQ_SHIFT 8
	109	#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
	110
640bd6e5 JN	111	#define V_GIF_SHIFT 9
	112	#define V_GIF_MASK (1 << V_GIF_SHIFT)
	113
6aa8b732 AK	114	#define V_INTR_PRIO_SHIFT 16
	115	#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
	116
	117	#define V_IGN_TPR_SHIFT 20
	118	#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
	119
	120	#define V_INTR_MASKING_SHIFT 24
	121	#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
	122
640bd6e5 JN	123	#define V_GIF_ENABLE_SHIFT 25
	124	#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
	125
44a95dae SS	126	#define AVIC_ENABLE_SHIFT 31
	127	#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
	128
8a77e909	129	#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
89c8a498	130	#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
8a77e909	131
6aa8b732 AK	132	#define SVM_INTERRUPT_SHADOW_MASK 1
	133
	134	#define SVM_IOIO_STR_SHIFT 2
	135	#define SVM_IOIO_REP_SHIFT 3
	136	#define SVM_IOIO_SIZE_SHIFT 4
	137	#define SVM_IOIO_ASIZE_SHIFT 7
	138
	139	#define SVM_IOIO_TYPE_MASK 1
	140	#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
	141	#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
	142	#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
	143	#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
	144
4a810181 JR	145	#define SVM_VM_CR_VALID_MASK 0x001fULL
	146	#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
	147	#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
	148
6aa8b732 AK	149	struct __attribute__ ((__packed__)) vmcb_seg {
	150	u16 selector;
	151	u16 attrib;
	152	u32 limit;
	153	u64 base;
	154	};
	155
	156	struct __attribute__ ((__packed__)) vmcb_save_area {
	157	struct vmcb_seg es;
	158	struct vmcb_seg cs;
	159	struct vmcb_seg ss;
	160	struct vmcb_seg ds;
	161	struct vmcb_seg fs;
	162	struct vmcb_seg gs;
	163	struct vmcb_seg gdtr;
	164	struct vmcb_seg ldtr;
	165	struct vmcb_seg idtr;
	166	struct vmcb_seg tr;
	167	u8 reserved_1[43];
	168	u8 cpl;
	169	u8 reserved_2[4];
	170	u64 efer;
	171	u8 reserved_3[112];
	172	u64 cr4;
	173	u64 cr3;
	174	u64 cr0;
	175	u64 dr7;
	176	u64 dr6;
	177	u64 rflags;
	178	u64 rip;
	179	u8 reserved_4[88];
	180	u64 rsp;
	181	u8 reserved_5[24];
	182	u64 rax;
	183	u64 star;
	184	u64 lstar;
	185	u64 cstar;
	186	u64 sfmask;
	187	u64 kernel_gs_base;
	188	u64 sysenter_cs;
	189	u64 sysenter_esp;
	190	u64 sysenter_eip;
	191	u64 cr2;
	192	u8 reserved_6[32];
	193	u64 g_pat;
	194	u64 dbgctl;
	195	u64 br_from;
	196	u64 br_to;
	197	u64 last_excp_from;
	198	u64 last_excp_to;
	199	};
	200
	201	struct __attribute__ ((__packed__)) vmcb {
	202	struct vmcb_control_area control;
	203	struct vmcb_save_area save;
	204	};
	205
6aa8b732 AK	206	#define SVM_CPUID_FUNC 0x8000000a
6aa8b732 AK	207
6031a61c JR	208	#define SVM_VM_CR_SVM_DISABLE 4
6031a61c JR	209
6aa8b732 AK	210	#define SVM_SELECTOR_S_SHIFT 4
	211	#define SVM_SELECTOR_DPL_SHIFT 5
	212	#define SVM_SELECTOR_P_SHIFT 7
	213	#define SVM_SELECTOR_AVL_SHIFT 8
	214	#define SVM_SELECTOR_L_SHIFT 9
	215	#define SVM_SELECTOR_DB_SHIFT 10
	216	#define SVM_SELECTOR_G_SHIFT 11
	217
	218	#define SVM_SELECTOR_TYPE_MASK (0xf)
	219	#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
	220	#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
	221	#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
	222	#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
	223	#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
	224	#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
	225	#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
	226
	227	#define SVM_SELECTOR_WRITE_MASK (1 << 1)
	228	#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
	229	#define SVM_SELECTOR_CODE_MASK (1 << 3)
	230
4ee546b4 RJ	231	#define INTERCEPT_CR0_READ 0
	232	#define INTERCEPT_CR3_READ 3
	233	#define INTERCEPT_CR4_READ 4
	234	#define INTERCEPT_CR8_READ 8
	235	#define INTERCEPT_CR0_WRITE (16 + 0)
	236	#define INTERCEPT_CR3_WRITE (16 + 3)
	237	#define INTERCEPT_CR4_WRITE (16 + 4)
	238	#define INTERCEPT_CR8_WRITE (16 + 8)
6aa8b732	239
3aed041a JR	240	#define INTERCEPT_DR0_READ 0
	241	#define INTERCEPT_DR1_READ 1
	242	#define INTERCEPT_DR2_READ 2
	243	#define INTERCEPT_DR3_READ 3
	244	#define INTERCEPT_DR4_READ 4
	245	#define INTERCEPT_DR5_READ 5
	246	#define INTERCEPT_DR6_READ 6
	247	#define INTERCEPT_DR7_READ 7
	248	#define INTERCEPT_DR0_WRITE (16 + 0)
	249	#define INTERCEPT_DR1_WRITE (16 + 1)
	250	#define INTERCEPT_DR2_WRITE (16 + 2)
	251	#define INTERCEPT_DR3_WRITE (16 + 3)
	252	#define INTERCEPT_DR4_WRITE (16 + 4)
	253	#define INTERCEPT_DR5_WRITE (16 + 5)
	254	#define INTERCEPT_DR6_WRITE (16 + 6)
	255	#define INTERCEPT_DR7_WRITE (16 + 7)
6aa8b732 AK	256
	257	#define SVM_EVTINJ_VEC_MASK 0xff
	258
	259	#define SVM_EVTINJ_TYPE_SHIFT 8
	260	#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
	261
	262	#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
	263	#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
	264	#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
	265	#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
	266
	267	#define SVM_EVTINJ_VALID (1 << 31)
	268	#define SVM_EVTINJ_VALID_ERR (1 << 11)
	269
	270	#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
64a7ec06	271	#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
6aa8b732 AK	272
	273	#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
	274	#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
	275	#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
	276	#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
	277
	278	#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
	279	#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
	280
37817f29 IE	281	#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
37817f29 IE	282	#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
e269fb21	283	#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
37817f29	284
7ff76d58 AP	285	#define SVM_EXITINFO_REG_MASK 0x0F
7ff76d58 AP	286
dc77270f	287	#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS \| X86_CR0_MP)
6aa8b732 AK	288
	289	#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
	290	#define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
	291	#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
	292	#define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
	293	#define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
	294	#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
	295
	296	#endif