Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
6aa8b732 AK |
2 | #ifndef __SVM_H |
3 | #define __SVM_H | |
4 | ||
af170c50 | 5 | #include <uapi/asm/svm.h> |
9780d51d | 6 | #include <uapi/asm/kvm.h> |
af170c50 | 7 | |
c45ad722 BM |
8 | /* |
9 | * 32-bit intercept words in the VMCB Control Area, starting | |
10 | * at Byte offset 000h. | |
11 | */ | |
12 | ||
13 | enum intercept_words { | |
03bfeeb9 | 14 | INTERCEPT_CR = 0, |
30abaa88 | 15 | INTERCEPT_DR, |
9780d51d | 16 | INTERCEPT_EXCEPTION, |
c62e2e94 BM |
17 | INTERCEPT_WORD3, |
18 | INTERCEPT_WORD4, | |
4c44e8d6 | 19 | INTERCEPT_WORD5, |
c45ad722 BM |
20 | MAX_INTERCEPT, |
21 | }; | |
26bf264e | 22 | |
03bfeeb9 BM |
23 | enum { |
24 | /* Byte offset 000h (word 0) */ | |
25 | INTERCEPT_CR0_READ = 0, | |
26 | INTERCEPT_CR3_READ = 3, | |
27 | INTERCEPT_CR4_READ = 4, | |
28 | INTERCEPT_CR8_READ = 8, | |
29 | INTERCEPT_CR0_WRITE = 16, | |
30 | INTERCEPT_CR3_WRITE = 16 + 3, | |
31 | INTERCEPT_CR4_WRITE = 16 + 4, | |
32 | INTERCEPT_CR8_WRITE = 16 + 8, | |
30abaa88 BM |
33 | /* Byte offset 004h (word 1) */ |
34 | INTERCEPT_DR0_READ = 32, | |
35 | INTERCEPT_DR1_READ, | |
36 | INTERCEPT_DR2_READ, | |
37 | INTERCEPT_DR3_READ, | |
38 | INTERCEPT_DR4_READ, | |
39 | INTERCEPT_DR5_READ, | |
40 | INTERCEPT_DR6_READ, | |
41 | INTERCEPT_DR7_READ, | |
42 | INTERCEPT_DR0_WRITE = 48, | |
43 | INTERCEPT_DR1_WRITE, | |
44 | INTERCEPT_DR2_WRITE, | |
45 | INTERCEPT_DR3_WRITE, | |
46 | INTERCEPT_DR4_WRITE, | |
47 | INTERCEPT_DR5_WRITE, | |
48 | INTERCEPT_DR6_WRITE, | |
49 | INTERCEPT_DR7_WRITE, | |
9780d51d BM |
50 | /* Byte offset 008h (word 2) */ |
51 | INTERCEPT_EXCEPTION_OFFSET = 64, | |
c62e2e94 BM |
52 | /* Byte offset 00Ch (word 3) */ |
53 | INTERCEPT_INTR = 96, | |
6aa8b732 AK |
54 | INTERCEPT_NMI, |
55 | INTERCEPT_SMI, | |
56 | INTERCEPT_INIT, | |
57 | INTERCEPT_VINTR, | |
58 | INTERCEPT_SELECTIVE_CR0, | |
59 | INTERCEPT_STORE_IDTR, | |
60 | INTERCEPT_STORE_GDTR, | |
61 | INTERCEPT_STORE_LDTR, | |
62 | INTERCEPT_STORE_TR, | |
63 | INTERCEPT_LOAD_IDTR, | |
64 | INTERCEPT_LOAD_GDTR, | |
65 | INTERCEPT_LOAD_LDTR, | |
66 | INTERCEPT_LOAD_TR, | |
67 | INTERCEPT_RDTSC, | |
68 | INTERCEPT_RDPMC, | |
69 | INTERCEPT_PUSHF, | |
70 | INTERCEPT_POPF, | |
71 | INTERCEPT_CPUID, | |
72 | INTERCEPT_RSM, | |
73 | INTERCEPT_IRET, | |
74 | INTERCEPT_INTn, | |
75 | INTERCEPT_INVD, | |
76 | INTERCEPT_PAUSE, | |
77 | INTERCEPT_HLT, | |
78 | INTERCEPT_INVLPG, | |
79 | INTERCEPT_INVLPGA, | |
80 | INTERCEPT_IOIO_PROT, | |
81 | INTERCEPT_MSR_PROT, | |
82 | INTERCEPT_TASK_SWITCH, | |
83 | INTERCEPT_FERR_FREEZE, | |
84 | INTERCEPT_SHUTDOWN, | |
c62e2e94 BM |
85 | /* Byte offset 010h (word 4) */ |
86 | INTERCEPT_VMRUN = 128, | |
6aa8b732 AK |
87 | INTERCEPT_VMMCALL, |
88 | INTERCEPT_VMLOAD, | |
89 | INTERCEPT_VMSAVE, | |
90 | INTERCEPT_STGI, | |
91 | INTERCEPT_CLGI, | |
92 | INTERCEPT_SKINIT, | |
93 | INTERCEPT_RDTSCP, | |
94 | INTERCEPT_ICEBP, | |
95 | INTERCEPT_WBINVD, | |
916ce236 JR |
96 | INTERCEPT_MONITOR, |
97 | INTERCEPT_MWAIT, | |
98 | INTERCEPT_MWAIT_COND, | |
81dd35d4 | 99 | INTERCEPT_XSETBV, |
0cb8410b | 100 | INTERCEPT_RDPRU, |
376c6d28 TL |
101 | TRAP_EFER_WRITE, |
102 | TRAP_CR0_WRITE, | |
103 | TRAP_CR1_WRITE, | |
104 | TRAP_CR2_WRITE, | |
105 | TRAP_CR3_WRITE, | |
106 | TRAP_CR4_WRITE, | |
107 | TRAP_CR5_WRITE, | |
108 | TRAP_CR6_WRITE, | |
109 | TRAP_CR7_WRITE, | |
110 | TRAP_CR8_WRITE, | |
4c44e8d6 BM |
111 | /* Byte offset 014h (word 5) */ |
112 | INTERCEPT_INVLPGB = 160, | |
113 | INTERCEPT_INVLPGB_ILLEGAL, | |
114 | INTERCEPT_INVPCID, | |
115 | INTERCEPT_MCOMMIT, | |
116 | INTERCEPT_TLBSYNC, | |
6aa8b732 AK |
117 | }; |
118 | ||
119 | ||
120 | struct __attribute__ ((__packed__)) vmcb_control_area { | |
c45ad722 | 121 | u32 intercepts[MAX_INTERCEPT]; |
c62e2e94 | 122 | u32 reserved_1[15 - MAX_INTERCEPT]; |
1d8fb44a | 123 | u16 pause_filter_thresh; |
565d0998 | 124 | u16 pause_filter_count; |
6aa8b732 AK |
125 | u64 iopm_base_pa; |
126 | u64 msrpm_base_pa; | |
127 | u64 tsc_offset; | |
128 | u32 asid; | |
129 | u8 tlb_ctl; | |
130 | u8 reserved_2[3]; | |
131 | u32 int_ctl; | |
132 | u32 int_vector; | |
133 | u32 int_state; | |
134 | u8 reserved_3[4]; | |
135 | u32 exit_code; | |
136 | u32 exit_code_hi; | |
137 | u64 exit_info_1; | |
138 | u64 exit_info_2; | |
139 | u32 exit_int_info; | |
140 | u32 exit_int_info_err; | |
141 | u64 nested_ctl; | |
3d5615e5 | 142 | u64 avic_vapic_bar; |
291bd20d | 143 | u64 ghcb_gpa; |
6aa8b732 AK |
144 | u32 event_inj; |
145 | u32 event_inj_err; | |
146 | u64 nested_cr3; | |
0dc92119 | 147 | u64 virt_ext; |
8d28fec4 RJ |
148 | u32 clean; |
149 | u32 reserved_5; | |
6bc31bdc | 150 | u64 next_rip; |
dc25e89e AP |
151 | u8 insn_len; |
152 | u8 insn_bytes[15]; | |
3d5615e5 SS |
153 | u64 avic_backing_page; /* Offset 0xe0 */ |
154 | u8 reserved_6[8]; /* Offset 0xe8 */ | |
155 | u64 avic_logical_id; /* Offset 0xf0 */ | |
156 | u64 avic_physical_id; /* Offset 0xf8 */ | |
376c6d28 TL |
157 | u8 reserved_7[8]; |
158 | u64 vmsa_pa; /* Used for an SEV-ES guest */ | |
59d21d67 VP |
159 | u8 reserved_8[720]; |
160 | /* | |
161 | * Offset 0x3e0, 32 bytes reserved | |
162 | * for use by hypervisor/software. | |
163 | */ | |
164 | u8 reserved_sw[32]; | |
6aa8b732 AK |
165 | }; |
166 | ||
167 | ||
168 | #define TLB_CONTROL_DO_NOTHING 0 | |
169 | #define TLB_CONTROL_FLUSH_ALL_ASID 1 | |
38e5e92f JR |
170 | #define TLB_CONTROL_FLUSH_ASID 3 |
171 | #define TLB_CONTROL_FLUSH_ASID_LOCAL 7 | |
6aa8b732 AK |
172 | |
173 | #define V_TPR_MASK 0x0f | |
174 | ||
175 | #define V_IRQ_SHIFT 8 | |
176 | #define V_IRQ_MASK (1 << V_IRQ_SHIFT) | |
177 | ||
640bd6e5 JN |
178 | #define V_GIF_SHIFT 9 |
179 | #define V_GIF_MASK (1 << V_GIF_SHIFT) | |
180 | ||
6aa8b732 AK |
181 | #define V_INTR_PRIO_SHIFT 16 |
182 | #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) | |
183 | ||
184 | #define V_IGN_TPR_SHIFT 20 | |
185 | #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) | |
186 | ||
0f923e07 ML |
187 | #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK) |
188 | ||
6aa8b732 AK |
189 | #define V_INTR_MASKING_SHIFT 24 |
190 | #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) | |
191 | ||
640bd6e5 JN |
192 | #define V_GIF_ENABLE_SHIFT 25 |
193 | #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT) | |
194 | ||
44a95dae SS |
195 | #define AVIC_ENABLE_SHIFT 31 |
196 | #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT) | |
197 | ||
8a77e909 | 198 | #define LBR_CTL_ENABLE_MASK BIT_ULL(0) |
89c8a498 | 199 | #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1) |
8a77e909 | 200 | |
f1c6366e TL |
201 | #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0) |
202 | #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1) | |
6aa8b732 AK |
203 | |
204 | #define SVM_IOIO_STR_SHIFT 2 | |
205 | #define SVM_IOIO_REP_SHIFT 3 | |
206 | #define SVM_IOIO_SIZE_SHIFT 4 | |
207 | #define SVM_IOIO_ASIZE_SHIFT 7 | |
208 | ||
209 | #define SVM_IOIO_TYPE_MASK 1 | |
210 | #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) | |
211 | #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) | |
212 | #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) | |
213 | #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) | |
214 | ||
4a810181 JR |
215 | #define SVM_VM_CR_VALID_MASK 0x001fULL |
216 | #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL | |
217 | #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL | |
218 | ||
cea3a19b | 219 | #define SVM_NESTED_CTL_NP_ENABLE BIT(0) |
ba7c3398 | 220 | #define SVM_NESTED_CTL_SEV_ENABLE BIT(1) |
376c6d28 | 221 | #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2) |
cea3a19b | 222 | |
39150352 | 223 | |
bb2aa78e ML |
224 | #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL |
225 | #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL | |
226 | #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL | |
227 | #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL | |
228 | ||
229 | ||
39150352 | 230 | /* AVIC */ |
0dacc3df | 231 | #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL) |
39150352 ML |
232 | #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 |
233 | #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) | |
234 | ||
4a204f78 | 235 | #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) |
39150352 ML |
236 | #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) |
237 | #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) | |
238 | #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) | |
0dacc3df | 239 | #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL) |
39150352 | 240 | |
0dacc3df ML |
241 | #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) |
242 | ||
243 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL | |
39150352 ML |
244 | |
245 | #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 | |
246 | #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 | |
247 | #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF | |
248 | ||
249 | enum avic_ipi_failure_cause { | |
250 | AVIC_IPI_FAILURE_INVALID_INT_TYPE, | |
251 | AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, | |
252 | AVIC_IPI_FAILURE_INVALID_TARGET, | |
253 | AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, | |
254 | }; | |
255 | ||
256 | ||
257 | /* | |
258 | * 0xff is broadcast, so the max index allowed for physical APIC ID | |
259 | * table is 0xfe. APIC IDs above 0xff are reserved. | |
260 | */ | |
261 | #define AVIC_MAX_PHYSICAL_ID_COUNT 0xff | |
262 | ||
263 | #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) | |
264 | #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL | |
265 | ||
266 | ||
976bc5e2 | 267 | struct vmcb_seg { |
6aa8b732 AK |
268 | u16 selector; |
269 | u16 attrib; | |
270 | u32 limit; | |
271 | u64 base; | |
976bc5e2 | 272 | } __packed; |
6aa8b732 | 273 | |
3dd2775b | 274 | /* Save area definition for legacy and SEV-MEM guests */ |
976bc5e2 | 275 | struct vmcb_save_area { |
6aa8b732 AK |
276 | struct vmcb_seg es; |
277 | struct vmcb_seg cs; | |
278 | struct vmcb_seg ss; | |
279 | struct vmcb_seg ds; | |
280 | struct vmcb_seg fs; | |
281 | struct vmcb_seg gs; | |
282 | struct vmcb_seg gdtr; | |
283 | struct vmcb_seg ldtr; | |
284 | struct vmcb_seg idtr; | |
285 | struct vmcb_seg tr; | |
046f773b BS |
286 | u8 reserved_1[42]; |
287 | u8 vmpl; | |
6aa8b732 AK |
288 | u8 cpl; |
289 | u8 reserved_2[4]; | |
290 | u64 efer; | |
3dd2775b TL |
291 | u8 reserved_3[112]; |
292 | u64 cr4; | |
293 | u64 cr3; | |
294 | u64 cr0; | |
295 | u64 dr7; | |
296 | u64 dr6; | |
297 | u64 rflags; | |
298 | u64 rip; | |
299 | u8 reserved_4[88]; | |
300 | u64 rsp; | |
301 | u64 s_cet; | |
302 | u64 ssp; | |
303 | u64 isst_addr; | |
304 | u64 rax; | |
305 | u64 star; | |
306 | u64 lstar; | |
307 | u64 cstar; | |
308 | u64 sfmask; | |
309 | u64 kernel_gs_base; | |
310 | u64 sysenter_cs; | |
311 | u64 sysenter_esp; | |
312 | u64 sysenter_eip; | |
313 | u64 cr2; | |
314 | u8 reserved_5[32]; | |
315 | u64 g_pat; | |
316 | u64 dbgctl; | |
317 | u64 br_from; | |
318 | u64 br_to; | |
319 | u64 last_excp_from; | |
320 | u64 last_excp_to; | |
321 | u8 reserved_6[72]; | |
322 | u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */ | |
323 | } __packed; | |
324 | ||
325 | /* Save area definition for SEV-ES and SEV-SNP guests */ | |
326 | struct sev_es_save_area { | |
327 | struct vmcb_seg es; | |
328 | struct vmcb_seg cs; | |
329 | struct vmcb_seg ss; | |
330 | struct vmcb_seg ds; | |
331 | struct vmcb_seg fs; | |
332 | struct vmcb_seg gs; | |
333 | struct vmcb_seg gdtr; | |
334 | struct vmcb_seg ldtr; | |
335 | struct vmcb_seg idtr; | |
336 | struct vmcb_seg tr; | |
337 | u8 reserved_1[43]; | |
338 | u8 cpl; | |
339 | u8 reserved_2[4]; | |
340 | u64 efer; | |
86137773 | 341 | u8 reserved_3[104]; |
3dd2775b | 342 | u64 xss; |
6aa8b732 AK |
343 | u64 cr4; |
344 | u64 cr3; | |
345 | u64 cr0; | |
346 | u64 dr7; | |
347 | u64 dr6; | |
348 | u64 rflags; | |
349 | u64 rip; | |
350 | u8 reserved_4[88]; | |
351 | u64 rsp; | |
352 | u8 reserved_5[24]; | |
353 | u64 rax; | |
354 | u64 star; | |
355 | u64 lstar; | |
356 | u64 cstar; | |
357 | u64 sfmask; | |
358 | u64 kernel_gs_base; | |
359 | u64 sysenter_cs; | |
360 | u64 sysenter_esp; | |
361 | u64 sysenter_eip; | |
362 | u64 cr2; | |
363 | u8 reserved_6[32]; | |
364 | u64 g_pat; | |
365 | u64 dbgctl; | |
366 | u64 br_from; | |
367 | u64 br_to; | |
368 | u64 last_excp_from; | |
369 | u64 last_excp_to; | |
3dd2775b | 370 | u8 reserved_7[80]; |
86137773 | 371 | u32 pkru; |
3dd2775b TL |
372 | u8 reserved_9[20]; |
373 | u64 reserved_10; /* rax already available at 0x01f8 */ | |
d07f46f9 TL |
374 | u64 rcx; |
375 | u64 rdx; | |
376 | u64 rbx; | |
3dd2775b | 377 | u64 reserved_11; /* rsp already available at 0x01d8 */ |
d07f46f9 TL |
378 | u64 rbp; |
379 | u64 rsi; | |
380 | u64 rdi; | |
381 | u64 r8; | |
382 | u64 r9; | |
383 | u64 r10; | |
384 | u64 r11; | |
385 | u64 r12; | |
386 | u64 r13; | |
387 | u64 r14; | |
388 | u64 r15; | |
3dd2775b | 389 | u8 reserved_12[16]; |
d07f46f9 TL |
390 | u64 sw_exit_code; |
391 | u64 sw_exit_info_1; | |
392 | u64 sw_exit_info_2; | |
393 | u64 sw_scratch; | |
046f773b | 394 | u64 sev_features; |
3dd2775b | 395 | u8 reserved_13[48]; |
d07f46f9 TL |
396 | u64 xcr0; |
397 | u8 valid_bitmap[16]; | |
398 | u64 x87_state_gpa; | |
976bc5e2 | 399 | } __packed; |
6aa8b732 | 400 | |
3dd2775b TL |
401 | #define GHCB_SHARED_BUF_SIZE 2032 |
402 | ||
d07f46f9 | 403 | struct ghcb { |
3dd2775b TL |
404 | struct sev_es_save_area save; |
405 | u8 reserved_save[2048 - sizeof(struct sev_es_save_area)]; | |
d07f46f9 | 406 | |
3dd2775b | 407 | u8 shared_buffer[GHCB_SHARED_BUF_SIZE]; |
d07f46f9 TL |
408 | |
409 | u8 reserved_1[10]; | |
410 | u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */ | |
411 | u32 ghcb_usage; | |
412 | } __packed; | |
413 | ||
414 | ||
3dd2775b TL |
415 | #define EXPECTED_VMCB_SAVE_AREA_SIZE 740 |
416 | #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1032 | |
59d21d67 | 417 | #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024 |
d07f46f9 | 418 | #define EXPECTED_GHCB_SIZE PAGE_SIZE |
7923ef4f PB |
419 | |
420 | static inline void __unused_size_checks(void) | |
421 | { | |
d07f46f9 | 422 | BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE); |
3dd2775b | 423 | BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE); |
d07f46f9 TL |
424 | BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE); |
425 | BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE); | |
7923ef4f PB |
426 | } |
427 | ||
976bc5e2 | 428 | struct vmcb { |
6aa8b732 AK |
429 | struct vmcb_control_area control; |
430 | struct vmcb_save_area save; | |
976bc5e2 | 431 | } __packed; |
6aa8b732 | 432 | |
6aa8b732 AK |
433 | #define SVM_CPUID_FUNC 0x8000000a |
434 | ||
6031a61c JR |
435 | #define SVM_VM_CR_SVM_DISABLE 4 |
436 | ||
6aa8b732 AK |
437 | #define SVM_SELECTOR_S_SHIFT 4 |
438 | #define SVM_SELECTOR_DPL_SHIFT 5 | |
439 | #define SVM_SELECTOR_P_SHIFT 7 | |
440 | #define SVM_SELECTOR_AVL_SHIFT 8 | |
441 | #define SVM_SELECTOR_L_SHIFT 9 | |
442 | #define SVM_SELECTOR_DB_SHIFT 10 | |
443 | #define SVM_SELECTOR_G_SHIFT 11 | |
444 | ||
445 | #define SVM_SELECTOR_TYPE_MASK (0xf) | |
446 | #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) | |
447 | #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) | |
448 | #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) | |
449 | #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) | |
450 | #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) | |
451 | #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) | |
452 | #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) | |
453 | ||
454 | #define SVM_SELECTOR_WRITE_MASK (1 << 1) | |
455 | #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK | |
456 | #define SVM_SELECTOR_CODE_MASK (1 << 3) | |
457 | ||
6aa8b732 AK |
458 | #define SVM_EVTINJ_VEC_MASK 0xff |
459 | ||
460 | #define SVM_EVTINJ_TYPE_SHIFT 8 | |
461 | #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) | |
462 | ||
463 | #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) | |
464 | #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) | |
465 | #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) | |
466 | #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) | |
467 | ||
468 | #define SVM_EVTINJ_VALID (1 << 31) | |
469 | #define SVM_EVTINJ_VALID_ERR (1 << 11) | |
470 | ||
471 | #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK | |
64a7ec06 | 472 | #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK |
6aa8b732 AK |
473 | |
474 | #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR | |
475 | #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI | |
476 | #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT | |
477 | #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT | |
478 | ||
479 | #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID | |
480 | #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR | |
481 | ||
37817f29 IE |
482 | #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 |
483 | #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 | |
e269fb21 | 484 | #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 |
37817f29 | 485 | |
7ff76d58 AP |
486 | #define SVM_EXITINFO_REG_MASK 0x0F |
487 | ||
dc77270f | 488 | #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) |
6aa8b732 | 489 | |
3702c2f4 JR |
490 | /* GHCB Accessor functions */ |
491 | ||
492 | #define GHCB_BITMAP_IDX(field) \ | |
3dd2775b | 493 | (offsetof(struct sev_es_save_area, field) / sizeof(u64)) |
3702c2f4 JR |
494 | |
495 | #define DEFINE_GHCB_ACCESSORS(field) \ | |
496 | static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \ | |
497 | { \ | |
498 | return test_bit(GHCB_BITMAP_IDX(field), \ | |
499 | (unsigned long *)&ghcb->save.valid_bitmap); \ | |
500 | } \ | |
501 | \ | |
0f60bde1 TL |
502 | static inline u64 ghcb_get_##field(struct ghcb *ghcb) \ |
503 | { \ | |
504 | return ghcb->save.field; \ | |
505 | } \ | |
506 | \ | |
507 | static inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \ | |
508 | { \ | |
509 | return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \ | |
510 | } \ | |
511 | \ | |
3702c2f4 JR |
512 | static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \ |
513 | { \ | |
514 | __set_bit(GHCB_BITMAP_IDX(field), \ | |
515 | (unsigned long *)&ghcb->save.valid_bitmap); \ | |
516 | ghcb->save.field = value; \ | |
517 | } | |
518 | ||
519 | DEFINE_GHCB_ACCESSORS(cpl) | |
520 | DEFINE_GHCB_ACCESSORS(rip) | |
521 | DEFINE_GHCB_ACCESSORS(rsp) | |
522 | DEFINE_GHCB_ACCESSORS(rax) | |
523 | DEFINE_GHCB_ACCESSORS(rcx) | |
524 | DEFINE_GHCB_ACCESSORS(rdx) | |
525 | DEFINE_GHCB_ACCESSORS(rbx) | |
526 | DEFINE_GHCB_ACCESSORS(rbp) | |
527 | DEFINE_GHCB_ACCESSORS(rsi) | |
528 | DEFINE_GHCB_ACCESSORS(rdi) | |
529 | DEFINE_GHCB_ACCESSORS(r8) | |
530 | DEFINE_GHCB_ACCESSORS(r9) | |
531 | DEFINE_GHCB_ACCESSORS(r10) | |
532 | DEFINE_GHCB_ACCESSORS(r11) | |
533 | DEFINE_GHCB_ACCESSORS(r12) | |
534 | DEFINE_GHCB_ACCESSORS(r13) | |
535 | DEFINE_GHCB_ACCESSORS(r14) | |
536 | DEFINE_GHCB_ACCESSORS(r15) | |
537 | DEFINE_GHCB_ACCESSORS(sw_exit_code) | |
538 | DEFINE_GHCB_ACCESSORS(sw_exit_info_1) | |
539 | DEFINE_GHCB_ACCESSORS(sw_exit_info_2) | |
540 | DEFINE_GHCB_ACCESSORS(sw_scratch) | |
541 | DEFINE_GHCB_ACCESSORS(xcr0) | |
542 | ||
6aa8b732 | 543 | #endif |