projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 28a27752 TG |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef _ASM_X86_SPECCTRL_H_ | |
| 3 | #define _ASM_X86_SPECCTRL_H_ | |
| 4 | ||
| 885f82bf | 5 | #include <linux/thread_info.h> |
| 28a27752 TG |
6 | #include <asm/nospec-branch.h> |
| 7 | ||
| 8 | /* | |
| 9 | * On VMENTER we must preserve whatever view of the SPEC_CTRL MSR | |
| 10 | * the guest has, while on VMEXIT we restore the host view. This | |
| 11 | * would be easier if SPEC_CTRL were architecturally maskable or | |
| 12 | * shadowable for guests but this is not (currently) the case. | |
| 13 | * Takes the guest view of SPEC_CTRL MSR as a parameter. | |
| 14 | */ | |
| 15 | extern void x86_spec_ctrl_set_guest(u64); | |
| 16 | extern void x86_spec_ctrl_restore_host(u64); | |
| 17 | ||
| 18 | /* AMD specific Speculative Store Bypass MSR data */ | |
| 19 | extern u64 x86_amd_ls_cfg_base; | |
| 20 | extern u64 x86_amd_ls_cfg_rds_mask; | |
| 21 | ||
| 885f82bf TG |
22 | /* The Intel SPEC CTRL MSR base value cache */ |
| 23 | extern u64 x86_spec_ctrl_base; | |
| 24 | ||
| 25 | static inline u64 rds_tif_to_spec_ctrl(u64 tifn) | |
| 26 | { | |
| 27 | BUILD_BUG_ON(TIF_RDS < SPEC_CTRL_RDS_SHIFT); | |
| 28 | return (tifn & _TIF_RDS) >> (TIF_RDS - SPEC_CTRL_RDS_SHIFT); | |
| 29 | } | |
| 30 | ||
| 31 | static inline u64 rds_tif_to_amd_ls_cfg(u64 tifn) | |
| 32 | { | |
| 33 | return (tifn & _TIF_RDS) ? x86_amd_ls_cfg_rds_mask : 0ULL; | |
| 34 | } | |
| 35 | ||
| 36 | extern void speculative_store_bypass_update(void); | |
| 37 | ||
| 28a27752 | 38 | #endif |