Commit | Line | Data |
---|---|---|
1965aae3 PA |
1 | #ifndef _ASM_X86_PROCESSOR_H |
2 | #define _ASM_X86_PROCESSOR_H | |
c758ecf6 | 3 | |
053de044 GOC |
4 | #include <asm/processor-flags.h> |
5 | ||
683e0253 GOC |
6 | /* Forward declaration, a strange C thing */ |
7 | struct task_struct; | |
8 | struct mm_struct; | |
9fda6a06 | 9 | struct vm86; |
683e0253 | 10 | |
2f66dcc9 GOC |
11 | #include <asm/math_emu.h> |
12 | #include <asm/segment.h> | |
2f66dcc9 | 13 | #include <asm/types.h> |
decb4c41 | 14 | #include <uapi/asm/sigcontext.h> |
2f66dcc9 | 15 | #include <asm/current.h> |
cd4d09ec | 16 | #include <asm/cpufeatures.h> |
2f66dcc9 | 17 | #include <asm/page.h> |
54321d94 | 18 | #include <asm/pgtable_types.h> |
5300db88 | 19 | #include <asm/percpu.h> |
2f66dcc9 GOC |
20 | #include <asm/msr.h> |
21 | #include <asm/desc_defs.h> | |
bd61643e | 22 | #include <asm/nops.h> |
f05e798a | 23 | #include <asm/special_insns.h> |
14b9675a | 24 | #include <asm/fpu/types.h> |
4d46a89e | 25 | |
2f66dcc9 | 26 | #include <linux/personality.h> |
5300db88 | 27 | #include <linux/cache.h> |
2f66dcc9 | 28 | #include <linux/threads.h> |
5cbc19a9 | 29 | #include <linux/math64.h> |
faa4602e | 30 | #include <linux/err.h> |
f05e798a DH |
31 | #include <linux/irqflags.h> |
32 | ||
33 | /* | |
34 | * We handle most unaligned accesses in hardware. On the other hand | |
35 | * unaligned DMA can be quite expensive on some Nehalem processors. | |
36 | * | |
37 | * Based on this we disable the IP header alignment in network drivers. | |
38 | */ | |
39 | #define NET_IP_ALIGN 0 | |
c72dcf83 | 40 | |
b332828c | 41 | #define HBP_NUM 4 |
0ccb8acc GOC |
42 | /* |
43 | * Default implementation of macro that returns current | |
44 | * instruction pointer ("program counter"). | |
45 | */ | |
46 | static inline void *current_text_addr(void) | |
47 | { | |
48 | void *pc; | |
4d46a89e IM |
49 | |
50 | asm volatile("mov $1f, %0; 1:":"=r" (pc)); | |
51 | ||
0ccb8acc GOC |
52 | return pc; |
53 | } | |
54 | ||
b8c1b8ea IM |
55 | /* |
56 | * These alignment constraints are for performance in the vSMP case, | |
57 | * but in the task_struct case we must also meet hardware imposed | |
58 | * alignment requirements of the FPU state: | |
59 | */ | |
dbcb4660 | 60 | #ifdef CONFIG_X86_VSMP |
4d46a89e IM |
61 | # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) |
62 | # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) | |
dbcb4660 | 63 | #else |
b8c1b8ea | 64 | # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state) |
4d46a89e | 65 | # define ARCH_MIN_MMSTRUCT_ALIGN 0 |
dbcb4660 GOC |
66 | #endif |
67 | ||
e0ba94f1 AS |
68 | enum tlb_infos { |
69 | ENTRIES, | |
70 | NR_INFO | |
71 | }; | |
72 | ||
73 | extern u16 __read_mostly tlb_lli_4k[NR_INFO]; | |
74 | extern u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
75 | extern u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
76 | extern u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
77 | extern u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
78 | extern u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 79 | extern u16 __read_mostly tlb_lld_1g[NR_INFO]; |
c4211f42 | 80 | |
5300db88 GOC |
81 | /* |
82 | * CPU type and hardware bug flags. Kept separately for each CPU. | |
83 | * Members of this structure are referenced in head.S, so think twice | |
84 | * before touching them. [mj] | |
85 | */ | |
86 | ||
87 | struct cpuinfo_x86 { | |
4d46a89e IM |
88 | __u8 x86; /* CPU family */ |
89 | __u8 x86_vendor; /* CPU vendor */ | |
90 | __u8 x86_model; | |
91 | __u8 x86_mask; | |
5300db88 | 92 | #ifdef CONFIG_X86_32 |
4d46a89e IM |
93 | char wp_works_ok; /* It doesn't on 386's */ |
94 | ||
95 | /* Problems on some 486Dx4's and old 386's: */ | |
4d46a89e | 96 | char rfu; |
4d46a89e | 97 | char pad0; |
60e019eb | 98 | char pad1; |
5300db88 | 99 | #else |
4d46a89e | 100 | /* Number of 4K pages in DTLB/ITLB combined(in pages): */ |
b1882e68 | 101 | int x86_tlbsize; |
13c6c532 | 102 | #endif |
4d46a89e IM |
103 | __u8 x86_virt_bits; |
104 | __u8 x86_phys_bits; | |
105 | /* CPUID returned core id bits: */ | |
106 | __u8 x86_coreid_bits; | |
107 | /* Max extended CPUID function supported: */ | |
108 | __u32 extended_cpuid_level; | |
4d46a89e IM |
109 | /* Maximum supported CPUID level, -1=no CPUID: */ |
110 | int cpuid_level; | |
65fc985b | 111 | __u32 x86_capability[NCAPINTS + NBUGINTS]; |
4d46a89e IM |
112 | char x86_vendor_id[16]; |
113 | char x86_model_id[64]; | |
114 | /* in KB - valid for CPUS which support this call: */ | |
115 | int x86_cache_size; | |
116 | int x86_cache_alignment; /* In bytes */ | |
cbc82b17 PWJ |
117 | /* Cache QoS architectural values: */ |
118 | int x86_cache_max_rmid; /* max index */ | |
119 | int x86_cache_occ_scale; /* scale to bytes */ | |
4d46a89e IM |
120 | int x86_power; |
121 | unsigned long loops_per_jiffy; | |
4d46a89e IM |
122 | /* cpuid returned max cores value: */ |
123 | u16 x86_max_cores; | |
124 | u16 apicid; | |
01aaea1a | 125 | u16 initial_apicid; |
4d46a89e | 126 | u16 x86_clflush_size; |
4d46a89e IM |
127 | /* number of cores as seen by the OS: */ |
128 | u16 booted_cores; | |
129 | /* Physical processor id: */ | |
130 | u16 phys_proc_id; | |
1f12e32f TG |
131 | /* Logical processor id: */ |
132 | u16 logical_proc_id; | |
4d46a89e IM |
133 | /* Core id: */ |
134 | u16 cpu_core_id; | |
135 | /* Index into per_cpu list: */ | |
136 | u16 cpu_index; | |
506ed6b5 | 137 | u32 microcode; |
2c773dd3 | 138 | }; |
5300db88 | 139 | |
47f10a36 HC |
140 | struct cpuid_regs { |
141 | u32 eax, ebx, ecx, edx; | |
142 | }; | |
143 | ||
144 | enum cpuid_regs_idx { | |
145 | CPUID_EAX = 0, | |
146 | CPUID_EBX, | |
147 | CPUID_ECX, | |
148 | CPUID_EDX, | |
149 | }; | |
150 | ||
4d46a89e IM |
151 | #define X86_VENDOR_INTEL 0 |
152 | #define X86_VENDOR_CYRIX 1 | |
153 | #define X86_VENDOR_AMD 2 | |
154 | #define X86_VENDOR_UMC 3 | |
4d46a89e IM |
155 | #define X86_VENDOR_CENTAUR 5 |
156 | #define X86_VENDOR_TRANSMETA 7 | |
157 | #define X86_VENDOR_NSC 8 | |
158 | #define X86_VENDOR_NUM 9 | |
159 | ||
160 | #define X86_VENDOR_UNKNOWN 0xff | |
5300db88 | 161 | |
1a53905a GOC |
162 | /* |
163 | * capabilities of CPUs | |
164 | */ | |
4d46a89e IM |
165 | extern struct cpuinfo_x86 boot_cpu_data; |
166 | extern struct cpuinfo_x86 new_cpu_data; | |
167 | ||
168 | extern struct tss_struct doublefault_tss; | |
3e0c3737 YL |
169 | extern __u32 cpu_caps_cleared[NCAPINTS]; |
170 | extern __u32 cpu_caps_set[NCAPINTS]; | |
5300db88 GOC |
171 | |
172 | #ifdef CONFIG_SMP | |
2c773dd3 | 173 | DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
5300db88 | 174 | #define cpu_data(cpu) per_cpu(cpu_info, cpu) |
5300db88 | 175 | #else |
7b543a53 | 176 | #define cpu_info boot_cpu_data |
5300db88 | 177 | #define cpu_data(cpu) boot_cpu_data |
5300db88 GOC |
178 | #endif |
179 | ||
1c6c727d JS |
180 | extern const struct seq_operations cpuinfo_op; |
181 | ||
4d46a89e IM |
182 | #define cache_line_size() (boot_cpu_data.x86_cache_alignment) |
183 | ||
184 | extern void cpu_detect(struct cpuinfo_x86 *c); | |
1a53905a | 185 | |
f580366f | 186 | extern void early_cpu_init(void); |
1a53905a GOC |
187 | extern void identify_boot_cpu(void); |
188 | extern void identify_secondary_cpu(struct cpuinfo_x86 *); | |
5300db88 | 189 | extern void print_cpu_info(struct cpuinfo_x86 *); |
21c3fcf3 | 190 | void print_cpu_msr(struct cpuinfo_x86 *); |
5300db88 | 191 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); |
47bdf337 HC |
192 | extern u32 get_scattered_cpuid_leaf(unsigned int level, |
193 | unsigned int sub_leaf, | |
194 | enum cpuid_regs_idx reg); | |
5300db88 | 195 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); |
04a15418 | 196 | extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); |
5300db88 | 197 | |
bbb65d2d | 198 | extern void detect_extended_topology(struct cpuinfo_x86 *c); |
1a53905a | 199 | extern void detect_ht(struct cpuinfo_x86 *c); |
1a53905a | 200 | |
d288e1cf FY |
201 | #ifdef CONFIG_X86_32 |
202 | extern int have_cpuid_p(void); | |
203 | #else | |
204 | static inline int have_cpuid_p(void) | |
205 | { | |
206 | return 1; | |
207 | } | |
208 | #endif | |
c758ecf6 | 209 | static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, |
4d46a89e | 210 | unsigned int *ecx, unsigned int *edx) |
c758ecf6 GOC |
211 | { |
212 | /* ecx is often an input as well as an output. */ | |
45a94d7c | 213 | asm volatile("cpuid" |
cca2e6f8 JP |
214 | : "=a" (*eax), |
215 | "=b" (*ebx), | |
216 | "=c" (*ecx), | |
217 | "=d" (*edx) | |
506ed6b5 AK |
218 | : "0" (*eax), "2" (*ecx) |
219 | : "memory"); | |
c758ecf6 GOC |
220 | } |
221 | ||
c72dcf83 GOC |
222 | static inline void load_cr3(pgd_t *pgdir) |
223 | { | |
224 | write_cr3(__pa(pgdir)); | |
225 | } | |
c758ecf6 | 226 | |
ca241c75 GOC |
227 | #ifdef CONFIG_X86_32 |
228 | /* This is the TSS defined by the hardware. */ | |
229 | struct x86_hw_tss { | |
4d46a89e IM |
230 | unsigned short back_link, __blh; |
231 | unsigned long sp0; | |
232 | unsigned short ss0, __ss0h; | |
cf9328cc | 233 | unsigned long sp1; |
76e4c490 AL |
234 | |
235 | /* | |
cf9328cc AL |
236 | * We don't use ring 1, so ss1 is a convenient scratch space in |
237 | * the same cacheline as sp0. We use ss1 to cache the value in | |
238 | * MSR_IA32_SYSENTER_CS. When we context switch | |
239 | * MSR_IA32_SYSENTER_CS, we first check if the new value being | |
240 | * written matches ss1, and, if it's not, then we wrmsr the new | |
241 | * value and update ss1. | |
76e4c490 | 242 | * |
cf9328cc AL |
243 | * The only reason we context switch MSR_IA32_SYSENTER_CS is |
244 | * that we set it to zero in vm86 tasks to avoid corrupting the | |
245 | * stack if we were to go through the sysenter path from vm86 | |
246 | * mode. | |
76e4c490 | 247 | */ |
76e4c490 AL |
248 | unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ |
249 | ||
250 | unsigned short __ss1h; | |
4d46a89e IM |
251 | unsigned long sp2; |
252 | unsigned short ss2, __ss2h; | |
253 | unsigned long __cr3; | |
254 | unsigned long ip; | |
255 | unsigned long flags; | |
256 | unsigned long ax; | |
257 | unsigned long cx; | |
258 | unsigned long dx; | |
259 | unsigned long bx; | |
260 | unsigned long sp; | |
261 | unsigned long bp; | |
262 | unsigned long si; | |
263 | unsigned long di; | |
264 | unsigned short es, __esh; | |
265 | unsigned short cs, __csh; | |
266 | unsigned short ss, __ssh; | |
267 | unsigned short ds, __dsh; | |
268 | unsigned short fs, __fsh; | |
269 | unsigned short gs, __gsh; | |
270 | unsigned short ldt, __ldth; | |
271 | unsigned short trace; | |
272 | unsigned short io_bitmap_base; | |
273 | ||
ca241c75 GOC |
274 | } __attribute__((packed)); |
275 | #else | |
276 | struct x86_hw_tss { | |
4d46a89e IM |
277 | u32 reserved1; |
278 | u64 sp0; | |
279 | u64 sp1; | |
280 | u64 sp2; | |
281 | u64 reserved2; | |
282 | u64 ist[7]; | |
283 | u32 reserved3; | |
284 | u32 reserved4; | |
285 | u16 reserved5; | |
286 | u16 io_bitmap_base; | |
287 | ||
ca241c75 GOC |
288 | } __attribute__((packed)) ____cacheline_aligned; |
289 | #endif | |
290 | ||
291 | /* | |
4d46a89e | 292 | * IO-bitmap sizes: |
ca241c75 | 293 | */ |
4d46a89e IM |
294 | #define IO_BITMAP_BITS 65536 |
295 | #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) | |
296 | #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) | |
297 | #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) | |
298 | #define INVALID_IO_BITMAP_OFFSET 0x8000 | |
ca241c75 GOC |
299 | |
300 | struct tss_struct { | |
4d46a89e IM |
301 | /* |
302 | * The hardware state: | |
303 | */ | |
304 | struct x86_hw_tss x86_tss; | |
ca241c75 GOC |
305 | |
306 | /* | |
307 | * The extra 1 is there because the CPU will access an | |
308 | * additional byte beyond the end of the IO permission | |
309 | * bitmap. The extra byte must be all 1 bits, and must | |
310 | * be within the limit. | |
311 | */ | |
4d46a89e | 312 | unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; |
4d46a89e | 313 | |
6dcc9414 | 314 | #ifdef CONFIG_X86_32 |
ca241c75 | 315 | /* |
2a41aa4f | 316 | * Space for the temporary SYSENTER stack. |
ca241c75 | 317 | */ |
2a41aa4f | 318 | unsigned long SYSENTER_stack_canary; |
d828c71f | 319 | unsigned long SYSENTER_stack[64]; |
6dcc9414 | 320 | #endif |
4d46a89e | 321 | |
84e65b0a | 322 | } ____cacheline_aligned; |
ca241c75 | 323 | |
24933b82 | 324 | DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); |
ca241c75 | 325 | |
a7fcf28d AL |
326 | #ifdef CONFIG_X86_32 |
327 | DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); | |
328 | #endif | |
329 | ||
4d46a89e IM |
330 | /* |
331 | * Save the original ist values for checking stack pointers during debugging | |
332 | */ | |
1a53905a | 333 | struct orig_ist { |
4d46a89e | 334 | unsigned long ist[7]; |
1a53905a GOC |
335 | }; |
336 | ||
fe676203 | 337 | #ifdef CONFIG_X86_64 |
2f66dcc9 | 338 | DECLARE_PER_CPU(struct orig_ist, orig_ist); |
26f80bd6 | 339 | |
947e76cd BG |
340 | union irq_stack_union { |
341 | char irq_stack[IRQ_STACK_SIZE]; | |
342 | /* | |
343 | * GCC hardcodes the stack canary as %gs:40. Since the | |
344 | * irq_stack is the object at %gs:0, we reserve the bottom | |
345 | * 48 bytes of the irq stack for the canary. | |
346 | */ | |
347 | struct { | |
348 | char gs_base[40]; | |
349 | unsigned long stack_canary; | |
350 | }; | |
351 | }; | |
352 | ||
277d5b40 | 353 | DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; |
2add8e23 BG |
354 | DECLARE_INIT_PER_CPU(irq_stack_union); |
355 | ||
26f80bd6 | 356 | DECLARE_PER_CPU(char *, irq_stack_ptr); |
9766cdbc | 357 | DECLARE_PER_CPU(unsigned int, irq_count); |
9766cdbc | 358 | extern asmlinkage void ignore_sysret(void); |
60a5317f TH |
359 | #else /* X86_64 */ |
360 | #ifdef CONFIG_CC_STACKPROTECTOR | |
1ea0d14e JF |
361 | /* |
362 | * Make sure stack canary segment base is cached-aligned: | |
363 | * "For Intel Atom processors, avoid non zero segment base address | |
364 | * that is not aligned to cache line boundary at all cost." | |
365 | * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) | |
366 | */ | |
367 | struct stack_canary { | |
368 | char __pad[20]; /* canary at %gs:20 */ | |
369 | unsigned long canary; | |
370 | }; | |
53f82452 | 371 | DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
96a388de | 372 | #endif |
198d208d SR |
373 | /* |
374 | * per-CPU IRQ handling stacks | |
375 | */ | |
376 | struct irq_stack { | |
377 | u32 stack[THREAD_SIZE/sizeof(u32)]; | |
378 | } __aligned(THREAD_SIZE); | |
379 | ||
380 | DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); | |
381 | DECLARE_PER_CPU(struct irq_stack *, softirq_stack); | |
60a5317f | 382 | #endif /* X86_64 */ |
c758ecf6 | 383 | |
bf15a8cf | 384 | extern unsigned int fpu_kernel_xstate_size; |
a1141e0b | 385 | extern unsigned int fpu_user_xstate_size; |
683e0253 | 386 | |
24f1e32c FW |
387 | struct perf_event; |
388 | ||
13d4ea09 AL |
389 | typedef struct { |
390 | unsigned long seg; | |
391 | } mm_segment_t; | |
392 | ||
cb38d377 | 393 | struct thread_struct { |
4d46a89e IM |
394 | /* Cached TLS descriptors: */ |
395 | struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; | |
396 | unsigned long sp0; | |
397 | unsigned long sp; | |
cb38d377 | 398 | #ifdef CONFIG_X86_32 |
4d46a89e | 399 | unsigned long sysenter_cs; |
cb38d377 | 400 | #else |
4d46a89e IM |
401 | unsigned short es; |
402 | unsigned short ds; | |
403 | unsigned short fsindex; | |
404 | unsigned short gsindex; | |
cb38d377 | 405 | #endif |
b9d989c7 AL |
406 | |
407 | u32 status; /* thread synchronous flags */ | |
408 | ||
d756f4ad | 409 | #ifdef CONFIG_X86_64 |
296f781a AL |
410 | unsigned long fsbase; |
411 | unsigned long gsbase; | |
412 | #else | |
413 | /* | |
414 | * XXX: this could presumably be unsigned short. Alternatively, | |
415 | * 32-bit kernels could be taught to use fsindex instead. | |
416 | */ | |
417 | unsigned long fs; | |
418 | unsigned long gs; | |
d756f4ad | 419 | #endif |
c5bedc68 | 420 | |
24f1e32c FW |
421 | /* Save middle states of ptrace breakpoints */ |
422 | struct perf_event *ptrace_bps[HBP_NUM]; | |
423 | /* Debug status used for traps, single steps, etc... */ | |
424 | unsigned long debugreg6; | |
326264a0 FW |
425 | /* Keep track of the exact dr7 value set by the user */ |
426 | unsigned long ptrace_dr7; | |
4d46a89e IM |
427 | /* Fault info: */ |
428 | unsigned long cr2; | |
51e7dc70 | 429 | unsigned long trap_nr; |
4d46a89e | 430 | unsigned long error_code; |
9fda6a06 | 431 | #ifdef CONFIG_VM86 |
4d46a89e | 432 | /* Virtual 86 mode info */ |
9fda6a06 | 433 | struct vm86 *vm86; |
cb38d377 | 434 | #endif |
4d46a89e IM |
435 | /* IO permissions: */ |
436 | unsigned long *io_bitmap_ptr; | |
437 | unsigned long iopl; | |
438 | /* Max allowed port in the bitmap, in bytes: */ | |
439 | unsigned io_bitmap_max; | |
0c8c0f03 | 440 | |
13d4ea09 AL |
441 | mm_segment_t addr_limit; |
442 | ||
2a53ccbc | 443 | unsigned int sig_on_uaccess_err:1; |
dfa9a942 AL |
444 | unsigned int uaccess_err:1; /* uaccess failed */ |
445 | ||
0c8c0f03 DH |
446 | /* Floating point and extended processor state */ |
447 | struct fpu fpu; | |
448 | /* | |
449 | * WARNING: 'fpu' is dynamically-sized. It *MUST* be at | |
450 | * the end. | |
451 | */ | |
cb38d377 GOC |
452 | }; |
453 | ||
b9d989c7 AL |
454 | /* |
455 | * Thread-synchronous status. | |
456 | * | |
457 | * This is different from the flags in that nobody else | |
458 | * ever touches our thread-synchronous status, so we don't | |
459 | * have to worry about atomic accesses. | |
460 | */ | |
461 | #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/ | |
462 | ||
62d7d7ed GOC |
463 | /* |
464 | * Set IOPL bits in EFLAGS from given mask | |
465 | */ | |
466 | static inline void native_set_iopl_mask(unsigned mask) | |
467 | { | |
468 | #ifdef CONFIG_X86_32 | |
469 | unsigned int reg; | |
4d46a89e | 470 | |
cca2e6f8 JP |
471 | asm volatile ("pushfl;" |
472 | "popl %0;" | |
473 | "andl %1, %0;" | |
474 | "orl %2, %0;" | |
475 | "pushl %0;" | |
476 | "popfl" | |
477 | : "=&r" (reg) | |
478 | : "i" (~X86_EFLAGS_IOPL), "r" (mask)); | |
62d7d7ed GOC |
479 | #endif |
480 | } | |
481 | ||
4d46a89e IM |
482 | static inline void |
483 | native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) | |
7818a1e0 GOC |
484 | { |
485 | tss->x86_tss.sp0 = thread->sp0; | |
486 | #ifdef CONFIG_X86_32 | |
4d46a89e | 487 | /* Only happens when SEP is enabled, no need to test "SEP"arately: */ |
7818a1e0 GOC |
488 | if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { |
489 | tss->x86_tss.ss1 = thread->sysenter_cs; | |
490 | wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); | |
491 | } | |
492 | #endif | |
493 | } | |
1b46cbe0 | 494 | |
e801f864 GOC |
495 | static inline void native_swapgs(void) |
496 | { | |
497 | #ifdef CONFIG_X86_64 | |
498 | asm volatile("swapgs" ::: "memory"); | |
499 | #endif | |
500 | } | |
501 | ||
a7fcf28d | 502 | static inline unsigned long current_top_of_stack(void) |
8ef46a67 | 503 | { |
a7fcf28d | 504 | #ifdef CONFIG_X86_64 |
24933b82 | 505 | return this_cpu_read_stable(cpu_tss.x86_tss.sp0); |
a7fcf28d AL |
506 | #else |
507 | /* sp0 on x86_32 is special in and around vm86 mode. */ | |
508 | return this_cpu_read_stable(cpu_current_top_of_stack); | |
509 | #endif | |
8ef46a67 AL |
510 | } |
511 | ||
7818a1e0 GOC |
512 | #ifdef CONFIG_PARAVIRT |
513 | #include <asm/paravirt.h> | |
514 | #else | |
4d46a89e | 515 | #define __cpuid native_cpuid |
1b46cbe0 | 516 | |
cca2e6f8 JP |
517 | static inline void load_sp0(struct tss_struct *tss, |
518 | struct thread_struct *thread) | |
7818a1e0 GOC |
519 | { |
520 | native_load_sp0(tss, thread); | |
521 | } | |
522 | ||
62d7d7ed | 523 | #define set_iopl_mask native_set_iopl_mask |
1b46cbe0 GOC |
524 | #endif /* CONFIG_PARAVIRT */ |
525 | ||
683e0253 GOC |
526 | /* Free all resources held by a thread. */ |
527 | extern void release_thread(struct task_struct *); | |
528 | ||
683e0253 | 529 | unsigned long get_wchan(struct task_struct *p); |
c758ecf6 GOC |
530 | |
531 | /* | |
532 | * Generic CPUID function | |
533 | * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx | |
534 | * resulting in stale register contents being returned. | |
535 | */ | |
536 | static inline void cpuid(unsigned int op, | |
537 | unsigned int *eax, unsigned int *ebx, | |
538 | unsigned int *ecx, unsigned int *edx) | |
539 | { | |
540 | *eax = op; | |
541 | *ecx = 0; | |
542 | __cpuid(eax, ebx, ecx, edx); | |
543 | } | |
544 | ||
545 | /* Some CPUID calls want 'count' to be placed in ecx */ | |
546 | static inline void cpuid_count(unsigned int op, int count, | |
547 | unsigned int *eax, unsigned int *ebx, | |
548 | unsigned int *ecx, unsigned int *edx) | |
549 | { | |
550 | *eax = op; | |
551 | *ecx = count; | |
552 | __cpuid(eax, ebx, ecx, edx); | |
553 | } | |
554 | ||
555 | /* | |
556 | * CPUID functions returning a single datum | |
557 | */ | |
558 | static inline unsigned int cpuid_eax(unsigned int op) | |
559 | { | |
560 | unsigned int eax, ebx, ecx, edx; | |
561 | ||
562 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 563 | |
c758ecf6 GOC |
564 | return eax; |
565 | } | |
4d46a89e | 566 | |
c758ecf6 GOC |
567 | static inline unsigned int cpuid_ebx(unsigned int op) |
568 | { | |
569 | unsigned int eax, ebx, ecx, edx; | |
570 | ||
571 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 572 | |
c758ecf6 GOC |
573 | return ebx; |
574 | } | |
4d46a89e | 575 | |
c758ecf6 GOC |
576 | static inline unsigned int cpuid_ecx(unsigned int op) |
577 | { | |
578 | unsigned int eax, ebx, ecx, edx; | |
579 | ||
580 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 581 | |
c758ecf6 GOC |
582 | return ecx; |
583 | } | |
4d46a89e | 584 | |
c758ecf6 GOC |
585 | static inline unsigned int cpuid_edx(unsigned int op) |
586 | { | |
587 | unsigned int eax, ebx, ecx, edx; | |
588 | ||
589 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 590 | |
c758ecf6 GOC |
591 | return edx; |
592 | } | |
593 | ||
683e0253 | 594 | /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ |
0b101e62 | 595 | static __always_inline void rep_nop(void) |
683e0253 | 596 | { |
cca2e6f8 | 597 | asm volatile("rep; nop" ::: "memory"); |
683e0253 GOC |
598 | } |
599 | ||
0b101e62 | 600 | static __always_inline void cpu_relax(void) |
4d46a89e IM |
601 | { |
602 | rep_nop(); | |
603 | } | |
604 | ||
c198b121 AL |
605 | /* |
606 | * This function forces the icache and prefetched instruction stream to | |
607 | * catch up with reality in two very specific cases: | |
608 | * | |
609 | * a) Text was modified using one virtual address and is about to be executed | |
610 | * from the same physical page at a different virtual address. | |
611 | * | |
612 | * b) Text was modified on a different CPU, may subsequently be | |
613 | * executed on this CPU, and you want to make sure the new version | |
614 | * gets executed. This generally means you're calling this in a IPI. | |
615 | * | |
616 | * If you're calling this for a different reason, you're probably doing | |
617 | * it wrong. | |
618 | */ | |
683e0253 GOC |
619 | static inline void sync_core(void) |
620 | { | |
45c39fb0 | 621 | /* |
c198b121 AL |
622 | * There are quite a few ways to do this. IRET-to-self is nice |
623 | * because it works on every CPU, at any CPL (so it's compatible | |
624 | * with paravirtualization), and it never exits to a hypervisor. | |
625 | * The only down sides are that it's a bit slow (it seems to be | |
626 | * a bit more than 2x slower than the fastest options) and that | |
627 | * it unmasks NMIs. The "push %cs" is needed because, in | |
628 | * paravirtual environments, __KERNEL_CS may not be a valid CS | |
629 | * value when we do IRET directly. | |
630 | * | |
631 | * In case NMI unmasking or performance ever becomes a problem, | |
632 | * the next best option appears to be MOV-to-CR2 and an | |
633 | * unconditional jump. That sequence also works on all CPUs, | |
634 | * but it will fault at CPL3 (i.e. Xen PV and lguest). | |
635 | * | |
636 | * CPUID is the conventional way, but it's nasty: it doesn't | |
637 | * exist on some 486-like CPUs, and it usually exits to a | |
638 | * hypervisor. | |
639 | * | |
640 | * Like all of Linux's memory ordering operations, this is a | |
641 | * compiler barrier as well. | |
45c39fb0 | 642 | */ |
c198b121 AL |
643 | register void *__sp asm(_ASM_SP); |
644 | ||
645 | #ifdef CONFIG_X86_32 | |
646 | asm volatile ( | |
647 | "pushfl\n\t" | |
648 | "pushl %%cs\n\t" | |
649 | "pushl $1f\n\t" | |
650 | "iret\n\t" | |
651 | "1:" | |
652 | : "+r" (__sp) : : "memory"); | |
45c39fb0 | 653 | #else |
c198b121 AL |
654 | unsigned int tmp; |
655 | ||
656 | asm volatile ( | |
657 | "mov %%ss, %0\n\t" | |
658 | "pushq %q0\n\t" | |
659 | "pushq %%rsp\n\t" | |
660 | "addq $8, (%%rsp)\n\t" | |
661 | "pushfq\n\t" | |
662 | "mov %%cs, %0\n\t" | |
663 | "pushq %q0\n\t" | |
664 | "pushq $1f\n\t" | |
665 | "iretq\n\t" | |
666 | "1:" | |
667 | : "=&r" (tmp), "+r" (__sp) : : "cc", "memory"); | |
5367b688 | 668 | #endif |
683e0253 GOC |
669 | } |
670 | ||
683e0253 | 671 | extern void select_idle_routine(const struct cpuinfo_x86 *c); |
07c94a38 | 672 | extern void amd_e400_c1e_apic_setup(void); |
683e0253 | 673 | |
4d46a89e | 674 | extern unsigned long boot_option_idle_override; |
683e0253 | 675 | |
d1896049 | 676 | enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, |
69fb3676 | 677 | IDLE_POLL}; |
d1896049 | 678 | |
1a53905a GOC |
679 | extern void enable_sep_cpu(void); |
680 | extern int sysenter_setup(void); | |
681 | ||
29c84391 | 682 | extern void early_trap_init(void); |
8170e6be | 683 | void early_trap_pf_init(void); |
29c84391 | 684 | |
1a53905a | 685 | /* Defined in head.S */ |
4d46a89e | 686 | extern struct desc_ptr early_gdt_descr; |
1a53905a GOC |
687 | |
688 | extern void cpu_set_gdt(int); | |
552be871 | 689 | extern void switch_to_new_gdt(int); |
11e3a840 | 690 | extern void load_percpu_segment(int); |
1a53905a | 691 | extern void cpu_init(void); |
1a53905a | 692 | |
c2724775 MM |
693 | static inline unsigned long get_debugctlmsr(void) |
694 | { | |
ea8e61b7 | 695 | unsigned long debugctlmsr = 0; |
c2724775 MM |
696 | |
697 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
698 | if (boot_cpu_data.x86 < 6) | |
699 | return 0; | |
700 | #endif | |
701 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
702 | ||
ea8e61b7 | 703 | return debugctlmsr; |
c2724775 MM |
704 | } |
705 | ||
5b0e5084 JB |
706 | static inline void update_debugctlmsr(unsigned long debugctlmsr) |
707 | { | |
708 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
709 | if (boot_cpu_data.x86 < 6) | |
710 | return; | |
711 | #endif | |
712 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
713 | } | |
714 | ||
9bd1190a ON |
715 | extern void set_task_blockstep(struct task_struct *task, bool on); |
716 | ||
4d46a89e IM |
717 | /* Boot loader type from the setup header: */ |
718 | extern int bootloader_type; | |
5031296c | 719 | extern int bootloader_version; |
1a53905a | 720 | |
4d46a89e | 721 | extern char ignore_fpu_irq; |
683e0253 GOC |
722 | |
723 | #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 | |
724 | #define ARCH_HAS_PREFETCHW | |
725 | #define ARCH_HAS_SPINLOCK_PREFETCH | |
726 | ||
ae2e15eb | 727 | #ifdef CONFIG_X86_32 |
a930dc45 | 728 | # define BASE_PREFETCH "" |
4d46a89e | 729 | # define ARCH_HAS_PREFETCH |
ae2e15eb | 730 | #else |
a930dc45 | 731 | # define BASE_PREFETCH "prefetcht0 %P1" |
ae2e15eb GOC |
732 | #endif |
733 | ||
4d46a89e IM |
734 | /* |
735 | * Prefetch instructions for Pentium III (+) and AMD Athlon (+) | |
736 | * | |
737 | * It's not worth to care about 3dnow prefetches for the K6 | |
738 | * because they are microcoded there and very slow. | |
739 | */ | |
ae2e15eb GOC |
740 | static inline void prefetch(const void *x) |
741 | { | |
a930dc45 | 742 | alternative_input(BASE_PREFETCH, "prefetchnta %P1", |
ae2e15eb | 743 | X86_FEATURE_XMM, |
a930dc45 | 744 | "m" (*(const char *)x)); |
ae2e15eb GOC |
745 | } |
746 | ||
4d46a89e IM |
747 | /* |
748 | * 3dnow prefetch to get an exclusive cache line. | |
749 | * Useful for spinlocks to avoid one state transition in the | |
750 | * cache coherency protocol: | |
751 | */ | |
ae2e15eb GOC |
752 | static inline void prefetchw(const void *x) |
753 | { | |
a930dc45 BP |
754 | alternative_input(BASE_PREFETCH, "prefetchw %P1", |
755 | X86_FEATURE_3DNOWPREFETCH, | |
756 | "m" (*(const char *)x)); | |
ae2e15eb GOC |
757 | } |
758 | ||
4d46a89e IM |
759 | static inline void spin_lock_prefetch(const void *x) |
760 | { | |
761 | prefetchw(x); | |
762 | } | |
763 | ||
d9e05cc5 AL |
764 | #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ |
765 | TOP_OF_KERNEL_STACK_PADDING) | |
766 | ||
2f66dcc9 GOC |
767 | #ifdef CONFIG_X86_32 |
768 | /* | |
769 | * User space process size: 3GB (default). | |
770 | */ | |
4d46a89e | 771 | #define TASK_SIZE PAGE_OFFSET |
d9517346 | 772 | #define TASK_SIZE_MAX TASK_SIZE |
4d46a89e IM |
773 | #define STACK_TOP TASK_SIZE |
774 | #define STACK_TOP_MAX STACK_TOP | |
775 | ||
776 | #define INIT_THREAD { \ | |
d9e05cc5 | 777 | .sp0 = TOP_OF_INIT_STACK, \ |
4d46a89e IM |
778 | .sysenter_cs = __KERNEL_CS, \ |
779 | .io_bitmap_ptr = NULL, \ | |
13d4ea09 | 780 | .addr_limit = KERNEL_DS, \ |
2f66dcc9 GOC |
781 | } |
782 | ||
2f66dcc9 | 783 | /* |
5c39403e | 784 | * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. |
2f66dcc9 | 785 | * This is necessary to guarantee that the entire "struct pt_regs" |
b595076a | 786 | * is accessible even if the CPU haven't stored the SS/ESP registers |
2f66dcc9 GOC |
787 | * on the stack (interrupt gate does not save these registers |
788 | * when switching to the same priv ring). | |
789 | * Therefore beware: accessing the ss/esp fields of the | |
790 | * "struct pt_regs" is possible, but they may contain the | |
791 | * completely wrong values. | |
792 | */ | |
5c39403e DV |
793 | #define task_pt_regs(task) \ |
794 | ({ \ | |
795 | unsigned long __ptr = (unsigned long)task_stack_page(task); \ | |
796 | __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ | |
797 | ((struct pt_regs *)__ptr) - 1; \ | |
2f66dcc9 GOC |
798 | }) |
799 | ||
4d46a89e | 800 | #define KSTK_ESP(task) (task_pt_regs(task)->sp) |
2f66dcc9 GOC |
801 | |
802 | #else | |
803 | /* | |
07114f0f AL |
804 | * User space process size. 47bits minus one guard page. The guard |
805 | * page is necessary on Intel CPUs: if a SYSCALL instruction is at | |
806 | * the highest possible canonical userspace address, then that | |
807 | * syscall will enter the kernel with a non-canonical return | |
808 | * address, and SYSRET will explode dangerously. We avoid this | |
809 | * particular problem by preventing anything from being mapped | |
810 | * at the maximum canonical address. | |
2f66dcc9 | 811 | */ |
d9517346 | 812 | #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) |
2f66dcc9 GOC |
813 | |
814 | /* This decides where the kernel will search for a free chunk of vm | |
815 | * space during mmap's. | |
816 | */ | |
4d46a89e IM |
817 | #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ |
818 | 0xc0000000 : 0xFFFFe000) | |
2f66dcc9 | 819 | |
6bd33008 | 820 | #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ |
d9517346 | 821 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
6bd33008 | 822 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ |
d9517346 | 823 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
2f66dcc9 | 824 | |
922a70d3 | 825 | #define STACK_TOP TASK_SIZE |
d9517346 | 826 | #define STACK_TOP_MAX TASK_SIZE_MAX |
922a70d3 | 827 | |
13d4ea09 AL |
828 | #define INIT_THREAD { \ |
829 | .sp0 = TOP_OF_INIT_STACK, \ | |
830 | .addr_limit = KERNEL_DS, \ | |
2f66dcc9 GOC |
831 | } |
832 | ||
4d46a89e | 833 | #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) |
89240ba0 | 834 | extern unsigned long KSTK_ESP(struct task_struct *task); |
d046ff8b | 835 | |
2f66dcc9 GOC |
836 | #endif /* CONFIG_X86_64 */ |
837 | ||
ffcb043b BG |
838 | extern unsigned long thread_saved_pc(struct task_struct *tsk); |
839 | ||
513ad84b IM |
840 | extern void start_thread(struct pt_regs *regs, unsigned long new_ip, |
841 | unsigned long new_sp); | |
842 | ||
4d46a89e IM |
843 | /* |
844 | * This decides where the kernel will search for a free chunk of vm | |
683e0253 GOC |
845 | * space during mmap's. |
846 | */ | |
847 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) | |
848 | ||
4d46a89e | 849 | #define KSTK_EIP(task) (task_pt_regs(task)->ip) |
683e0253 | 850 | |
529e25f6 EB |
851 | /* Get/set a process' ability to use the timestamp counter instruction */ |
852 | #define GET_TSC_CTL(adr) get_tsc_mode((adr)) | |
853 | #define SET_TSC_CTL(val) set_tsc_mode((val)) | |
854 | ||
855 | extern int get_tsc_mode(unsigned long adr); | |
856 | extern int set_tsc_mode(unsigned int val); | |
857 | ||
fe3d197f | 858 | /* Register/unregister a process' MPX related resource */ |
46a6e0cf DH |
859 | #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() |
860 | #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() | |
fe3d197f DH |
861 | |
862 | #ifdef CONFIG_X86_INTEL_MPX | |
46a6e0cf DH |
863 | extern int mpx_enable_management(void); |
864 | extern int mpx_disable_management(void); | |
fe3d197f | 865 | #else |
46a6e0cf | 866 | static inline int mpx_enable_management(void) |
fe3d197f DH |
867 | { |
868 | return -EINVAL; | |
869 | } | |
46a6e0cf | 870 | static inline int mpx_disable_management(void) |
fe3d197f DH |
871 | { |
872 | return -EINVAL; | |
873 | } | |
874 | #endif /* CONFIG_X86_INTEL_MPX */ | |
875 | ||
8b84c8df | 876 | extern u16 amd_get_nb_id(int cpu); |
cc2749e4 | 877 | extern u32 amd_get_nodes_per_socket(void); |
6a812691 | 878 | |
96e39ac0 JW |
879 | static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) |
880 | { | |
881 | uint32_t base, eax, signature[3]; | |
882 | ||
883 | for (base = 0x40000000; base < 0x40010000; base += 0x100) { | |
884 | cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); | |
885 | ||
886 | if (!memcmp(sig, signature, 12) && | |
887 | (leaves == 0 || ((eax - base) >= leaves))) | |
888 | return base; | |
889 | } | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
f05e798a DH |
894 | extern unsigned long arch_align_stack(unsigned long sp); |
895 | extern void free_init_pages(char *what, unsigned long begin, unsigned long end); | |
896 | ||
897 | void default_idle(void); | |
6a377ddc LB |
898 | #ifdef CONFIG_XEN |
899 | bool xen_set_default_idle(void); | |
900 | #else | |
901 | #define xen_set_default_idle 0 | |
902 | #endif | |
f05e798a DH |
903 | |
904 | void stop_this_cpu(void *dummy); | |
4d067d8e | 905 | void df_debug(struct pt_regs *regs, long error_code); |
1965aae3 | 906 | #endif /* _ASM_X86_PROCESSOR_H */ |