Commit | Line | Data |
---|---|---|
a072738e CG |
1 | /* |
2 | * Netburst Perfomance Events (P4, old Xeon) | |
3 | */ | |
4 | ||
5 | #ifndef PERF_EVENT_P4_H | |
6 | #define PERF_EVENT_P4_H | |
7 | ||
8 | #include <linux/cpu.h> | |
9 | #include <linux/bitops.h> | |
10 | ||
11 | /* | |
12 | * NetBurst has perfomance MSRs shared between | |
13 | * threads if HT is turned on, ie for both logical | |
14 | * processors (mem: in turn in Atom with HT support | |
15 | * perf-MSRs are not shared and every thread has its | |
16 | * own perf-MSRs set) | |
17 | */ | |
d814f301 CG |
18 | #define ARCH_P4_TOTAL_ESCR (46) |
19 | #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ | |
20 | #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) | |
21 | #define ARCH_P4_MAX_CCCR (18) | |
d814f301 | 22 | |
047a3772 CG |
23 | #define ARCH_P4_CNTRVAL_BITS (40) |
24 | #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1) | |
7d44ec19 | 25 | #define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1)) |
047a3772 | 26 | |
d814f301 CG |
27 | #define P4_ESCR_EVENT_MASK 0x7e000000U |
28 | #define P4_ESCR_EVENT_SHIFT 25 | |
29 | #define P4_ESCR_EVENTMASK_MASK 0x01fffe00U | |
30 | #define P4_ESCR_EVENTMASK_SHIFT 9 | |
31 | #define P4_ESCR_TAG_MASK 0x000001e0U | |
32 | #define P4_ESCR_TAG_SHIFT 5 | |
33 | #define P4_ESCR_TAG_ENABLE 0x00000010U | |
34 | #define P4_ESCR_T0_OS 0x00000008U | |
35 | #define P4_ESCR_T0_USR 0x00000004U | |
36 | #define P4_ESCR_T1_OS 0x00000002U | |
37 | #define P4_ESCR_T1_USR 0x00000001U | |
38 | ||
39 | #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) | |
40 | #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) | |
41 | #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) | |
a072738e | 42 | |
a072738e CG |
43 | #define P4_CCCR_OVF 0x80000000U |
44 | #define P4_CCCR_CASCADE 0x40000000U | |
45 | #define P4_CCCR_OVF_PMI_T0 0x04000000U | |
46 | #define P4_CCCR_OVF_PMI_T1 0x08000000U | |
47 | #define P4_CCCR_FORCE_OVF 0x02000000U | |
48 | #define P4_CCCR_EDGE 0x01000000U | |
49 | #define P4_CCCR_THRESHOLD_MASK 0x00f00000U | |
50 | #define P4_CCCR_THRESHOLD_SHIFT 20 | |
a072738e CG |
51 | #define P4_CCCR_COMPLEMENT 0x00080000U |
52 | #define P4_CCCR_COMPARE 0x00040000U | |
53 | #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U | |
54 | #define P4_CCCR_ESCR_SELECT_SHIFT 13 | |
55 | #define P4_CCCR_ENABLE 0x00001000U | |
56 | #define P4_CCCR_THREAD_SINGLE 0x00010000U | |
57 | #define P4_CCCR_THREAD_BOTH 0x00020000U | |
58 | #define P4_CCCR_THREAD_ANY 0x00030000U | |
f34edbc1 | 59 | #define P4_CCCR_RESERVED 0x00000fffU |
a072738e | 60 | |
d814f301 CG |
61 | #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) |
62 | #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) | |
63 | ||
d814f301 CG |
64 | #define P4_GEN_ESCR_EMASK(class, name, bit) \ |
65 | class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) | |
66 | #define P4_ESCR_EMASK_BIT(class, name) class##__##name | |
a072738e CG |
67 | |
68 | /* | |
69 | * config field is 64bit width and consists of | |
70 | * HT << 63 | ESCR << 32 | CCCR | |
71 | * where HT is HyperThreading bit (since ESCR | |
72 | * has it reserved we may use it for own purpose) | |
73 | * | |
74 | * note that this is NOT the addresses of respective | |
75 | * ESCR and CCCR but rather an only packed value should | |
76 | * be unpacked and written to a proper addresses | |
77 | * | |
39ef13a4 | 78 | * the base idea is to pack as much info as possible |
a072738e CG |
79 | */ |
80 | #define p4_config_pack_escr(v) (((u64)(v)) << 32) | |
81 | #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) | |
82 | #define p4_config_unpack_escr(v) (((u64)(v)) >> 32) | |
d814f301 | 83 | #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) |
a072738e CG |
84 | |
85 | #define p4_config_unpack_emask(v) \ | |
86 | ({ \ | |
87 | u32 t = p4_config_unpack_escr((v)); \ | |
d814f301 CG |
88 | t = t & P4_ESCR_EVENTMASK_MASK; \ |
89 | t = t >> P4_ESCR_EVENTMASK_SHIFT; \ | |
90 | t; \ | |
91 | }) | |
92 | ||
93 | #define p4_config_unpack_event(v) \ | |
94 | ({ \ | |
95 | u32 t = p4_config_unpack_escr((v)); \ | |
96 | t = t & P4_ESCR_EVENT_MASK; \ | |
97 | t = t >> P4_ESCR_EVENT_SHIFT; \ | |
a072738e CG |
98 | t; \ |
99 | }) | |
100 | ||
101 | #define P4_CONFIG_HT_SHIFT 63 | |
102 | #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) | |
103 | ||
c9cf4a01 CG |
104 | /* |
105 | * The bits we allow to pass for RAW events | |
106 | */ | |
107 | #define P4_CONFIG_MASK_ESCR \ | |
108 | P4_ESCR_EVENT_MASK | \ | |
109 | P4_ESCR_EVENTMASK_MASK | \ | |
110 | P4_ESCR_TAG_MASK | \ | |
111 | P4_ESCR_TAG_ENABLE | |
112 | ||
113 | #define P4_CONFIG_MASK_CCCR \ | |
114 | P4_CCCR_EDGE | \ | |
115 | P4_CCCR_THRESHOLD_MASK | \ | |
116 | P4_CCCR_COMPLEMENT | \ | |
117 | P4_CCCR_COMPARE | \ | |
118 | P4_CCCR_THREAD_ANY | \ | |
119 | P4_CCCR_RESERVED | |
120 | ||
121 | /* some dangerous bits are reserved for kernel internals */ | |
122 | #define P4_CONFIG_MASK \ | |
123 | (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)) | \ | |
124 | (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR)) | |
125 | ||
a072738e CG |
126 | static inline bool p4_is_event_cascaded(u64 config) |
127 | { | |
128 | u32 cccr = p4_config_unpack_cccr(config); | |
129 | return !!(cccr & P4_CCCR_CASCADE); | |
130 | } | |
131 | ||
132 | static inline int p4_ht_config_thread(u64 config) | |
133 | { | |
134 | return !!(config & P4_CONFIG_HT); | |
135 | } | |
136 | ||
137 | static inline u64 p4_set_ht_bit(u64 config) | |
138 | { | |
139 | return config | P4_CONFIG_HT; | |
140 | } | |
141 | ||
142 | static inline u64 p4_clear_ht_bit(u64 config) | |
143 | { | |
144 | return config & ~P4_CONFIG_HT; | |
145 | } | |
146 | ||
147 | static inline int p4_ht_active(void) | |
148 | { | |
149 | #ifdef CONFIG_SMP | |
150 | return smp_num_siblings > 1; | |
151 | #endif | |
152 | return 0; | |
153 | } | |
154 | ||
155 | static inline int p4_ht_thread(int cpu) | |
156 | { | |
157 | #ifdef CONFIG_SMP | |
158 | if (smp_num_siblings == 2) | |
159 | return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); | |
160 | #endif | |
161 | return 0; | |
162 | } | |
163 | ||
164 | static inline int p4_should_swap_ts(u64 config, int cpu) | |
165 | { | |
166 | return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); | |
167 | } | |
168 | ||
169 | static inline u32 p4_default_cccr_conf(int cpu) | |
170 | { | |
171 | /* | |
172 | * Note that P4_CCCR_THREAD_ANY is "required" on | |
173 | * non-HT machines (on HT machines we count TS events | |
174 | * regardless the state of second logical processor | |
175 | */ | |
176 | u32 cccr = P4_CCCR_THREAD_ANY; | |
177 | ||
178 | if (!p4_ht_thread(cpu)) | |
179 | cccr |= P4_CCCR_OVF_PMI_T0; | |
180 | else | |
181 | cccr |= P4_CCCR_OVF_PMI_T1; | |
182 | ||
183 | return cccr; | |
184 | } | |
185 | ||
186 | static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) | |
187 | { | |
188 | u32 escr = 0; | |
189 | ||
190 | if (!p4_ht_thread(cpu)) { | |
191 | if (!exclude_os) | |
d814f301 | 192 | escr |= P4_ESCR_T0_OS; |
a072738e | 193 | if (!exclude_usr) |
d814f301 | 194 | escr |= P4_ESCR_T0_USR; |
a072738e CG |
195 | } else { |
196 | if (!exclude_os) | |
d814f301 | 197 | escr |= P4_ESCR_T1_OS; |
a072738e | 198 | if (!exclude_usr) |
d814f301 | 199 | escr |= P4_ESCR_T1_USR; |
a072738e CG |
200 | } |
201 | ||
202 | return escr; | |
203 | } | |
204 | ||
39ef13a4 CG |
205 | /* |
206 | * This are the events which should be used in "Event Select" | |
207 | * field of ESCR register, they are like unique keys which allow | |
208 | * the kernel to determinate which CCCR and COUNTER should be | |
209 | * used to track an event | |
210 | */ | |
d814f301 CG |
211 | enum P4_EVENTS { |
212 | P4_EVENT_TC_DELIVER_MODE, | |
213 | P4_EVENT_BPU_FETCH_REQUEST, | |
214 | P4_EVENT_ITLB_REFERENCE, | |
215 | P4_EVENT_MEMORY_CANCEL, | |
216 | P4_EVENT_MEMORY_COMPLETE, | |
217 | P4_EVENT_LOAD_PORT_REPLAY, | |
218 | P4_EVENT_STORE_PORT_REPLAY, | |
219 | P4_EVENT_MOB_LOAD_REPLAY, | |
220 | P4_EVENT_PAGE_WALK_TYPE, | |
221 | P4_EVENT_BSQ_CACHE_REFERENCE, | |
222 | P4_EVENT_IOQ_ALLOCATION, | |
223 | P4_EVENT_IOQ_ACTIVE_ENTRIES, | |
224 | P4_EVENT_FSB_DATA_ACTIVITY, | |
225 | P4_EVENT_BSQ_ALLOCATION, | |
226 | P4_EVENT_BSQ_ACTIVE_ENTRIES, | |
227 | P4_EVENT_SSE_INPUT_ASSIST, | |
228 | P4_EVENT_PACKED_SP_UOP, | |
229 | P4_EVENT_PACKED_DP_UOP, | |
230 | P4_EVENT_SCALAR_SP_UOP, | |
231 | P4_EVENT_SCALAR_DP_UOP, | |
232 | P4_EVENT_64BIT_MMX_UOP, | |
233 | P4_EVENT_128BIT_MMX_UOP, | |
234 | P4_EVENT_X87_FP_UOP, | |
235 | P4_EVENT_TC_MISC, | |
236 | P4_EVENT_GLOBAL_POWER_EVENTS, | |
237 | P4_EVENT_TC_MS_XFER, | |
238 | P4_EVENT_UOP_QUEUE_WRITES, | |
239 | P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, | |
240 | P4_EVENT_RETIRED_BRANCH_TYPE, | |
241 | P4_EVENT_RESOURCE_STALL, | |
242 | P4_EVENT_WC_BUFFER, | |
243 | P4_EVENT_B2B_CYCLES, | |
244 | P4_EVENT_BNR, | |
245 | P4_EVENT_SNOOP, | |
246 | P4_EVENT_RESPONSE, | |
247 | P4_EVENT_FRONT_END_EVENT, | |
248 | P4_EVENT_EXECUTION_EVENT, | |
249 | P4_EVENT_REPLAY_EVENT, | |
250 | P4_EVENT_INSTR_RETIRED, | |
251 | P4_EVENT_UOPS_RETIRED, | |
252 | P4_EVENT_UOP_TYPE, | |
253 | P4_EVENT_BRANCH_RETIRED, | |
254 | P4_EVENT_MISPRED_BRANCH_RETIRED, | |
255 | P4_EVENT_X87_ASSIST, | |
256 | P4_EVENT_MACHINE_CLEAR, | |
257 | P4_EVENT_INSTR_COMPLETED, | |
258 | }; | |
259 | ||
260 | #define P4_OPCODE(event) event##_OPCODE | |
261 | #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0) | |
262 | #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8) | |
263 | #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel) | |
264 | ||
a072738e CG |
265 | /* |
266 | * Comments below the event represent ESCR restriction | |
267 | * for this event and counter index per ESCR | |
268 | * | |
269 | * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early | |
270 | * processor builds (family 0FH, models 01H-02H). These MSRs | |
271 | * are not available on later versions, so that we don't use | |
272 | * them completely | |
273 | * | |
274 | * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly | |
275 | * working so that we should not use this CCCR and respective | |
276 | * counter as result | |
277 | */ | |
d814f301 CG |
278 | enum P4_EVENT_OPCODES { |
279 | P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), | |
a072738e CG |
280 | /* |
281 | * MSR_P4_TC_ESCR0: 4, 5 | |
282 | * MSR_P4_TC_ESCR1: 6, 7 | |
283 | */ | |
284 | ||
d814f301 | 285 | P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00), |
a072738e CG |
286 | /* |
287 | * MSR_P4_BPU_ESCR0: 0, 1 | |
288 | * MSR_P4_BPU_ESCR1: 2, 3 | |
289 | */ | |
290 | ||
d814f301 | 291 | P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03), |
a072738e CG |
292 | /* |
293 | * MSR_P4_ITLB_ESCR0: 0, 1 | |
294 | * MSR_P4_ITLB_ESCR1: 2, 3 | |
295 | */ | |
296 | ||
d814f301 | 297 | P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05), |
a072738e CG |
298 | /* |
299 | * MSR_P4_DAC_ESCR0: 8, 9 | |
300 | * MSR_P4_DAC_ESCR1: 10, 11 | |
301 | */ | |
302 | ||
d814f301 | 303 | P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02), |
a072738e CG |
304 | /* |
305 | * MSR_P4_SAAT_ESCR0: 8, 9 | |
306 | * MSR_P4_SAAT_ESCR1: 10, 11 | |
307 | */ | |
308 | ||
d814f301 | 309 | P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02), |
a072738e CG |
310 | /* |
311 | * MSR_P4_SAAT_ESCR0: 8, 9 | |
312 | * MSR_P4_SAAT_ESCR1: 10, 11 | |
313 | */ | |
314 | ||
d814f301 | 315 | P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02), |
a072738e CG |
316 | /* |
317 | * MSR_P4_SAAT_ESCR0: 8, 9 | |
318 | * MSR_P4_SAAT_ESCR1: 10, 11 | |
319 | */ | |
320 | ||
d814f301 | 321 | P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02), |
a072738e CG |
322 | /* |
323 | * MSR_P4_MOB_ESCR0: 0, 1 | |
324 | * MSR_P4_MOB_ESCR1: 2, 3 | |
325 | */ | |
326 | ||
d814f301 | 327 | P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04), |
a072738e CG |
328 | /* |
329 | * MSR_P4_PMH_ESCR0: 0, 1 | |
330 | * MSR_P4_PMH_ESCR1: 2, 3 | |
331 | */ | |
332 | ||
d814f301 | 333 | P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07), |
a072738e CG |
334 | /* |
335 | * MSR_P4_BSU_ESCR0: 0, 1 | |
336 | * MSR_P4_BSU_ESCR1: 2, 3 | |
337 | */ | |
338 | ||
d814f301 | 339 | P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06), |
a072738e CG |
340 | /* |
341 | * MSR_P4_FSB_ESCR0: 0, 1 | |
342 | * MSR_P4_FSB_ESCR1: 2, 3 | |
343 | */ | |
344 | ||
d814f301 | 345 | P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06), |
a072738e CG |
346 | /* |
347 | * MSR_P4_FSB_ESCR1: 2, 3 | |
348 | */ | |
349 | ||
d814f301 | 350 | P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06), |
a072738e CG |
351 | /* |
352 | * MSR_P4_FSB_ESCR0: 0, 1 | |
353 | * MSR_P4_FSB_ESCR1: 2, 3 | |
354 | */ | |
355 | ||
d814f301 | 356 | P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07), |
a072738e CG |
357 | /* |
358 | * MSR_P4_BSU_ESCR0: 0, 1 | |
359 | */ | |
360 | ||
d814f301 | 361 | P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07), |
a072738e | 362 | /* |
8ea7f544 | 363 | * NOTE: no ESCR name in docs, it's guessed |
a072738e CG |
364 | * MSR_P4_BSU_ESCR1: 2, 3 |
365 | */ | |
366 | ||
d814f301 | 367 | P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01), |
a072738e | 368 | /* |
e4495262 CG |
369 | * MSR_P4_FIRM_ESCR0: 8, 9 |
370 | * MSR_P4_FIRM_ESCR1: 10, 11 | |
a072738e CG |
371 | */ |
372 | ||
d814f301 | 373 | P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01), |
a072738e CG |
374 | /* |
375 | * MSR_P4_FIRM_ESCR0: 8, 9 | |
376 | * MSR_P4_FIRM_ESCR1: 10, 11 | |
377 | */ | |
378 | ||
d814f301 | 379 | P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01), |
a072738e CG |
380 | /* |
381 | * MSR_P4_FIRM_ESCR0: 8, 9 | |
382 | * MSR_P4_FIRM_ESCR1: 10, 11 | |
383 | */ | |
384 | ||
d814f301 | 385 | P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01), |
a072738e CG |
386 | /* |
387 | * MSR_P4_FIRM_ESCR0: 8, 9 | |
388 | * MSR_P4_FIRM_ESCR1: 10, 11 | |
389 | */ | |
390 | ||
d814f301 | 391 | P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01), |
a072738e CG |
392 | /* |
393 | * MSR_P4_FIRM_ESCR0: 8, 9 | |
394 | * MSR_P4_FIRM_ESCR1: 10, 11 | |
395 | */ | |
396 | ||
d814f301 | 397 | P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01), |
a072738e CG |
398 | /* |
399 | * MSR_P4_FIRM_ESCR0: 8, 9 | |
400 | * MSR_P4_FIRM_ESCR1: 10, 11 | |
401 | */ | |
402 | ||
d814f301 | 403 | P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01), |
a072738e CG |
404 | /* |
405 | * MSR_P4_FIRM_ESCR0: 8, 9 | |
406 | * MSR_P4_FIRM_ESCR1: 10, 11 | |
407 | */ | |
408 | ||
d814f301 | 409 | P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01), |
a072738e CG |
410 | /* |
411 | * MSR_P4_FIRM_ESCR0: 8, 9 | |
412 | * MSR_P4_FIRM_ESCR1: 10, 11 | |
413 | */ | |
414 | ||
d814f301 | 415 | P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01), |
a072738e CG |
416 | /* |
417 | * MSR_P4_TC_ESCR0: 4, 5 | |
418 | * MSR_P4_TC_ESCR1: 6, 7 | |
419 | */ | |
420 | ||
d814f301 | 421 | P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06), |
a072738e CG |
422 | /* |
423 | * MSR_P4_FSB_ESCR0: 0, 1 | |
424 | * MSR_P4_FSB_ESCR1: 2, 3 | |
425 | */ | |
426 | ||
d814f301 | 427 | P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00), |
a072738e CG |
428 | /* |
429 | * MSR_P4_MS_ESCR0: 4, 5 | |
430 | * MSR_P4_MS_ESCR1: 6, 7 | |
431 | */ | |
432 | ||
d814f301 | 433 | P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00), |
a072738e CG |
434 | /* |
435 | * MSR_P4_MS_ESCR0: 4, 5 | |
436 | * MSR_P4_MS_ESCR1: 6, 7 | |
437 | */ | |
438 | ||
d814f301 | 439 | P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02), |
a072738e CG |
440 | /* |
441 | * MSR_P4_TBPU_ESCR0: 4, 5 | |
9c8c6bad | 442 | * MSR_P4_TBPU_ESCR1: 6, 7 |
a072738e CG |
443 | */ |
444 | ||
d814f301 | 445 | P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02), |
a072738e CG |
446 | /* |
447 | * MSR_P4_TBPU_ESCR0: 4, 5 | |
9c8c6bad | 448 | * MSR_P4_TBPU_ESCR1: 6, 7 |
a072738e CG |
449 | */ |
450 | ||
d814f301 | 451 | P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01), |
a072738e CG |
452 | /* |
453 | * MSR_P4_ALF_ESCR0: 12, 13, 16 | |
454 | * MSR_P4_ALF_ESCR1: 14, 15, 17 | |
455 | */ | |
456 | ||
d814f301 | 457 | P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05), |
a072738e CG |
458 | /* |
459 | * MSR_P4_DAC_ESCR0: 8, 9 | |
460 | * MSR_P4_DAC_ESCR1: 10, 11 | |
461 | */ | |
462 | ||
d814f301 | 463 | P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03), |
a072738e CG |
464 | /* |
465 | * MSR_P4_FSB_ESCR0: 0, 1 | |
466 | * MSR_P4_FSB_ESCR1: 2, 3 | |
467 | */ | |
468 | ||
d814f301 | 469 | P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03), |
a072738e CG |
470 | /* |
471 | * MSR_P4_FSB_ESCR0: 0, 1 | |
472 | * MSR_P4_FSB_ESCR1: 2, 3 | |
473 | */ | |
474 | ||
d814f301 | 475 | P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03), |
a072738e CG |
476 | /* |
477 | * MSR_P4_FSB_ESCR0: 0, 1 | |
478 | * MSR_P4_FSB_ESCR1: 2, 3 | |
479 | */ | |
480 | ||
d814f301 | 481 | P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03), |
a072738e CG |
482 | /* |
483 | * MSR_P4_FSB_ESCR0: 0, 1 | |
484 | * MSR_P4_FSB_ESCR1: 2, 3 | |
485 | */ | |
486 | ||
d814f301 | 487 | P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05), |
a072738e CG |
488 | /* |
489 | * MSR_P4_CRU_ESCR2: 12, 13, 16 | |
490 | * MSR_P4_CRU_ESCR3: 14, 15, 17 | |
491 | */ | |
492 | ||
d814f301 | 493 | P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05), |
a072738e CG |
494 | /* |
495 | * MSR_P4_CRU_ESCR2: 12, 13, 16 | |
496 | * MSR_P4_CRU_ESCR3: 14, 15, 17 | |
497 | */ | |
498 | ||
d814f301 | 499 | P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05), |
a072738e CG |
500 | /* |
501 | * MSR_P4_CRU_ESCR2: 12, 13, 16 | |
502 | * MSR_P4_CRU_ESCR3: 14, 15, 17 | |
503 | */ | |
504 | ||
d814f301 | 505 | P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04), |
a072738e | 506 | /* |
e4495262 CG |
507 | * MSR_P4_CRU_ESCR0: 12, 13, 16 |
508 | * MSR_P4_CRU_ESCR1: 14, 15, 17 | |
a072738e CG |
509 | */ |
510 | ||
d814f301 | 511 | P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04), |
a072738e | 512 | /* |
8ea7f544 LM |
513 | * MSR_P4_CRU_ESCR0: 12, 13, 16 |
514 | * MSR_P4_CRU_ESCR1: 14, 15, 17 | |
a072738e CG |
515 | */ |
516 | ||
d814f301 | 517 | P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02), |
a072738e CG |
518 | /* |
519 | * MSR_P4_RAT_ESCR0: 12, 13, 16 | |
520 | * MSR_P4_RAT_ESCR1: 14, 15, 17 | |
521 | */ | |
522 | ||
d814f301 | 523 | P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05), |
a072738e CG |
524 | /* |
525 | * MSR_P4_CRU_ESCR2: 12, 13, 16 | |
526 | * MSR_P4_CRU_ESCR3: 14, 15, 17 | |
527 | */ | |
528 | ||
d814f301 | 529 | P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04), |
a072738e CG |
530 | /* |
531 | * MSR_P4_CRU_ESCR0: 12, 13, 16 | |
532 | * MSR_P4_CRU_ESCR1: 14, 15, 17 | |
533 | */ | |
534 | ||
d814f301 | 535 | P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05), |
a072738e CG |
536 | /* |
537 | * MSR_P4_CRU_ESCR2: 12, 13, 16 | |
538 | * MSR_P4_CRU_ESCR3: 14, 15, 17 | |
539 | */ | |
540 | ||
d814f301 | 541 | P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05), |
a072738e CG |
542 | /* |
543 | * MSR_P4_CRU_ESCR2: 12, 13, 16 | |
544 | * MSR_P4_CRU_ESCR3: 14, 15, 17 | |
545 | */ | |
546 | ||
d814f301 | 547 | P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04), |
a072738e CG |
548 | /* |
549 | * MSR_P4_CRU_ESCR0: 12, 13, 16 | |
550 | * MSR_P4_CRU_ESCR1: 14, 15, 17 | |
551 | */ | |
d814f301 | 552 | }; |
a072738e CG |
553 | |
554 | /* | |
d814f301 CG |
555 | * a caller should use P4_ESCR_EMASK_NAME helper to |
556 | * pick the EventMask needed, for example | |
a072738e | 557 | * |
39ef13a4 | 558 | * P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) |
a072738e | 559 | */ |
d814f301 CG |
560 | enum P4_ESCR_EMASKS { |
561 | P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0), | |
562 | P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1), | |
563 | P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2), | |
564 | P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3), | |
565 | P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4), | |
566 | P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5), | |
567 | P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6), | |
568 | ||
569 | P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0), | |
570 | ||
571 | P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0), | |
572 | P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1), | |
573 | P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2), | |
574 | ||
575 | P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2), | |
576 | P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3), | |
577 | ||
578 | P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0), | |
579 | P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1), | |
580 | ||
581 | P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1), | |
582 | ||
583 | P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1), | |
584 | ||
585 | P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1), | |
586 | P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3), | |
587 | P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), | |
588 | P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), | |
589 | ||
590 | P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0), | |
591 | P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1), | |
592 | ||
593 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), | |
594 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), | |
595 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), | |
596 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), | |
597 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), | |
598 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), | |
599 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), | |
600 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), | |
601 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), | |
602 | ||
603 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0), | |
604 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5), | |
605 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6), | |
606 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7), | |
607 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8), | |
608 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9), | |
609 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10), | |
610 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11), | |
611 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13), | |
612 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14), | |
613 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15), | |
614 | ||
615 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), | |
616 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), | |
617 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), | |
618 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), | |
619 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), | |
620 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), | |
621 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), | |
622 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), | |
623 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13), | |
624 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14), | |
625 | P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), | |
626 | ||
627 | P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0), | |
628 | P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1), | |
629 | P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), | |
630 | P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3), | |
631 | P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4), | |
632 | P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), | |
633 | ||
634 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0), | |
635 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1), | |
636 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2), | |
637 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3), | |
638 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5), | |
639 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), | |
640 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), | |
641 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), | |
642 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), | |
643 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), | |
644 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11), | |
645 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12), | |
646 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13), | |
647 | ||
648 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), | |
649 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), | |
650 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), | |
651 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), | |
652 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), | |
653 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), | |
654 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), | |
655 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), | |
656 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), | |
657 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), | |
658 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), | |
659 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), | |
660 | P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), | |
661 | ||
662 | P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15), | |
663 | ||
664 | P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15), | |
665 | ||
666 | P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15), | |
667 | ||
668 | P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15), | |
669 | ||
670 | P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15), | |
671 | ||
672 | P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15), | |
673 | ||
674 | P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15), | |
675 | ||
676 | P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15), | |
677 | ||
678 | P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4), | |
679 | ||
680 | P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0), | |
681 | ||
682 | P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0), | |
683 | ||
684 | P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), | |
685 | P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), | |
686 | P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2), | |
687 | ||
688 | P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), | |
689 | P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), | |
690 | P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), | |
691 | P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), | |
692 | ||
693 | P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), | |
694 | P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2), | |
695 | P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3), | |
696 | P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4), | |
697 | ||
698 | P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5), | |
699 | ||
700 | P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0), | |
701 | P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1), | |
702 | ||
703 | P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0), | |
704 | P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1), | |
705 | ||
706 | P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0), | |
707 | P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1), | |
708 | P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2), | |
709 | P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3), | |
710 | P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4), | |
711 | P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5), | |
712 | P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6), | |
713 | P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7), | |
714 | ||
715 | P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0), | |
716 | P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1), | |
717 | ||
718 | P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0), | |
719 | P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1), | |
720 | P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2), | |
721 | P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3), | |
722 | ||
723 | P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0), | |
724 | P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1), | |
a072738e | 725 | |
d814f301 CG |
726 | P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1), |
727 | P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2), | |
728 | ||
729 | P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0), | |
730 | P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1), | |
731 | P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2), | |
732 | P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3), | |
a072738e | 733 | |
d814f301 | 734 | P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0), |
a072738e | 735 | |
d814f301 CG |
736 | P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0), |
737 | P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1), | |
738 | P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2), | |
739 | P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3), | |
740 | P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4), | |
a072738e | 741 | |
d814f301 CG |
742 | P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0), |
743 | P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1), | |
744 | P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2), | |
a072738e | 745 | |
d814f301 CG |
746 | P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0), |
747 | P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1), | |
a072738e CG |
748 | }; |
749 | ||
39ef13a4 | 750 | /* |
39ef13a4 CG |
751 | * Note we have UOP and PEBS bits reserved for now |
752 | * just in case if we will need them once | |
753 | */ | |
754 | #define P4_PEBS_CONFIG_ENABLE (1 << 7) | |
755 | #define P4_PEBS_CONFIG_UOP_TAG (1 << 8) | |
756 | #define P4_PEBS_CONFIG_METRIC_MASK 0x3f | |
757 | #define P4_PEBS_CONFIG_MASK 0xff | |
758 | ||
759 | /* | |
760 | * mem: Only counters MSR_IQ_COUNTER4 (16) and | |
761 | * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling | |
762 | */ | |
763 | #define P4_PEBS_ENABLE 0x02000000U | |
764 | #define P4_PEBS_ENABLE_UOP_TAG 0x01000000U | |
765 | ||
766 | #define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK) | |
767 | #define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK) | |
768 | ||
769 | #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask)) | |
770 | ||
771 | enum P4_PEBS_METRIC { | |
772 | P4_PEBS_METRIC__none, | |
773 | ||
774 | P4_PEBS_METRIC__1stl_cache_load_miss_retired, | |
775 | P4_PEBS_METRIC__2ndl_cache_load_miss_retired, | |
776 | P4_PEBS_METRIC__dtlb_load_miss_retired, | |
777 | P4_PEBS_METRIC__dtlb_store_miss_retired, | |
778 | P4_PEBS_METRIC__dtlb_all_miss_retired, | |
779 | P4_PEBS_METRIC__tagged_mispred_branch, | |
780 | P4_PEBS_METRIC__mob_load_replay_retired, | |
781 | P4_PEBS_METRIC__split_load_retired, | |
782 | P4_PEBS_METRIC__split_store_retired, | |
783 | ||
784 | P4_PEBS_METRIC__max | |
cb7d6b50 LM |
785 | }; |
786 | ||
af86da53 CG |
787 | /* |
788 | * Notes on internal configuration of ESCR+CCCR tuples | |
789 | * | |
790 | * Since P4 has quite the different architecture of | |
791 | * performance registers in compare with "architectural" | |
792 | * once and we have on 64 bits to keep configuration | |
793 | * of performance event, the following trick is used. | |
794 | * | |
795 | * 1) Since both ESCR and CCCR registers have only low | |
796 | * 32 bits valuable, we pack them into a single 64 bit | |
797 | * configuration. Low 32 bits of such config correspond | |
798 | * to low 32 bits of CCCR register and high 32 bits | |
799 | * correspond to low 32 bits of ESCR register. | |
800 | * | |
801 | * 2) The meaning of every bit of such config field can | |
802 | * be found in Intel SDM but it should be noted that | |
803 | * we "borrow" some reserved bits for own usage and | |
804 | * clean them or set to a proper value when we do | |
805 | * a real write to hardware registers. | |
806 | * | |
807 | * 3) The format of bits of config is the following | |
808 | * and should be either 0 or set to some predefined | |
809 | * values: | |
810 | * | |
811 | * Low 32 bits | |
812 | * ----------- | |
813 | * 0-6: P4_PEBS_METRIC enum | |
814 | * 7-11: reserved | |
815 | * 12: reserved (Enable) | |
816 | * 13-15: reserved (ESCR select) | |
817 | * 16-17: Active Thread | |
818 | * 18: Compare | |
819 | * 19: Complement | |
820 | * 20-23: Threshold | |
821 | * 24: Edge | |
822 | * 25: reserved (FORCE_OVF) | |
823 | * 26: reserved (OVF_PMI_T0) | |
824 | * 27: reserved (OVF_PMI_T1) | |
825 | * 28-29: reserved | |
826 | * 30: reserved (Cascade) | |
827 | * 31: reserved (OVF) | |
828 | * | |
829 | * High 32 bits | |
830 | * ------------ | |
831 | * 0: reserved (T1_USR) | |
832 | * 1: reserved (T1_OS) | |
833 | * 2: reserved (T0_USR) | |
834 | * 3: reserved (T0_OS) | |
835 | * 4: Tag Enable | |
836 | * 5-8: Tag Value | |
837 | * 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper) | |
838 | * 25-30: enum P4_EVENTS | |
839 | * 31: reserved (HT thread) | |
840 | */ | |
841 | ||
a072738e | 842 | #endif /* PERF_EVENT_P4_H */ |
39ef13a4 | 843 |