Commit | Line | Data |
---|---|---|
cdd6c482 IM |
1 | #ifndef _ASM_X86_PERF_EVENT_H |
2 | #define _ASM_X86_PERF_EVENT_H | |
003a46cf | 3 | |
eb2b8618 | 4 | /* |
cdd6c482 | 5 | * Performance event hw details: |
eb2b8618 IM |
6 | */ |
7 | ||
8 | #define X86_PMC_MAX_GENERIC 8 | |
9 | #define X86_PMC_MAX_FIXED 3 | |
10 | ||
862a1a5f IM |
11 | #define X86_PMC_IDX_GENERIC 0 |
12 | #define X86_PMC_IDX_FIXED 32 | |
13 | #define X86_PMC_IDX_MAX 64 | |
14 | ||
241771ef IM |
15 | #define MSR_ARCH_PERFMON_PERFCTR0 0xc1 |
16 | #define MSR_ARCH_PERFMON_PERFCTR1 0xc2 | |
003a46cf | 17 | |
241771ef IM |
18 | #define MSR_ARCH_PERFMON_EVENTSEL0 0x186 |
19 | #define MSR_ARCH_PERFMON_EVENTSEL1 0x187 | |
003a46cf | 20 | |
241771ef | 21 | #define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22) |
b27d515a | 22 | #define ARCH_PERFMON_EVENTSEL_ANY (1 << 21) |
241771ef IM |
23 | #define ARCH_PERFMON_EVENTSEL_INT (1 << 20) |
24 | #define ARCH_PERFMON_EVENTSEL_OS (1 << 17) | |
25 | #define ARCH_PERFMON_EVENTSEL_USR (1 << 16) | |
003a46cf | 26 | |
2f18d1e8 IM |
27 | /* |
28 | * Includes eventsel and unit mask as well: | |
29 | */ | |
30 | #define ARCH_PERFMON_EVENT_MASK 0xffff | |
31 | ||
04a705df SE |
32 | /* |
33 | * filter mask to validate fixed counter events. | |
34 | * the following filters disqualify for fixed counters: | |
35 | * - inv | |
36 | * - edge | |
37 | * - cnt-mask | |
38 | * The other filters are supported by fixed counters. | |
39 | * The any-thread option is supported starting with v3. | |
40 | */ | |
41 | #define ARCH_PERFMON_EVENT_FILTER_MASK 0xff840000 | |
42 | ||
241771ef IM |
43 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c |
44 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) | |
04a705df | 45 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 |
003a46cf | 46 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ |
241771ef IM |
47 | (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) |
48 | ||
49 | #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 | |
003a46cf | 50 | |
eb2b8618 IM |
51 | /* |
52 | * Intel "Architectural Performance Monitoring" CPUID | |
53 | * detection/enumeration details: | |
54 | */ | |
003a46cf TG |
55 | union cpuid10_eax { |
56 | struct { | |
57 | unsigned int version_id:8; | |
cdd6c482 | 58 | unsigned int num_events:8; |
003a46cf TG |
59 | unsigned int bit_width:8; |
60 | unsigned int mask_length:8; | |
61 | } split; | |
62 | unsigned int full; | |
63 | }; | |
64 | ||
703e937c IM |
65 | union cpuid10_edx { |
66 | struct { | |
cdd6c482 | 67 | unsigned int num_events_fixed:4; |
703e937c IM |
68 | unsigned int reserved:28; |
69 | } split; | |
70 | unsigned int full; | |
71 | }; | |
72 | ||
73 | ||
74 | /* | |
cdd6c482 | 75 | * Fixed-purpose performance events: |
703e937c IM |
76 | */ |
77 | ||
862a1a5f IM |
78 | /* |
79 | * All 3 fixed-mode PMCs are configured via this single MSR: | |
80 | */ | |
81 | #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d | |
82 | ||
83 | /* | |
84 | * The counts are available in three separate MSRs: | |
85 | */ | |
86 | ||
703e937c IM |
87 | /* Instr_Retired.Any: */ |
88 | #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309 | |
2f18d1e8 | 89 | #define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0) |
703e937c IM |
90 | |
91 | /* CPU_CLK_Unhalted.Core: */ | |
92 | #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a | |
2f18d1e8 | 93 | #define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1) |
703e937c IM |
94 | |
95 | /* CPU_CLK_Unhalted.Ref: */ | |
96 | #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b | |
2f18d1e8 | 97 | #define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2) |
703e937c | 98 | |
30dd568c MM |
99 | /* |
100 | * We model BTS tracing as another fixed-mode PMC. | |
101 | * | |
cdd6c482 IM |
102 | * We choose a value in the middle of the fixed event range, since lower |
103 | * values are used by actual fixed events and higher values are used | |
30dd568c MM |
104 | * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. |
105 | */ | |
106 | #define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) | |
107 | ||
108 | ||
cdd6c482 IM |
109 | #ifdef CONFIG_PERF_EVENTS |
110 | extern void init_hw_perf_events(void); | |
111 | extern void perf_events_lapic_init(void); | |
194002b2 | 112 | |
cdd6c482 | 113 | #define PERF_EVENT_INDEX_OFFSET 0 |
194002b2 | 114 | |
241771ef | 115 | #else |
cdd6c482 IM |
116 | static inline void init_hw_perf_events(void) { } |
117 | static inline void perf_events_lapic_init(void) { } | |
241771ef IM |
118 | #endif |
119 | ||
cdd6c482 | 120 | #endif /* _ASM_X86_PERF_EVENT_H */ |