[linux-2.6-block.git] / arch / x86 / include / asm / perf_event.h

#ifndef _ASM_X86_PERF_EVENT_H
#define _ASM_X86_PERF_EVENT_H

/*
 * Performance event hw details:
 */

#define X86_PMC_MAX_GENERIC					8
#define X86_PMC_MAX_FIXED					3

#define X86_PMC_IDX_GENERIC				        0
#define X86_PMC_IDX_FIXED				       32
#define X86_PMC_IDX_MAX					       64

#define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
#define MSR_ARCH_PERFMON_PERFCTR1			      0xc2

#define MSR_ARCH_PERFMON_EVENTSEL0			     0x186
#define MSR_ARCH_PERFMON_EVENTSEL1			     0x187

#define ARCH_PERFMON_EVENTSEL0_ENABLE			  (1 << 22)
#define ARCH_PERFMON_EVENTSEL_INT			  (1 << 20)
#define ARCH_PERFMON_EVENTSEL_OS			  (1 << 17)
#define ARCH_PERFMON_EVENTSEL_USR			  (1 << 16)

/*
 * Includes eventsel and unit mask as well:
 */


#define INTEL_ARCH_EVTSEL_MASK		0x000000FFULL
#define INTEL_ARCH_UNIT_MASK		0x0000FF00ULL
#define INTEL_ARCH_EDGE_MASK		0x00040000ULL
#define INTEL_ARCH_INV_MASK		0x00800000ULL
#define INTEL_ARCH_CNT_MASK		0xFF000000ULL
#define INTEL_ARCH_EVENT_MASK	(INTEL_ARCH_UNIT_MASK|INTEL_ARCH_EVTSEL_MASK)

/*
 * filter mask to validate fixed counter events.
 * the following filters disqualify for fixed counters:
 *  - inv
 *  - edge
 *  - cnt-mask
 *  The other filters are supported by fixed counters.
 *  The any-thread option is supported starting with v3.
 */
#define INTEL_ARCH_FIXED_MASK \
	(INTEL_ARCH_CNT_MASK| \
	 INTEL_ARCH_INV_MASK| \
	 INTEL_ARCH_EDGE_MASK|\
	 INTEL_ARCH_UNIT_MASK|\
	 INTEL_ARCH_EVENT_MASK)

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		      0x3c
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX			 0
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
		(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))

#define ARCH_PERFMON_BRANCH_MISSES_RETIRED			 6

/*
 * Intel "Architectural Performance Monitoring" CPUID
 * detection/enumeration details:
 */
union cpuid10_eax {
	struct {
		unsigned int version_id:8;
		unsigned int num_events:8;
		unsigned int bit_width:8;
		unsigned int mask_length:8;
	} split;
	unsigned int full;
};

union cpuid10_edx {
	struct {
		unsigned int num_events_fixed:4;
		unsigned int reserved:28;
	} split;
	unsigned int full;
};


/*
 * Fixed-purpose performance events:
 */

/*
 * All 3 fixed-mode PMCs are configured via this single MSR:
 */
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL			0x38d

/*
 * The counts are available in three separate MSRs:
 */

/* Instr_Retired.Any: */
#define MSR_ARCH_PERFMON_FIXED_CTR0			0x309
#define X86_PMC_IDX_FIXED_INSTRUCTIONS			(X86_PMC_IDX_FIXED + 0)

/* CPU_CLK_Unhalted.Core: */
#define MSR_ARCH_PERFMON_FIXED_CTR1			0x30a
#define X86_PMC_IDX_FIXED_CPU_CYCLES			(X86_PMC_IDX_FIXED + 1)

/* CPU_CLK_Unhalted.Ref: */
#define MSR_ARCH_PERFMON_FIXED_CTR2			0x30b
#define X86_PMC_IDX_FIXED_BUS_CYCLES			(X86_PMC_IDX_FIXED + 2)

/*
 * We model BTS tracing as another fixed-mode PMC.
 *
 * We choose a value in the middle of the fixed event range, since lower
 * values are used by actual fixed events and higher values are used
 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 */
#define X86_PMC_IDX_FIXED_BTS				(X86_PMC_IDX_FIXED + 16)


#ifdef CONFIG_PERF_EVENTS
extern void init_hw_perf_events(void);
extern void perf_events_lapic_init(void);

#define PERF_EVENT_INDEX_OFFSET			0

#else
static inline void init_hw_perf_events(void)		{ }
static inline void perf_events_lapic_init(void)	{ }
#endif

#endif /* _ASM_X86_PERF_EVENT_H */
Commit	Line	Data
cdd6c482 IM	1	#ifndef _ASM_X86_PERF_EVENT_H
cdd6c482 IM	2	#define _ASM_X86_PERF_EVENT_H
003a46cf	3
eb2b8618	4	/*
cdd6c482	5	* Performance event hw details:
eb2b8618 IM	6	*/
	7
	8	#define X86_PMC_MAX_GENERIC 8
	9	#define X86_PMC_MAX_FIXED 3
	10
862a1a5f IM	11	#define X86_PMC_IDX_GENERIC 0
	12	#define X86_PMC_IDX_FIXED 32
	13	#define X86_PMC_IDX_MAX 64
	14
241771ef IM	15	#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
241771ef IM	16	#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
003a46cf	17
241771ef IM	18	#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
241771ef IM	19	#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
003a46cf	20
241771ef IM	21	#define ARCH_PERFMON_EVENTSEL0_ENABLE (1 << 22)
	22	#define ARCH_PERFMON_EVENTSEL_INT (1 << 20)
	23	#define ARCH_PERFMON_EVENTSEL_OS (1 << 17)
	24	#define ARCH_PERFMON_EVENTSEL_USR (1 << 16)
003a46cf	25
2f18d1e8 IM	26	/*
	27	* Includes eventsel and unit mask as well:
	28	*/
1da53e02 SE	29
	30
	31	#define INTEL_ARCH_EVTSEL_MASK 0x000000FFULL
	32	#define INTEL_ARCH_UNIT_MASK 0x0000FF00ULL
	33	#define INTEL_ARCH_EDGE_MASK 0x00040000ULL
	34	#define INTEL_ARCH_INV_MASK 0x00800000ULL
	35	#define INTEL_ARCH_CNT_MASK 0xFF000000ULL
	36	#define INTEL_ARCH_EVENT_MASK (INTEL_ARCH_UNIT_MASK\|INTEL_ARCH_EVTSEL_MASK)
2f18d1e8	37
04a705df SE	38	/*
	39	* filter mask to validate fixed counter events.
	40	* the following filters disqualify for fixed counters:
	41	* - inv
	42	* - edge
	43	* - cnt-mask
	44	* The other filters are supported by fixed counters.
	45	* The any-thread option is supported starting with v3.
	46	*/
1da53e02 SE	47	#define INTEL_ARCH_FIXED_MASK \
	48	(INTEL_ARCH_CNT_MASK\| \
	49	INTEL_ARCH_INV_MASK\| \
	50	INTEL_ARCH_EDGE_MASK\|\
	51	INTEL_ARCH_UNIT_MASK\|\
	52	INTEL_ARCH_EVENT_MASK)
04a705df	53
241771ef IM	54	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
241771ef IM	55	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
04a705df	56	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
003a46cf	57	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
241771ef IM	58	(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
	59
	60	#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
003a46cf	61
eb2b8618 IM	62	/*
	63	* Intel "Architectural Performance Monitoring" CPUID
	64	* detection/enumeration details:
	65	*/
003a46cf TG	66	union cpuid10_eax {
	67	struct {
	68	unsigned int version_id:8;
cdd6c482	69	unsigned int num_events:8;
003a46cf TG	70	unsigned int bit_width:8;
	71	unsigned int mask_length:8;
	72	} split;
	73	unsigned int full;
	74	};
	75
703e937c IM	76	union cpuid10_edx {
703e937c IM	77	struct {
cdd6c482	78	unsigned int num_events_fixed:4;
703e937c IM	79	unsigned int reserved:28;
	80	} split;
	81	unsigned int full;
	82	};
	83
	84
	85	/*
cdd6c482	86	* Fixed-purpose performance events:
703e937c IM	87	*/
703e937c IM	88
862a1a5f IM	89	/*
	90	* All 3 fixed-mode PMCs are configured via this single MSR:
	91	*/
	92	#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
	93
	94	/*
	95	* The counts are available in three separate MSRs:
	96	*/
	97
703e937c IM	98	/* Instr_Retired.Any: */
703e937c IM	99	#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
2f18d1e8	100	#define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0)
703e937c IM	101
	102	/* CPU_CLK_Unhalted.Core: */
	103	#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
2f18d1e8	104	#define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1)
703e937c IM	105
	106	/* CPU_CLK_Unhalted.Ref: */
	107	#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
2f18d1e8	108	#define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2)
703e937c	109
30dd568c MM	110	/*
	111	* We model BTS tracing as another fixed-mode PMC.
	112	*
cdd6c482 IM	113	* We choose a value in the middle of the fixed event range, since lower
cdd6c482 IM	114	* values are used by actual fixed events and higher values are used
30dd568c MM	115	* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
	116	*/
	117	#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
	118
	119
cdd6c482 IM	120	#ifdef CONFIG_PERF_EVENTS
	121	extern void init_hw_perf_events(void);
	122	extern void perf_events_lapic_init(void);
194002b2	123
cdd6c482	124	#define PERF_EVENT_INDEX_OFFSET 0
194002b2	125
241771ef	126	#else
cdd6c482 IM	127	static inline void init_hw_perf_events(void) { }
cdd6c482 IM	128	static inline void perf_events_lapic_init(void) { }
241771ef IM	129	#endif
241771ef IM	130
cdd6c482	131	#endif /* _ASM_X86_PERF_EVENT_H */