[linux-block.git] / arch / x86 / include / asm / perf_event.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_PERF_EVENT_H
#define _ASM_X86_PERF_EVENT_H

/*
 * Performance event hw details:
 */

#define INTEL_PMC_MAX_GENERIC				       32
#define INTEL_PMC_MAX_FIXED					4
#define INTEL_PMC_IDX_FIXED				       32

#define X86_PMC_IDX_MAX					       64

#define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
#define MSR_ARCH_PERFMON_PERFCTR1			      0xc2

#define MSR_ARCH_PERFMON_EVENTSEL0			     0x186
#define MSR_ARCH_PERFMON_EVENTSEL1			     0x187

#define ARCH_PERFMON_EVENTSEL_EVENT			0x000000FFULL
#define ARCH_PERFMON_EVENTSEL_UMASK			0x0000FF00ULL
#define ARCH_PERFMON_EVENTSEL_USR			(1ULL << 16)
#define ARCH_PERFMON_EVENTSEL_OS			(1ULL << 17)
#define ARCH_PERFMON_EVENTSEL_EDGE			(1ULL << 18)
#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL		(1ULL << 19)
#define ARCH_PERFMON_EVENTSEL_INT			(1ULL << 20)
#define ARCH_PERFMON_EVENTSEL_ANY			(1ULL << 21)
#define ARCH_PERFMON_EVENTSEL_ENABLE			(1ULL << 22)
#define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
#define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL

#define HSW_IN_TX					(1ULL << 32)
#define HSW_IN_TX_CHECKPOINTED				(1ULL << 33)
#define ICL_EVENTSEL_ADAPTIVE				(1ULL << 34)
#define ICL_FIXED_0_ADAPTIVE				(1ULL << 32)

#define AMD64_EVENTSEL_INT_CORE_ENABLE			(1ULL << 36)
#define AMD64_EVENTSEL_GUESTONLY			(1ULL << 40)
#define AMD64_EVENTSEL_HOSTONLY				(1ULL << 41)

#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT		37
#define AMD64_EVENTSEL_INT_CORE_SEL_MASK		\
	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)

#define AMD64_EVENTSEL_EVENT	\
	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
#define INTEL_ARCH_EVENT_MASK	\
	(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)

#define AMD64_L3_SLICE_SHIFT				48
#define AMD64_L3_SLICE_MASK				\
	((0xFULL) << AMD64_L3_SLICE_SHIFT)

#define AMD64_L3_THREAD_SHIFT				56
#define AMD64_L3_THREAD_MASK				\
	((0xFFULL) << AMD64_L3_THREAD_SHIFT)

#define X86_RAW_EVENT_MASK		\
	(ARCH_PERFMON_EVENTSEL_EVENT |	\
	 ARCH_PERFMON_EVENTSEL_UMASK |	\
	 ARCH_PERFMON_EVENTSEL_EDGE  |	\
	 ARCH_PERFMON_EVENTSEL_INV   |	\
	 ARCH_PERFMON_EVENTSEL_CMASK)
#define X86_ALL_EVENT_FLAGS  			\
	(ARCH_PERFMON_EVENTSEL_EDGE |  		\
	 ARCH_PERFMON_EVENTSEL_INV | 		\
	 ARCH_PERFMON_EVENTSEL_CMASK | 		\
	 ARCH_PERFMON_EVENTSEL_ANY | 		\
	 ARCH_PERFMON_EVENTSEL_PIN_CONTROL | 	\
	 HSW_IN_TX | 				\
	 HSW_IN_TX_CHECKPOINTED)
#define AMD64_RAW_EVENT_MASK		\
	(X86_RAW_EVENT_MASK          |  \
	 AMD64_EVENTSEL_EVENT)
#define AMD64_RAW_EVENT_MASK_NB		\
	(AMD64_EVENTSEL_EVENT        |  \
	 ARCH_PERFMON_EVENTSEL_UMASK)
#define AMD64_NUM_COUNTERS				4
#define AMD64_NUM_COUNTERS_CORE				6
#define AMD64_NUM_COUNTERS_NB				4

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX		0
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
		(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))

#define ARCH_PERFMON_BRANCH_MISSES_RETIRED		6
#define ARCH_PERFMON_EVENTS_COUNT			7

#define PEBS_DATACFG_MEMINFO	BIT_ULL(0)
#define PEBS_DATACFG_GP	BIT_ULL(1)
#define PEBS_DATACFG_XMMS	BIT_ULL(2)
#define PEBS_DATACFG_LBRS	BIT_ULL(3)
#define PEBS_DATACFG_LBR_SHIFT	24

/*
 * Intel "Architectural Performance Monitoring" CPUID
 * detection/enumeration details:
 */
union cpuid10_eax {
	struct {
		unsigned int version_id:8;
		unsigned int num_counters:8;
		unsigned int bit_width:8;
		unsigned int mask_length:8;
	} split;
	unsigned int full;
};

union cpuid10_ebx {
	struct {
		unsigned int no_unhalted_core_cycles:1;
		unsigned int no_instructions_retired:1;
		unsigned int no_unhalted_reference_cycles:1;
		unsigned int no_llc_reference:1;
		unsigned int no_llc_misses:1;
		unsigned int no_branch_instruction_retired:1;
		unsigned int no_branch_misses_retired:1;
	} split;
	unsigned int full;
};

union cpuid10_edx {
	struct {
		unsigned int num_counters_fixed:5;
		unsigned int bit_width_fixed:8;
		unsigned int reserved:19;
	} split;
	unsigned int full;
};

struct x86_pmu_capability {
	int		version;
	int		num_counters_gp;
	int		num_counters_fixed;
	int		bit_width_gp;
	int		bit_width_fixed;
	unsigned int	events_mask;
	int		events_mask_len;
};

/*
 * Fixed-purpose performance events:
 */

/*
 * All 3 fixed-mode PMCs are configured via this single MSR:
 */
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL	0x38d

/*
 * The counts are available in three separate MSRs:
 */

/* Instr_Retired.Any: */
#define MSR_ARCH_PERFMON_FIXED_CTR0	0x309
#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS	(INTEL_PMC_IDX_FIXED + 0)

/* CPU_CLK_Unhalted.Core: */
#define MSR_ARCH_PERFMON_FIXED_CTR1	0x30a
#define INTEL_PMC_IDX_FIXED_CPU_CYCLES	(INTEL_PMC_IDX_FIXED + 1)

/* CPU_CLK_Unhalted.Ref: */
#define MSR_ARCH_PERFMON_FIXED_CTR2	0x30b
#define INTEL_PMC_IDX_FIXED_REF_CYCLES	(INTEL_PMC_IDX_FIXED + 2)
#define INTEL_PMC_MSK_FIXED_REF_CYCLES	(1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)

/*
 * We model BTS tracing as another fixed-mode PMC.
 *
 * We choose a value in the middle of the fixed event range, since lower
 * values are used by actual fixed events and higher values are used
 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 */
#define INTEL_PMC_IDX_FIXED_BTS				(INTEL_PMC_IDX_FIXED + 16)

#define GLOBAL_STATUS_COND_CHG				BIT_ULL(63)
#define GLOBAL_STATUS_BUFFER_OVF			BIT_ULL(62)
#define GLOBAL_STATUS_UNC_OVF				BIT_ULL(61)
#define GLOBAL_STATUS_ASIF				BIT_ULL(60)
#define GLOBAL_STATUS_COUNTERS_FROZEN			BIT_ULL(59)
#define GLOBAL_STATUS_LBRS_FROZEN			BIT_ULL(58)
#define GLOBAL_STATUS_TRACE_TOPAPMI			BIT_ULL(55)

/*
 * Adaptive PEBS v4
 */

struct pebs_basic {
	u64 format_size;
	u64 ip;
	u64 applicable_counters;
	u64 tsc;
};

struct pebs_meminfo {
	u64 address;
	u64 aux;
	u64 latency;
	u64 tsx_tuning;
};

struct pebs_gprs {
	u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
	u64 r8, r9, r10, r11, r12, r13, r14, r15;
};

struct pebs_xmm {
	u64 xmm[16*2];	/* two entries for each register */
};

struct pebs_lbr_entry {
	u64 from, to, info;
};

struct pebs_lbr {
	struct pebs_lbr_entry lbr[0]; /* Variable length */
};

/*
 * IBS cpuid feature detection
 */

#define IBS_CPUID_FEATURES		0x8000001b

/*
 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
 * bit 0 is used to indicate the existence of IBS.
 */
#define IBS_CAPS_AVAIL			(1U<<0)
#define IBS_CAPS_FETCHSAM		(1U<<1)
#define IBS_CAPS_OPSAM			(1U<<2)
#define IBS_CAPS_RDWROPCNT		(1U<<3)
#define IBS_CAPS_OPCNT			(1U<<4)
#define IBS_CAPS_BRNTRGT		(1U<<5)
#define IBS_CAPS_OPCNTEXT		(1U<<6)
#define IBS_CAPS_RIPINVALIDCHK		(1U<<7)
#define IBS_CAPS_OPBRNFUSE		(1U<<8)
#define IBS_CAPS_FETCHCTLEXTD		(1U<<9)
#define IBS_CAPS_OPDATA4		(1U<<10)

#define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\
					 | IBS_CAPS_FETCHSAM	\
					 | IBS_CAPS_OPSAM)

/*
 * IBS APIC setup
 */
#define IBSCTL				0x1cc
#define IBSCTL_LVT_OFFSET_VALID		(1ULL<<8)
#define IBSCTL_LVT_OFFSET_MASK		0x0F

/* IBS fetch bits/masks */
#define IBS_FETCH_RAND_EN	(1ULL<<57)
#define IBS_FETCH_VAL		(1ULL<<49)
#define IBS_FETCH_ENABLE	(1ULL<<48)
#define IBS_FETCH_CNT		0xFFFF0000ULL
#define IBS_FETCH_MAX_CNT	0x0000FFFFULL

/*
 * IBS op bits/masks
 * The lower 7 bits of the current count are random bits
 * preloaded by hardware and ignored in software
 */
#define IBS_OP_CUR_CNT		(0xFFF80ULL<<32)
#define IBS_OP_CUR_CNT_RAND	(0x0007FULL<<32)
#define IBS_OP_CNT_CTL		(1ULL<<19)
#define IBS_OP_VAL		(1ULL<<18)
#define IBS_OP_ENABLE		(1ULL<<17)
#define IBS_OP_MAX_CNT		0x0000FFFFULL
#define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */
#define IBS_RIP_INVALID		(1ULL<<38)

#ifdef CONFIG_X86_LOCAL_APIC
extern u32 get_ibs_caps(void);
#else
static inline u32 get_ibs_caps(void) { return 0; }
#endif

#ifdef CONFIG_PERF_EVENTS
extern void perf_events_lapic_init(void);

/*
 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
 * unused and ABI specified to be 0, so nobody should care what we do with
 * them.
 *
 * EXACT - the IP points to the exact instruction that triggered the
 *         event (HW bugs exempt).
 * VM    - original X86_VM_MASK; see set_linear_ip().
 */
#define PERF_EFLAGS_EXACT	(1UL << 3)
#define PERF_EFLAGS_VM		(1UL << 5)

struct pt_regs;
struct x86_perf_regs {
	struct pt_regs	regs;
	u64		*xmm_regs;
};

extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_misc_flags(regs)	perf_misc_flags(regs)

#include <asm/stacktrace.h>

/*
 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
 * and the comment with PERF_EFLAGS_EXACT.
 */
#define perf_arch_fetch_caller_regs(regs, __ip)		{	\
	(regs)->ip = (__ip);					\
	(regs)->sp = (unsigned long)__builtin_frame_address(0);	\
	(regs)->cs = __KERNEL_CS;				\
	regs->flags = 0;					\
}

struct perf_guest_switch_msr {
	unsigned msr;
	u64 host, guest;
};

extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
extern void perf_check_microcode(void);
extern int x86_perf_rdpmc_index(struct perf_event *event);
#else
static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
{
	*nr = 0;
	return NULL;
}

static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	memset(cap, 0, sizeof(*cap));
}

static inline void perf_events_lapic_init(void)	{ }
static inline void perf_check_microcode(void) { }
#endif

#ifdef CONFIG_CPU_SUP_INTEL
 extern void intel_pt_handle_vmx(int on);
#endif

#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
 extern void amd_pmu_enable_virt(void);
 extern void amd_pmu_disable_virt(void);
#else
 static inline void amd_pmu_enable_virt(void) { }
 static inline void amd_pmu_disable_virt(void) { }
#endif

#define arch_perf_out_copy_user copy_from_user_nmi

#endif /* _ASM_X86_PERF_EVENT_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
cdd6c482 IM	2	#ifndef _ASM_X86_PERF_EVENT_H
cdd6c482 IM	3	#define _ASM_X86_PERF_EVENT_H
003a46cf	4
eb2b8618	5	/*
cdd6c482	6	* Performance event hw details:
eb2b8618 IM	7	*/
eb2b8618 IM	8
15c7ad51	9	#define INTEL_PMC_MAX_GENERIC 32
60176089	10	#define INTEL_PMC_MAX_FIXED 4
15c7ad51	11	#define INTEL_PMC_IDX_FIXED 32
eb2b8618	12
862a1a5f IM	13	#define X86_PMC_IDX_MAX 64
862a1a5f IM	14
241771ef IM	15	#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
241771ef IM	16	#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
003a46cf	17
241771ef IM	18	#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
241771ef IM	19	#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
003a46cf	20
a098f448 RR	21	#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
	22	#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
	23	#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
	24	#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
	25	#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
a7b9d2cc	26	#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
a098f448 RR	27	#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
	28	#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
	29	#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
	30	#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
	31	#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
	32
3a632cb2 AK	33	#define HSW_IN_TX (1ULL << 32)
3a632cb2 AK	34	#define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
c22497f5 KL	35	#define ICL_EVENTSEL_ADAPTIVE (1ULL << 34)
c22497f5 KL	36	#define ICL_FIXED_0_ADAPTIVE (1ULL << 32)
3a632cb2	37
e259514e	38	#define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
9f19010a JS	39	#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
9f19010a JS	40	#define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
011af857	41
e259514e JS	42	#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
	43	#define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
	44	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
	45
a098f448 RR	46	#define AMD64_EVENTSEL_EVENT \
	47	(ARCH_PERFMON_EVENTSEL_EVENT \| (0x0FULL << 32))
	48	#define INTEL_ARCH_EVENT_MASK \
	49	(ARCH_PERFMON_EVENTSEL_UMASK \| ARCH_PERFMON_EVENTSEL_EVENT)
	50
d7cbbe49 NJ	51	#define AMD64_L3_SLICE_SHIFT 48
	52	#define AMD64_L3_SLICE_MASK \
	53	((0xFULL) << AMD64_L3_SLICE_SHIFT)
	54
	55	#define AMD64_L3_THREAD_SHIFT 56
	56	#define AMD64_L3_THREAD_MASK \
	57	((0xFFULL) << AMD64_L3_THREAD_SHIFT)
	58
a098f448 RR	59	#define X86_RAW_EVENT_MASK \
	60	(ARCH_PERFMON_EVENTSEL_EVENT \| \
	61	ARCH_PERFMON_EVENTSEL_UMASK \| \
	62	ARCH_PERFMON_EVENTSEL_EDGE \| \
	63	ARCH_PERFMON_EVENTSEL_INV \| \
	64	ARCH_PERFMON_EVENTSEL_CMASK)
86a04461 AK	65	#define X86_ALL_EVENT_FLAGS \
	66	(ARCH_PERFMON_EVENTSEL_EDGE \| \
	67	ARCH_PERFMON_EVENTSEL_INV \| \
	68	ARCH_PERFMON_EVENTSEL_CMASK \| \
	69	ARCH_PERFMON_EVENTSEL_ANY \| \
	70	ARCH_PERFMON_EVENTSEL_PIN_CONTROL \| \
	71	HSW_IN_TX \| \
	72	HSW_IN_TX_CHECKPOINTED)
a098f448 RR	73	#define AMD64_RAW_EVENT_MASK \
	74	(X86_RAW_EVENT_MASK \| \
	75	AMD64_EVENTSEL_EVENT)
e259514e JS	76	#define AMD64_RAW_EVENT_MASK_NB \
	77	(AMD64_EVENTSEL_EVENT \| \
	78	ARCH_PERFMON_EVENTSEL_UMASK)
ee5789db	79	#define AMD64_NUM_COUNTERS 4
b1dc3c48	80	#define AMD64_NUM_COUNTERS_CORE 6
e259514e	81	#define AMD64_NUM_COUNTERS_NB 4
04a705df	82
ee5789db	83	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
241771ef	84	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
ee5789db	85	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
003a46cf	86	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
241771ef IM	87	(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
241771ef IM	88
ee5789db	89	#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
ffb871bc	90	#define ARCH_PERFMON_EVENTS_COUNT 7
003a46cf	91
c22497f5 KL	92	#define PEBS_DATACFG_MEMINFO BIT_ULL(0)
	93	#define PEBS_DATACFG_GP BIT_ULL(1)
	94	#define PEBS_DATACFG_XMMS BIT_ULL(2)
	95	#define PEBS_DATACFG_LBRS BIT_ULL(3)
	96	#define PEBS_DATACFG_LBR_SHIFT 24
	97
eb2b8618 IM	98	/*
	99	* Intel "Architectural Performance Monitoring" CPUID
	100	* detection/enumeration details:
	101	*/
003a46cf TG	102	union cpuid10_eax {
	103	struct {
	104	unsigned int version_id:8;
948b1bb8	105	unsigned int num_counters:8;
003a46cf TG	106	unsigned int bit_width:8;
	107	unsigned int mask_length:8;
	108	} split;
	109	unsigned int full;
	110	};
	111
ffb871bc GN	112	union cpuid10_ebx {
	113	struct {
	114	unsigned int no_unhalted_core_cycles:1;
	115	unsigned int no_instructions_retired:1;
	116	unsigned int no_unhalted_reference_cycles:1;
	117	unsigned int no_llc_reference:1;
	118	unsigned int no_llc_misses:1;
	119	unsigned int no_branch_instruction_retired:1;
	120	unsigned int no_branch_misses_retired:1;
	121	} split;
	122	unsigned int full;
	123	};
	124
703e937c IM	125	union cpuid10_edx {
703e937c IM	126	struct {
e768aee8 LS	127	unsigned int num_counters_fixed:5;
	128	unsigned int bit_width_fixed:8;
	129	unsigned int reserved:19;
703e937c IM	130	} split;
	131	unsigned int full;
	132	};
	133
b3d9468a GN	134	struct x86_pmu_capability {
	135	int version;
	136	int num_counters_gp;
	137	int num_counters_fixed;
	138	int bit_width_gp;
	139	int bit_width_fixed;
	140	unsigned int events_mask;
	141	int events_mask_len;
	142	};
703e937c IM	143
703e937c IM	144	/*
cdd6c482	145	* Fixed-purpose performance events:
703e937c IM	146	*/
703e937c IM	147
862a1a5f IM	148	/*
	149	* All 3 fixed-mode PMCs are configured via this single MSR:
	150	*/
cd09c0c4	151	#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
862a1a5f IM	152
	153	/*
	154	* The counts are available in three separate MSRs:
	155	*/
	156
703e937c	157	/* Instr_Retired.Any: */
cd09c0c4	158	#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
15c7ad51	159	#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
703e937c IM	160
703e937c IM	161	/* CPU_CLK_Unhalted.Core: */
cd09c0c4	162	#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
15c7ad51	163	#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
703e937c IM	164
703e937c IM	165	/* CPU_CLK_Unhalted.Ref: */
cd09c0c4	166	#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
15c7ad51 RR	167	#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
15c7ad51 RR	168	#define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
703e937c	169
30dd568c MM	170	/*
	171	* We model BTS tracing as another fixed-mode PMC.
	172	*
cdd6c482 IM	173	* We choose a value in the middle of the fixed event range, since lower
cdd6c482 IM	174	* values are used by actual fixed events and higher values are used
30dd568c MM	175	* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
30dd568c MM	176	*/
15c7ad51	177	#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
30dd568c	178
b83ff1c8 AK	179	#define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
	180	#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(62)
	181	#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
	182	#define GLOBAL_STATUS_ASIF BIT_ULL(60)
	183	#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
	184	#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(58)
5690ae28	185	#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(55)
b83ff1c8	186
c22497f5 KL	187	/*
	188	* Adaptive PEBS v4
	189	*/
	190
	191	struct pebs_basic {
	192	u64 format_size;
	193	u64 ip;
	194	u64 applicable_counters;
	195	u64 tsc;
	196	};
	197
	198	struct pebs_meminfo {
	199	u64 address;
	200	u64 aux;
	201	u64 latency;
	202	u64 tsx_tuning;
	203	};
	204
	205	struct pebs_gprs {
	206	u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
	207	u64 r8, r9, r10, r11, r12, r13, r14, r15;
	208	};
	209
	210	struct pebs_xmm {
	211	u64 xmm[162]; / two entries for each register */
	212	};
	213
	214	struct pebs_lbr_entry {
	215	u64 from, to, info;
	216	};
	217
	218	struct pebs_lbr {
	219	struct pebs_lbr_entry lbr[0]; /* Variable length */
	220	};
	221
ee5789db RR	222	/*
	223	* IBS cpuid feature detection
	224	*/
	225
	226	#define IBS_CPUID_FEATURES 0x8000001b
	227
	228	/*
	229	* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
	230	* bit 0 is used to indicate the existence of IBS.
	231	*/
	232	#define IBS_CAPS_AVAIL (1U<<0)
	233	#define IBS_CAPS_FETCHSAM (1U<<1)
	234	#define IBS_CAPS_OPSAM (1U<<2)
	235	#define IBS_CAPS_RDWROPCNT (1U<<3)
	236	#define IBS_CAPS_OPCNT (1U<<4)
	237	#define IBS_CAPS_BRNTRGT (1U<<5)
	238	#define IBS_CAPS_OPCNTEXT (1U<<6)
d47e8238	239	#define IBS_CAPS_RIPINVALIDCHK (1U<<7)
904cb367 AG	240	#define IBS_CAPS_OPBRNFUSE (1U<<8)
	241	#define IBS_CAPS_FETCHCTLEXTD (1U<<9)
	242	#define IBS_CAPS_OPDATA4 (1U<<10)
ee5789db RR	243
	244	#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
	245	\| IBS_CAPS_FETCHSAM \
	246	\| IBS_CAPS_OPSAM)
	247
	248	/*
	249	* IBS APIC setup
	250	*/
	251	#define IBSCTL 0x1cc
	252	#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
	253	#define IBSCTL_LVT_OFFSET_MASK 0x0F
	254
0f4cd769	255	/* IBS fetch bits/masks */
b47fad3b RR	256	#define IBS_FETCH_RAND_EN (1ULL<<57)
	257	#define IBS_FETCH_VAL (1ULL<<49)
	258	#define IBS_FETCH_ENABLE (1ULL<<48)
	259	#define IBS_FETCH_CNT 0xFFFF0000ULL
	260	#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
1d6040f1	261
0f4cd769 KP	262	/*
	263	* IBS op bits/masks
	264	* The lower 7 bits of the current count are random bits
	265	* preloaded by hardware and ignored in software
	266	*/
	267	#define IBS_OP_CUR_CNT (0xFFF80ULL<<32)
	268	#define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32)
b47fad3b RR	269	#define IBS_OP_CNT_CTL (1ULL<<19)
	270	#define IBS_OP_VAL (1ULL<<18)
	271	#define IBS_OP_ENABLE (1ULL<<17)
	272	#define IBS_OP_MAX_CNT 0x0000FFFFULL
	273	#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
d47e8238	274	#define IBS_RIP_INVALID (1ULL<<38)
30dd568c	275
978da300	276	#ifdef CONFIG_X86_LOCAL_APIC
b7169166	277	extern u32 get_ibs_caps(void);
978da300 RR	278	#else
	279	static inline u32 get_ibs_caps(void) { return 0; }
	280	#endif
b7169166	281
cdd6c482	282	#ifdef CONFIG_PERF_EVENTS
cdd6c482	283	extern void perf_events_lapic_init(void);
194002b2	284
ef21f683	285	/*
d07bdfd3 PZ	286	* Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
	287	* unused and ABI specified to be 0, so nobody should care what we do with
	288	* them.
	289	*
	290	* EXACT - the IP points to the exact instruction that triggered the
	291	* event (HW bugs exempt).
	292	* VM - original X86_VM_MASK; see set_linear_ip().
ef21f683 PZ	293	*/
ef21f683 PZ	294	#define PERF_EFLAGS_EXACT (1UL << 3)
d07bdfd3	295	#define PERF_EFLAGS_VM (1UL << 5)
ef21f683	296
39447b38	297	struct pt_regs;
878068ea KL	298	struct x86_perf_regs {
	299	struct pt_regs regs;
	300	u64 *xmm_regs;
	301	};
	302
39447b38 ZY	303	extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
	304	extern unsigned long perf_misc_flags(struct pt_regs *regs);
	305	#define perf_misc_flags(regs) perf_misc_flags(regs)
ef21f683	306
b0f82b81 FW	307	#include <asm/stacktrace.h>
	308
	309	/*
	310	* We abuse bit 3 from flags to pass exact information, see perf_misc_flags
	311	* and the comment with PERF_EFLAGS_EXACT.
	312	*/
	313	#define perf_arch_fetch_caller_regs(regs, __ip) { \
	314	(regs)->ip = (__ip); \
d15d3568	315	(regs)->sp = (unsigned long)__builtin_frame_address(0); \
b0f82b81 FW	316	(regs)->cs = __KERNEL_CS; \
	317	regs->flags = 0; \
	318	}
	319
144d31e6 GN	320	struct perf_guest_switch_msr {
	321	unsigned msr;
	322	u64 host, guest;
	323	};
	324
	325	extern struct perf_guest_switch_msr perf_guest_get_msrs(int nr);
b3d9468a	326	extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
c93dc84c	327	extern void perf_check_microcode(void);
1182a495	328	extern int x86_perf_rdpmc_index(struct perf_event *event);
241771ef	329	#else
35d56ca9	330	static inline struct perf_guest_switch_msr perf_guest_get_msrs(int nr)
144d31e6 GN	331	{
	332	*nr = 0;
	333	return NULL;
	334	}
	335
b3d9468a GN	336	static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
	337	{
	338	memset(cap, 0, sizeof(*cap));
	339	}
	340
cdd6c482	341	static inline void perf_events_lapic_init(void) { }
c93dc84c	342	static inline void perf_check_microcode(void) { }
241771ef IM	343	#endif
241771ef IM	344
1c5ac21a AS	345	#ifdef CONFIG_CPU_SUP_INTEL
	346	extern void intel_pt_handle_vmx(int on);
	347	#endif
	348
1018faa6 JR	349	#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
	350	extern void amd_pmu_enable_virt(void);
	351	extern void amd_pmu_disable_virt(void);
	352	#else
	353	static inline void amd_pmu_enable_virt(void) { }
	354	static inline void amd_pmu_disable_virt(void) { }
	355	#endif
	356
91d7753a FW	357	#define arch_perf_out_copy_user copy_from_user_nmi
91d7753a FW	358
cdd6c482	359	#endif /* _ASM_X86_PERF_EVENT_H */