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Linux 5.8-rc6
[linux-2.6-block.git] / arch / x86 / include / asm / percpu.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1965aae3
PA		 2#ifndef _ASM_X86_PERCPU_H
3#define _ASM_X86_PERCPU_H
3334052a 4
1a51e3a0 5#ifdef CONFIG_X86_64
9939ddaf
TH		 6#define __percpu_seg gs
7#define __percpu_mov_op movq
1a51e3a0 8#else
9939ddaf
TH		 9#define __percpu_seg fs
10#define __percpu_mov_op movl
96a388de 11#endif
3334052a 12
13#ifdef __ASSEMBLY__
14
15/*
16 * PER_CPU finds an address of a per-cpu variable.
17 *
18 * Args:
19 * var - variable name
20 * reg - 32bit register
21 *
22 * The resulting address is stored in the "reg" argument.
23 *
24 * Example:
25 * PER_CPU(cpu_gdt_descr, %ebx)
26 */
27#ifdef CONFIG_SMP
9939ddaf 28#define PER_CPU(var, reg) \
dd17c8f7
RR		 29 __percpu_mov_op %__percpu_seg:this_cpu_off, reg; \
30 lea var(reg), reg
31#define PER_CPU_VAR(var) %__percpu_seg:var
3334052a 32#else /* ! SMP */
dd17c8f7
RR		 33#define PER_CPU(var, reg) __percpu_mov_op $var, reg
34#define PER_CPU_VAR(var) var
3334052a 35#endif /* SMP */
36
2add8e23
BG		 37#ifdef CONFIG_X86_64_SMP
38#define INIT_PER_CPU_VAR(var) init_per_cpu__##var
39#else
dd17c8f7 40#define INIT_PER_CPU_VAR(var) var
2add8e23
BG		 41#endif
42
3334052a 43#else /* ...!ASSEMBLY */
44
e59a1bb2 45#include <linux/kernel.h>
9939ddaf 46#include <linux/stringify.h>
3334052a 47
9939ddaf 48#ifdef CONFIG_SMP
d7c3f8ce 49#define __percpu_prefix "%%"__stringify(__percpu_seg)":"
c6ae41e7 50#define __my_cpu_offset this_cpu_read(this_cpu_off)
db7829c6
BG		 51
52/*
53 * Compared to the generic __my_cpu_offset version, the following
54 * saves one instruction and avoids clobbering a temp register.
55 */
bbc344e1 56#define arch_raw_cpu_ptr(ptr) \
db7829c6
BG		 57({ \
58 unsigned long tcp_ptr__; \
db7829c6
BG		 59 asm volatile("add " __percpu_arg(1) ", %0" \
60 : "=r" (tcp_ptr__) \
61 : "m" (this_cpu_off), "0" (ptr)); \
62 (typeof(*(ptr)) __kernel __force *)tcp_ptr__; \
63})
9939ddaf 64#else
d7c3f8ce 65#define __percpu_prefix ""
9939ddaf 66#endif
3334052a 67
97b67ae5 68#define __percpu_arg(x) __percpu_prefix "%" #x
d7c3f8ce 69
2add8e23
BG		 70/*
71 * Initialized pointers to per-cpu variables needed for the boot
72 * processor need to use these macros to get the proper address
73 * offset from __per_cpu_load on SMP.
74 *
75 * There also must be an entry in vmlinux_64.lds.S
76 */
77#define DECLARE_INIT_PER_CPU(var) \
dd17c8f7 78 extern typeof(var) init_per_cpu_var(var)
2add8e23
BG		 79
80#ifdef CONFIG_X86_64_SMP
81#define init_per_cpu_var(var) init_per_cpu__##var
82#else
dd17c8f7 83#define init_per_cpu_var(var) var
2add8e23
BG		 84#endif
85
3334052a 86/* For arch-specific code, we can use direct single-insn ops (they
87 * don't give an lvalue though). */
88extern void __bad_percpu_size(void);
89
0b9ccc0a 90#define percpu_to_op(qual, op, var, val) \
bc9e3be2 91do { \
0f5e4816 92 typedef typeof(var) pto_T__; \
bc9e3be2 93 if (0) { \
0f5e4816
TH		 94 pto_T__ pto_tmp__; \
95 pto_tmp__ = (val); \
23b764d0 96 (void)pto_tmp__; \
bc9e3be2
JP		 97 } \
98 switch (sizeof(var)) { \
99 case 1: \
0b9ccc0a 100 asm qual (op "b %1,"__percpu_arg(0) \
bc9e3be2 101 : "+m" (var) \
0f5e4816 102 : "qi" ((pto_T__)(val))); \
bc9e3be2
JP		 103 break; \
104 case 2: \
0b9ccc0a 105 asm qual (op "w %1,"__percpu_arg(0) \
bc9e3be2 106 : "+m" (var) \
0f5e4816 107 : "ri" ((pto_T__)(val))); \
bc9e3be2
JP		 108 break; \
109 case 4: \
0b9ccc0a 110 asm qual (op "l %1,"__percpu_arg(0) \
bc9e3be2 111 : "+m" (var) \
0f5e4816 112 : "ri" ((pto_T__)(val))); \
bc9e3be2 113 break; \
9939ddaf 114 case 8: \
0b9ccc0a 115 asm qual (op "q %1,"__percpu_arg(0) \
9939ddaf 116 : "+m" (var) \
0f5e4816 117 : "re" ((pto_T__)(val))); \
9939ddaf 118 break; \
bc9e3be2
JP		 119 default: __bad_percpu_size(); \
120 } \
121} while (0)
122
5917dae8
CL		 123/*
124 * Generate a percpu add to memory instruction and optimize code
40f0a5d0 125 * if one is added or subtracted.
5917dae8 126 */
0b9ccc0a 127#define percpu_add_op(qual, var, val) \
5917dae8
CL		 128do { \
129 typedef typeof(var) pao_T__; \
130 const int pao_ID__ = (__builtin_constant_p(val) && \
bd09d9a3
GT		 131 ((val) == 1 || (val) == -1)) ? \
132 (int)(val) : 0; \
5917dae8
CL		 133 if (0) { \
134 pao_T__ pao_tmp__; \
135 pao_tmp__ = (val); \
23b764d0 136 (void)pao_tmp__; \
5917dae8
CL		 137 } \
138 switch (sizeof(var)) { \
139 case 1: \
140 if (pao_ID__ == 1) \
0b9ccc0a 141 asm qual ("incb "__percpu_arg(0) : "+m" (var)); \
5917dae8 142 else if (pao_ID__ == -1) \
0b9ccc0a 143 asm qual ("decb "__percpu_arg(0) : "+m" (var)); \
5917dae8 144 else \
0b9ccc0a 145 asm qual ("addb %1, "__percpu_arg(0) \
5917dae8
CL		 146 : "+m" (var) \
147 : "qi" ((pao_T__)(val))); \
148 break; \
149 case 2: \
150 if (pao_ID__ == 1) \
0b9ccc0a 151 asm qual ("incw "__percpu_arg(0) : "+m" (var)); \
5917dae8 152 else if (pao_ID__ == -1) \
0b9ccc0a 153 asm qual ("decw "__percpu_arg(0) : "+m" (var)); \
5917dae8 154 else \
0b9ccc0a 155 asm qual ("addw %1, "__percpu_arg(0) \
5917dae8
CL		 156 : "+m" (var) \
157 : "ri" ((pao_T__)(val))); \
158 break; \
159 case 4: \
160 if (pao_ID__ == 1) \
0b9ccc0a 161 asm qual ("incl "__percpu_arg(0) : "+m" (var)); \
5917dae8 162 else if (pao_ID__ == -1) \
0b9ccc0a 163 asm qual ("decl "__percpu_arg(0) : "+m" (var)); \
5917dae8 164 else \
0b9ccc0a 165 asm qual ("addl %1, "__percpu_arg(0) \
5917dae8
CL		 166 : "+m" (var) \
167 : "ri" ((pao_T__)(val))); \
168 break; \
169 case 8: \
170 if (pao_ID__ == 1) \
0b9ccc0a 171 asm qual ("incq "__percpu_arg(0) : "+m" (var)); \
5917dae8 172 else if (pao_ID__ == -1) \
0b9ccc0a 173 asm qual ("decq "__percpu_arg(0) : "+m" (var)); \
5917dae8 174 else \
0b9ccc0a 175 asm qual ("addq %1, "__percpu_arg(0) \
5917dae8
CL		 176 : "+m" (var) \
177 : "re" ((pao_T__)(val))); \
178 break; \
179 default: __bad_percpu_size(); \
180 } \
181} while (0)
182
0b9ccc0a 183#define percpu_from_op(qual, op, var) \
bc9e3be2 184({ \
0f5e4816 185 typeof(var) pfo_ret__; \
bc9e3be2
JP		 186 switch (sizeof(var)) { \
187 case 1: \
0b9ccc0a 188 asm qual (op "b "__percpu_arg(1)",%0" \
0f5e4816 189 : "=q" (pfo_ret__) \
97b67ae5 190 : "m" (var)); \
bc9e3be2
JP		 191 break; \
192 case 2: \
0b9ccc0a 193 asm qual (op "w "__percpu_arg(1)",%0" \
0f5e4816 194 : "=r" (pfo_ret__) \
97b67ae5 195 : "m" (var)); \
bc9e3be2
JP		 196 break; \
197 case 4: \
0b9ccc0a 198 asm qual (op "l "__percpu_arg(1)",%0" \
0f5e4816 199 : "=r" (pfo_ret__) \
97b67ae5 200 : "m" (var)); \
9939ddaf
TH		 201 break; \
202 case 8: \
0b9ccc0a 203 asm qual (op "q "__percpu_arg(1)",%0" \
0f5e4816 204 : "=r" (pfo_ret__) \
97b67ae5
JB		 205 : "m" (var)); \
206 break; \
207 default: __bad_percpu_size(); \
208 } \
209 pfo_ret__; \
210})
211
212#define percpu_stable_op(op, var) \
213({ \
214 typeof(var) pfo_ret__; \
215 switch (sizeof(var)) { \
216 case 1: \
217 asm(op "b "__percpu_arg(P1)",%0" \
218 : "=q" (pfo_ret__) \
219 : "p" (&(var))); \
220 break; \
221 case 2: \
222 asm(op "w "__percpu_arg(P1)",%0" \
223 : "=r" (pfo_ret__) \
224 : "p" (&(var))); \
225 break; \
226 case 4: \
227 asm(op "l "__percpu_arg(P1)",%0" \
228 : "=r" (pfo_ret__) \
229 : "p" (&(var))); \
230 break; \
231 case 8: \
232 asm(op "q "__percpu_arg(P1)",%0" \
233 : "=r" (pfo_ret__) \
234 : "p" (&(var))); \
bc9e3be2
JP		 235 break; \
236 default: __bad_percpu_size(); \
237 } \
0f5e4816 238 pfo_ret__; \
bc9e3be2 239})
3334052a 240
0b9ccc0a 241#define percpu_unary_op(qual, op, var) \
402af0d7
JB		 242({ \
243 switch (sizeof(var)) { \
244 case 1: \
0b9ccc0a 245 asm qual (op "b "__percpu_arg(0) \
402af0d7
JB		 246 : "+m" (var)); \
247 break; \
248 case 2: \
0b9ccc0a 249 asm qual (op "w "__percpu_arg(0) \
402af0d7
JB		 250 : "+m" (var)); \
251 break; \
252 case 4: \
0b9ccc0a 253 asm qual (op "l "__percpu_arg(0) \
402af0d7
JB		 254 : "+m" (var)); \
255 break; \
256 case 8: \
0b9ccc0a 257 asm qual (op "q "__percpu_arg(0) \
402af0d7
JB		 258 : "+m" (var)); \
259 break; \
260 default: __bad_percpu_size(); \
261 } \
262})
263
40304775
TH		 264/*
265 * Add return operation
266 */
0b9ccc0a 267#define percpu_add_return_op(qual, var, val) \
40304775
TH		 268({ \
269 typeof(var) paro_ret__ = val; \
270 switch (sizeof(var)) { \
271 case 1: \
0b9ccc0a 272 asm qual ("xaddb %0, "__percpu_arg(1) \
40304775
TH		 273 : "+q" (paro_ret__), "+m" (var) \
274 : : "memory"); \
275 break; \
276 case 2: \
0b9ccc0a 277 asm qual ("xaddw %0, "__percpu_arg(1) \
40304775
TH		 278 : "+r" (paro_ret__), "+m" (var) \
279 : : "memory"); \
280 break; \
281 case 4: \
0b9ccc0a 282 asm qual ("xaddl %0, "__percpu_arg(1) \
40304775
TH		 283 : "+r" (paro_ret__), "+m" (var) \
284 : : "memory"); \
285 break; \
286 case 8: \
0b9ccc0a 287 asm qual ("xaddq %0, "__percpu_arg(1) \
40304775
TH		 288 : "+re" (paro_ret__), "+m" (var) \
289 : : "memory"); \
290 break; \
291 default: __bad_percpu_size(); \
292 } \
293 paro_ret__ += val; \
294 paro_ret__; \
295})
296
7296e08a 297/*
8270137a
CL		 298 * xchg is implemented using cmpxchg without a lock prefix. xchg is
299 * expensive due to the implied lock prefix. The processor cannot prefetch
300 * cachelines if xchg is used.
7296e08a 301 */
0b9ccc0a 302#define percpu_xchg_op(qual, var, nval) \
7296e08a
CL		 303({ \
304 typeof(var) pxo_ret__; \
305 typeof(var) pxo_new__ = (nval); \
306 switch (sizeof(var)) { \
307 case 1: \
0b9ccc0a 308 asm qual ("\n\tmov "__percpu_arg(1)",%%al" \
889a7a6a 309 "\n1:\tcmpxchgb %2, "__percpu_arg(1) \
8270137a 310 "\n\tjnz 1b" \
889a7a6a 311 : "=&a" (pxo_ret__), "+m" (var) \
7296e08a
CL		 312 : "q" (pxo_new__) \
313 : "memory"); \
314 break; \
315 case 2: \
0b9ccc0a 316 asm qual ("\n\tmov "__percpu_arg(1)",%%ax" \
889a7a6a 317 "\n1:\tcmpxchgw %2, "__percpu_arg(1) \
8270137a 318 "\n\tjnz 1b" \
889a7a6a 319 : "=&a" (pxo_ret__), "+m" (var) \
7296e08a
CL		 320 : "r" (pxo_new__) \
321 : "memory"); \
322 break; \
323 case 4: \
0b9ccc0a 324 asm qual ("\n\tmov "__percpu_arg(1)",%%eax" \
889a7a6a 325 "\n1:\tcmpxchgl %2, "__percpu_arg(1) \
8270137a 326 "\n\tjnz 1b" \
889a7a6a 327 : "=&a" (pxo_ret__), "+m" (var) \
7296e08a
CL		 328 : "r" (pxo_new__) \
329 : "memory"); \
330 break; \
331 case 8: \
0b9ccc0a 332 asm qual ("\n\tmov "__percpu_arg(1)",%%rax" \
889a7a6a 333 "\n1:\tcmpxchgq %2, "__percpu_arg(1) \
8270137a 334 "\n\tjnz 1b" \
889a7a6a 335 : "=&a" (pxo_ret__), "+m" (var) \
7296e08a
CL		 336 : "r" (pxo_new__) \
337 : "memory"); \
338 break; \
339 default: __bad_percpu_size(); \
340 } \
341 pxo_ret__; \
342})
343
344/*
345 * cmpxchg has no such implied lock semantics as a result it is much
346 * more efficient for cpu local operations.
347 */
0b9ccc0a 348#define percpu_cmpxchg_op(qual, var, oval, nval) \
7296e08a
CL		 349({ \
350 typeof(var) pco_ret__; \
351 typeof(var) pco_old__ = (oval); \
352 typeof(var) pco_new__ = (nval); \
353 switch (sizeof(var)) { \
354 case 1: \
0b9ccc0a 355 asm qual ("cmpxchgb %2, "__percpu_arg(1) \
7296e08a
CL		 356 : "=a" (pco_ret__), "+m" (var) \
357 : "q" (pco_new__), "0" (pco_old__) \
358 : "memory"); \
359 break; \
360 case 2: \
0b9ccc0a 361 asm qual ("cmpxchgw %2, "__percpu_arg(1) \
7296e08a
CL		 362 : "=a" (pco_ret__), "+m" (var) \
363 : "r" (pco_new__), "0" (pco_old__) \
364 : "memory"); \
365 break; \
366 case 4: \
0b9ccc0a 367 asm qual ("cmpxchgl %2, "__percpu_arg(1) \
7296e08a
CL		 368 : "=a" (pco_ret__), "+m" (var) \
369 : "r" (pco_new__), "0" (pco_old__) \
370 : "memory"); \
371 break; \
372 case 8: \
0b9ccc0a 373 asm qual ("cmpxchgq %2, "__percpu_arg(1) \
7296e08a
CL		 374 : "=a" (pco_ret__), "+m" (var) \
375 : "r" (pco_new__), "0" (pco_old__) \
376 : "memory"); \
377 break; \
378 default: __bad_percpu_size(); \
379 } \
380 pco_ret__; \
381})
382
ed8d9adf 383/*
641b695c 384 * this_cpu_read() makes gcc load the percpu variable every time it is
c6ae41e7
AS		 385 * accessed while this_cpu_read_stable() allows the value to be cached.
386 * this_cpu_read_stable() is more efficient and can be used if its value
ed8d9adf
LT		 387 * is guaranteed to be valid across cpus. The current users include
388 * get_current() and get_thread_info() both of which are actually
389 * per-thread variables implemented as per-cpu variables and thus
390 * stable for the duration of the respective task.
391 */
97b67ae5 392#define this_cpu_read_stable(var) percpu_stable_op("mov", var)
9939ddaf 393
0b9ccc0a
PZ		 394#define raw_cpu_read_1(pcp) percpu_from_op(, "mov", pcp)
395#define raw_cpu_read_2(pcp) percpu_from_op(, "mov", pcp)
396#define raw_cpu_read_4(pcp) percpu_from_op(, "mov", pcp)
b3ca1c10 397
0b9ccc0a
PZ		 398#define raw_cpu_write_1(pcp, val) percpu_to_op(, "mov", (pcp), val)
399#define raw_cpu_write_2(pcp, val) percpu_to_op(, "mov", (pcp), val)
400#define raw_cpu_write_4(pcp, val) percpu_to_op(, "mov", (pcp), val)
401#define raw_cpu_add_1(pcp, val) percpu_add_op(, (pcp), val)
402#define raw_cpu_add_2(pcp, val) percpu_add_op(, (pcp), val)
403#define raw_cpu_add_4(pcp, val) percpu_add_op(, (pcp), val)
404#define raw_cpu_and_1(pcp, val) percpu_to_op(, "and", (pcp), val)
405#define raw_cpu_and_2(pcp, val) percpu_to_op(, "and", (pcp), val)
406#define raw_cpu_and_4(pcp, val) percpu_to_op(, "and", (pcp), val)
407#define raw_cpu_or_1(pcp, val) percpu_to_op(, "or", (pcp), val)
408#define raw_cpu_or_2(pcp, val) percpu_to_op(, "or", (pcp), val)
409#define raw_cpu_or_4(pcp, val) percpu_to_op(, "or", (pcp), val)
2234a6d3
PZ		 410
411/*
412 * raw_cpu_xchg() can use a load-store since it is not required to be
413 * IRQ-safe.
414 */
415#define raw_percpu_xchg_op(var, nval) \
416({ \
417 typeof(var) pxo_ret__ = raw_cpu_read(var); \
418 raw_cpu_write(var, (nval)); \
419 pxo_ret__; \
420})
421
422#define raw_cpu_xchg_1(pcp, val) raw_percpu_xchg_op(pcp, val)
423#define raw_cpu_xchg_2(pcp, val) raw_percpu_xchg_op(pcp, val)
424#define raw_cpu_xchg_4(pcp, val) raw_percpu_xchg_op(pcp, val)
30ed1a79 425
0b9ccc0a
PZ		 426#define this_cpu_read_1(pcp) percpu_from_op(volatile, "mov", pcp)
427#define this_cpu_read_2(pcp) percpu_from_op(volatile, "mov", pcp)
428#define this_cpu_read_4(pcp) percpu_from_op(volatile, "mov", pcp)
429#define this_cpu_write_1(pcp, val) percpu_to_op(volatile, "mov", (pcp), val)
430#define this_cpu_write_2(pcp, val) percpu_to_op(volatile, "mov", (pcp), val)
431#define this_cpu_write_4(pcp, val) percpu_to_op(volatile, "mov", (pcp), val)
432#define this_cpu_add_1(pcp, val) percpu_add_op(volatile, (pcp), val)
433#define this_cpu_add_2(pcp, val) percpu_add_op(volatile, (pcp), val)
434#define this_cpu_add_4(pcp, val) percpu_add_op(volatile, (pcp), val)
435#define this_cpu_and_1(pcp, val) percpu_to_op(volatile, "and", (pcp), val)
436#define this_cpu_and_2(pcp, val) percpu_to_op(volatile, "and", (pcp), val)
437#define this_cpu_and_4(pcp, val) percpu_to_op(volatile, "and", (pcp), val)
438#define this_cpu_or_1(pcp, val) percpu_to_op(volatile, "or", (pcp), val)
439#define this_cpu_or_2(pcp, val) percpu_to_op(volatile, "or", (pcp), val)
440#define this_cpu_or_4(pcp, val) percpu_to_op(volatile, "or", (pcp), val)
441#define this_cpu_xchg_1(pcp, nval) percpu_xchg_op(volatile, pcp, nval)
442#define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(volatile, pcp, nval)
443#define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(volatile, pcp, nval)
30ed1a79 444
0b9ccc0a
PZ		 445#define raw_cpu_add_return_1(pcp, val) percpu_add_return_op(, pcp, val)
446#define raw_cpu_add_return_2(pcp, val) percpu_add_return_op(, pcp, val)
447#define raw_cpu_add_return_4(pcp, val) percpu_add_return_op(, pcp, val)
448#define raw_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(, pcp, oval, nval)
449#define raw_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(, pcp, oval, nval)
450#define raw_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(, pcp, oval, nval)
7296e08a 451
0b9ccc0a
PZ		 452#define this_cpu_add_return_1(pcp, val) percpu_add_return_op(volatile, pcp, val)
453#define this_cpu_add_return_2(pcp, val) percpu_add_return_op(volatile, pcp, val)
454#define this_cpu_add_return_4(pcp, val) percpu_add_return_op(volatile, pcp, val)
455#define this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(volatile, pcp, oval, nval)
456#define this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(volatile, pcp, oval, nval)
457#define this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(volatile, pcp, oval, nval)
7296e08a 458
b9ec40af 459#ifdef CONFIG_X86_CMPXCHG64
cebef5be 460#define percpu_cmpxchg8b_double(pcp1, pcp2, o1, o2, n1, n2) \
b9ec40af 461({ \
cebef5be
JB		 462 bool __ret; \
463 typeof(pcp1) __o1 = (o1), __n1 = (n1); \
464 typeof(pcp2) __o2 = (o2), __n2 = (n2); \
1966c5e5
UB		 465 asm volatile("cmpxchg8b "__percpu_arg(1) \
466 CC_SET(z) \
467 : CC_OUT(z) (__ret), "+m" (pcp1), "+m" (pcp2), "+a" (__o1), "+d" (__o2) \
468 : "b" (__n1), "c" (__n2)); \
b9ec40af
CL		 469 __ret; \
470})
471
b3ca1c10 472#define raw_cpu_cmpxchg_double_4 percpu_cmpxchg8b_double
cebef5be 473#define this_cpu_cmpxchg_double_4 percpu_cmpxchg8b_double
b9ec40af
CL		 474#endif /* CONFIG_X86_CMPXCHG64 */
475
30ed1a79
CL		 476/*
477 * Per cpu atomic 64 bit operations are only available under 64 bit.
478 * 32 bit must fall back to generic operations.
479 */
480#ifdef CONFIG_X86_64
0b9ccc0a
PZ		 481#define raw_cpu_read_8(pcp) percpu_from_op(, "mov", pcp)
482#define raw_cpu_write_8(pcp, val) percpu_to_op(, "mov", (pcp), val)
483#define raw_cpu_add_8(pcp, val) percpu_add_op(, (pcp), val)
484#define raw_cpu_and_8(pcp, val) percpu_to_op(, "and", (pcp), val)
485#define raw_cpu_or_8(pcp, val) percpu_to_op(, "or", (pcp), val)
486#define raw_cpu_add_return_8(pcp, val) percpu_add_return_op(, pcp, val)
2234a6d3 487#define raw_cpu_xchg_8(pcp, nval) raw_percpu_xchg_op(pcp, nval)
0b9ccc0a 488#define raw_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(, pcp, oval, nval)
b3ca1c10 489
0b9ccc0a
PZ		 490#define this_cpu_read_8(pcp) percpu_from_op(volatile, "mov", pcp)
491#define this_cpu_write_8(pcp, val) percpu_to_op(volatile, "mov", (pcp), val)
492#define this_cpu_add_8(pcp, val) percpu_add_op(volatile, (pcp), val)
493#define this_cpu_and_8(pcp, val) percpu_to_op(volatile, "and", (pcp), val)
494#define this_cpu_or_8(pcp, val) percpu_to_op(volatile, "or", (pcp), val)
495#define this_cpu_add_return_8(pcp, val) percpu_add_return_op(volatile, pcp, val)
496#define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(volatile, pcp, nval)
497#define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(volatile, pcp, oval, nval)
30ed1a79 498
b9ec40af
CL		 499/*
500 * Pretty complex macro to generate cmpxchg16 instruction. The instruction
501 * is not supported on early AMD64 processors so we must be able to emulate
502 * it in software. The address used in the cmpxchg16 instruction must be
503 * aligned to a 16 byte boundary.
504 */
cebef5be 505#define percpu_cmpxchg16b_double(pcp1, pcp2, o1, o2, n1, n2) \
b9ec40af 506({ \
cebef5be
JB		 507 bool __ret; \
508 typeof(pcp1) __o1 = (o1), __n1 = (n1); \
509 typeof(pcp2) __o2 = (o2), __n2 = (n2); \
510 alternative_io("leaq %P1,%%rsi\n\tcall this_cpu_cmpxchg16b_emu\n\t", \
511 "cmpxchg16b " __percpu_arg(1) "\n\tsetz %0\n\t", \
b9ec40af 512 X86_FEATURE_CX16, \
cebef5be
JB		 513 ASM_OUTPUT2("=a" (__ret), "+m" (pcp1), \
514 "+m" (pcp2), "+d" (__o2)), \
515 "b" (__n1), "c" (__n2), "a" (__o1) : "rsi"); \
b9ec40af
CL		 516 __ret; \
517})
518
b3ca1c10 519#define raw_cpu_cmpxchg_double_8 percpu_cmpxchg16b_double
cebef5be 520#define this_cpu_cmpxchg_double_8 percpu_cmpxchg16b_double
b9ec40af 521
30ed1a79
CL		 522#endif
523
117780ee 524static __always_inline bool x86_this_cpu_constant_test_bit(unsigned int nr,
349c004e
CL		 525 const unsigned long __percpu *addr)
526{
799bc3c5
LR		 527 unsigned long __percpu *a =
528 (unsigned long __percpu *)addr + nr / BITS_PER_LONG;
349c004e 529
641b695c 530#ifdef CONFIG_X86_64
b3ca1c10 531 return ((1UL << (nr % BITS_PER_LONG)) & raw_cpu_read_8(*a)) != 0;
641b695c 532#else
b3ca1c10 533 return ((1UL << (nr % BITS_PER_LONG)) & raw_cpu_read_4(*a)) != 0;
641b695c 534#endif
349c004e
CL		 535}
536
117780ee 537static inline bool x86_this_cpu_variable_test_bit(int nr,
349c004e
CL		 538 const unsigned long __percpu *addr)
539{
117780ee 540 bool oldbit;
349c004e 541
22636f8c 542 asm volatile("btl "__percpu_arg(2)",%1"
64be6d36
PA		 543 CC_SET(c)
544 : CC_OUT(c) (oldbit)
799bc3c5 545 : "m" (*(unsigned long __percpu *)addr), "Ir" (nr));
349c004e
CL		 546
547 return oldbit;
548}
549
550#define x86_this_cpu_test_bit(nr, addr) \
551 (__builtin_constant_p((nr)) \
552 ? x86_this_cpu_constant_test_bit((nr), (addr)) \
553 : x86_this_cpu_variable_test_bit((nr), (addr)))
554
555
6dbde353
IM		 556#include <asm-generic/percpu.h>
557
558/* We can use this directly for local CPU (faster). */
2c773dd3 559DECLARE_PER_CPU_READ_MOSTLY(unsigned long, this_cpu_off);
6dbde353 560
3334052a 561#endif /* !__ASSEMBLY__ */
23ca4bba
MT		 562
563#ifdef CONFIG_SMP
564
565/*
566 * Define the "EARLY_PER_CPU" macros. These are used for some per_cpu
567 * variables that are initialized and accessed before there are per_cpu
568 * areas allocated.
569 */
570
571#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \
572 DEFINE_PER_CPU(_type, _name) = _initvalue; \
573 __typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \
574 { [0 ... NR_CPUS-1] = _initvalue }; \
c6a92a25 575 __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
23ca4bba 576
c35f7741
IY		 577#define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue) \
578 DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue; \
579 __typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \
580 { [0 ... NR_CPUS-1] = _initvalue }; \
581 __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
582
23ca4bba
MT		 583#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \
584 EXPORT_PER_CPU_SYMBOL(_name)
585
586#define DECLARE_EARLY_PER_CPU(_type, _name) \
587 DECLARE_PER_CPU(_type, _name); \
588 extern __typeof__(_type) *_name##_early_ptr; \
589 extern __typeof__(_type) _name##_early_map[]
590
c35f7741
IY		 591#define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name) \
592 DECLARE_PER_CPU_READ_MOSTLY(_type, _name); \
593 extern __typeof__(_type) *_name##_early_ptr; \
594 extern __typeof__(_type) _name##_early_map[]
595
23ca4bba
MT		 596#define early_per_cpu_ptr(_name) (_name##_early_ptr)
597#define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx])
598#define early_per_cpu(_name, _cpu) \
f10fcd47
TH		 599 *(early_per_cpu_ptr(_name) ? \
600 &early_per_cpu_ptr(_name)[_cpu] : \
601 &per_cpu(_name, _cpu))
23ca4bba
MT		 602
603#else /* !CONFIG_SMP */
604#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \
605 DEFINE_PER_CPU(_type, _name) = _initvalue
606
c35f7741
IY		 607#define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue) \
608 DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue
609
23ca4bba
MT		 610#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \
611 EXPORT_PER_CPU_SYMBOL(_name)
612
613#define DECLARE_EARLY_PER_CPU(_type, _name) \
614 DECLARE_PER_CPU(_type, _name)
615
c35f7741
IY		 616#define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name) \
617 DECLARE_PER_CPU_READ_MOSTLY(_type, _name)
618
23ca4bba
MT		 619#define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu)
620#define early_per_cpu_ptr(_name) NULL
621/* no early_per_cpu_map() */
622
623#endif /* !CONFIG_SMP */
624
1965aae3 625#endif /* _ASM_X86_PERCPU_H */
Linux 6.x block layer and io_uring tree(s)