[linux-2.6-block.git] / arch / x86 / include / asm / pci_x86.h

/*
 *	Low-Level PCI Access for i386 machines.
 *
 *	(c) 1999 Martin Mares <mj@ucw.cz>
 */

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
#else
#define DBG(fmt, ...)				\
do {						\
	if (0)					\
		printk(fmt, ##__VA_ARGS__);	\
} while (0)
#endif

#define PCI_PROBE_BIOS		0x0001
#define PCI_PROBE_CONF1		0x0002
#define PCI_PROBE_CONF2		0x0004
#define PCI_PROBE_MMCONF	0x0008
#define PCI_PROBE_MASK		0x000f
#define PCI_PROBE_NOEARLY	0x0010

#define PCI_NO_CHECKS		0x0400
#define PCI_USE_PIRQ_MASK	0x0800
#define PCI_ASSIGN_ROMS		0x1000
#define PCI_BIOS_IRQ_SCAN	0x2000
#define PCI_ASSIGN_ALL_BUSSES	0x4000
#define PCI_CAN_SKIP_ISA_ALIGN	0x8000
#define PCI_USE__CRS		0x10000
#define PCI_CHECK_ENABLE_AMD_MMCONF	0x20000
#define PCI_HAS_IO_ECS		0x40000
#define PCI_NOASSIGN_ROMS	0x80000
#define PCI_ROOT_NO_CRS		0x100000
#define PCI_NOASSIGN_BARS	0x200000

extern unsigned int pci_probe;
extern unsigned long pirq_table_addr;

enum pci_bf_sort_state {
	pci_bf_sort_default,
	pci_force_nobf,
	pci_force_bf,
	pci_dmi_bf,
};

/* pci-i386.c */

void pcibios_resource_survey(void);
void pcibios_set_cache_line_size(void);

/* pci-pc.c */

extern int pcibios_last_bus;
extern struct pci_ops pci_root_ops;

void pcibios_scan_specific_bus(int busn);

/* pci-irq.c */

struct irq_info {
	u8 bus, devfn;			/* Bus, device and function */
	struct {
		u8 link;		/* IRQ line ID, chipset dependent,
					   0 = not routed */
		u16 bitmap;		/* Available IRQs */
	} __attribute__((packed)) irq[4];
	u8 slot;			/* Slot number, 0=onboard */
	u8 rfu;
} __attribute__((packed));

struct irq_routing_table {
	u32 signature;			/* PIRQ_SIGNATURE should be here */
	u16 version;			/* PIRQ_VERSION */
	u16 size;			/* Table size in bytes */
	u8 rtr_bus, rtr_devfn;		/* Where the interrupt router lies */
	u16 exclusive_irqs;		/* IRQs devoted exclusively to
					   PCI usage */
	u16 rtr_vendor, rtr_device;	/* Vendor and device ID of
					   interrupt router */
	u32 miniport_data;		/* Crap */
	u8 rfu[11];
	u8 checksum;			/* Modulo 256 checksum must give 0 */
	struct irq_info slots[0];
} __attribute__((packed));

extern unsigned int pcibios_irq_mask;

extern raw_spinlock_t pci_config_lock;

extern int (*pcibios_enable_irq)(struct pci_dev *dev);
extern void (*pcibios_disable_irq)(struct pci_dev *dev);

extern bool mp_should_keep_irq(struct device *dev);

struct pci_raw_ops {
	int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 *val);
	int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 val);
};

extern const struct pci_raw_ops *raw_pci_ops;
extern const struct pci_raw_ops *raw_pci_ext_ops;

extern const struct pci_raw_ops pci_mmcfg;
extern const struct pci_raw_ops pci_direct_conf1;
extern bool port_cf9_safe;

/* arch_initcall level */
extern int pci_direct_probe(void);
extern void pci_direct_init(int type);
extern void pci_pcbios_init(void);
extern void __init dmi_check_pciprobe(void);
extern void __init dmi_check_skip_isa_align(void);

/* some common used subsys_initcalls */
extern int __init pci_acpi_init(void);
extern void __init pcibios_irq_init(void);
extern int __init pcibios_init(void);
extern int pci_legacy_init(void);
extern void pcibios_fixup_irqs(void);

/* pci-mmconfig.c */

/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)

struct pci_mmcfg_region {
	struct list_head list;
	struct resource res;
	u64 address;
	char __iomem *virt;
	u16 segment;
	u8 start_bus;
	u8 end_bus;
	char name[PCI_MMCFG_RESOURCE_NAME_LEN];
};

extern int __init pci_mmcfg_arch_init(void);
extern void __init pci_mmcfg_arch_free(void);
extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
			       phys_addr_t addr);
extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);

extern struct list_head pci_mmcfg_list;

#define PCI_MMCFG_BUS_OFFSET(bus)      ((bus) << 20)

/*
 * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use
 * %eax.  No other source or target registers may be used.  The following
 * mmio_config_* accessors enforce this.  See "BIOS and Kernel Developer's
 * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1,
 * "MMIO Configuration Coding Requirements".
 */
static inline unsigned char mmio_config_readb(void __iomem *pos)
{
	u8 val;
	asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
	return val;
}

static inline unsigned short mmio_config_readw(void __iomem *pos)
{
	u16 val;
	asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
	return val;
}

static inline unsigned int mmio_config_readl(void __iomem *pos)
{
	u32 val;
	asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
	return val;
}

static inline void mmio_config_writeb(void __iomem *pos, u8 val)
{
	asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
}

static inline void mmio_config_writew(void __iomem *pos, u16 val)
{
	asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
}

static inline void mmio_config_writel(void __iomem *pos, u32 val)
{
	asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
}

#ifdef CONFIG_PCI
# ifdef CONFIG_ACPI
#  define x86_default_pci_init		pci_acpi_init
# else
#  define x86_default_pci_init		pci_legacy_init
# endif
# define x86_default_pci_init_irq	pcibios_irq_init
# define x86_default_pci_fixup_irqs	pcibios_fixup_irqs
#else
# define x86_default_pci_init		NULL
# define x86_default_pci_init_irq	NULL
# define x86_default_pci_fixup_irqs	NULL
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Access for i386 machines.
	3	*
	4	* (c) 1999 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#undef DEBUG
	8
	9	#ifdef DEBUG
c767a54b	10	#define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
1da177e4	11	#else
c767a54b JP	12	#define DBG(fmt, ...) \
	13	do { \
	14	if (0) \
	15	printk(fmt, ##__VA_ARGS__); \
	16	} while (0)
1da177e4 LT	17	#endif
	18
	19	#define PCI_PROBE_BIOS 0x0001
	20	#define PCI_PROBE_CONF1 0x0002
	21	#define PCI_PROBE_CONF2 0x0004
	22	#define PCI_PROBE_MMCONF 0x0008
79e453d4	23	#define PCI_PROBE_MASK 0x000f
0637a70a	24	#define PCI_PROBE_NOEARLY 0x0010
1da177e4	25
1da177e4 LT	26	#define PCI_NO_CHECKS 0x0400
	27	#define PCI_USE_PIRQ_MASK 0x0800
	28	#define PCI_ASSIGN_ROMS 0x1000
	29	#define PCI_BIOS_IRQ_SCAN 0x2000
	30	#define PCI_ASSIGN_ALL_BUSSES 0x4000
036fff4c	31	#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
236e946b	32	#define PCI_USE__CRS 0x10000
5f0b2976	33	#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
3a27dd1c	34	#define PCI_HAS_IO_ECS 0x40000
dc7c65db	35	#define PCI_NOASSIGN_ROMS 0x80000
7bc5e3f2	36	#define PCI_ROOT_NO_CRS 0x100000
7bd1c365	37	#define PCI_NOASSIGN_BARS 0x200000
1da177e4 LT	38
1da177e4 LT	39	extern unsigned int pci_probe;
120bb424	40	extern unsigned long pirq_table_addr;
1da177e4	41
6b4b78fe MD	42	enum pci_bf_sort_state {
	43	pci_bf_sort_default,
	44	pci_force_nobf,
	45	pci_force_bf,
	46	pci_dmi_bf,
	47	};
	48
1da177e4 LT	49	/* pci-i386.c */
1da177e4 LT	50
1da177e4	51	void pcibios_resource_survey(void);
44de3395	52	void pcibios_set_cache_line_size(void);
1da177e4 LT	53
	54	/* pci-pc.c */
	55
	56	extern int pcibios_last_bus;
1da177e4 LT	57	extern struct pci_ops pci_root_ops;
1da177e4 LT	58
5707b24a AR	59	void pcibios_scan_specific_bus(int busn);
5707b24a AR	60
1da177e4 LT	61	/* pci-irq.c */
	62
	63	struct irq_info {
	64	u8 bus, devfn; /* Bus, device and function */
	65	struct {
82487711 JSR	66	u8 link; /* IRQ line ID, chipset dependent,
82487711 JSR	67	0 = not routed */
1da177e4 LT	68	u16 bitmap; /* Available IRQs */
	69	} __attribute__((packed)) irq[4];
	70	u8 slot; /* Slot number, 0=onboard */
	71	u8 rfu;
	72	} __attribute__((packed));
	73
	74	struct irq_routing_table {
	75	u32 signature; /* PIRQ_SIGNATURE should be here */
	76	u16 version; /* PIRQ_VERSION */
	77	u16 size; /* Table size in bytes */
	78	u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
82487711 JSR	79	u16 exclusive_irqs; /* IRQs devoted exclusively to
	80	PCI usage */
	81	u16 rtr_vendor, rtr_device; /* Vendor and device ID of
	82	interrupt router */
1da177e4 LT	83	u32 miniport_data; /* Crap */
1da177e4 LT	84	u8 rfu[11];
82487711	85	u8 checksum; /* Modulo 256 checksum must give 0 */
1da177e4 LT	86	struct irq_info slots[0];
	87	} __attribute__((packed));
	88
	89	extern unsigned int pcibios_irq_mask;
	90
d19f61f0	91	extern raw_spinlock_t pci_config_lock;
1da177e4 LT	92
1da177e4 LT	93	extern int (pcibios_enable_irq)(struct pci_dev dev);
87bec66b	94	extern void (pcibios_disable_irq)(struct pci_dev dev);
928cf8c6	95
6c777e87 BH	96	extern bool mp_should_keep_irq(struct device *dev);
6c777e87 BH	97
b6ce068a MW	98	struct pci_raw_ops {
	99	int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
	100	int reg, int len, u32 *val);
	101	int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
	102	int reg, int len, u32 val);
	103	};
	104
72da0b07 JB	105	extern const struct pci_raw_ops *raw_pci_ops;
72da0b07 JB	106	extern const struct pci_raw_ops *raw_pci_ext_ops;
b6ce068a	107
c0fa4078	108	extern const struct pci_raw_ops pci_mmcfg;
72da0b07	109	extern const struct pci_raw_ops pci_direct_conf1;
14d7ca5c	110	extern bool port_cf9_safe;
928cf8c6	111
8dd779b1	112	/* arch_initcall level */
5e544d61 AK	113	extern int pci_direct_probe(void);
5e544d61 AK	114	extern void pci_direct_init(int type);
92c05fc1	115	extern void pci_pcbios_init(void);
8dd779b1 RR	116	extern void __init dmi_check_pciprobe(void);
	117	extern void __init dmi_check_skip_isa_align(void);
	118
	119	/* some common used subsys_initcalls */
	120	extern int __init pci_acpi_init(void);
ab3b3793	121	extern void __init pcibios_irq_init(void);
8dd779b1	122	extern int __init pcibios_init(void);
b72d0db9	123	extern int pci_legacy_init(void);
9325a28c	124	extern void pcibios_fixup_irqs(void);
5e544d61	125
b7867394 OG	126	/* pci-mmconfig.c */
b7867394 OG	127
56ddf4d3 BH	128	/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
	129	#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
	130
d215a9c8	131	struct pci_mmcfg_region {
ff097ddd	132	struct list_head list;
56ddf4d3	133	struct resource res;
d215a9c8	134	u64 address;
3f0f5503	135	char __iomem *virt;
d7e6b66f BH	136	u16 segment;
	137	u8 start_bus;
	138	u8 end_bus;
56ddf4d3	139	char name[PCI_MMCFG_RESOURCE_NAME_LEN];
d215a9c8 BH	140	};
d215a9c8 BH	141
429d512e	142	extern int __init pci_mmcfg_arch_init(void);
0b64ad71	143	extern void __init pci_mmcfg_arch_free(void);
a18e3690	144	extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
9cf0105d	145	extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
a18e3690 GKH	146	extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
a18e3690 GKH	147	phys_addr_t addr);
9c95111b	148	extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
f6e1d8cc	149	extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
3320ad99	150
ff097ddd	151	extern struct list_head pci_mmcfg_list;
c4bf2f37	152
df5eb1d6 BH	153	#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
df5eb1d6 BH	154
3320ad99	155	/*
21461775 TN	156	* On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use
	157	* %eax. No other source or target registers may be used. The following
	158	* mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's
	159	* Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1,
	160	* "MMIO Configuration Coding Requirements".
3320ad99	161	*/
	162	static inline unsigned char mmio_config_readb(void __iomem *pos)
	163	{
	164	u8 val;
	165	asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
	166	return val;
	167	}
	168
	169	static inline unsigned short mmio_config_readw(void __iomem *pos)
	170	{
	171	u16 val;
	172	asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
	173	return val;
	174	}
	175
	176	static inline unsigned int mmio_config_readl(void __iomem *pos)
	177	{
	178	u32 val;
	179	asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
	180	return val;
	181	}
	182
	183	static inline void mmio_config_writeb(void __iomem *pos, u8 val)
	184	{
82487711	185	asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99	186	}
	187
	188	static inline void mmio_config_writew(void __iomem *pos, u16 val)
	189	{
82487711	190	asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99	191	}
	192
	193	static inline void mmio_config_writel(void __iomem *pos, u32 val)
	194	{
82487711	195	asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99	196	}
b72d0db9 TG	197
	198	#ifdef CONFIG_PCI
	199	# ifdef CONFIG_ACPI
	200	# define x86_default_pci_init pci_acpi_init
	201	# else
	202	# define x86_default_pci_init pci_legacy_init
	203	# endif
ab3b3793	204	# define x86_default_pci_init_irq pcibios_irq_init
9325a28c	205	# define x86_default_pci_fixup_irqs pcibios_fixup_irqs
b72d0db9 TG	206	#else
b72d0db9 TG	207	# define x86_default_pci_init NULL
ab3b3793	208	# define x86_default_pci_init_irq NULL
9325a28c	209	# define x86_default_pci_fixup_irqs NULL
b72d0db9	210	#endif