Commit | Line | Data |
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1965aae3 PA |
1 | #ifndef _ASM_X86_PARAVIRT_H |
2 | #define _ASM_X86_PARAVIRT_H | |
d3561b7f RR |
3 | /* Various instructions on x86 need to be replaced for |
4 | * para-virtualization: those hooks are defined here. */ | |
b239fb25 JF |
5 | |
6 | #ifdef CONFIG_PARAVIRT | |
54321d94 | 7 | #include <asm/pgtable_types.h> |
658be9d3 | 8 | #include <asm/asm.h> |
d3561b7f | 9 | |
ac5672f8 | 10 | #include <asm/paravirt_types.h> |
ecb93d1c | 11 | |
d3561b7f | 12 | #ifndef __ASSEMBLY__ |
187f1882 | 13 | #include <linux/bug.h> |
3dc494e8 | 14 | #include <linux/types.h> |
d4c10477 | 15 | #include <linux/cpumask.h> |
87b240cb | 16 | #include <asm/frame.h> |
1a45b7aa | 17 | |
faca6227 | 18 | static inline void load_sp0(struct tss_struct *tss, |
d3561b7f RR |
19 | struct thread_struct *thread) |
20 | { | |
faca6227 | 21 | PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread); |
d3561b7f RR |
22 | } |
23 | ||
d3561b7f RR |
24 | /* The paravirtualized CPUID instruction. */ |
25 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, | |
26 | unsigned int *ecx, unsigned int *edx) | |
27 | { | |
93b1eab3 | 28 | PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx); |
d3561b7f RR |
29 | } |
30 | ||
31 | /* | |
32 | * These special macros can be used to get or set a debugging register | |
33 | */ | |
f8822f42 JF |
34 | static inline unsigned long paravirt_get_debugreg(int reg) |
35 | { | |
93b1eab3 | 36 | return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg); |
f8822f42 JF |
37 | } |
38 | #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) | |
39 | static inline void set_debugreg(unsigned long val, int reg) | |
40 | { | |
93b1eab3 | 41 | PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val); |
f8822f42 | 42 | } |
d3561b7f | 43 | |
f8822f42 JF |
44 | static inline void clts(void) |
45 | { | |
93b1eab3 | 46 | PVOP_VCALL0(pv_cpu_ops.clts); |
f8822f42 | 47 | } |
d3561b7f | 48 | |
f8822f42 JF |
49 | static inline unsigned long read_cr0(void) |
50 | { | |
93b1eab3 | 51 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0); |
f8822f42 | 52 | } |
d3561b7f | 53 | |
f8822f42 JF |
54 | static inline void write_cr0(unsigned long x) |
55 | { | |
93b1eab3 | 56 | PVOP_VCALL1(pv_cpu_ops.write_cr0, x); |
f8822f42 JF |
57 | } |
58 | ||
59 | static inline unsigned long read_cr2(void) | |
60 | { | |
93b1eab3 | 61 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2); |
f8822f42 JF |
62 | } |
63 | ||
64 | static inline void write_cr2(unsigned long x) | |
65 | { | |
93b1eab3 | 66 | PVOP_VCALL1(pv_mmu_ops.write_cr2, x); |
f8822f42 JF |
67 | } |
68 | ||
69 | static inline unsigned long read_cr3(void) | |
70 | { | |
93b1eab3 | 71 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3); |
f8822f42 | 72 | } |
d3561b7f | 73 | |
f8822f42 JF |
74 | static inline void write_cr3(unsigned long x) |
75 | { | |
93b1eab3 | 76 | PVOP_VCALL1(pv_mmu_ops.write_cr3, x); |
f8822f42 | 77 | } |
d3561b7f | 78 | |
1e02ce4c | 79 | static inline unsigned long __read_cr4(void) |
f8822f42 | 80 | { |
93b1eab3 | 81 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4); |
f8822f42 | 82 | } |
1e02ce4c | 83 | static inline unsigned long __read_cr4_safe(void) |
f8822f42 | 84 | { |
93b1eab3 | 85 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe); |
f8822f42 | 86 | } |
d3561b7f | 87 | |
1e02ce4c | 88 | static inline void __write_cr4(unsigned long x) |
f8822f42 | 89 | { |
93b1eab3 | 90 | PVOP_VCALL1(pv_cpu_ops.write_cr4, x); |
f8822f42 | 91 | } |
3dc494e8 | 92 | |
94ea03cd | 93 | #ifdef CONFIG_X86_64 |
4c9890c2 GOC |
94 | static inline unsigned long read_cr8(void) |
95 | { | |
96 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8); | |
97 | } | |
98 | ||
99 | static inline void write_cr8(unsigned long x) | |
100 | { | |
101 | PVOP_VCALL1(pv_cpu_ops.write_cr8, x); | |
102 | } | |
94ea03cd | 103 | #endif |
4c9890c2 | 104 | |
df9ee292 | 105 | static inline void arch_safe_halt(void) |
d3561b7f | 106 | { |
93b1eab3 | 107 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
d3561b7f RR |
108 | } |
109 | ||
110 | static inline void halt(void) | |
111 | { | |
c8217b83 | 112 | PVOP_VCALL0(pv_irq_ops.halt); |
f8822f42 JF |
113 | } |
114 | ||
115 | static inline void wbinvd(void) | |
116 | { | |
93b1eab3 | 117 | PVOP_VCALL0(pv_cpu_ops.wbinvd); |
d3561b7f | 118 | } |
d3561b7f | 119 | |
93b1eab3 | 120 | #define get_kernel_rpl() (pv_info.kernel_rpl) |
d3561b7f | 121 | |
dd2f4a00 AL |
122 | static inline u64 paravirt_read_msr(unsigned msr) |
123 | { | |
124 | return PVOP_CALL1(u64, pv_cpu_ops.read_msr, msr); | |
125 | } | |
126 | ||
127 | static inline void paravirt_write_msr(unsigned msr, | |
128 | unsigned low, unsigned high) | |
129 | { | |
130 | return PVOP_VCALL3(pv_cpu_ops.write_msr, msr, low, high); | |
131 | } | |
132 | ||
c2ee03b2 | 133 | static inline u64 paravirt_read_msr_safe(unsigned msr, int *err) |
f8822f42 | 134 | { |
c2ee03b2 | 135 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr_safe, msr, err); |
f8822f42 | 136 | } |
132ec92f | 137 | |
c2ee03b2 AL |
138 | static inline int paravirt_write_msr_safe(unsigned msr, |
139 | unsigned low, unsigned high) | |
f8822f42 | 140 | { |
c2ee03b2 | 141 | return PVOP_CALL3(int, pv_cpu_ops.write_msr_safe, msr, low, high); |
f8822f42 JF |
142 | } |
143 | ||
49cd740b JP |
144 | #define rdmsr(msr, val1, val2) \ |
145 | do { \ | |
4985ce15 | 146 | u64 _l = paravirt_read_msr(msr); \ |
f8822f42 JF |
147 | val1 = (u32)_l; \ |
148 | val2 = _l >> 32; \ | |
49cd740b | 149 | } while (0) |
d3561b7f | 150 | |
49cd740b JP |
151 | #define wrmsr(msr, val1, val2) \ |
152 | do { \ | |
4985ce15 | 153 | paravirt_write_msr(msr, val1, val2); \ |
49cd740b | 154 | } while (0) |
d3561b7f | 155 | |
49cd740b JP |
156 | #define rdmsrl(msr, val) \ |
157 | do { \ | |
4985ce15 | 158 | val = paravirt_read_msr(msr); \ |
49cd740b | 159 | } while (0) |
d3561b7f | 160 | |
47edb651 AL |
161 | static inline void wrmsrl(unsigned msr, u64 val) |
162 | { | |
163 | wrmsr(msr, (u32)val, (u32)(val>>32)); | |
164 | } | |
165 | ||
c2ee03b2 | 166 | #define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b) |
d3561b7f RR |
167 | |
168 | /* rdmsr with exception handling */ | |
c2ee03b2 AL |
169 | #define rdmsr_safe(msr, a, b) \ |
170 | ({ \ | |
171 | int _err; \ | |
172 | u64 _l = paravirt_read_msr_safe(msr, &_err); \ | |
173 | (*a) = (u32)_l; \ | |
174 | (*b) = _l >> 32; \ | |
175 | _err; \ | |
49cd740b | 176 | }) |
d3561b7f | 177 | |
1de87bd4 AK |
178 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
179 | { | |
180 | int err; | |
181 | ||
c2ee03b2 | 182 | *p = paravirt_read_msr_safe(msr, &err); |
1de87bd4 AK |
183 | return err; |
184 | } | |
177fed1e | 185 | |
688340ea JF |
186 | static inline unsigned long long paravirt_sched_clock(void) |
187 | { | |
93b1eab3 | 188 | return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); |
688340ea | 189 | } |
6cb9a835 | 190 | |
c5905afb IM |
191 | struct static_key; |
192 | extern struct static_key paravirt_steal_enabled; | |
193 | extern struct static_key paravirt_steal_rq_enabled; | |
3c404b57 GC |
194 | |
195 | static inline u64 paravirt_steal_clock(int cpu) | |
196 | { | |
197 | return PVOP_CALL1(u64, pv_time_ops.steal_clock, cpu); | |
198 | } | |
199 | ||
f8822f42 JF |
200 | static inline unsigned long long paravirt_read_pmc(int counter) |
201 | { | |
93b1eab3 | 202 | return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); |
f8822f42 | 203 | } |
d3561b7f | 204 | |
49cd740b JP |
205 | #define rdpmc(counter, low, high) \ |
206 | do { \ | |
f8822f42 JF |
207 | u64 _l = paravirt_read_pmc(counter); \ |
208 | low = (u32)_l; \ | |
209 | high = _l >> 32; \ | |
49cd740b | 210 | } while (0) |
3dc494e8 | 211 | |
1ff4d58a AK |
212 | #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter)) |
213 | ||
38ffbe66 JF |
214 | static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) |
215 | { | |
216 | PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries); | |
217 | } | |
218 | ||
219 | static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) | |
220 | { | |
221 | PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries); | |
222 | } | |
223 | ||
f8822f42 JF |
224 | static inline void load_TR_desc(void) |
225 | { | |
93b1eab3 | 226 | PVOP_VCALL0(pv_cpu_ops.load_tr_desc); |
f8822f42 | 227 | } |
6b68f01b | 228 | static inline void load_gdt(const struct desc_ptr *dtr) |
f8822f42 | 229 | { |
93b1eab3 | 230 | PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr); |
f8822f42 | 231 | } |
6b68f01b | 232 | static inline void load_idt(const struct desc_ptr *dtr) |
f8822f42 | 233 | { |
93b1eab3 | 234 | PVOP_VCALL1(pv_cpu_ops.load_idt, dtr); |
f8822f42 JF |
235 | } |
236 | static inline void set_ldt(const void *addr, unsigned entries) | |
237 | { | |
93b1eab3 | 238 | PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries); |
f8822f42 | 239 | } |
6b68f01b | 240 | static inline void store_idt(struct desc_ptr *dtr) |
f8822f42 | 241 | { |
93b1eab3 | 242 | PVOP_VCALL1(pv_cpu_ops.store_idt, dtr); |
f8822f42 JF |
243 | } |
244 | static inline unsigned long paravirt_store_tr(void) | |
245 | { | |
93b1eab3 | 246 | return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr); |
f8822f42 JF |
247 | } |
248 | #define store_tr(tr) ((tr) = paravirt_store_tr()) | |
249 | static inline void load_TLS(struct thread_struct *t, unsigned cpu) | |
250 | { | |
93b1eab3 | 251 | PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); |
f8822f42 | 252 | } |
75b8bb3e | 253 | |
9f9d489a JF |
254 | #ifdef CONFIG_X86_64 |
255 | static inline void load_gs_index(unsigned int gs) | |
256 | { | |
257 | PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs); | |
258 | } | |
259 | #endif | |
260 | ||
75b8bb3e GOC |
261 | static inline void write_ldt_entry(struct desc_struct *dt, int entry, |
262 | const void *desc) | |
f8822f42 | 263 | { |
75b8bb3e | 264 | PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc); |
f8822f42 | 265 | } |
014b15be GOC |
266 | |
267 | static inline void write_gdt_entry(struct desc_struct *dt, int entry, | |
268 | void *desc, int type) | |
f8822f42 | 269 | { |
014b15be | 270 | PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type); |
f8822f42 | 271 | } |
014b15be | 272 | |
8d947344 | 273 | static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) |
f8822f42 | 274 | { |
8d947344 | 275 | PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g); |
f8822f42 JF |
276 | } |
277 | static inline void set_iopl_mask(unsigned mask) | |
278 | { | |
93b1eab3 | 279 | PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask); |
f8822f42 | 280 | } |
3dc494e8 | 281 | |
d3561b7f | 282 | /* The paravirtualized I/O functions */ |
49cd740b JP |
283 | static inline void slow_down_io(void) |
284 | { | |
93b1eab3 | 285 | pv_cpu_ops.io_delay(); |
d3561b7f | 286 | #ifdef REALLY_SLOW_IO |
93b1eab3 JF |
287 | pv_cpu_ops.io_delay(); |
288 | pv_cpu_ops.io_delay(); | |
289 | pv_cpu_ops.io_delay(); | |
d3561b7f RR |
290 | #endif |
291 | } | |
292 | ||
d6dd61c8 JF |
293 | static inline void paravirt_activate_mm(struct mm_struct *prev, |
294 | struct mm_struct *next) | |
295 | { | |
93b1eab3 | 296 | PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next); |
d6dd61c8 JF |
297 | } |
298 | ||
a1ea1c03 DH |
299 | static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm, |
300 | struct mm_struct *mm) | |
d6dd61c8 | 301 | { |
93b1eab3 | 302 | PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm); |
d6dd61c8 JF |
303 | } |
304 | ||
a1ea1c03 | 305 | static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) |
d6dd61c8 | 306 | { |
93b1eab3 | 307 | PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm); |
d6dd61c8 JF |
308 | } |
309 | ||
f8822f42 JF |
310 | static inline void __flush_tlb(void) |
311 | { | |
93b1eab3 | 312 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_user); |
f8822f42 JF |
313 | } |
314 | static inline void __flush_tlb_global(void) | |
315 | { | |
93b1eab3 | 316 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); |
f8822f42 JF |
317 | } |
318 | static inline void __flush_tlb_single(unsigned long addr) | |
319 | { | |
93b1eab3 | 320 | PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); |
f8822f42 | 321 | } |
da181a8b | 322 | |
4595f962 RR |
323 | static inline void flush_tlb_others(const struct cpumask *cpumask, |
324 | struct mm_struct *mm, | |
e7b52ffd AS |
325 | unsigned long start, |
326 | unsigned long end) | |
d4c10477 | 327 | { |
e7b52ffd | 328 | PVOP_VCALL4(pv_mmu_ops.flush_tlb_others, cpumask, mm, start, end); |
d4c10477 JF |
329 | } |
330 | ||
eba0045f JF |
331 | static inline int paravirt_pgd_alloc(struct mm_struct *mm) |
332 | { | |
333 | return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm); | |
334 | } | |
335 | ||
336 | static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd) | |
337 | { | |
338 | PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd); | |
339 | } | |
340 | ||
f8639939 | 341 | static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn) |
f8822f42 | 342 | { |
6944a9c8 | 343 | PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn); |
f8822f42 | 344 | } |
f8639939 | 345 | static inline void paravirt_release_pte(unsigned long pfn) |
f8822f42 | 346 | { |
6944a9c8 | 347 | PVOP_VCALL1(pv_mmu_ops.release_pte, pfn); |
f8822f42 | 348 | } |
c119ecce | 349 | |
f8639939 | 350 | static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn) |
f8822f42 | 351 | { |
6944a9c8 | 352 | PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn); |
f8822f42 | 353 | } |
c119ecce | 354 | |
f8639939 | 355 | static inline void paravirt_release_pmd(unsigned long pfn) |
da181a8b | 356 | { |
6944a9c8 | 357 | PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn); |
da181a8b RR |
358 | } |
359 | ||
f8639939 | 360 | static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn) |
2761fa09 JF |
361 | { |
362 | PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn); | |
363 | } | |
f8639939 | 364 | static inline void paravirt_release_pud(unsigned long pfn) |
2761fa09 JF |
365 | { |
366 | PVOP_VCALL1(pv_mmu_ops.release_pud, pfn); | |
367 | } | |
368 | ||
f8822f42 JF |
369 | static inline void pte_update(struct mm_struct *mm, unsigned long addr, |
370 | pte_t *ptep) | |
da181a8b | 371 | { |
93b1eab3 | 372 | PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep); |
da181a8b | 373 | } |
331127f7 | 374 | |
773221f4 | 375 | static inline pte_t __pte(pteval_t val) |
da181a8b | 376 | { |
773221f4 JF |
377 | pteval_t ret; |
378 | ||
379 | if (sizeof(pteval_t) > sizeof(long)) | |
da5de7c2 JF |
380 | ret = PVOP_CALLEE2(pteval_t, |
381 | pv_mmu_ops.make_pte, | |
382 | val, (u64)val >> 32); | |
773221f4 | 383 | else |
da5de7c2 JF |
384 | ret = PVOP_CALLEE1(pteval_t, |
385 | pv_mmu_ops.make_pte, | |
386 | val); | |
773221f4 | 387 | |
c8e5393a | 388 | return (pte_t) { .pte = ret }; |
da181a8b RR |
389 | } |
390 | ||
773221f4 JF |
391 | static inline pteval_t pte_val(pte_t pte) |
392 | { | |
393 | pteval_t ret; | |
394 | ||
395 | if (sizeof(pteval_t) > sizeof(long)) | |
da5de7c2 JF |
396 | ret = PVOP_CALLEE2(pteval_t, pv_mmu_ops.pte_val, |
397 | pte.pte, (u64)pte.pte >> 32); | |
773221f4 | 398 | else |
da5de7c2 JF |
399 | ret = PVOP_CALLEE1(pteval_t, pv_mmu_ops.pte_val, |
400 | pte.pte); | |
773221f4 JF |
401 | |
402 | return ret; | |
403 | } | |
404 | ||
ef38503e | 405 | static inline pgd_t __pgd(pgdval_t val) |
da181a8b | 406 | { |
ef38503e JF |
407 | pgdval_t ret; |
408 | ||
409 | if (sizeof(pgdval_t) > sizeof(long)) | |
da5de7c2 JF |
410 | ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.make_pgd, |
411 | val, (u64)val >> 32); | |
ef38503e | 412 | else |
da5de7c2 JF |
413 | ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.make_pgd, |
414 | val); | |
ef38503e JF |
415 | |
416 | return (pgd_t) { ret }; | |
417 | } | |
418 | ||
419 | static inline pgdval_t pgd_val(pgd_t pgd) | |
420 | { | |
421 | pgdval_t ret; | |
422 | ||
423 | if (sizeof(pgdval_t) > sizeof(long)) | |
da5de7c2 JF |
424 | ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.pgd_val, |
425 | pgd.pgd, (u64)pgd.pgd >> 32); | |
ef38503e | 426 | else |
da5de7c2 JF |
427 | ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.pgd_val, |
428 | pgd.pgd); | |
ef38503e JF |
429 | |
430 | return ret; | |
f8822f42 JF |
431 | } |
432 | ||
08b882c6 JF |
433 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
434 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, | |
435 | pte_t *ptep) | |
436 | { | |
437 | pteval_t ret; | |
438 | ||
439 | ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start, | |
440 | mm, addr, ptep); | |
441 | ||
442 | return (pte_t) { .pte = ret }; | |
443 | } | |
444 | ||
445 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr, | |
446 | pte_t *ptep, pte_t pte) | |
447 | { | |
448 | if (sizeof(pteval_t) > sizeof(long)) | |
449 | /* 5 arg words */ | |
450 | pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte); | |
451 | else | |
452 | PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit, | |
453 | mm, addr, ptep, pte.pte); | |
454 | } | |
455 | ||
4eed80cd JF |
456 | static inline void set_pte(pte_t *ptep, pte_t pte) |
457 | { | |
458 | if (sizeof(pteval_t) > sizeof(long)) | |
459 | PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, | |
460 | pte.pte, (u64)pte.pte >> 32); | |
461 | else | |
462 | PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, | |
463 | pte.pte); | |
464 | } | |
465 | ||
466 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
467 | pte_t *ptep, pte_t pte) | |
468 | { | |
469 | if (sizeof(pteval_t) > sizeof(long)) | |
470 | /* 5 arg words */ | |
471 | pv_mmu_ops.set_pte_at(mm, addr, ptep, pte); | |
472 | else | |
473 | PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte); | |
474 | } | |
475 | ||
331127f7 AA |
476 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
477 | pmd_t *pmdp, pmd_t pmd) | |
478 | { | |
331127f7 AA |
479 | if (sizeof(pmdval_t) > sizeof(long)) |
480 | /* 5 arg words */ | |
481 | pv_mmu_ops.set_pmd_at(mm, addr, pmdp, pmd); | |
482 | else | |
cacf061c AA |
483 | PVOP_VCALL4(pv_mmu_ops.set_pmd_at, mm, addr, pmdp, |
484 | native_pmd_val(pmd)); | |
331127f7 | 485 | } |
331127f7 | 486 | |
60b3f626 JF |
487 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
488 | { | |
489 | pmdval_t val = native_pmd_val(pmd); | |
490 | ||
491 | if (sizeof(pmdval_t) > sizeof(long)) | |
492 | PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32); | |
493 | else | |
494 | PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val); | |
495 | } | |
496 | ||
98233368 | 497 | #if CONFIG_PGTABLE_LEVELS >= 3 |
1fe91514 GOC |
498 | static inline pmd_t __pmd(pmdval_t val) |
499 | { | |
500 | pmdval_t ret; | |
501 | ||
502 | if (sizeof(pmdval_t) > sizeof(long)) | |
da5de7c2 JF |
503 | ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.make_pmd, |
504 | val, (u64)val >> 32); | |
1fe91514 | 505 | else |
da5de7c2 JF |
506 | ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.make_pmd, |
507 | val); | |
1fe91514 GOC |
508 | |
509 | return (pmd_t) { ret }; | |
510 | } | |
511 | ||
512 | static inline pmdval_t pmd_val(pmd_t pmd) | |
513 | { | |
514 | pmdval_t ret; | |
515 | ||
516 | if (sizeof(pmdval_t) > sizeof(long)) | |
da5de7c2 JF |
517 | ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.pmd_val, |
518 | pmd.pmd, (u64)pmd.pmd >> 32); | |
1fe91514 | 519 | else |
da5de7c2 JF |
520 | ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.pmd_val, |
521 | pmd.pmd); | |
1fe91514 GOC |
522 | |
523 | return ret; | |
524 | } | |
525 | ||
526 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
527 | { | |
528 | pudval_t val = native_pud_val(pud); | |
529 | ||
530 | if (sizeof(pudval_t) > sizeof(long)) | |
531 | PVOP_VCALL3(pv_mmu_ops.set_pud, pudp, | |
532 | val, (u64)val >> 32); | |
533 | else | |
534 | PVOP_VCALL2(pv_mmu_ops.set_pud, pudp, | |
535 | val); | |
536 | } | |
98233368 | 537 | #if CONFIG_PGTABLE_LEVELS == 4 |
9042219c EH |
538 | static inline pud_t __pud(pudval_t val) |
539 | { | |
540 | pudval_t ret; | |
541 | ||
542 | if (sizeof(pudval_t) > sizeof(long)) | |
da5de7c2 JF |
543 | ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.make_pud, |
544 | val, (u64)val >> 32); | |
9042219c | 545 | else |
da5de7c2 JF |
546 | ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.make_pud, |
547 | val); | |
9042219c EH |
548 | |
549 | return (pud_t) { ret }; | |
550 | } | |
551 | ||
552 | static inline pudval_t pud_val(pud_t pud) | |
553 | { | |
554 | pudval_t ret; | |
555 | ||
556 | if (sizeof(pudval_t) > sizeof(long)) | |
4767afbf JF |
557 | ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.pud_val, |
558 | pud.pud, (u64)pud.pud >> 32); | |
9042219c | 559 | else |
4767afbf JF |
560 | ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.pud_val, |
561 | pud.pud); | |
9042219c EH |
562 | |
563 | return ret; | |
564 | } | |
565 | ||
566 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
567 | { | |
568 | pgdval_t val = native_pgd_val(pgd); | |
569 | ||
570 | if (sizeof(pgdval_t) > sizeof(long)) | |
571 | PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp, | |
572 | val, (u64)val >> 32); | |
573 | else | |
574 | PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, | |
575 | val); | |
576 | } | |
577 | ||
578 | static inline void pgd_clear(pgd_t *pgdp) | |
579 | { | |
580 | set_pgd(pgdp, __pgd(0)); | |
581 | } | |
582 | ||
583 | static inline void pud_clear(pud_t *pudp) | |
584 | { | |
585 | set_pud(pudp, __pud(0)); | |
586 | } | |
587 | ||
98233368 | 588 | #endif /* CONFIG_PGTABLE_LEVELS == 4 */ |
9042219c | 589 | |
98233368 | 590 | #endif /* CONFIG_PGTABLE_LEVELS >= 3 */ |
1fe91514 | 591 | |
4eed80cd JF |
592 | #ifdef CONFIG_X86_PAE |
593 | /* Special-case pte-setting operations for PAE, which can't update a | |
594 | 64-bit pte atomically */ | |
595 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
596 | { | |
597 | PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep, | |
598 | pte.pte, pte.pte >> 32); | |
599 | } | |
600 | ||
4eed80cd JF |
601 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
602 | pte_t *ptep) | |
603 | { | |
604 | PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep); | |
605 | } | |
60b3f626 JF |
606 | |
607 | static inline void pmd_clear(pmd_t *pmdp) | |
608 | { | |
609 | PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp); | |
610 | } | |
4eed80cd JF |
611 | #else /* !CONFIG_X86_PAE */ |
612 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
613 | { | |
614 | set_pte(ptep, pte); | |
615 | } | |
616 | ||
4eed80cd JF |
617 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
618 | pte_t *ptep) | |
619 | { | |
620 | set_pte_at(mm, addr, ptep, __pte(0)); | |
621 | } | |
60b3f626 JF |
622 | |
623 | static inline void pmd_clear(pmd_t *pmdp) | |
624 | { | |
625 | set_pmd(pmdp, __pmd(0)); | |
626 | } | |
4eed80cd JF |
627 | #endif /* CONFIG_X86_PAE */ |
628 | ||
7fd7d83d | 629 | #define __HAVE_ARCH_START_CONTEXT_SWITCH |
224101ed | 630 | static inline void arch_start_context_switch(struct task_struct *prev) |
f8822f42 | 631 | { |
224101ed | 632 | PVOP_VCALL1(pv_cpu_ops.start_context_switch, prev); |
f8822f42 JF |
633 | } |
634 | ||
224101ed | 635 | static inline void arch_end_context_switch(struct task_struct *next) |
f8822f42 | 636 | { |
224101ed | 637 | PVOP_VCALL1(pv_cpu_ops.end_context_switch, next); |
f8822f42 JF |
638 | } |
639 | ||
9226d125 | 640 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE |
f8822f42 JF |
641 | static inline void arch_enter_lazy_mmu_mode(void) |
642 | { | |
8965c1c0 | 643 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter); |
f8822f42 JF |
644 | } |
645 | ||
646 | static inline void arch_leave_lazy_mmu_mode(void) | |
647 | { | |
8965c1c0 | 648 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave); |
f8822f42 JF |
649 | } |
650 | ||
511ba86e BO |
651 | static inline void arch_flush_lazy_mmu_mode(void) |
652 | { | |
653 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.flush); | |
654 | } | |
9226d125 | 655 | |
aeaaa59c | 656 | static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx, |
3b3809ac | 657 | phys_addr_t phys, pgprot_t flags) |
aeaaa59c JF |
658 | { |
659 | pv_mmu_ops.set_fixmap(idx, phys, flags); | |
660 | } | |
661 | ||
b4ecc126 | 662 | #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS) |
4bb689ee | 663 | |
62c7a1e9 | 664 | #ifdef CONFIG_QUEUED_SPINLOCKS |
f233f7f1 PZI |
665 | |
666 | static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock, | |
667 | u32 val) | |
668 | { | |
669 | PVOP_VCALL2(pv_lock_ops.queued_spin_lock_slowpath, lock, val); | |
670 | } | |
671 | ||
672 | static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock) | |
673 | { | |
674 | PVOP_VCALLEE1(pv_lock_ops.queued_spin_unlock, lock); | |
675 | } | |
676 | ||
677 | static __always_inline void pv_wait(u8 *ptr, u8 val) | |
678 | { | |
679 | PVOP_VCALL2(pv_lock_ops.wait, ptr, val); | |
680 | } | |
681 | ||
682 | static __always_inline void pv_kick(int cpu) | |
683 | { | |
684 | PVOP_VCALL1(pv_lock_ops.kick, cpu); | |
685 | } | |
686 | ||
62c7a1e9 | 687 | #else /* !CONFIG_QUEUED_SPINLOCKS */ |
f233f7f1 | 688 | |
545ac138 JF |
689 | static __always_inline void __ticket_lock_spinning(struct arch_spinlock *lock, |
690 | __ticket_t ticket) | |
74d4affd | 691 | { |
354714dd | 692 | PVOP_VCALLEE2(pv_lock_ops.lock_spinning, lock, ticket); |
74d4affd JF |
693 | } |
694 | ||
96f853ea | 695 | static __always_inline void __ticket_unlock_kick(struct arch_spinlock *lock, |
545ac138 | 696 | __ticket_t ticket) |
74d4affd | 697 | { |
545ac138 | 698 | PVOP_VCALL2(pv_lock_ops.unlock_kick, lock, ticket); |
74d4affd JF |
699 | } |
700 | ||
62c7a1e9 | 701 | #endif /* CONFIG_QUEUED_SPINLOCKS */ |
f233f7f1 PZI |
702 | |
703 | #endif /* SMP && PARAVIRT_SPINLOCKS */ | |
4bb689ee | 704 | |
2e47d3e6 | 705 | #ifdef CONFIG_X86_32 |
ecb93d1c JF |
706 | #define PV_SAVE_REGS "pushl %ecx; pushl %edx;" |
707 | #define PV_RESTORE_REGS "popl %edx; popl %ecx;" | |
708 | ||
709 | /* save and restore all caller-save registers, except return value */ | |
e584f559 JF |
710 | #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;" |
711 | #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;" | |
ecb93d1c | 712 | |
2e47d3e6 GOC |
713 | #define PV_FLAGS_ARG "0" |
714 | #define PV_EXTRA_CLOBBERS | |
715 | #define PV_VEXTRA_CLOBBERS | |
716 | #else | |
ecb93d1c JF |
717 | /* save and restore all caller-save registers, except return value */ |
718 | #define PV_SAVE_ALL_CALLER_REGS \ | |
719 | "push %rcx;" \ | |
720 | "push %rdx;" \ | |
721 | "push %rsi;" \ | |
722 | "push %rdi;" \ | |
723 | "push %r8;" \ | |
724 | "push %r9;" \ | |
725 | "push %r10;" \ | |
726 | "push %r11;" | |
727 | #define PV_RESTORE_ALL_CALLER_REGS \ | |
728 | "pop %r11;" \ | |
729 | "pop %r10;" \ | |
730 | "pop %r9;" \ | |
731 | "pop %r8;" \ | |
732 | "pop %rdi;" \ | |
733 | "pop %rsi;" \ | |
734 | "pop %rdx;" \ | |
735 | "pop %rcx;" | |
736 | ||
2e47d3e6 GOC |
737 | /* We save some registers, but all of them, that's too much. We clobber all |
738 | * caller saved registers but the argument parameter */ | |
739 | #define PV_SAVE_REGS "pushq %%rdi;" | |
740 | #define PV_RESTORE_REGS "popq %%rdi;" | |
c24481e9 JF |
741 | #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi" |
742 | #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi" | |
2e47d3e6 GOC |
743 | #define PV_FLAGS_ARG "D" |
744 | #endif | |
745 | ||
ecb93d1c JF |
746 | /* |
747 | * Generate a thunk around a function which saves all caller-save | |
748 | * registers except for the return value. This allows C functions to | |
749 | * be called from assembler code where fewer than normal registers are | |
750 | * available. It may also help code generation around calls from C | |
751 | * code if the common case doesn't use many registers. | |
752 | * | |
753 | * When a callee is wrapped in a thunk, the caller can assume that all | |
754 | * arg regs and all scratch registers are preserved across the | |
755 | * call. The return value in rax/eax will not be saved, even for void | |
756 | * functions. | |
757 | */ | |
87b240cb | 758 | #define PV_THUNK_NAME(func) "__raw_callee_save_" #func |
ecb93d1c JF |
759 | #define PV_CALLEE_SAVE_REGS_THUNK(func) \ |
760 | extern typeof(func) __raw_callee_save_##func; \ | |
ecb93d1c JF |
761 | \ |
762 | asm(".pushsection .text;" \ | |
87b240cb JP |
763 | ".globl " PV_THUNK_NAME(func) ";" \ |
764 | ".type " PV_THUNK_NAME(func) ", @function;" \ | |
765 | PV_THUNK_NAME(func) ":" \ | |
766 | FRAME_BEGIN \ | |
ecb93d1c JF |
767 | PV_SAVE_ALL_CALLER_REGS \ |
768 | "call " #func ";" \ | |
769 | PV_RESTORE_ALL_CALLER_REGS \ | |
87b240cb | 770 | FRAME_END \ |
ecb93d1c JF |
771 | "ret;" \ |
772 | ".popsection") | |
773 | ||
774 | /* Get a reference to a callee-save function */ | |
775 | #define PV_CALLEE_SAVE(func) \ | |
776 | ((struct paravirt_callee_save) { __raw_callee_save_##func }) | |
777 | ||
778 | /* Promise that "func" already uses the right calling convention */ | |
779 | #define __PV_IS_CALLEE_SAVE(func) \ | |
780 | ((struct paravirt_callee_save) { func }) | |
781 | ||
b5908548 | 782 | static inline notrace unsigned long arch_local_save_flags(void) |
139ec7c4 | 783 | { |
71999d98 | 784 | return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl); |
139ec7c4 RR |
785 | } |
786 | ||
b5908548 | 787 | static inline notrace void arch_local_irq_restore(unsigned long f) |
139ec7c4 | 788 | { |
71999d98 | 789 | PVOP_VCALLEE1(pv_irq_ops.restore_fl, f); |
139ec7c4 RR |
790 | } |
791 | ||
b5908548 | 792 | static inline notrace void arch_local_irq_disable(void) |
139ec7c4 | 793 | { |
71999d98 | 794 | PVOP_VCALLEE0(pv_irq_ops.irq_disable); |
139ec7c4 RR |
795 | } |
796 | ||
b5908548 | 797 | static inline notrace void arch_local_irq_enable(void) |
139ec7c4 | 798 | { |
71999d98 | 799 | PVOP_VCALLEE0(pv_irq_ops.irq_enable); |
139ec7c4 RR |
800 | } |
801 | ||
b5908548 | 802 | static inline notrace unsigned long arch_local_irq_save(void) |
139ec7c4 RR |
803 | { |
804 | unsigned long f; | |
805 | ||
df9ee292 DH |
806 | f = arch_local_save_flags(); |
807 | arch_local_irq_disable(); | |
139ec7c4 RR |
808 | return f; |
809 | } | |
810 | ||
74d4affd | 811 | |
294688c0 | 812 | /* Make sure as little as possible of this mess escapes. */ |
d5822035 | 813 | #undef PARAVIRT_CALL |
1a45b7aa JF |
814 | #undef __PVOP_CALL |
815 | #undef __PVOP_VCALL | |
f8822f42 JF |
816 | #undef PVOP_VCALL0 |
817 | #undef PVOP_CALL0 | |
818 | #undef PVOP_VCALL1 | |
819 | #undef PVOP_CALL1 | |
820 | #undef PVOP_VCALL2 | |
821 | #undef PVOP_CALL2 | |
822 | #undef PVOP_VCALL3 | |
823 | #undef PVOP_CALL3 | |
824 | #undef PVOP_VCALL4 | |
825 | #undef PVOP_CALL4 | |
139ec7c4 | 826 | |
6f30c1ac TG |
827 | extern void default_banner(void); |
828 | ||
d3561b7f RR |
829 | #else /* __ASSEMBLY__ */ |
830 | ||
658be9d3 | 831 | #define _PVSITE(ptype, clobbers, ops, word, algn) \ |
139ec7c4 RR |
832 | 771:; \ |
833 | ops; \ | |
834 | 772:; \ | |
835 | .pushsection .parainstructions,"a"; \ | |
658be9d3 GOC |
836 | .align algn; \ |
837 | word 771b; \ | |
139ec7c4 RR |
838 | .byte ptype; \ |
839 | .byte 772b-771b; \ | |
840 | .short clobbers; \ | |
841 | .popsection | |
842 | ||
658be9d3 | 843 | |
9104a18d | 844 | #define COND_PUSH(set, mask, reg) \ |
ecb93d1c | 845 | .if ((~(set)) & mask); push %reg; .endif |
9104a18d | 846 | #define COND_POP(set, mask, reg) \ |
ecb93d1c | 847 | .if ((~(set)) & mask); pop %reg; .endif |
9104a18d | 848 | |
658be9d3 | 849 | #ifdef CONFIG_X86_64 |
9104a18d JF |
850 | |
851 | #define PV_SAVE_REGS(set) \ | |
852 | COND_PUSH(set, CLBR_RAX, rax); \ | |
853 | COND_PUSH(set, CLBR_RCX, rcx); \ | |
854 | COND_PUSH(set, CLBR_RDX, rdx); \ | |
855 | COND_PUSH(set, CLBR_RSI, rsi); \ | |
856 | COND_PUSH(set, CLBR_RDI, rdi); \ | |
857 | COND_PUSH(set, CLBR_R8, r8); \ | |
858 | COND_PUSH(set, CLBR_R9, r9); \ | |
859 | COND_PUSH(set, CLBR_R10, r10); \ | |
860 | COND_PUSH(set, CLBR_R11, r11) | |
861 | #define PV_RESTORE_REGS(set) \ | |
862 | COND_POP(set, CLBR_R11, r11); \ | |
863 | COND_POP(set, CLBR_R10, r10); \ | |
864 | COND_POP(set, CLBR_R9, r9); \ | |
865 | COND_POP(set, CLBR_R8, r8); \ | |
866 | COND_POP(set, CLBR_RDI, rdi); \ | |
867 | COND_POP(set, CLBR_RSI, rsi); \ | |
868 | COND_POP(set, CLBR_RDX, rdx); \ | |
869 | COND_POP(set, CLBR_RCX, rcx); \ | |
870 | COND_POP(set, CLBR_RAX, rax) | |
871 | ||
6057fc82 | 872 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8) |
658be9d3 | 873 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8) |
491eccb7 | 874 | #define PARA_INDIRECT(addr) *addr(%rip) |
658be9d3 | 875 | #else |
9104a18d JF |
876 | #define PV_SAVE_REGS(set) \ |
877 | COND_PUSH(set, CLBR_EAX, eax); \ | |
878 | COND_PUSH(set, CLBR_EDI, edi); \ | |
879 | COND_PUSH(set, CLBR_ECX, ecx); \ | |
880 | COND_PUSH(set, CLBR_EDX, edx) | |
881 | #define PV_RESTORE_REGS(set) \ | |
882 | COND_POP(set, CLBR_EDX, edx); \ | |
883 | COND_POP(set, CLBR_ECX, ecx); \ | |
884 | COND_POP(set, CLBR_EDI, edi); \ | |
885 | COND_POP(set, CLBR_EAX, eax) | |
886 | ||
6057fc82 | 887 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) |
658be9d3 | 888 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4) |
491eccb7 | 889 | #define PARA_INDIRECT(addr) *%cs:addr |
658be9d3 GOC |
890 | #endif |
891 | ||
93b1eab3 JF |
892 | #define INTERRUPT_RETURN \ |
893 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ | |
491eccb7 | 894 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret)) |
d5822035 JF |
895 | |
896 | #define DISABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 897 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ |
ecb93d1c | 898 | PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
491eccb7 | 899 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \ |
ecb93d1c | 900 | PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
d5822035 JF |
901 | |
902 | #define ENABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 903 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ |
ecb93d1c | 904 | PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \ |
491eccb7 | 905 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \ |
ecb93d1c | 906 | PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);) |
d5822035 | 907 | |
6057fc82 | 908 | #ifdef CONFIG_X86_32 |
491eccb7 JF |
909 | #define GET_CR0_INTO_EAX \ |
910 | push %ecx; push %edx; \ | |
911 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \ | |
42c24fa2 | 912 | pop %edx; pop %ecx |
2be29982 | 913 | #else /* !CONFIG_X86_32 */ |
a00394f8 JF |
914 | |
915 | /* | |
916 | * If swapgs is used while the userspace stack is still current, | |
917 | * there's no way to call a pvop. The PV replacement *must* be | |
918 | * inlined, or the swapgs instruction must be trapped and emulated. | |
919 | */ | |
920 | #define SWAPGS_UNSAFE_STACK \ | |
921 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
922 | swapgs) | |
923 | ||
9104a18d JF |
924 | /* |
925 | * Note: swapgs is very special, and in practise is either going to be | |
926 | * implemented with a single "swapgs" instruction or something very | |
927 | * special. Either way, we don't need to save any registers for | |
928 | * it. | |
929 | */ | |
e801f864 GOC |
930 | #define SWAPGS \ |
931 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
9104a18d | 932 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs) \ |
e801f864 GOC |
933 | ) |
934 | ||
ffc4bc9c PA |
935 | #define GET_CR2_INTO_RAX \ |
936 | call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2) | |
4a8c4c4e | 937 | |
fab58420 JF |
938 | #define PARAVIRT_ADJUST_EXCEPTION_FRAME \ |
939 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \ | |
940 | CLBR_NONE, \ | |
941 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_adjust_exception_frame)) | |
942 | ||
2be29982 JF |
943 | #define USERGS_SYSRET64 \ |
944 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \ | |
d75cd22f | 945 | CLBR_NONE, \ |
2be29982 | 946 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64)) |
2be29982 | 947 | #endif /* CONFIG_X86_32 */ |
139ec7c4 | 948 | |
d3561b7f | 949 | #endif /* __ASSEMBLY__ */ |
6f30c1ac TG |
950 | #else /* CONFIG_PARAVIRT */ |
951 | # define default_banner x86_init_noop | |
a1ea1c03 DH |
952 | #ifndef __ASSEMBLY__ |
953 | static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm, | |
954 | struct mm_struct *mm) | |
955 | { | |
956 | } | |
957 | ||
958 | static inline void paravirt_arch_exit_mmap(struct mm_struct *mm) | |
959 | { | |
960 | } | |
961 | #endif /* __ASSEMBLY__ */ | |
6f30c1ac | 962 | #endif /* !CONFIG_PARAVIRT */ |
1965aae3 | 963 | #endif /* _ASM_X86_PARAVIRT_H */ |