Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1965aae3 PA |
2 | #ifndef _ASM_X86_MSR_INDEX_H |
3 | #define _ASM_X86_MSR_INDEX_H | |
4bc5aa91 | 4 | |
d8eabc37 TG |
5 | #include <linux/bits.h> |
6 | ||
97fa21f6 | 7 | /* CPU model specific register (MSR) numbers. */ |
4bc5aa91 PA |
8 | |
9 | /* x86-64 specific MSRs */ | |
10 | #define MSR_EFER 0xc0000080 /* extended feature register */ | |
11 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ | |
12 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ | |
13 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ | |
14 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ | |
15 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ | |
16 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ | |
17 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ | |
5df97400 | 18 | #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ |
4bc5aa91 PA |
19 | |
20 | /* EFER bits: */ | |
21 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ | |
22 | #define _EFER_LME 8 /* Long mode enable */ | |
23 | #define _EFER_LMA 10 /* Long mode active (read-only) */ | |
24 | #define _EFER_NX 11 /* No execute enable */ | |
9962d032 | 25 | #define _EFER_SVME 12 /* Enable virtualization */ |
eec4b140 | 26 | #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ |
d2062693 | 27 | #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ |
e7862eda | 28 | #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ |
4bc5aa91 PA |
29 | |
30 | #define EFER_SCE (1<<_EFER_SCE) | |
31 | #define EFER_LME (1<<_EFER_LME) | |
32 | #define EFER_LMA (1<<_EFER_LMA) | |
33 | #define EFER_NX (1<<_EFER_NX) | |
9962d032 | 34 | #define EFER_SVME (1<<_EFER_SVME) |
eec4b140 | 35 | #define EFER_LMSLE (1<<_EFER_LMSLE) |
d2062693 | 36 | #define EFER_FFXSR (1<<_EFER_FFXSR) |
e7862eda | 37 | #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) |
4bc5aa91 PA |
38 | |
39 | /* Intel MSRs. Some also available on other CPUs */ | |
3f5a7896 | 40 | |
6650cdd9 PZI |
41 | #define MSR_TEST_CTRL 0x00000033 |
42 | #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 | |
43 | #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) | |
44 | ||
1e340c60 | 45 | #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ |
d8eabc37 | 46 | #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ |
5bfbe3ad | 47 | #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ |
d8eabc37 | 48 | #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ |
9f65fb29 | 49 | #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ |
d8eabc37 | 50 | #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ |
4ad3278d PG |
51 | #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ |
52 | #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) | |
1e340c60 | 53 | |
0125acda BL |
54 | /* A mask for bits which the kernel toggles when controlling mitigations */ |
55 | #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ | |
56 | | SPEC_CTRL_RRSBA_DIS_S) | |
57 | ||
1e340c60 | 58 | #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ |
d8eabc37 | 59 | #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ |
1b5277c0 | 60 | #define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */ |
1e340c60 | 61 | |
3f5a7896 TL |
62 | #define MSR_PPIN_CTL 0x0000004e |
63 | #define MSR_PPIN 0x0000004f | |
64 | ||
4bc5aa91 PA |
65 | #define MSR_IA32_PERFCTR0 0x000000c1 |
66 | #define MSR_IA32_PERFCTR1 0x000000c2 | |
67 | #define MSR_FSB_FREQ 0x000000cd | |
5369a21e | 68 | #define MSR_PLATFORM_INFO 0x000000ce |
90218ac7 KH |
69 | #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 |
70 | #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) | |
4bc5aa91 | 71 | |
bd688c69 FY |
72 | #define MSR_IA32_UMWAIT_CONTROL 0xe1 |
73 | #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) | |
74 | #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) | |
75 | /* | |
76 | * The time field is bit[31:2], but representing a 32bit value with | |
77 | * bit[1:0] zero. | |
78 | */ | |
79 | #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) | |
80 | ||
6650cdd9 PZI |
81 | /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ |
82 | #define MSR_IA32_CORE_CAPS 0x000000cf | |
db1af129 TL |
83 | #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 |
84 | #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) | |
6650cdd9 PZI |
85 | #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 |
86 | #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) | |
87 | ||
40496c8e | 88 | #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 |
14796fca LB |
89 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) |
90 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) | |
bfb53ccf | 91 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
a00072a2 MT |
92 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) |
93 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) | |
14796fca | 94 | |
4bc5aa91 | 95 | #define MSR_MTRRcap 0x000000fe |
1e340c60 DW |
96 | |
97 | #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a | |
d8eabc37 TG |
98 | #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ |
99 | #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ | |
6ad0ad2b | 100 | #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ |
d8eabc37 TG |
101 | #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ |
102 | #define ARCH_CAP_SSB_NO BIT(4) /* | |
103 | * Not susceptible to Speculative Store Bypass | |
104 | * attack, so no Speculative Store Bypass | |
105 | * control required. | |
106 | */ | |
ed5194c2 AK |
107 | #define ARCH_CAP_MDS_NO BIT(5) /* |
108 | * Not susceptible to | |
109 | * Microarchitectural Data | |
110 | * Sampling (MDS) vulnerabilities. | |
111 | */ | |
db4d30fb VT |
112 | #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* |
113 | * The processor is not susceptible to a | |
114 | * machine check error due to modifying the | |
115 | * code page size along with either the | |
116 | * physical address or cache type | |
117 | * without TLB invalidation. | |
118 | */ | |
c2955f27 | 119 | #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ |
1b42f017 PG |
120 | #define ARCH_CAP_TAA_NO BIT(8) /* |
121 | * Not susceptible to | |
122 | * TSX Async Abort (TAA) vulnerabilities. | |
123 | */ | |
51802186 PG |
124 | #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* |
125 | * Not susceptible to SBDR and SSDP | |
126 | * variants of Processor MMIO stale data | |
127 | * vulnerabilities. | |
128 | */ | |
129 | #define ARCH_CAP_FBSDP_NO BIT(14) /* | |
130 | * Not susceptible to FBSDP variant of | |
131 | * Processor MMIO stale data | |
132 | * vulnerabilities. | |
133 | */ | |
134 | #define ARCH_CAP_PSDP_NO BIT(15) /* | |
135 | * Not susceptible to PSDP variant of | |
136 | * Processor MMIO stale data | |
137 | * vulnerabilities. | |
138 | */ | |
139 | #define ARCH_CAP_FB_CLEAR BIT(17) /* | |
140 | * VERW clears CPU fill buffer | |
141 | * even on MDS_NO CPUs. | |
142 | */ | |
027bbb88 PG |
143 | #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* |
144 | * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] | |
145 | * bit available to control VERW | |
146 | * behavior. | |
147 | */ | |
4ad3278d PG |
148 | #define ARCH_CAP_RRSBA BIT(19) /* |
149 | * Indicates RET may use predictors | |
150 | * other than the RSB. With eIBRS | |
151 | * enabled predictions in kernel mode | |
152 | * are restricted to targets in | |
153 | * kernel. | |
154 | */ | |
2b129932 DS |
155 | #define ARCH_CAP_PBRSB_NO BIT(24) /* |
156 | * Not susceptible to Post-Barrier | |
157 | * Return Stack Buffer Predictions. | |
158 | */ | |
8974eb58 DS |
159 | #define ARCH_CAP_GDS_CTRL BIT(25) /* |
160 | * CPU is vulnerable to Gather | |
161 | * Data Sampling (GDS) and | |
162 | * has controls for mitigation. | |
163 | */ | |
164 | #define ARCH_CAP_GDS_NO BIT(26) /* | |
165 | * CPU is not vulnerable to Gather | |
166 | * Data Sampling (GDS). | |
167 | */ | |
1e340c60 | 168 | |
b8d1d163 DS |
169 | #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* |
170 | * IA32_XAPIC_DISABLE_STATUS MSR | |
171 | * supported | |
172 | */ | |
173 | ||
3fa045be | 174 | #define MSR_IA32_FLUSH_CMD 0x0000010b |
d8eabc37 TG |
175 | #define L1D_FLUSH BIT(0) /* |
176 | * Writeback and invalidate the | |
177 | * L1 data cache. | |
178 | */ | |
3fa045be | 179 | |
4bc5aa91 | 180 | #define MSR_IA32_BBL_CR_CTL 0x00000119 |
91c9c3ed | 181 | #define MSR_IA32_BBL_CR_CTL3 0x0000011e |
4bc5aa91 | 182 | |
c2955f27 PG |
183 | #define MSR_IA32_TSX_CTRL 0x00000122 |
184 | #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ | |
185 | #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ | |
186 | ||
7e5b3c26 | 187 | #define MSR_IA32_MCU_OPT_CTRL 0x00000123 |
400331f8 PG |
188 | #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ |
189 | #define RTM_ALLOW BIT(1) /* TSX development mode */ | |
027bbb88 | 190 | #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ |
8974eb58 DS |
191 | #define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ |
192 | #define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ | |
7e5b3c26 | 193 | |
4bc5aa91 PA |
194 | #define MSR_IA32_SYSENTER_CS 0x00000174 |
195 | #define MSR_IA32_SYSENTER_ESP 0x00000175 | |
196 | #define MSR_IA32_SYSENTER_EIP 0x00000176 | |
197 | ||
198 | #define MSR_IA32_MCG_CAP 0x00000179 | |
199 | #define MSR_IA32_MCG_STATUS 0x0000017a | |
200 | #define MSR_IA32_MCG_CTL 0x0000017b | |
68299a42 | 201 | #define MSR_ERROR_CONTROL 0x0000017f |
bc12edb8 | 202 | #define MSR_IA32_MCG_EXT_CTL 0x000004d0 |
4bc5aa91 | 203 | |
a7e3ed1e AK |
204 | #define MSR_OFFCORE_RSP_0 0x000001a6 |
205 | #define MSR_OFFCORE_RSP_1 0x000001a7 | |
c4d30668 LB |
206 | #define MSR_TURBO_RATIO_LIMIT 0x000001ad |
207 | #define MSR_TURBO_RATIO_LIMIT1 0x000001ae | |
208 | #define MSR_TURBO_RATIO_LIMIT2 0x000001af | |
a7e3ed1e | 209 | |
38aaf921 KL |
210 | #define MSR_SNOOP_RSP_0 0x00001328 |
211 | #define MSR_SNOOP_RSP_1 0x00001329 | |
212 | ||
225ce539 SE |
213 | #define MSR_LBR_SELECT 0x000001c8 |
214 | #define MSR_LBR_TOS 0x000001c9 | |
ed7bde7a SP |
215 | |
216 | #define MSR_IA32_POWER_CTL 0x000001fc | |
217 | #define MSR_IA32_POWER_CTL_BIT_EE 19 | |
218 | ||
db1af129 TL |
219 | /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ |
220 | #define MSR_INTEGRITY_CAPS 0x000002d9 | |
c68e3d47 JJ |
221 | #define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 |
222 | #define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) | |
db1af129 TL |
223 | #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 |
224 | #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) | |
225 | ||
225ce539 SE |
226 | #define MSR_LBR_NHM_FROM 0x00000680 |
227 | #define MSR_LBR_NHM_TO 0x000006c0 | |
228 | #define MSR_LBR_CORE_FROM 0x00000040 | |
229 | #define MSR_LBR_CORE_TO 0x00000060 | |
230 | ||
b83ff1c8 AK |
231 | #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ |
232 | #define LBR_INFO_MISPRED BIT_ULL(63) | |
233 | #define LBR_INFO_IN_TX BIT_ULL(62) | |
234 | #define LBR_INFO_ABORT BIT_ULL(61) | |
d6a162a4 | 235 | #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) |
b83ff1c8 | 236 | #define LBR_INFO_CYCLES 0xffff |
d6a162a4 KL |
237 | #define LBR_INFO_BR_TYPE_OFFSET 56 |
238 | #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) | |
239 | ||
240 | #define MSR_ARCH_LBR_CTL 0x000014ce | |
241 | #define ARCH_LBR_CTL_LBREN BIT(0) | |
242 | #define ARCH_LBR_CTL_CPL_OFFSET 1 | |
243 | #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) | |
244 | #define ARCH_LBR_CTL_STACK_OFFSET 3 | |
245 | #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) | |
246 | #define ARCH_LBR_CTL_FILTER_OFFSET 16 | |
247 | #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) | |
248 | #define MSR_ARCH_LBR_DEPTH 0x000014cf | |
249 | #define MSR_ARCH_LBR_FROM_0 0x00001500 | |
250 | #define MSR_ARCH_LBR_TO_0 0x00001600 | |
251 | #define MSR_ARCH_LBR_INFO_0 0x00001200 | |
b83ff1c8 | 252 | |
4bc5aa91 | 253 | #define MSR_IA32_PEBS_ENABLE 0x000003f1 |
c22497f5 | 254 | #define MSR_PEBS_DATA_CFG 0x000003f2 |
4bc5aa91 PA |
255 | #define MSR_IA32_DS_AREA 0x00000600 |
256 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345 | |
d0946a88 KL |
257 | #define PERF_CAP_METRICS_IDX 15 |
258 | #define PERF_CAP_PT_IDX 16 | |
259 | ||
f20093ee | 260 | #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 |
c59a1f10 LX |
261 | #define PERF_CAP_PEBS_TRAP BIT_ULL(6) |
262 | #define PERF_CAP_ARCH_REG BIT_ULL(7) | |
263 | #define PERF_CAP_PEBS_FORMAT 0xf00 | |
264 | #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) | |
265 | #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ | |
266 | PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) | |
4bc5aa91 | 267 | |
52ca9ced | 268 | #define MSR_IA32_RTIT_CTL 0x00000570 |
887eda13 CP |
269 | #define RTIT_CTL_TRACEEN BIT(0) |
270 | #define RTIT_CTL_CYCLEACC BIT(1) | |
271 | #define RTIT_CTL_OS BIT(2) | |
272 | #define RTIT_CTL_USR BIT(3) | |
273 | #define RTIT_CTL_PWR_EVT_EN BIT(4) | |
274 | #define RTIT_CTL_FUP_ON_PTW BIT(5) | |
69843a91 | 275 | #define RTIT_CTL_FABRIC_EN BIT(6) |
887eda13 CP |
276 | #define RTIT_CTL_CR3EN BIT(7) |
277 | #define RTIT_CTL_TOPA BIT(8) | |
278 | #define RTIT_CTL_MTC_EN BIT(9) | |
279 | #define RTIT_CTL_TSC_EN BIT(10) | |
280 | #define RTIT_CTL_DISRETC BIT(11) | |
281 | #define RTIT_CTL_PTW_EN BIT(12) | |
282 | #define RTIT_CTL_BRANCH_EN BIT(13) | |
28c24ded | 283 | #define RTIT_CTL_EVENT_EN BIT(31) |
161a9a33 | 284 | #define RTIT_CTL_NOTNT BIT_ULL(55) |
887eda13 CP |
285 | #define RTIT_CTL_MTC_RANGE_OFFSET 14 |
286 | #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) | |
287 | #define RTIT_CTL_CYC_THRESH_OFFSET 19 | |
288 | #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) | |
289 | #define RTIT_CTL_PSB_FREQ_OFFSET 24 | |
290 | #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) | |
291 | #define RTIT_CTL_ADDR0_OFFSET 32 | |
292 | #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) | |
293 | #define RTIT_CTL_ADDR1_OFFSET 36 | |
294 | #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) | |
295 | #define RTIT_CTL_ADDR2_OFFSET 40 | |
296 | #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) | |
297 | #define RTIT_CTL_ADDR3_OFFSET 44 | |
298 | #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) | |
52ca9ced | 299 | #define MSR_IA32_RTIT_STATUS 0x00000571 |
887eda13 CP |
300 | #define RTIT_STATUS_FILTEREN BIT(0) |
301 | #define RTIT_STATUS_CONTEXTEN BIT(1) | |
302 | #define RTIT_STATUS_TRIGGEREN BIT(2) | |
303 | #define RTIT_STATUS_BUFFOVF BIT(3) | |
304 | #define RTIT_STATUS_ERROR BIT(4) | |
305 | #define RTIT_STATUS_STOPPED BIT(5) | |
69843a91 LK |
306 | #define RTIT_STATUS_BYTECNT_OFFSET 32 |
307 | #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) | |
f127fa09 AS |
308 | #define MSR_IA32_RTIT_ADDR0_A 0x00000580 |
309 | #define MSR_IA32_RTIT_ADDR0_B 0x00000581 | |
310 | #define MSR_IA32_RTIT_ADDR1_A 0x00000582 | |
311 | #define MSR_IA32_RTIT_ADDR1_B 0x00000583 | |
312 | #define MSR_IA32_RTIT_ADDR2_A 0x00000584 | |
313 | #define MSR_IA32_RTIT_ADDR2_B 0x00000585 | |
314 | #define MSR_IA32_RTIT_ADDR3_A 0x00000586 | |
315 | #define MSR_IA32_RTIT_ADDR3_B 0x00000587 | |
52ca9ced AS |
316 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 |
317 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 | |
318 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 | |
319 | ||
4bc5aa91 PA |
320 | #define MSR_MTRRfix64K_00000 0x00000250 |
321 | #define MSR_MTRRfix16K_80000 0x00000258 | |
322 | #define MSR_MTRRfix16K_A0000 0x00000259 | |
323 | #define MSR_MTRRfix4K_C0000 0x00000268 | |
324 | #define MSR_MTRRfix4K_C8000 0x00000269 | |
325 | #define MSR_MTRRfix4K_D0000 0x0000026a | |
326 | #define MSR_MTRRfix4K_D8000 0x0000026b | |
327 | #define MSR_MTRRfix4K_E0000 0x0000026c | |
328 | #define MSR_MTRRfix4K_E8000 0x0000026d | |
329 | #define MSR_MTRRfix4K_F0000 0x0000026e | |
330 | #define MSR_MTRRfix4K_F8000 0x0000026f | |
331 | #define MSR_MTRRdefType 0x000002ff | |
332 | ||
2e5d9c85 | 333 | #define MSR_IA32_CR_PAT 0x00000277 |
334 | ||
4bc5aa91 PA |
335 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 |
336 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db | |
337 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc | |
338 | #define MSR_IA32_LASTINTFROMIP 0x000001dd | |
339 | #define MSR_IA32_LASTINTTOIP 0x000001de | |
340 | ||
f0f2f9fe FY |
341 | #define MSR_IA32_PASID 0x00000d93 |
342 | #define MSR_IA32_PASID_VALID BIT_ULL(31) | |
343 | ||
d2499d8b | 344 | /* DEBUGCTLMSR bits (others vary by model): */ |
7c5ecaf7 | 345 | #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ |
b9894a2f | 346 | #define DEBUGCTLMSR_BTF_SHIFT 1 |
7c5ecaf7 | 347 | #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ |
ebb1064e | 348 | #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) |
7c5ecaf7 PZ |
349 | #define DEBUGCTLMSR_TR (1UL << 6) |
350 | #define DEBUGCTLMSR_BTS (1UL << 7) | |
351 | #define DEBUGCTLMSR_BTINT (1UL << 8) | |
352 | #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) | |
353 | #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) | |
354 | #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) | |
af3bdb99 | 355 | #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) |
6089327f KL |
356 | #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 |
357 | #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) | |
d2499d8b | 358 | |
d0dc8494 AK |
359 | #define MSR_PEBS_FRONTEND 0x000003f7 |
360 | ||
4bc5aa91 PA |
361 | #define MSR_IA32_MC0_CTL 0x00000400 |
362 | #define MSR_IA32_MC0_STATUS 0x00000401 | |
363 | #define MSR_IA32_MC0_ADDR 0x00000402 | |
364 | #define MSR_IA32_MC0_MISC 0x00000403 | |
365 | ||
9c63a650 LB |
366 | /* C-state Residency Counters */ |
367 | #define MSR_PKG_C3_RESIDENCY 0x000003f8 | |
368 | #define MSR_PKG_C6_RESIDENCY 0x000003f9 | |
0539ba11 | 369 | #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa |
9c63a650 LB |
370 | #define MSR_PKG_C7_RESIDENCY 0x000003fa |
371 | #define MSR_CORE_C3_RESIDENCY 0x000003fc | |
372 | #define MSR_CORE_C6_RESIDENCY 0x000003fd | |
373 | #define MSR_CORE_C7_RESIDENCY 0x000003fe | |
fb5d4327 | 374 | #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff |
9c63a650 | 375 | #define MSR_PKG_C2_RESIDENCY 0x0000060d |
ca58710f KCA |
376 | #define MSR_PKG_C8_RESIDENCY 0x00000630 |
377 | #define MSR_PKG_C9_RESIDENCY 0x00000631 | |
378 | #define MSR_PKG_C10_RESIDENCY 0x00000632 | |
9c63a650 | 379 | |
5a63426e LB |
380 | /* Interrupt Response Limit */ |
381 | #define MSR_PKGC3_IRTL 0x0000060a | |
382 | #define MSR_PKGC6_IRTL 0x0000060b | |
383 | #define MSR_PKGC7_IRTL 0x0000060c | |
384 | #define MSR_PKGC8_IRTL 0x00000633 | |
385 | #define MSR_PKGC9_IRTL 0x00000634 | |
386 | #define MSR_PKGC10_IRTL 0x00000635 | |
387 | ||
3fc808aa LB |
388 | /* Run Time Average Power Limiting (RAPL) Interface */ |
389 | ||
f52ba931 | 390 | #define MSR_VR_CURRENT_CONFIG 0x00000601 |
3fc808aa LB |
391 | #define MSR_RAPL_POWER_UNIT 0x00000606 |
392 | ||
393 | #define MSR_PKG_POWER_LIMIT 0x00000610 | |
394 | #define MSR_PKG_ENERGY_STATUS 0x00000611 | |
395 | #define MSR_PKG_PERF_STATUS 0x00000613 | |
396 | #define MSR_PKG_POWER_INFO 0x00000614 | |
397 | ||
398 | #define MSR_DRAM_POWER_LIMIT 0x00000618 | |
399 | #define MSR_DRAM_ENERGY_STATUS 0x00000619 | |
400 | #define MSR_DRAM_PERF_STATUS 0x0000061b | |
401 | #define MSR_DRAM_POWER_INFO 0x0000061c | |
402 | ||
403 | #define MSR_PP0_POWER_LIMIT 0x00000638 | |
404 | #define MSR_PP0_ENERGY_STATUS 0x00000639 | |
405 | #define MSR_PP0_POLICY 0x0000063a | |
406 | #define MSR_PP0_PERF_STATUS 0x0000063b | |
407 | ||
408 | #define MSR_PP1_POWER_LIMIT 0x00000640 | |
409 | #define MSR_PP1_ENERGY_STATUS 0x00000641 | |
410 | #define MSR_PP1_POLICY 0x00000642 | |
411 | ||
5cde2653 | 412 | #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 |
43756a29 | 413 | #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a |
298ed2b3 | 414 | #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b |
5cde2653 | 415 | |
4a6772f5 | 416 | /* Config TDP MSRs */ |
6fb3143b LB |
417 | #define MSR_CONFIG_TDP_NOMINAL 0x00000648 |
418 | #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 | |
419 | #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A | |
420 | #define MSR_CONFIG_TDP_CONTROL 0x0000064B | |
421 | #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C | |
422 | ||
dcee75b3 | 423 | #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D |
4af184ee | 424 | #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 |
dcee75b3 | 425 | |
0b2bb692 LB |
426 | #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 |
427 | #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 | |
428 | #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A | |
429 | #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B | |
430 | ||
144b44b1 | 431 | #define MSR_CORE_C1_RES 0x00000660 |
0539ba11 | 432 | #define MSR_MODULE_C6_RES_MS 0x00000664 |
144b44b1 | 433 | |
8c058d53 LB |
434 | #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 |
435 | #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 | |
436 | ||
8a34fd02 LB |
437 | #define MSR_ATOM_CORE_RATIOS 0x0000066a |
438 | #define MSR_ATOM_CORE_VIDS 0x0000066b | |
439 | #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c | |
440 | #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d | |
441 | ||
3a9a941d LB |
442 | #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 |
443 | #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 | |
444 | #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 | |
445 | ||
991625f3 PZ |
446 | /* Control-flow Enforcement Technology MSRs */ |
447 | #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ | |
448 | #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ | |
449 | #define CET_SHSTK_EN BIT_ULL(0) | |
450 | #define CET_WRSS_EN BIT_ULL(1) | |
451 | #define CET_ENDBR_EN BIT_ULL(2) | |
452 | #define CET_LEG_IW_EN BIT_ULL(3) | |
453 | #define CET_NO_TRACK_EN BIT_ULL(4) | |
454 | #define CET_SUPPRESS_DISABLE BIT_ULL(5) | |
455 | #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) | |
456 | #define CET_SUPPRESS BIT_ULL(10) | |
457 | #define CET_WAIT_ENDBR BIT_ULL(11) | |
458 | ||
459 | #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ | |
460 | #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ | |
461 | #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ | |
462 | #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ | |
463 | #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ | |
464 | ||
2f86dc4c DB |
465 | /* Hardware P state interface */ |
466 | #define MSR_PPERF 0x0000064e | |
467 | #define MSR_PERF_LIMIT_REASONS 0x0000064f | |
468 | #define MSR_PM_ENABLE 0x00000770 | |
469 | #define MSR_HWP_CAPABILITIES 0x00000771 | |
470 | #define MSR_HWP_REQUEST_PKG 0x00000772 | |
471 | #define MSR_HWP_INTERRUPT 0x00000773 | |
472 | #define MSR_HWP_REQUEST 0x00000774 | |
473 | #define MSR_HWP_STATUS 0x00000777 | |
474 | ||
475 | /* CPUID.6.EAX */ | |
476 | #define HWP_BASE_BIT (1<<7) | |
477 | #define HWP_NOTIFICATIONS_BIT (1<<8) | |
478 | #define HWP_ACTIVITY_WINDOW_BIT (1<<9) | |
479 | #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) | |
480 | #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) | |
481 | ||
482 | /* IA32_HWP_CAPABILITIES */ | |
670e27d8 LB |
483 | #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) |
484 | #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) | |
485 | #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) | |
486 | #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) | |
2f86dc4c DB |
487 | |
488 | /* IA32_HWP_REQUEST */ | |
489 | #define HWP_MIN_PERF(x) (x & 0xff) | |
490 | #define HWP_MAX_PERF(x) ((x & 0xff) << 8) | |
491 | #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) | |
2fc49cb0 | 492 | #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) |
8d84e906 LB |
493 | #define HWP_EPP_PERFORMANCE 0x00 |
494 | #define HWP_EPP_BALANCE_PERFORMANCE 0x80 | |
495 | #define HWP_EPP_BALANCE_POWERSAVE 0xC0 | |
496 | #define HWP_EPP_POWERSAVE 0xFF | |
2fc49cb0 LB |
497 | #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) |
498 | #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) | |
2f86dc4c DB |
499 | |
500 | /* IA32_HWP_STATUS */ | |
501 | #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) | |
502 | #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) | |
503 | ||
504 | /* IA32_HWP_INTERRUPT */ | |
505 | #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) | |
506 | #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) | |
507 | ||
5bbc097d JR |
508 | #define MSR_AMD64_MC0_MASK 0xc0010044 |
509 | ||
a2d32bcb AK |
510 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |
511 | #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) | |
512 | #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) | |
513 | #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) | |
514 | ||
5bbc097d JR |
515 | #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) |
516 | ||
03195c6b AK |
517 | /* These are consecutive and not in the normal 4er MCE bank block */ |
518 | #define MSR_IA32_MC0_CTL2 0x00000280 | |
a2d32bcb AK |
519 | #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) |
520 | ||
4bc5aa91 PA |
521 | #define MSR_P6_PERFCTR0 0x000000c1 |
522 | #define MSR_P6_PERFCTR1 0x000000c2 | |
523 | #define MSR_P6_EVNTSEL0 0x00000186 | |
524 | #define MSR_P6_EVNTSEL1 0x00000187 | |
525 | ||
e717bf4e VW |
526 | #define MSR_KNC_PERFCTR0 0x00000020 |
527 | #define MSR_KNC_PERFCTR1 0x00000021 | |
528 | #define MSR_KNC_EVNTSEL0 0x00000028 | |
529 | #define MSR_KNC_EVNTSEL1 0x00000029 | |
530 | ||
069e0c3c AK |
531 | /* Alternative perfctr range with full access. */ |
532 | #define MSR_IA32_PMC0 0x000004c1 | |
533 | ||
42880f72 AS |
534 | /* Auto-reload via MSR instead of DS area */ |
535 | #define MSR_RELOAD_PMC0 0x000014c1 | |
536 | #define MSR_RELOAD_FIXED_CTR0 0x00001309 | |
537 | ||
342061c5 BP |
538 | /* |
539 | * AMD64 MSRs. Not complete. See the architecture manual for a more | |
540 | * complete list. | |
541 | */ | |
29d0887f | 542 | #define MSR_AMD64_PATCH_LEVEL 0x0000008b |
fbc0db76 | 543 | #define MSR_AMD64_TSC_RATIO 0xc0000104 |
12db648c | 544 | #define MSR_AMD64_NB_CFG 0xc001001f |
29d0887f | 545 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
342061c5 BP |
546 | #define MSR_AMD_PERF_CTL 0xc0010062 |
547 | #define MSR_AMD_PERF_STATUS 0xc0010063 | |
548 | #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 | |
035a02c1 AH |
549 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
550 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 | |
4e3f77d8 JB |
551 | #define MSR_AMD_PPIN_CTL 0xc00102f0 |
552 | #define MSR_AMD_PPIN 0xc00102f1 | |
1068ed45 | 553 | #define MSR_AMD64_CPUID_FN_1 0xc0011004 |
3b564968 | 554 | #define MSR_AMD64_LS_CFG 0xc0011020 |
67ec6607 | 555 | #define MSR_AMD64_DC_CFG 0xc0011022 |
2632daeb BP |
556 | |
557 | #define MSR_AMD64_DE_CFG 0xc0011029 | |
558 | #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 | |
559 | #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) | |
522b1d69 | 560 | #define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 |
2632daeb | 561 | |
f0322bd3 | 562 | #define MSR_AMD64_BU_CFG2 0xc001102a |
4f8a6b1a SE |
563 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 |
564 | #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 | |
565 | #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 | |
b7074f1f RR |
566 | #define MSR_AMD64_IBSFETCH_REG_COUNT 3 |
567 | #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) | |
4f8a6b1a SE |
568 | #define MSR_AMD64_IBSOPCTL 0xc0011033 |
569 | #define MSR_AMD64_IBSOPRIP 0xc0011034 | |
570 | #define MSR_AMD64_IBSOPDATA 0xc0011035 | |
571 | #define MSR_AMD64_IBSOPDATA2 0xc0011036 | |
572 | #define MSR_AMD64_IBSOPDATA3 0xc0011037 | |
573 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 | |
574 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 | |
b7074f1f RR |
575 | #define MSR_AMD64_IBSOP_REG_COUNT 7 |
576 | #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) | |
4f8a6b1a | 577 | #define MSR_AMD64_IBSCTL 0xc001103a |
25da6950 | 578 | #define MSR_AMD64_IBSBRTARGET 0xc001103b |
36e1be8a | 579 | #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c |
904cb367 | 580 | #define MSR_AMD64_IBSOPDATA4 0xc001103d |
b7074f1f | 581 | #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ |
39150352 | 582 | #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b |
69372cf0 | 583 | #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e |
29dcc60f | 584 | #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 |
1958b5fc TL |
585 | #define MSR_AMD64_SEV 0xc0010131 |
586 | #define MSR_AMD64_SEV_ENABLED_BIT 0 | |
b57de6cd | 587 | #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 |
f742b90e | 588 | #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 |
1958b5fc | 589 | #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) |
b57de6cd | 590 | #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) |
f742b90e | 591 | #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) |
4f8a6b1a | 592 | |
8c29f016 ND |
593 | /* SNP feature bits enabled by the hypervisor */ |
594 | #define MSR_AMD64_SNP_VTOM BIT_ULL(3) | |
595 | #define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4) | |
596 | #define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5) | |
597 | #define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6) | |
598 | #define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7) | |
599 | #define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8) | |
600 | #define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9) | |
601 | #define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10) | |
602 | #define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11) | |
603 | #define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12) | |
604 | #define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14) | |
605 | #define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16) | |
606 | #define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17) | |
607 | ||
608 | /* SNP feature bits reserved for future use. */ | |
609 | #define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13) | |
610 | #define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15) | |
611 | #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18) | |
612 | ||
11fb0683 TL |
613 | #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f |
614 | ||
89aa94b4 HR |
615 | /* AMD Collaborative Processor Performance Control MSRs */ |
616 | #define MSR_AMD_CPPC_CAP1 0xc00102b0 | |
617 | #define MSR_AMD_CPPC_ENABLE 0xc00102b1 | |
618 | #define MSR_AMD_CPPC_CAP2 0xc00102b2 | |
619 | #define MSR_AMD_CPPC_REQ 0xc00102b3 | |
620 | #define MSR_AMD_CPPC_STATUS 0xc00102b4 | |
621 | ||
622 | #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) | |
623 | #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) | |
624 | #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) | |
625 | #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) | |
626 | ||
627 | #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) | |
628 | #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) | |
629 | #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) | |
630 | #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) | |
631 | ||
089be16d SD |
632 | /* AMD Performance Counter Global Status and Control MSRs */ |
633 | #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 | |
634 | #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 | |
635 | #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 | |
636 | ||
ca5b7c0d SD |
637 | /* AMD Last Branch Record MSRs */ |
638 | #define MSR_AMD64_LBR_SELECT 0xc000010e | |
639 | ||
f454b18e BPA |
640 | /* Zen4 */ |
641 | #define MSR_ZEN4_BP_CFG 0xc001102e | |
642 | #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 | |
aaf24884 | 643 | |
f454b18e | 644 | /* Zen 2 */ |
d7caac99 PZ |
645 | #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 |
646 | #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) | |
647 | ||
f454b18e BPA |
648 | /* Fam 17h MSRs */ |
649 | #define MSR_F17H_IRPERF 0xc00000e9 | |
650 | ||
c43ca509 JS |
651 | /* Fam 16h MSRs */ |
652 | #define MSR_F16H_L2I_PERF_CTL 0xc0010230 | |
653 | #define MSR_F16H_L2I_PERF_CTR 0xc0010231 | |
d6d55f0b JS |
654 | #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 |
655 | #define MSR_F16H_DR2_ADDR_MASK 0xc001101a | |
656 | #define MSR_F16H_DR3_ADDR_MASK 0xc001101b | |
657 | #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 | |
c43ca509 | 658 | |
da169f5d | 659 | /* Fam 15h MSRs */ |
99e40204 BP |
660 | #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a |
661 | #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b | |
da169f5d | 662 | #define MSR_F15H_PERF_CTL 0xc0010200 |
e84b7119 JN |
663 | #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL |
664 | #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) | |
665 | #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) | |
666 | #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) | |
667 | #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) | |
668 | #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) | |
669 | ||
da169f5d | 670 | #define MSR_F15H_PERF_CTR 0xc0010201 |
e84b7119 JN |
671 | #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR |
672 | #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) | |
673 | #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) | |
674 | #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) | |
675 | #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) | |
676 | #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) | |
677 | ||
e259514e JS |
678 | #define MSR_F15H_NB_PERF_CTL 0xc0010240 |
679 | #define MSR_F15H_NB_PERF_CTR 0xc0010241 | |
8a224261 | 680 | #define MSR_F15H_PTSC 0xc0010280 |
ae8b7875 | 681 | #define MSR_F15H_IC_CFG 0xc0011021 |
0e1b869f | 682 | #define MSR_F15H_EX_CFG 0xc001102c |
da169f5d | 683 | |
2274c33e YL |
684 | /* Fam 10h MSRs */ |
685 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 | |
686 | #define FAM10H_MMIO_CONF_ENABLE (1<<0) | |
687 | #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf | |
688 | #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 | |
37db6c8f | 689 | #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL |
2274c33e | 690 | #define FAM10H_MMIO_CONF_BASE_SHIFT 20 |
9d260ebc | 691 | #define MSR_FAM10H_NODE_ID 0xc001100c |
2274c33e | 692 | |
4f8a6b1a SE |
693 | /* K8 MSRs */ |
694 | #define MSR_K8_TOP_MEM1 0xc001001a | |
695 | #define MSR_K8_TOP_MEM2 0xc001001d | |
059e5c32 BS |
696 | #define MSR_AMD64_SYSCFG 0xc0010010 |
697 | #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 | |
698 | #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) | |
aa83f3f2 TG |
699 | #define MSR_K8_INT_PENDING_MSG 0xc0010055 |
700 | /* C1E active bits in int pending message */ | |
701 | #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 | |
8346ea17 | 702 | #define MSR_K8_TSEG_ADDR 0xc0010112 |
3afb1121 | 703 | #define MSR_K8_TSEG_MASK 0xc0010113 |
4f8a6b1a SE |
704 | #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ |
705 | #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ | |
706 | #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ | |
707 | ||
708 | /* K7 MSRs */ | |
4bc5aa91 PA |
709 | #define MSR_K7_EVNTSEL0 0xc0010000 |
710 | #define MSR_K7_PERFCTR0 0xc0010004 | |
711 | #define MSR_K7_EVNTSEL1 0xc0010001 | |
712 | #define MSR_K7_PERFCTR1 0xc0010005 | |
713 | #define MSR_K7_EVNTSEL2 0xc0010002 | |
714 | #define MSR_K7_PERFCTR2 0xc0010006 | |
715 | #define MSR_K7_EVNTSEL3 0xc0010003 | |
716 | #define MSR_K7_PERFCTR3 0xc0010007 | |
4bc5aa91 | 717 | #define MSR_K7_CLK_CTL 0xc001001b |
4bc5aa91 | 718 | #define MSR_K7_HWCR 0xc0010015 |
18c71ce9 TL |
719 | #define MSR_K7_HWCR_SMMLOCK_BIT 0 |
720 | #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) | |
21b5ee59 KP |
721 | #define MSR_K7_HWCR_IRPERF_EN_BIT 30 |
722 | #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) | |
4bc5aa91 PA |
723 | #define MSR_K7_FID_VID_CTL 0xc0010041 |
724 | #define MSR_K7_FID_VID_STATUS 0xc0010042 | |
4bc5aa91 PA |
725 | |
726 | /* K6 MSRs */ | |
4bc5aa91 PA |
727 | #define MSR_K6_WHCR 0xc0000082 |
728 | #define MSR_K6_UWCCR 0xc0000085 | |
729 | #define MSR_K6_EPMR 0xc0000086 | |
730 | #define MSR_K6_PSOR 0xc0000087 | |
731 | #define MSR_K6_PFIR 0xc0000088 | |
732 | ||
733 | /* Centaur-Hauls/IDT defined MSRs. */ | |
734 | #define MSR_IDT_FCR1 0x00000107 | |
735 | #define MSR_IDT_FCR2 0x00000108 | |
736 | #define MSR_IDT_FCR3 0x00000109 | |
737 | #define MSR_IDT_FCR4 0x0000010a | |
738 | ||
739 | #define MSR_IDT_MCR0 0x00000110 | |
740 | #define MSR_IDT_MCR1 0x00000111 | |
741 | #define MSR_IDT_MCR2 0x00000112 | |
742 | #define MSR_IDT_MCR3 0x00000113 | |
743 | #define MSR_IDT_MCR4 0x00000114 | |
744 | #define MSR_IDT_MCR5 0x00000115 | |
745 | #define MSR_IDT_MCR6 0x00000116 | |
746 | #define MSR_IDT_MCR7 0x00000117 | |
747 | #define MSR_IDT_MCR_CTRL 0x00000120 | |
748 | ||
749 | /* VIA Cyrix defined MSRs*/ | |
750 | #define MSR_VIA_FCR 0x00001107 | |
751 | #define MSR_VIA_LONGHAUL 0x0000110a | |
752 | #define MSR_VIA_RNG 0x0000110b | |
753 | #define MSR_VIA_BCR2 0x00001147 | |
754 | ||
755 | /* Transmeta defined MSRs */ | |
756 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 | |
757 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 | |
758 | #define MSR_TMTA_LRTI_READOUT 0x80868018 | |
759 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a | |
760 | ||
761 | /* Intel defined MSRs. */ | |
762 | #define MSR_IA32_P5_MC_ADDR 0x00000000 | |
763 | #define MSR_IA32_P5_MC_TYPE 0x00000001 | |
764 | #define MSR_IA32_TSC 0x00000010 | |
765 | #define MSR_IA32_PLATFORM_ID 0x00000017 | |
766 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a | |
b9a52c4b | 767 | #define MSR_EBC_FREQUENCY_ID 0x0000002c |
1ed51011 | 768 | #define MSR_SMI_COUNT 0x00000034 |
32ad73db SC |
769 | |
770 | /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ | |
771 | #define MSR_IA32_FEAT_CTL 0x0000003a | |
772 | #define FEAT_CTL_LOCKED BIT(0) | |
773 | #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) | |
774 | #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) | |
d205e0f1 | 775 | #define FEAT_CTL_SGX_LC_ENABLED BIT(17) |
e7b6385b | 776 | #define FEAT_CTL_SGX_ENABLED BIT(18) |
32ad73db SC |
777 | #define FEAT_CTL_LMCE_ENABLED BIT(20) |
778 | ||
ba904635 | 779 | #define MSR_IA32_TSC_ADJUST 0x0000003b |
da8999d3 | 780 | #define MSR_IA32_BNDCFGS 0x00000d90 |
4bc5aa91 | 781 | |
4531662d JM |
782 | #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc |
783 | ||
dae1bd58 CB |
784 | #define MSR_IA32_XFD 0x000001c4 |
785 | #define MSR_IA32_XFD_ERR 0x000001c5 | |
6229ad27 FY |
786 | #define MSR_IA32_XSS 0x00000da0 |
787 | ||
4bc5aa91 PA |
788 | #define MSR_IA32_APICBASE 0x0000001b |
789 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
790 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
791 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) | |
792 | ||
793 | #define MSR_IA32_UCODE_WRITE 0x00000079 | |
794 | #define MSR_IA32_UCODE_REV 0x0000008b | |
795 | ||
d205e0f1 SC |
796 | /* Intel SGX Launch Enclave Public Key Hash MSRs */ |
797 | #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C | |
798 | #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D | |
799 | #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E | |
800 | #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F | |
801 | ||
e9ac033e EK |
802 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b |
803 | #define MSR_IA32_SMBASE 0x0000009e | |
804 | ||
4bc5aa91 PA |
805 | #define MSR_IA32_PERF_STATUS 0x00000198 |
806 | #define MSR_IA32_PERF_CTL 0x00000199 | |
e7ddf4b7 | 807 | #define INTEL_PERF_CTL_MASK 0xffff |
4bc5aa91 | 808 | |
ada54345 SE |
809 | /* AMD Branch Sampling configuration */ |
810 | #define MSR_AMD_DBG_EXTN_CFG 0xc000010f | |
811 | #define MSR_AMD_SAMP_BR_FROM 0xc0010300 | |
812 | ||
ca5b7c0d SD |
813 | #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) |
814 | ||
4bc5aa91 PA |
815 | #define MSR_IA32_MPERF 0x000000e7 |
816 | #define MSR_IA32_APERF 0x000000e8 | |
817 | ||
818 | #define MSR_IA32_THERM_CONTROL 0x0000019a | |
819 | #define MSR_IA32_THERM_INTERRUPT 0x0000019b | |
ba2d0f2b | 820 | |
9792db61 FY |
821 | #define THERM_INT_HIGH_ENABLE (1 << 0) |
822 | #define THERM_INT_LOW_ENABLE (1 << 1) | |
823 | #define THERM_INT_PLN_ENABLE (1 << 24) | |
ba2d0f2b | 824 | |
4bc5aa91 | 825 | #define MSR_IA32_THERM_STATUS 0x0000019c |
ba2d0f2b TG |
826 | |
827 | #define THERM_STATUS_PROCHOT (1 << 0) | |
9792db61 | 828 | #define THERM_STATUS_POWER_LIMIT (1 << 10) |
ba2d0f2b | 829 | |
f3a0867b BZ |
830 | #define MSR_THERM2_CTL 0x0000019d |
831 | ||
832 | #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) | |
833 | ||
4bc5aa91 PA |
834 | #define MSR_IA32_MISC_ENABLE 0x000001a0 |
835 | ||
a321cedb CE |
836 | #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
837 | ||
98af7459 | 838 | #define MSR_MISC_FEATURE_CONTROL 0x000001a4 |
2f86dc4c DB |
839 | #define MSR_MISC_PWR_MGMT 0x000001aa |
840 | ||
23016bf0 | 841 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |
d0117a0e LB |
842 | #define ENERGY_PERF_BIAS_PERFORMANCE 0 |
843 | #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 | |
844 | #define ENERGY_PERF_BIAS_NORMAL 6 | |
7420ae3b | 845 | #define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 |
d0117a0e LB |
846 | #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 |
847 | #define ENERGY_PERF_BIAS_POWERSAVE 15 | |
23016bf0 | 848 | |
9792db61 FY |
849 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |
850 | ||
851 | #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) | |
852 | #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) | |
7b8f40b3 | 853 | #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) |
9792db61 FY |
854 | |
855 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 | |
856 | ||
857 | #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) | |
858 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) | |
859 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) | |
7b8f40b3 | 860 | #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) |
9792db61 | 861 | |
9e76a97e D |
862 | /* Thermal Thresholds Support */ |
863 | #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) | |
864 | #define THERM_SHIFT_THRESHOLD0 8 | |
865 | #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) | |
866 | #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) | |
867 | #define THERM_SHIFT_THRESHOLD1 16 | |
868 | #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) | |
869 | #define THERM_STATUS_THRESHOLD0 (1 << 6) | |
870 | #define THERM_LOG_THRESHOLD0 (1 << 7) | |
871 | #define THERM_STATUS_THRESHOLD1 (1 << 8) | |
872 | #define THERM_LOG_THRESHOLD1 (1 << 9) | |
873 | ||
bdf21a49 | 874 | /* MISC_ENABLE bits: architectural */ |
0b131be8 PA |
875 | #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 |
876 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) | |
877 | #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 | |
878 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) | |
879 | #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 | |
880 | #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) | |
881 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 | |
882 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) | |
883 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 | |
884 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) | |
885 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 | |
886 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) | |
887 | #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 | |
888 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) | |
889 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 | |
c45f7736 | 890 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) |
0b131be8 PA |
891 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 |
892 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) | |
893 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 | |
894 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) | |
bdf21a49 PA |
895 | |
896 | /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ | |
0b131be8 PA |
897 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 |
898 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) | |
899 | #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 | |
900 | #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) | |
901 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 | |
902 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) | |
903 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 | |
904 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) | |
905 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 | |
906 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) | |
907 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 | |
908 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) | |
909 | #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 | |
910 | #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) | |
911 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 | |
912 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) | |
913 | #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 | |
914 | #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) | |
915 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 | |
916 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) | |
917 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 | |
918 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) | |
919 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 | |
920 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) | |
921 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 | |
922 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) | |
923 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 | |
924 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) | |
925 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 | |
926 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) | |
bdf21a49 | 927 | |
ab6d9468 KH |
928 | /* MISC_FEATURES_ENABLES non-architectural features */ |
929 | #define MSR_MISC_FEATURES_ENABLES 0x00000140 | |
ae47eda9 | 930 | |
e9ea1e7f KH |
931 | #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 |
932 | #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) | |
ab6d9468 | 933 | #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 |
ae47eda9 | 934 | |
279f1461 SS |
935 | #define MSR_IA32_TSC_DEADLINE 0x000006E0 |
936 | ||
52f64909 PZI |
937 | |
938 | #define MSR_TSX_FORCE_ABORT 0x0000010F | |
939 | ||
940 | #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 | |
941 | #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) | |
1348924b PG |
942 | #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 |
943 | #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) | |
944 | #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 | |
945 | #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) | |
52f64909 | 946 | |
4bc5aa91 PA |
947 | /* P4/Xeon+ specific */ |
948 | #define MSR_IA32_MCG_EAX 0x00000180 | |
949 | #define MSR_IA32_MCG_EBX 0x00000181 | |
950 | #define MSR_IA32_MCG_ECX 0x00000182 | |
951 | #define MSR_IA32_MCG_EDX 0x00000183 | |
952 | #define MSR_IA32_MCG_ESI 0x00000184 | |
953 | #define MSR_IA32_MCG_EDI 0x00000185 | |
954 | #define MSR_IA32_MCG_EBP 0x00000186 | |
955 | #define MSR_IA32_MCG_ESP 0x00000187 | |
956 | #define MSR_IA32_MCG_EFLAGS 0x00000188 | |
957 | #define MSR_IA32_MCG_EIP 0x00000189 | |
958 | #define MSR_IA32_MCG_RESERVED 0x0000018a | |
959 | ||
960 | /* Pentium IV performance counter MSRs */ | |
961 | #define MSR_P4_BPU_PERFCTR0 0x00000300 | |
962 | #define MSR_P4_BPU_PERFCTR1 0x00000301 | |
963 | #define MSR_P4_BPU_PERFCTR2 0x00000302 | |
964 | #define MSR_P4_BPU_PERFCTR3 0x00000303 | |
965 | #define MSR_P4_MS_PERFCTR0 0x00000304 | |
966 | #define MSR_P4_MS_PERFCTR1 0x00000305 | |
967 | #define MSR_P4_MS_PERFCTR2 0x00000306 | |
968 | #define MSR_P4_MS_PERFCTR3 0x00000307 | |
969 | #define MSR_P4_FLAME_PERFCTR0 0x00000308 | |
970 | #define MSR_P4_FLAME_PERFCTR1 0x00000309 | |
971 | #define MSR_P4_FLAME_PERFCTR2 0x0000030a | |
972 | #define MSR_P4_FLAME_PERFCTR3 0x0000030b | |
973 | #define MSR_P4_IQ_PERFCTR0 0x0000030c | |
974 | #define MSR_P4_IQ_PERFCTR1 0x0000030d | |
975 | #define MSR_P4_IQ_PERFCTR2 0x0000030e | |
976 | #define MSR_P4_IQ_PERFCTR3 0x0000030f | |
977 | #define MSR_P4_IQ_PERFCTR4 0x00000310 | |
978 | #define MSR_P4_IQ_PERFCTR5 0x00000311 | |
979 | #define MSR_P4_BPU_CCCR0 0x00000360 | |
980 | #define MSR_P4_BPU_CCCR1 0x00000361 | |
981 | #define MSR_P4_BPU_CCCR2 0x00000362 | |
982 | #define MSR_P4_BPU_CCCR3 0x00000363 | |
983 | #define MSR_P4_MS_CCCR0 0x00000364 | |
984 | #define MSR_P4_MS_CCCR1 0x00000365 | |
985 | #define MSR_P4_MS_CCCR2 0x00000366 | |
986 | #define MSR_P4_MS_CCCR3 0x00000367 | |
987 | #define MSR_P4_FLAME_CCCR0 0x00000368 | |
988 | #define MSR_P4_FLAME_CCCR1 0x00000369 | |
989 | #define MSR_P4_FLAME_CCCR2 0x0000036a | |
990 | #define MSR_P4_FLAME_CCCR3 0x0000036b | |
991 | #define MSR_P4_IQ_CCCR0 0x0000036c | |
992 | #define MSR_P4_IQ_CCCR1 0x0000036d | |
993 | #define MSR_P4_IQ_CCCR2 0x0000036e | |
994 | #define MSR_P4_IQ_CCCR3 0x0000036f | |
995 | #define MSR_P4_IQ_CCCR4 0x00000370 | |
996 | #define MSR_P4_IQ_CCCR5 0x00000371 | |
997 | #define MSR_P4_ALF_ESCR0 0x000003ca | |
998 | #define MSR_P4_ALF_ESCR1 0x000003cb | |
999 | #define MSR_P4_BPU_ESCR0 0x000003b2 | |
1000 | #define MSR_P4_BPU_ESCR1 0x000003b3 | |
1001 | #define MSR_P4_BSU_ESCR0 0x000003a0 | |
1002 | #define MSR_P4_BSU_ESCR1 0x000003a1 | |
1003 | #define MSR_P4_CRU_ESCR0 0x000003b8 | |
1004 | #define MSR_P4_CRU_ESCR1 0x000003b9 | |
1005 | #define MSR_P4_CRU_ESCR2 0x000003cc | |
1006 | #define MSR_P4_CRU_ESCR3 0x000003cd | |
1007 | #define MSR_P4_CRU_ESCR4 0x000003e0 | |
1008 | #define MSR_P4_CRU_ESCR5 0x000003e1 | |
1009 | #define MSR_P4_DAC_ESCR0 0x000003a8 | |
1010 | #define MSR_P4_DAC_ESCR1 0x000003a9 | |
1011 | #define MSR_P4_FIRM_ESCR0 0x000003a4 | |
1012 | #define MSR_P4_FIRM_ESCR1 0x000003a5 | |
1013 | #define MSR_P4_FLAME_ESCR0 0x000003a6 | |
1014 | #define MSR_P4_FLAME_ESCR1 0x000003a7 | |
1015 | #define MSR_P4_FSB_ESCR0 0x000003a2 | |
1016 | #define MSR_P4_FSB_ESCR1 0x000003a3 | |
1017 | #define MSR_P4_IQ_ESCR0 0x000003ba | |
1018 | #define MSR_P4_IQ_ESCR1 0x000003bb | |
1019 | #define MSR_P4_IS_ESCR0 0x000003b4 | |
1020 | #define MSR_P4_IS_ESCR1 0x000003b5 | |
1021 | #define MSR_P4_ITLB_ESCR0 0x000003b6 | |
1022 | #define MSR_P4_ITLB_ESCR1 0x000003b7 | |
1023 | #define MSR_P4_IX_ESCR0 0x000003c8 | |
1024 | #define MSR_P4_IX_ESCR1 0x000003c9 | |
1025 | #define MSR_P4_MOB_ESCR0 0x000003aa | |
1026 | #define MSR_P4_MOB_ESCR1 0x000003ab | |
1027 | #define MSR_P4_MS_ESCR0 0x000003c0 | |
1028 | #define MSR_P4_MS_ESCR1 0x000003c1 | |
1029 | #define MSR_P4_PMH_ESCR0 0x000003ac | |
1030 | #define MSR_P4_PMH_ESCR1 0x000003ad | |
1031 | #define MSR_P4_RAT_ESCR0 0x000003bc | |
1032 | #define MSR_P4_RAT_ESCR1 0x000003bd | |
1033 | #define MSR_P4_SAAT_ESCR0 0x000003ae | |
1034 | #define MSR_P4_SAAT_ESCR1 0x000003af | |
1035 | #define MSR_P4_SSU_ESCR0 0x000003be | |
1036 | #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ | |
1037 | ||
1038 | #define MSR_P4_TBPU_ESCR0 0x000003c2 | |
1039 | #define MSR_P4_TBPU_ESCR1 0x000003c3 | |
1040 | #define MSR_P4_TC_ESCR0 0x000003c4 | |
1041 | #define MSR_P4_TC_ESCR1 0x000003c5 | |
1042 | #define MSR_P4_U2L_ESCR0 0x000003b0 | |
1043 | #define MSR_P4_U2L_ESCR1 0x000003b1 | |
1044 | ||
cb7d6b50 LM |
1045 | #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 |
1046 | ||
4bc5aa91 PA |
1047 | /* Intel Core-based CPU performance counters */ |
1048 | #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 | |
1049 | #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a | |
1050 | #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b | |
7b2c05a1 | 1051 | #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c |
4bc5aa91 PA |
1052 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d |
1053 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e | |
1054 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f | |
1055 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 | |
1056 | ||
59a854e2 KL |
1057 | #define MSR_PERF_METRICS 0x00000329 |
1058 | ||
8479e04e LK |
1059 | /* PERF_GLOBAL_OVF_CTL bits */ |
1060 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 | |
1061 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) | |
c715eb9f LK |
1062 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 |
1063 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) | |
1064 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 | |
1065 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) | |
8479e04e | 1066 | |
4bc5aa91 PA |
1067 | /* Geode defined MSRs */ |
1068 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 | |
1069 | ||
315a6558 SY |
1070 | /* Intel VT MSRs */ |
1071 | #define MSR_IA32_VMX_BASIC 0x00000480 | |
1072 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 | |
1073 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 | |
1074 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 | |
1075 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 | |
1076 | #define MSR_IA32_VMX_MISC 0x00000485 | |
1077 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 | |
1078 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 | |
1079 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 | |
1080 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 | |
1081 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a | |
1082 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | |
1083 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | |
b87a51ae NHE |
1084 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d |
1085 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e | |
1086 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f | |
1087 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 | |
cae50139 | 1088 | #define MSR_IA32_VMX_VMFUNC 0x00000491 |
465932db | 1089 | #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 |
b87a51ae NHE |
1090 | |
1091 | /* VMX_BASIC bits and bitmasks */ | |
1092 | #define VMX_BASIC_VMCS_SIZE_SHIFT 32 | |
3dbcd8da | 1093 | #define VMX_BASIC_TRUE_CTLS (1ULL << 55) |
b87a51ae NHE |
1094 | #define VMX_BASIC_64 0x0001000000000000LLU |
1095 | #define VMX_BASIC_MEM_TYPE_SHIFT 50 | |
1096 | #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU | |
1097 | #define VMX_BASIC_MEM_TYPE_WB 6LLU | |
1098 | #define VMX_BASIC_INOUT 0x0040000000000000LLU | |
315a6558 | 1099 | |
97fa21f6 BP |
1100 | /* Resctrl MSRs: */ |
1101 | /* - Intel: */ | |
1102 | #define MSR_IA32_L3_QOS_CFG 0xc81 | |
1103 | #define MSR_IA32_L2_QOS_CFG 0xc82 | |
1104 | #define MSR_IA32_QM_EVTSEL 0xc8d | |
1105 | #define MSR_IA32_QM_CTR 0xc8e | |
1106 | #define MSR_IA32_PQR_ASSOC 0xc8f | |
1107 | #define MSR_IA32_L3_CBM_BASE 0xc90 | |
1108 | #define MSR_IA32_L2_CBM_BASE 0xd10 | |
1109 | #define MSR_IA32_MBA_THRTL_BASE 0xd50 | |
1110 | ||
1111 | /* - AMD: */ | |
1112 | #define MSR_IA32_MBA_BW_BASE 0xc0000200 | |
5b6fac3f | 1113 | #define MSR_IA32_SMBA_BW_BASE 0xc0000280 |
dc2a3e85 | 1114 | #define MSR_IA32_EVT_CFG_BASE 0xc0000400 |
97fa21f6 | 1115 | |
89662e56 | 1116 | /* MSR_IA32_VMX_MISC bits */ |
f99e3daf | 1117 | #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) |
89662e56 | 1118 | #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) |
7854cbca | 1119 | #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F |
9962d032 AG |
1120 | /* AMD-V MSRs */ |
1121 | ||
1122 | #define MSR_VM_CR 0xc0010114 | |
0367b433 | 1123 | #define MSR_VM_IGNNE 0xc0010115 |
9962d032 AG |
1124 | #define MSR_VM_HSAVE_PA 0xc0010117 |
1125 | ||
7b8f40b3 RN |
1126 | /* Hardware Feedback Interface */ |
1127 | #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 | |
1128 | #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 | |
1129 | ||
b8d1d163 DS |
1130 | /* x2APIC locked status */ |
1131 | #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD | |
1132 | #define LEGACY_XAPIC_DISABLED BIT(0) /* | |
1133 | * x2APIC mode is locked and | |
1134 | * disabling x2APIC will cause | |
1135 | * a #GP | |
1136 | */ | |
1137 | ||
1965aae3 | 1138 | #endif /* _ASM_X86_MSR_INDEX_H */ |