[linux-block.git] / arch / x86 / include / asm / mce.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_MCE_H
#define _ASM_X86_MCE_H

#include <uapi/asm/mce.h>

/*
 * Machine Check support for x86
 */

/* MCG_CAP register defines */
#define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
#define MCG_CTL_P		BIT_ULL(8)   /* MCG_CTL register available */
#define MCG_EXT_P		BIT_ULL(9)   /* Extended registers available */
#define MCG_CMCI_P		BIT_ULL(10)  /* CMCI supported */
#define MCG_SEAM_NR		BIT_ULL(12)  /* MCG_STATUS_SEAM_NR supported */
#define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
#define MCG_EXT_CNT_SHIFT	16
#define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
#define MCG_SER_P		BIT_ULL(24)  /* MCA recovery/new status bits */
#define MCG_ELOG_P		BIT_ULL(26)  /* Extended error log supported */
#define MCG_LMCE_P		BIT_ULL(27)  /* Local machine check supported */

/* MCG_STATUS register defines */
#define MCG_STATUS_RIPV		BIT_ULL(0)   /* restart ip valid */
#define MCG_STATUS_EIPV		BIT_ULL(1)   /* ip points to correct instruction */
#define MCG_STATUS_MCIP		BIT_ULL(2)   /* machine check in progress */
#define MCG_STATUS_LMCES	BIT_ULL(3)   /* LMCE signaled */
#define MCG_STATUS_SEAM_NR	BIT_ULL(12)  /* Machine check inside SEAM non-root mode */

/* MCG_EXT_CTL register defines */
#define MCG_EXT_CTL_LMCE_EN	BIT_ULL(0) /* Enable LMCE */

/* MCi_STATUS register defines */
#define MCI_STATUS_VAL		BIT_ULL(63)  /* valid error */
#define MCI_STATUS_OVER		BIT_ULL(62)  /* previous errors lost */
#define MCI_STATUS_UC		BIT_ULL(61)  /* uncorrected error */
#define MCI_STATUS_EN		BIT_ULL(60)  /* error enabled */
#define MCI_STATUS_MISCV	BIT_ULL(59)  /* misc error reg. valid */
#define MCI_STATUS_ADDRV	BIT_ULL(58)  /* addr reg. valid */
#define MCI_STATUS_PCC		BIT_ULL(57)  /* processor context corrupt */
#define MCI_STATUS_S		BIT_ULL(56)  /* Signaled machine check */
#define MCI_STATUS_AR		BIT_ULL(55)  /* Action required */
#define MCI_STATUS_CEC_SHIFT	38           /* Corrected Error Count */
#define MCI_STATUS_CEC_MASK	GENMASK_ULL(52,38)
#define MCI_STATUS_CEC(c)	(((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
#define MCI_STATUS_MSCOD(m)	(((m) >> 16) & 0xffff)

/* AMD-specific bits */
#define MCI_STATUS_TCC		BIT_ULL(55)  /* Task context corrupt */
#define MCI_STATUS_SYNDV	BIT_ULL(53)  /* synd reg. valid */
#define MCI_STATUS_DEFERRED	BIT_ULL(44)  /* uncorrected error, deferred exception */
#define MCI_STATUS_POISON	BIT_ULL(43)  /* access poisonous data */
#define MCI_STATUS_SCRUB	BIT_ULL(40)  /* Error detected during scrub operation */

/*
 * McaX field if set indicates a given bank supports MCA extensions:
 *  - Deferred error interrupt type is specifiable by bank.
 *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
 *    But should not be used to determine MSR numbers.
 *  - TCC bit is present in MCx_STATUS.
 */
#define MCI_CONFIG_MCAX		0x1
#define MCI_CONFIG_FRUTEXT	BIT_ULL(9)
#define MCI_IPID_MCATYPE	0xFFFF0000
#define MCI_IPID_HWID		0xFFF

/*
 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
 * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
 * errors to indicate that errors are being filtered by hardware.
 * We should mask out bit 12 when looking for specific signatures
 * of uncorrected errors - so the F bit is deliberately skipped
 * in this #define.
 */
#define MCACOD		  0xefff     /* MCA Error Code */

/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
#define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
#define MCACOD_SCRUBMSK	0xeff0	/* Skip bit 12 ('F' bit) */
#define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */
#define MCACOD_DATA	0x0134	/* Data Load */
#define MCACOD_INSTR	0x0150	/* Instruction Fetch */

/* MCi_MISC register defines */
#define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
#define MCI_MISC_ADDR_MODE(m)	(((m) >> 6) & 7)
#define  MCI_MISC_ADDR_SEGOFF	0	/* segment offset */
#define  MCI_MISC_ADDR_LINEAR	1	/* linear address */
#define  MCI_MISC_ADDR_PHYS	2	/* physical address */
#define  MCI_MISC_ADDR_MEM	3	/* memory address */
#define  MCI_MISC_ADDR_GENERIC	7	/* generic */

/* MCi_ADDR register defines */
#define MCI_ADDR_PHYSADDR	GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)

/* CTL2 register defines */
#define MCI_CTL2_CMCI_EN		BIT_ULL(30)
#define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL

#define MCJ_CTX_MASK		3
#define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
#define MCJ_CTX_RANDOM		0    /* inject context: random */
#define MCJ_CTX_PROCESS		0x1  /* inject context: process */
#define MCJ_CTX_IRQ		0x2  /* inject context: IRQ */
#define MCJ_NMI_BROADCAST	0x4  /* do NMI broadcasting */
#define MCJ_EXCEPTION		0x8  /* raise as exception */
#define MCJ_IRQ_BROADCAST	0x10 /* do IRQ broadcasting */

#define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */

#define MCE_LOG_MIN_LEN 32U
#define MCE_LOG_SIGNATURE	"MACHINECHECK"

/* AMD Scalable MCA */
#define MSR_AMD64_SMCA_MC0_CTL		0xc0002000
#define MSR_AMD64_SMCA_MC0_STATUS	0xc0002001
#define MSR_AMD64_SMCA_MC0_ADDR		0xc0002002
#define MSR_AMD64_SMCA_MC0_MISC0	0xc0002003
#define MSR_AMD64_SMCA_MC0_CONFIG	0xc0002004
#define MSR_AMD64_SMCA_MC0_IPID		0xc0002005
#define MSR_AMD64_SMCA_MC0_SYND		0xc0002006
#define MSR_AMD64_SMCA_MC0_DESTAT	0xc0002008
#define MSR_AMD64_SMCA_MC0_DEADDR	0xc0002009
#define MSR_AMD64_SMCA_MC0_MISC1	0xc000200a
/* Registers MISC2 to MISC4 are at offsets B to D. */
#define MSR_AMD64_SMCA_MC0_SYND1	0xc000200e
#define MSR_AMD64_SMCA_MC0_SYND2	0xc000200f
#define MSR_AMD64_SMCA_MCx_CTL(x)	(MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_STATUS(x)	(MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_ADDR(x)	(MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_MISC(x)	(MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_CONFIG(x)	(MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_IPID(x)	(MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_SYND(x)	(MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_DESTAT(x)	(MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_DEADDR(x)	(MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_MISCy(x, y)	((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
#define MSR_AMD64_SMCA_MCx_SYND1(x)	(MSR_AMD64_SMCA_MC0_SYND1 + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_SYND2(x)	(MSR_AMD64_SMCA_MC0_SYND2 + 0x10*(x))

#define XEC(x, mask)			(((x) >> 16) & mask)

/* mce.kflags flag bits for logging etc. */
#define	MCE_HANDLED_CEC		BIT_ULL(0)
#define	MCE_HANDLED_UC		BIT_ULL(1)
#define	MCE_HANDLED_EXTLOG	BIT_ULL(2)
#define	MCE_HANDLED_NFIT	BIT_ULL(3)
#define	MCE_HANDLED_EDAC	BIT_ULL(4)
#define	MCE_HANDLED_MCELOG	BIT_ULL(5)

/*
 * Indicates an MCE which has happened in kernel space but from
 * which the kernel can recover simply by executing fixup_exception()
 * so that an error is returned to the caller of the function that
 * hit the machine check.
 */
#define MCE_IN_KERNEL_RECOV	BIT_ULL(6)

/*
 * Indicates an MCE that happened in kernel space while copying data
 * from user. In this case fixup_exception() gets the kernel to the
 * error exit for the copy function. Machine check handler can then
 * treat it like a fault taken in user mode.
 */
#define MCE_IN_KERNEL_COPYIN	BIT_ULL(7)

/*
 * This structure contains all data related to the MCE log.  Also
 * carries a signature to make it easier to find from external
 * debugging tools.  Each entry is only valid when its finished flag
 * is set.
 */
struct mce_log_buffer {
	char signature[12]; /* "MACHINECHECK" */
	unsigned len;	    /* = elements in .mce_entry[] */
	unsigned next;
	unsigned flags;
	unsigned recordlen;	/* length of struct mce */
	struct mce entry[];
};

/* Highest last */
enum mce_notifier_prios {
	MCE_PRIO_LOWEST,
	MCE_PRIO_MCELOG,
	MCE_PRIO_EDAC,
	MCE_PRIO_NFIT,
	MCE_PRIO_EXTLOG,
	MCE_PRIO_UC,
	MCE_PRIO_EARLY,
	MCE_PRIO_CEC,
	MCE_PRIO_HIGHEST = MCE_PRIO_CEC
};

/**
 * struct mce_hw_err - Hardware Error Record.
 * @m:		Machine Check record.
 * @vendor:	Vendor-specific error information.
 *
 * Vendor-specific fields should not be added to struct mce. Instead, vendors
 * should export their vendor-specific data through their structure in the
 * vendor union below.
 *
 * AMD's vendor data is parsed by error decoding tools for supplemental error
 * information. Thus, current offsets of existing fields must be maintained.
 * Only add new fields at the end of AMD's vendor structure.
 */
struct mce_hw_err {
	struct mce m;

	union vendor_info {
		struct {
			u64 synd1;		/* MCA_SYND1 MSR */
			u64 synd2;		/* MCA_SYND2 MSR */
		} amd;
	} vendor;
};

#define	to_mce_hw_err(mce) container_of(mce, struct mce_hw_err, m)

struct notifier_block;
extern void mce_register_decode_chain(struct notifier_block *nb);
extern void mce_unregister_decode_chain(struct notifier_block *nb);

#include <linux/percpu.h>
#include <linux/atomic.h>

extern int mce_p5_enabled;

#ifdef CONFIG_ARCH_HAS_COPY_MC
extern void enable_copy_mc_fragile(void);
unsigned long __must_check copy_mc_fragile(void *dst, const void *src, unsigned cnt);
#else
static inline void enable_copy_mc_fragile(void)
{
}
#endif

struct cper_ia_proc_ctx;

#ifdef CONFIG_X86_MCE
int mcheck_init(void);
void mcheck_cpu_init(struct cpuinfo_x86 *c);
void mcheck_cpu_clear(struct cpuinfo_x86 *c);
int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
			       u64 lapic_id);
#else
static inline int mcheck_init(void) { return 0; }
static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
					     u64 lapic_id) { return -EINVAL; }
#endif

void mce_prep_record(struct mce_hw_err *err);
void mce_log(struct mce_hw_err *err);
DECLARE_PER_CPU(struct device *, mce_device);

/* Maximum number of MCA banks per CPU. */
#define MAX_NR_BANKS 64

#ifdef CONFIG_X86_MCE_INTEL
void mce_intel_feature_init(struct cpuinfo_x86 *c);
void mce_intel_feature_clear(struct cpuinfo_x86 *c);
void cmci_clear(void);
void cmci_reenable(void);
void cmci_rediscover(void);
void cmci_recheck(void);
#else
static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
static inline void cmci_clear(void) {}
static inline void cmci_reenable(void) {}
static inline void cmci_rediscover(void) {}
static inline void cmci_recheck(void) {}
#endif

bool mce_available(struct cpuinfo_x86 *c);
bool mce_is_memory_error(struct mce *m);
bool mce_is_correctable(struct mce *m);
bool mce_usable_address(struct mce *m);

DECLARE_PER_CPU(unsigned, mce_exception_count);
DECLARE_PER_CPU(unsigned, mce_poll_count);

typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);

enum mcp_flags {
	MCP_TIMESTAMP	= BIT(0),	/* log time stamp */
	MCP_UC		= BIT(1),	/* log uncorrected errors */
	MCP_DONTLOG	= BIT(2),	/* only clear, don't log */
	MCP_QUEUE_LOG	= BIT(3),	/* only queue to genpool */
};

void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);

DECLARE_PER_CPU(struct mce, injectm);

/* Disable CMCI/polling for MCA bank claimed by firmware */
extern void mce_disable_bank(int bank);

/*
 * Exception handler
 */
void do_machine_check(struct pt_regs *pt_regs);

/*
 * Threshold handler
 */
extern void (*mce_threshold_vector)(void);

/* Deferred error interrupt handler */
extern void (*deferred_error_int_vector)(void);

/*
 * Used by APEI to report memory error via /dev/mcelog
 */

struct cper_sec_mem_err;
extern void apei_mce_report_mem_error(int corrected,
				      struct cper_sec_mem_err *mem_err);

/*
 * Enumerate new IP types and HWID values in AMD processors which support
 * Scalable MCA.
 */
#ifdef CONFIG_X86_MCE_AMD

/* These may be used by multiple smca_hwid_mcatypes */
enum smca_bank_types {
	SMCA_LS = 0,	/* Load Store */
	SMCA_LS_V2,
	SMCA_IF,	/* Instruction Fetch */
	SMCA_L2_CACHE,	/* L2 Cache */
	SMCA_DE,	/* Decoder Unit */
	SMCA_RESERVED,	/* Reserved */
	SMCA_EX,	/* Execution Unit */
	SMCA_FP,	/* Floating Point */
	SMCA_L3_CACHE,	/* L3 Cache */
	SMCA_CS,	/* Coherent Slave */
	SMCA_CS_V2,
	SMCA_PIE,	/* Power, Interrupts, etc. */
	SMCA_UMC,	/* Unified Memory Controller */
	SMCA_UMC_V2,
	SMCA_MA_LLC,	/* Memory Attached Last Level Cache */
	SMCA_PB,	/* Parameter Block */
	SMCA_PSP,	/* Platform Security Processor */
	SMCA_PSP_V2,
	SMCA_SMU,	/* System Management Unit */
	SMCA_SMU_V2,
	SMCA_MP5,	/* Microprocessor 5 Unit */
	SMCA_MPDMA,	/* MPDMA Unit */
	SMCA_NBIO,	/* Northbridge IO Unit */
	SMCA_PCIE,	/* PCI Express Unit */
	SMCA_PCIE_V2,
	SMCA_XGMI_PCS,	/* xGMI PCS Unit */
	SMCA_NBIF,	/* NBIF Unit */
	SMCA_SHUB,	/* System HUB Unit */
	SMCA_SATA,	/* SATA Unit */
	SMCA_USB,	/* USB Unit */
	SMCA_USR_DP,	/* Ultra Short Reach Data Plane Controller */
	SMCA_USR_CP,	/* Ultra Short Reach Control Plane Controller */
	SMCA_GMI_PCS,	/* GMI PCS Unit */
	SMCA_XGMI_PHY,	/* xGMI PHY Unit */
	SMCA_WAFL_PHY,	/* WAFL PHY Unit */
	SMCA_GMI_PHY,	/* GMI PHY Unit */
	N_SMCA_BANK_TYPES
};

extern bool amd_mce_is_memory_error(struct mce *m);

extern int mce_threshold_create_device(unsigned int cpu);
extern int mce_threshold_remove_device(unsigned int cpu);

void mce_amd_feature_init(struct cpuinfo_x86 *c);
enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank);
#else

static inline int mce_threshold_create_device(unsigned int cpu)		{ return 0; };
static inline int mce_threshold_remove_device(unsigned int cpu)		{ return 0; };
static inline bool amd_mce_is_memory_error(struct mce *m)		{ return false; };
static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)		{ }
#endif

unsigned long copy_mc_fragile_handle_tail(char *to, char *from, unsigned len);

#endif /* _ASM_X86_MCE_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1965aae3 PA	2	#ifndef _ASM_X86_MCE_H
1965aae3 PA	3	#define _ASM_X86_MCE_H
e2f43029	4
af170c50	5	#include <uapi/asm/mce.h>
e2f43029	6
f51bde6f BP	7	/*
	8	* Machine Check support for x86
	9	*/
	10
	11	/* MCG_CAP register defines */
	12	#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
93ac5754 QZ	13	#define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
	14	#define MCG_EXT_P BIT_ULL(9) /* Extended registers available */
	15	#define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
7911f145	16	#define MCG_SEAM_NR BIT_ULL(12) /* MCG_STATUS_SEAM_NR supported */
f51bde6f BP	17	#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
	18	#define MCG_EXT_CNT_SHIFT 16
	19	#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
93ac5754 QZ	20	#define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */
	21	#define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */
	22	#define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */
f51bde6f BP	23
f51bde6f BP	24	/* MCG_STATUS register defines */
93ac5754 QZ	25	#define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */
	26	#define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */
	27	#define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */
	28	#define MCG_STATUS_LMCES BIT_ULL(3) /* LMCE signaled */
7911f145	29	#define MCG_STATUS_SEAM_NR BIT_ULL(12) /* Machine check inside SEAM non-root mode */
bc12edb8 AR	30
bc12edb8 AR	31	/* MCG_EXT_CTL register defines */
93ac5754	32	#define MCG_EXT_CTL_LMCE_EN BIT_ULL(0) /* Enable LMCE */
f51bde6f BP	33
f51bde6f BP	34	/* MCi_STATUS register defines */
93ac5754 QZ	35	#define MCI_STATUS_VAL BIT_ULL(63) /* valid error */
	36	#define MCI_STATUS_OVER BIT_ULL(62) /* previous errors lost */
	37	#define MCI_STATUS_UC BIT_ULL(61) /* uncorrected error */
	38	#define MCI_STATUS_EN BIT_ULL(60) /* error enabled */
	39	#define MCI_STATUS_MISCV BIT_ULL(59) /* misc error reg. valid */
	40	#define MCI_STATUS_ADDRV BIT_ULL(58) /* addr reg. valid */
	41	#define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
	42	#define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
	43	#define MCI_STATUS_AR BIT_ULL(55) /* Action required */
e5276b1f QZ	44	#define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */
	45	#define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38)
	46	#define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
2738c69a	47	#define MCI_STATUS_MSCOD(m) (((m) >> 16) & 0xffff)
0ca06c08	48
e3480271	49	/* AMD-specific bits */
93ac5754 QZ	50	#define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */
	51	#define MCI_STATUS_SYNDV BIT_ULL(53) /* synd reg. valid */
	52	#define MCI_STATUS_DEFERRED BIT_ULL(44) /* uncorrected error, deferred exception */
	53	#define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */
3f4da372	54	#define MCI_STATUS_SCRUB BIT_ULL(40) /* Error detected during scrub operation */
be0aec23 AG	55
	56	/*
	57	* McaX field if set indicates a given bank supports MCA extensions:
	58	* - Deferred error interrupt type is specifiable by bank.
	59	* - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
	60	* But should not be used to determine MSR numbers.
	61	* - TCC bit is present in MCx_STATUS.
	62	*/
	63	#define MCI_CONFIG_MCAX 0x1
612c2add	64	#define MCI_CONFIG_FRUTEXT BIT_ULL(9)
be0aec23 AG	65	#define MCI_IPID_MCATYPE 0xFFFF0000
be0aec23 AG	66	#define MCI_IPID_HWID 0xFFF
e3480271	67
0ca06c08 TL	68	/*
	69	* Note that the full MCACOD field of IA32_MCi_STATUS MSR is
	70	* bits 15:0. But bit 12 is the 'F' bit, defined for corrected
	71	* errors to indicate that errors are being filtered by hardware.
	72	* We should mask out bit 12 when looking for specific signatures
	73	* of uncorrected errors - so the F bit is deliberately skipped
	74	* in this #define.
	75	*/
	76	#define MCACOD 0xefff /* MCA Error Code */
f51bde6f BP	77
	78	/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
	79	#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
0ca06c08	80	#define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
f51bde6f BP	81	#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
	82	#define MCACOD_DATA 0x0134 /* Data Load */
	83	#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
	84
	85	/* MCi_MISC register defines */
	86	#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
	87	#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
	88	#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
	89	#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
	90	#define MCI_MISC_ADDR_PHYS 2 /* physical address */
	91	#define MCI_MISC_ADDR_MEM 3 /* memory address */
	92	#define MCI_MISC_ADDR_GENERIC 7 /* generic */
	93
8a01ec97 TL	94	/* MCi_ADDR register defines */
	95	#define MCI_ADDR_PHYSADDR GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)
	96
f51bde6f	97	/* CTL2 register defines */
93ac5754	98	#define MCI_CTL2_CMCI_EN BIT_ULL(30)
f51bde6f BP	99	#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
	100
	101	#define MCJ_CTX_MASK 3
	102	#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
	103	#define MCJ_CTX_RANDOM 0 /* inject context: random */
	104	#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
	105	#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
	106	#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
	107	#define MCJ_EXCEPTION 0x8 /* raise as exception */
a9093684	108	#define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
f51bde6f BP	109
	110	#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
	111
d8ecca40	112	#define MCE_LOG_MIN_LEN 32U
f51bde6f BP	113	#define MCE_LOG_SIGNATURE "MACHINECHECK"
f51bde6f BP	114
adc53f2e	115	/* AMD Scalable MCA */
a9750a31 YG	116	#define MSR_AMD64_SMCA_MC0_CTL 0xc0002000
	117	#define MSR_AMD64_SMCA_MC0_STATUS 0xc0002001
	118	#define MSR_AMD64_SMCA_MC0_ADDR 0xc0002002
8dd1e17a	119	#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003
adc53f2e	120	#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
be0aec23	121	#define MSR_AMD64_SMCA_MC0_IPID 0xc0002005
db819d60	122	#define MSR_AMD64_SMCA_MC0_SYND 0xc0002006
34102009 YG	123	#define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008
34102009 YG	124	#define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009
8dd1e17a	125	#define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a
d4fca135 AN	126	/* Registers MISC2 to MISC4 are at offsets B to D. */
	127	#define MSR_AMD64_SMCA_MC0_SYND1 0xc000200e
	128	#define MSR_AMD64_SMCA_MC0_SYND2 0xc000200f
a9750a31 YG	129	#define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
	130	#define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
	131	#define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
8dd1e17a	132	#define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
adc53f2e	133	#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
be0aec23	134	#define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
db819d60	135	#define MSR_AMD64_SMCA_MCx_SYND(x) (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
34102009 YG	136	#define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
34102009 YG	137	#define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
8dd1e17a	138	#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
d4fca135 AN	139	#define MSR_AMD64_SMCA_MCx_SYND1(x) (MSR_AMD64_SMCA_MC0_SYND1 + 0x10*(x))
d4fca135 AN	140	#define MSR_AMD64_SMCA_MCx_SYND2(x) (MSR_AMD64_SMCA_MC0_SYND2 + 0x10*(x))
adc53f2e	141
3e0fdec8 BP	142	#define XEC(x, mask) (((x) >> 16) & mask)
3e0fdec8 BP	143
1de08dcc TL	144	/* mce.kflags flag bits for logging etc. */
	145	#define MCE_HANDLED_CEC BIT_ULL(0)
	146	#define MCE_HANDLED_UC BIT_ULL(1)
	147	#define MCE_HANDLED_EXTLOG BIT_ULL(2)
	148	#define MCE_HANDLED_NFIT BIT_ULL(3)
	149	#define MCE_HANDLED_EDAC BIT_ULL(4)
	150	#define MCE_HANDLED_MCELOG BIT_ULL(5)
278b917f YS	151
	152	/*
	153	* Indicates an MCE which has happened in kernel space but from
	154	* which the kernel can recover simply by executing fixup_exception()
	155	* so that an error is returned to the caller of the function that
	156	* hit the machine check.
	157	*/
1df73b21	158	#define MCE_IN_KERNEL_RECOV BIT_ULL(6)
1de08dcc	159
278b917f YS	160	/*
	161	* Indicates an MCE that happened in kernel space while copying data
	162	* from user. In this case fixup_exception() gets the kernel to the
	163	* error exit for the copy function. Machine check handler can then
	164	* treat it like a fault taken in user mode.
	165	*/
	166	#define MCE_IN_KERNEL_COPYIN BIT_ULL(7)
	167
f51bde6f BP	168	/*
	169	* This structure contains all data related to the MCE log. Also
	170	* carries a signature to make it easier to find from external
	171	* debugging tools. Each entry is only valid when its finished flag
	172	* is set.
	173	*/
e64edfcc	174	struct mce_log_buffer {
f51bde6f	175	char signature[12]; /* "MACHINECHECK" */
d8ecca40	176	unsigned len; /* = elements in .mce_entry[] */
f51bde6f BP	177	unsigned next;
	178	unsigned flags;
	179	unsigned recordlen; /* length of struct mce */
d8ecca40	180	struct mce entry[];
f51bde6f	181	};
d203f0b8	182
c9c6d216	183	/* Highest last */
9026cc82	184	enum mce_notifier_prios {
c9c6d216 TL	185	MCE_PRIO_LOWEST,
	186	MCE_PRIO_MCELOG,
	187	MCE_PRIO_EDAC,
	188	MCE_PRIO_NFIT,
	189	MCE_PRIO_EXTLOG,
	190	MCE_PRIO_UC,
	191	MCE_PRIO_EARLY,
15af3659 ZL	192	MCE_PRIO_CEC,
15af3659 ZL	193	MCE_PRIO_HIGHEST = MCE_PRIO_CEC
9026cc82 BP	194	};
9026cc82 BP	195
750fd239 AN	196	/**
	197	* struct mce_hw_err - Hardware Error Record.
	198	* @m: Machine Check record.
d4fca135 AN	199	* @vendor: Vendor-specific error information.
	200	*
	201	* Vendor-specific fields should not be added to struct mce. Instead, vendors
	202	* should export their vendor-specific data through their structure in the
	203	* vendor union below.
	204	*
	205	* AMD's vendor data is parsed by error decoding tools for supplemental error
	206	* information. Thus, current offsets of existing fields must be maintained.
	207	* Only add new fields at the end of AMD's vendor structure.
750fd239 AN	208	*/
	209	struct mce_hw_err {
	210	struct mce m;
d4fca135 AN	211
	212	union vendor_info {
	213	struct {
	214	u64 synd1; /* MCA_SYND1 MSR */
	215	u64 synd2; /* MCA_SYND2 MSR */
	216	} amd;
	217	} vendor;
750fd239 AN	218	};
	219
	220	#define to_mce_hw_err(mce) container_of(mce, struct mce_hw_err, m)
	221
704ae091	222	struct notifier_block;
eef4dfa0	223	extern void mce_register_decode_chain(struct notifier_block *nb);
3653ada5	224	extern void mce_unregister_decode_chain(struct notifier_block *nb);
df39a2e4	225
9e55e44e	226	#include <linux/percpu.h>
60063497	227	#include <linux/atomic.h>
9e55e44e	228
c6978369	229	extern int mce_p5_enabled;
e2f43029	230
ec6347bb DW	231	#ifdef CONFIG_ARCH_HAS_COPY_MC
	232	extern void enable_copy_mc_fragile(void);
	233	unsigned long __must_check copy_mc_fragile(void dst, const void src, unsigned cnt);
	234	#else
	235	static inline void enable_copy_mc_fragile(void)
	236	{
	237	}
	238	#endif
	239
4a24d80b SK	240	struct cper_ia_proc_ctx;
4a24d80b SK	241
58995d2d	242	#ifdef CONFIG_X86_MCE
a2202aa2	243	int mcheck_init(void);
5e09954a	244	void mcheck_cpu_init(struct cpuinfo_x86 *c);
8838eb6c	245	void mcheck_cpu_clear(struct cpuinfo_x86 *c);
4a24d80b SK	246	int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
4a24d80b SK	247	u64 lapic_id);
58995d2d	248	#else
a2202aa2	249	static inline int mcheck_init(void) { return 0; }
5e09954a	250	static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
8838eb6c	251	static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
4a24d80b SK	252	static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
4a24d80b SK	253	u64 lapic_id) { return -EINVAL; }
58995d2d HS	254	#endif
58995d2d HS	255
750fd239 AN	256	void mce_prep_record(struct mce_hw_err *err);
750fd239 AN	257	void mce_log(struct mce_hw_err *err);
d6126ef5	258	DECLARE_PER_CPU(struct device *, mce_device);
e2f43029	259
a0bc32b3 AG	260	/* Maximum number of MCA banks per CPU. */
a0bc32b3 AG	261	#define MAX_NR_BANKS 64
41fdff32	262
e2f43029 TG	263	#ifdef CONFIG_X86_MCE_INTEL
e2f43029 TG	264	void mce_intel_feature_init(struct cpuinfo_x86 *c);
8838eb6c	265	void mce_intel_feature_clear(struct cpuinfo_x86 *c);
88ccbedd AK	266	void cmci_clear(void);
88ccbedd AK	267	void cmci_reenable(void);
7a0c819d	268	void cmci_rediscover(void);
88ccbedd	269	void cmci_recheck(void);
e2f43029 TG	270	#else
e2f43029 TG	271	static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
8838eb6c	272	static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
88ccbedd AK	273	static inline void cmci_clear(void) {}
88ccbedd AK	274	static inline void cmci_reenable(void) {}
7a0c819d	275	static inline void cmci_rediscover(void) {}
88ccbedd	276	static inline void cmci_recheck(void) {}
e2f43029 TG	277	#endif
e2f43029 TG	278
c845cb8d	279	bool mce_available(struct cpuinfo_x86 *c);
2d1f4061	280	bool mce_is_memory_error(struct mce *m);
5d96c934	281	bool mce_is_correctable(struct mce *m);
1bae0cfe	282	bool mce_usable_address(struct mce *m);
88ccbedd	283
01ca79f1	284	DECLARE_PER_CPU(unsigned, mce_exception_count);
ca84f696	285	DECLARE_PER_CPU(unsigned, mce_poll_count);
01ca79f1	286
ee031c31 AK	287	typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
	288	DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
	289
b79109c3	290	enum mcp_flags {
3f2f0680 BP	291	MCP_TIMESTAMP = BIT(0), /* log time stamp */
	292	MCP_UC = BIT(1), /* log uncorrected errors */
	293	MCP_DONTLOG = BIT(2), /* only clear, don't log */
3bff147b	294	MCP_QUEUE_LOG = BIT(3), /* only queue to genpool */
b79109c3	295	};
5b9d292e YG	296
5b9d292e YG	297	void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
b79109c3	298
ea149b36	299	DECLARE_PER_CPU(struct mce, injectm);
66f5ddf3	300
c3d1fb56 NR	301	/* Disable CMCI/polling for MCA bank claimed by firmware */
	302	extern void mce_disable_bank(int bank);
	303
58995d2d HS	304	/*
	305	* Exception handler
	306	*/
8cd501c1	307	void do_machine_check(struct pt_regs *pt_regs);
58995d2d HS	308
	309	/*
	310	* Threshold handler
	311	*/
b2762686 AK	312	extern void (*mce_threshold_vector)(void);
b2762686 AK	313
24fd78a8 AG	314	/* Deferred error interrupt handler */
	315	extern void (*deferred_error_int_vector)(void);
	316
d334a491 HY	317	/*
	318	* Used by APEI to report memory error via /dev/mcelog
	319	*/
	320
	321	struct cper_sec_mem_err;
	322	extern void apei_mce_report_mem_error(int corrected,
	323	struct cper_sec_mem_err *mem_err);
	324
be0aec23 AG	325	/*
	326	* Enumerate new IP types and HWID values in AMD processors which support
	327	* Scalable MCA.
	328	*/
	329	#ifdef CONFIG_X86_MCE_AMD
be0aec23	330
5896820e YG	331	/* These may be used by multiple smca_hwid_mcatypes */
5896820e YG	332	enum smca_bank_types {
be0aec23	333	SMCA_LS = 0, /* Load Store */
94a311ce	334	SMCA_LS_V2,
be0aec23	335	SMCA_IF, /* Instruction Fetch */
5896820e YG	336	SMCA_L2_CACHE, /* L2 Cache */
5896820e YG	337	SMCA_DE, /* Decoder Unit */
68627a69	338	SMCA_RESERVED, /* Reserved */
5896820e	339	SMCA_EX, /* Execution Unit */
be0aec23	340	SMCA_FP, /* Floating Point */
5896820e YG	341	SMCA_L3_CACHE, /* L3 Cache */
5896820e YG	342	SMCA_CS, /* Coherent Slave */
94a311ce	343	SMCA_CS_V2,
5896820e YG	344	SMCA_PIE, /* Power, Interrupts, etc. */
5896820e YG	345	SMCA_UMC, /* Unified Memory Controller */
94a311ce	346	SMCA_UMC_V2,
47b744ea	347	SMCA_MA_LLC, /* Memory Attached Last Level Cache */
5896820e YG	348	SMCA_PB, /* Parameter Block */
5896820e YG	349	SMCA_PSP, /* Platform Security Processor */
94a311ce	350	SMCA_PSP_V2,
5896820e	351	SMCA_SMU, /* System Management Unit */
94a311ce	352	SMCA_SMU_V2,
cbfa447e	353	SMCA_MP5, /* Microprocessor 5 Unit */
5176a93a	354	SMCA_MPDMA, /* MPDMA Unit */
cbfa447e YG	355	SMCA_NBIO, /* Northbridge IO Unit */
cbfa447e YG	356	SMCA_PCIE, /* PCI Express Unit */
94a311ce M	357	SMCA_PCIE_V2,
94a311ce M	358	SMCA_XGMI_PCS, /* xGMI PCS Unit */
5176a93a YG	359	SMCA_NBIF, /* NBIF Unit */
	360	SMCA_SHUB, /* System HUB Unit */
	361	SMCA_SATA, /* SATA Unit */
	362	SMCA_USB, /* USB Unit */
47b744ea M	363	SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */
47b744ea M	364	SMCA_USR_CP, /* Ultra Short Reach Control Plane Controller */
5176a93a	365	SMCA_GMI_PCS, /* GMI PCS Unit */
94a311ce M	366	SMCA_XGMI_PHY, /* xGMI PHY Unit */
94a311ce M	367	SMCA_WAFL_PHY, /* WAFL PHY Unit */
5176a93a	368	SMCA_GMI_PHY, /* GMI PHY Unit */
5896820e YG	369	N_SMCA_BANK_TYPES
	370	};
	371
c6708d50	372	extern bool amd_mce_is_memory_error(struct mce *m);
e71c3978	373
4d7b02d5 SAS	374	extern int mce_threshold_create_device(unsigned int cpu);
4d7b02d5 SAS	375	extern int mce_threshold_remove_device(unsigned int cpu);
e71c3978	376
9308fd40	377	void mce_amd_feature_init(struct cpuinfo_x86 *c);
91f75eb4	378	enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank);
9308fd40	379	#else
e71c3978	380
9308fd40 YG	381	static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
	382	static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
	383	static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
	384	static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
be0aec23 AG	385	#endif
be0aec23 AG	386
e9c2a283 AB	387	unsigned long copy_mc_fragile_handle_tail(char to, char from, unsigned len);
e9c2a283 AB	388
1965aae3	389	#endif /* _ASM_X86_MCE_H */