[linux-2.6-block.git] / arch / x86 / include / asm / mce.h

#ifndef _ASM_X86_MCE_H
#define _ASM_X86_MCE_H

#include <linux/types.h>
#include <asm/ioctls.h>

/*
 * Machine Check support for x86
 */

#define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
#define MCG_CTL_P		(1ULL<<8)    /* MCG_CTL register available */
#define MCG_EXT_P		(1ULL<<9)    /* Extended registers available */
#define MCG_CMCI_P		(1ULL<<10)   /* CMCI supported */
#define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
#define MCG_EXT_CNT_SHIFT	16
#define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
#define MCG_SER_P	 	(1ULL<<24)   /* MCA recovery/new status bits */

#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */

#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
#define MCI_STATUS_S	 (1ULL<<56)  /* Signaled machine check */
#define MCI_STATUS_AR	 (1ULL<<55)  /* Action required */

/* MISC register defines */
#define MCM_ADDR_SEGOFF  0	/* segment offset */
#define MCM_ADDR_LINEAR  1	/* linear address */
#define MCM_ADDR_PHYS	 2	/* physical address */
#define MCM_ADDR_MEM	 3	/* memory address */
#define MCM_ADDR_GENERIC 7	/* generic */

#define MCJ_CTX_MASK		3
#define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
#define MCJ_CTX_RANDOM		0    /* inject context: random */
#define MCJ_CTX_PROCESS		1    /* inject context: process */
#define MCJ_CTX_IRQ		2    /* inject context: IRQ */
#define MCJ_NMI_BROADCAST	4    /* do NMI broadcasting */
#define MCJ_EXCEPTION		8    /* raise as exception */

/* Fields are zero when not available */
struct mce {
	__u64 status;
	__u64 misc;
	__u64 addr;
	__u64 mcgstatus;
	__u64 ip;
	__u64 tsc;	/* cpu time stamp counter */
	__u64 time;	/* wall time_t when error was detected */
	__u8  cpuvendor;	/* cpu vendor as encoded in system.h */
	__u8  inject_flags;	/* software inject flags */
	__u16  pad;
	__u32 cpuid;	/* CPUID 1 EAX */
	__u8  cs;		/* code segment */
	__u8  bank;	/* machine check bank */
	__u8  cpu;	/* cpu number; obsolete; use extcpu now */
	__u8  finished;   /* entry is valid */
	__u32 extcpu;	/* linux cpu number that detected the error */
	__u32 socketid;	/* CPU socket ID */
	__u32 apicid;	/* CPU initial apic ID */
	__u64 mcgcap;	/* MCGCAP MSR: machine check capabilities of CPU */
};

/*
 * This structure contains all data related to the MCE log.  Also
 * carries a signature to make it easier to find from external
 * debugging tools.  Each entry is only valid when its finished flag
 * is set.
 */

#define MCE_LOG_LEN 32

struct mce_log {
	char signature[12]; /* "MACHINECHECK" */
	unsigned len;	    /* = MCE_LOG_LEN */
	unsigned next;
	unsigned flags;
	unsigned recordlen;	/* length of struct mce */
	struct mce entry[MCE_LOG_LEN];
};

#define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */

#define MCE_LOG_SIGNATURE	"MACHINECHECK"

#define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
#define MCE_GET_LOG_LEN      _IOR('M', 2, int)
#define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)

/* Software defined banks */
#define MCE_EXTENDED_BANK	128
#define MCE_THERMAL_BANK	MCE_EXTENDED_BANK + 0

#define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
#define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
#define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
#define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
#define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
#define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
#define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
#define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)


#ifdef __KERNEL__

extern struct atomic_notifier_head x86_mce_decoder_chain;

#include <linux/percpu.h>
#include <linux/init.h>
#include <asm/atomic.h>

extern int mce_disabled;
extern int mce_p5_enabled;

#ifdef CONFIG_X86_MCE
int mcheck_init(void);
void mcheck_cpu_init(struct cpuinfo_x86 *c);
#else
static inline int mcheck_init(void) { return 0; }
static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
#endif

#ifdef CONFIG_X86_ANCIENT_MCE
void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
void winchip_mcheck_init(struct cpuinfo_x86 *c);
static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
#else
static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
static inline void enable_p5_mce(void) {}
#endif

extern void (*x86_mce_decode_callback)(struct mce *m);

void mce_setup(struct mce *m);
void mce_log(struct mce *m);
DECLARE_PER_CPU(struct sys_device, mce_dev);

/*
 * Maximum banks number.
 * This is the limit of the current register layout on
 * Intel CPUs.
 */
#define MAX_NR_BANKS 32

#ifdef CONFIG_X86_MCE_INTEL
extern int mce_cmci_disabled;
extern int mce_ignore_ce;
void mce_intel_feature_init(struct cpuinfo_x86 *c);
void cmci_clear(void);
void cmci_reenable(void);
void cmci_rediscover(int dying);
void cmci_recheck(void);
#else
static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
static inline void cmci_clear(void) {}
static inline void cmci_reenable(void) {}
static inline void cmci_rediscover(int dying) {}
static inline void cmci_recheck(void) {}
#endif

#ifdef CONFIG_X86_MCE_AMD
void mce_amd_feature_init(struct cpuinfo_x86 *c);
#else
static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
#endif

int mce_available(struct cpuinfo_x86 *c);

DECLARE_PER_CPU(unsigned, mce_exception_count);
DECLARE_PER_CPU(unsigned, mce_poll_count);

extern atomic_t mce_entry;

typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);

enum mcp_flags {
	MCP_TIMESTAMP = (1 << 0),	/* log time stamp */
	MCP_UC = (1 << 1),		/* log uncorrected errors */
	MCP_DONTLOG = (1 << 2),		/* only clear, don't log */
};
void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);

int mce_notify_irq(void);
void mce_notify_process(void);

DECLARE_PER_CPU(struct mce, injectm);
extern struct file_operations mce_chrdev_ops;

/*
 * Exception handler
 */

/* Call the installed machine check handler for this CPU setup. */
extern void (*machine_check_vector)(struct pt_regs *, long error_code);
void do_machine_check(struct pt_regs *, long);

/*
 * Threshold handler
 */

extern void (*mce_threshold_vector)(void);
extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);

/*
 * Thermal handler
 */

void intel_init_thermal(struct cpuinfo_x86 *c);

void mce_log_therm_throt_event(__u64 status);

#ifdef CONFIG_X86_THERMAL_VECTOR
extern void mcheck_intel_therm_init(void);
#else
static inline void mcheck_intel_therm_init(void) { }
#endif

#endif /* __KERNEL__ */
#endif /* _ASM_X86_MCE_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_MCE_H
1965aae3 PA	2	#define _ASM_X86_MCE_H
e2f43029	3
999b697b	4	#include <linux/types.h>
e2f43029	5	#include <asm/ioctls.h>
e2f43029 TG	6
	7	/*
	8	* Machine Check support for x86
	9	*/
	10
01c6680a	11	#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
e4876839	12	#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
01c6680a TG	13	#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
	14	#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
	15	#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
	16	#define MCG_EXT_CNT_SHIFT 16
	17	#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
ed7290d0	18	#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
e2f43029	19
06b851d9 IM	20	#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
	21	#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
	22	#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
e2f43029	23
06b851d9 IM	24	#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
	25	#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
	26	#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
	27	#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
	28	#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
	29	#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
	30	#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
ed7290d0 AK	31	#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
	32	#define MCI_STATUS_AR (1ULL<<55) /* Action required */
	33
	34	/* MISC register defines */
	35	#define MCM_ADDR_SEGOFF 0 /* segment offset */
	36	#define MCM_ADDR_LINEAR 1 /* linear address */
	37	#define MCM_ADDR_PHYS 2 /* physical address */
	38	#define MCM_ADDR_MEM 3 /* memory address */
	39	#define MCM_ADDR_GENERIC 7 /* generic */
e2f43029	40
5b7e88ed HY	41	#define MCJ_CTX_MASK 3
	42	#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
	43	#define MCJ_CTX_RANDOM 0 /* inject context: random */
	44	#define MCJ_CTX_PROCESS 1 /* inject context: process */
	45	#define MCJ_CTX_IRQ 2 /* inject context: IRQ */
	46	#define MCJ_NMI_BROADCAST 4 /* do NMI broadcasting */
0dcc6685	47	#define MCJ_EXCEPTION 8 /* raise as exception */
5b7e88ed	48
e2f43029 TG	49	/* Fields are zero when not available */
	50	struct mce {
	51	__u64 status;
	52	__u64 misc;
	53	__u64 addr;
	54	__u64 mcgstatus;
65ea5b03	55	__u64 ip;
e2f43029	56	__u64 tsc; /* cpu time stamp counter */
8ee08347 AK	57	__u64 time; /* wall time_t when error was detected */
8ee08347 AK	58	__u8 cpuvendor; /* cpu vendor as encoded in system.h */
5b7e88ed HY	59	__u8 inject_flags; /* software inject flags */
5b7e88ed HY	60	__u16 pad;
8ee08347	61	__u32 cpuid; /* CPUID 1 EAX */
e2f43029 TG	62	__u8 cs; /* code segment */
e2f43029 TG	63	__u8 bank; /* machine check bank */
d620c67f	64	__u8 cpu; /* cpu number; obsolete; use extcpu now */
e2f43029	65	__u8 finished; /* entry is valid */
d620c67f	66	__u32 extcpu; /* linux cpu number that detected the error */
8ee08347 AK	67	__u32 socketid; /* CPU socket ID */
	68	__u32 apicid; /* CPU initial apic ID */
	69	__u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
e2f43029 TG	70	};
	71
	72	/*
	73	* This structure contains all data related to the MCE log. Also
	74	* carries a signature to make it easier to find from external
	75	* debugging tools. Each entry is only valid when its finished flag
	76	* is set.
	77	*/
	78
	79	#define MCE_LOG_LEN 32
	80
	81	struct mce_log {
	82	char signature[12]; /* "MACHINECHECK" */
	83	unsigned len; /* = MCE_LOG_LEN */
	84	unsigned next;
	85	unsigned flags;
f6fb0ac0	86	unsigned recordlen; /* length of struct mce */
e2f43029 TG	87	struct mce entry[MCE_LOG_LEN];
	88	};
	89
	90	#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
	91
	92	#define MCE_LOG_SIGNATURE "MACHINECHECK"
	93
	94	#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
	95	#define MCE_GET_LOG_LEN _IOR('M', 2, int)
	96	#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
	97
	98	/* Software defined banks */
	99	#define MCE_EXTENDED_BANK 128
	100	#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
	101
	102	#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
	103	#define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
	104	#define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
	105	#define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
	106	#define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
	107	#define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
	108	#define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
	109	#define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
	110
fb253195	111
e2f43029 TG	112	#ifdef __KERNEL__
e2f43029 TG	113
df39a2e4 AC	114	extern struct atomic_notifier_head x86_mce_decoder_chain;
df39a2e4 AC	115
9e55e44e HS	116	#include <linux/percpu.h>
	117	#include <linux/init.h>
	118	#include <asm/atomic.h>
	119
e2f43029	120	extern int mce_disabled;
c6978369	121	extern int mce_p5_enabled;
e2f43029	122
58995d2d	123	#ifdef CONFIG_X86_MCE
a2202aa2	124	int mcheck_init(void);
5e09954a	125	void mcheck_cpu_init(struct cpuinfo_x86 *c);
58995d2d	126	#else
a2202aa2	127	static inline int mcheck_init(void) { return 0; }
5e09954a	128	static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
58995d2d HS	129	#endif
58995d2d HS	130
9e55e44e HS	131	#ifdef CONFIG_X86_ANCIENT_MCE
	132	void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
	133	void winchip_mcheck_init(struct cpuinfo_x86 *c);
c6978369	134	static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
9e55e44e HS	135	#else
	136	static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
	137	static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
c6978369	138	static inline void enable_p5_mce(void) {}
9e55e44e HS	139	#endif
9e55e44e HS	140
f436f8bb IM	141	extern void (x86_mce_decode_callback)(struct mce m);
f436f8bb IM	142
b5f2fa4e	143	void mce_setup(struct mce *m);
e2f43029	144	void mce_log(struct mce *m);
cb491fca	145	DECLARE_PER_CPU(struct sys_device, mce_dev);
e2f43029	146
41fdff32	147	/*
3ccdccfa AK	148	* Maximum banks number.
	149	* This is the limit of the current register layout on
	150	* Intel CPUs.
41fdff32	151	*/
3ccdccfa	152	#define MAX_NR_BANKS 32
41fdff32	153
e2f43029	154	#ifdef CONFIG_X86_MCE_INTEL
62fdac59 HS	155	extern int mce_cmci_disabled;
62fdac59 HS	156	extern int mce_ignore_ce;
e2f43029	157	void mce_intel_feature_init(struct cpuinfo_x86 *c);
88ccbedd AK	158	void cmci_clear(void);
	159	void cmci_reenable(void);
	160	void cmci_rediscover(int dying);
	161	void cmci_recheck(void);
e2f43029 TG	162	#else
e2f43029 TG	163	static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
88ccbedd AK	164	static inline void cmci_clear(void) {}
	165	static inline void cmci_reenable(void) {}
	166	static inline void cmci_rediscover(int dying) {}
	167	static inline void cmci_recheck(void) {}
e2f43029 TG	168	#endif
	169
	170	#ifdef CONFIG_X86_MCE_AMD
	171	void mce_amd_feature_init(struct cpuinfo_x86 *c);
	172	#else
	173	static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
	174	#endif
	175
38736072	176	int mce_available(struct cpuinfo_x86 *c);
88ccbedd	177
01ca79f1	178	DECLARE_PER_CPU(unsigned, mce_exception_count);
ca84f696	179	DECLARE_PER_CPU(unsigned, mce_poll_count);
01ca79f1	180
e2f43029 TG	181	extern atomic_t mce_entry;
e2f43029 TG	182
ee031c31 AK	183	typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
	184	DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
	185
b79109c3 AK	186	enum mcp_flags {
	187	MCP_TIMESTAMP = (1 << 0), /* log time stamp */
	188	MCP_UC = (1 << 1), /* log uncorrected errors */
5679af4c	189	MCP_DONTLOG = (1 << 2), /* only clear, don't log */
b79109c3	190	};
38736072	191	void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
b79109c3	192
9ff36ee9	193	int mce_notify_irq(void);
9b1beaf2	194	void mce_notify_process(void);
e2f43029	195
ea149b36 AK	196	DECLARE_PER_CPU(struct mce, injectm);
	197	extern struct file_operations mce_chrdev_ops;
	198
58995d2d HS	199	/*
	200	* Exception handler
	201	*/
	202
	203	/* Call the installed machine check handler for this CPU setup. */
	204	extern void (machine_check_vector)(struct pt_regs , long error_code);
	205	void do_machine_check(struct pt_regs *, long);
	206
	207	/*
	208	* Threshold handler
	209	*/
e2f43029	210
b2762686	211	extern void (*mce_threshold_vector)(void);
58995d2d	212	extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
b2762686	213
e8ce2c5e HS	214	/*
	215	* Thermal handler
	216	*/
	217
e8ce2c5e HS	218	void intel_init_thermal(struct cpuinfo_x86 *c);
e8ce2c5e HS	219
e8ce2c5e	220	void mce_log_therm_throt_event(__u64 status);
a2202aa2 YW	221
	222	#ifdef CONFIG_X86_THERMAL_VECTOR
	223	extern void mcheck_intel_therm_init(void);
	224	#else
	225	static inline void mcheck_intel_therm_init(void) { }
	226	#endif
	227
e2f43029	228	#endif /* __KERNEL__ */
1965aae3	229	#endif /* _ASM_X86_MCE_H */