[linux-block.git] / arch / x86 / include / asm / mce.h

#ifndef _ASM_X86_MCE_H
#define _ASM_X86_MCE_H

#ifdef __x86_64__

#include <linux/types.h>
#include <asm/ioctls.h>

/*
 * Machine Check support for x86
 */

#define MCG_CTL_P	 (1UL<<8)   /* MCG_CAP register available */
#define MCG_EXT_P	 (1ULL<<9)   /* Extended registers available */
#define MCG_CMCI_P	 (1ULL<<10)  /* CMCI supported */

#define MCG_STATUS_RIPV  (1UL<<0)   /* restart ip valid */
#define MCG_STATUS_EIPV  (1UL<<1)   /* ip points to correct instruction */
#define MCG_STATUS_MCIP  (1UL<<2)   /* machine check in progress */

#define MCI_STATUS_VAL   (1UL<<63)  /* valid error */
#define MCI_STATUS_OVER  (1UL<<62)  /* previous errors lost */
#define MCI_STATUS_UC    (1UL<<61)  /* uncorrected error */
#define MCI_STATUS_EN    (1UL<<60)  /* error enabled */
#define MCI_STATUS_MISCV (1UL<<59)  /* misc error reg. valid */
#define MCI_STATUS_ADDRV (1UL<<58)  /* addr reg. valid */
#define MCI_STATUS_PCC   (1UL<<57)  /* processor context corrupt */

/* Fields are zero when not available */
struct mce {
	__u64 status;
	__u64 misc;
	__u64 addr;
	__u64 mcgstatus;
	__u64 ip;
	__u64 tsc;	/* cpu time stamp counter */
	__u64 res1;	/* for future extension */
	__u64 res2;	/* dito. */
	__u8  cs;		/* code segment */
	__u8  bank;	/* machine check bank */
	__u8  cpu;	/* cpu that raised the error */
	__u8  finished;   /* entry is valid */
	__u32 pad;
};

/*
 * This structure contains all data related to the MCE log.  Also
 * carries a signature to make it easier to find from external
 * debugging tools.  Each entry is only valid when its finished flag
 * is set.
 */

#define MCE_LOG_LEN 32

struct mce_log {
	char signature[12]; /* "MACHINECHECK" */
	unsigned len;	    /* = MCE_LOG_LEN */
	unsigned next;
	unsigned flags;
	unsigned pad0;
	struct mce entry[MCE_LOG_LEN];
};

#define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */

#define MCE_LOG_SIGNATURE	"MACHINECHECK"

#define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
#define MCE_GET_LOG_LEN      _IOR('M', 2, int)
#define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)

/* Software defined banks */
#define MCE_EXTENDED_BANK	128
#define MCE_THERMAL_BANK	MCE_EXTENDED_BANK + 0

#define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
#define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
#define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
#define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
#define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
#define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
#define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
#define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)

#endif /* __x86_64__ */

#ifdef __KERNEL__

#ifdef CONFIG_X86_32
extern int mce_disabled;
#else /* CONFIG_X86_32 */

#include <asm/atomic.h>

void mce_setup(struct mce *m);
void mce_log(struct mce *m);
DECLARE_PER_CPU(struct sys_device, device_mce);
extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);

/*
 * To support more than 128 would need to escape the predefined
 * Linux defined extended banks first.
 */
#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)

#ifdef CONFIG_X86_MCE_INTEL
void mce_intel_feature_init(struct cpuinfo_x86 *c);
void cmci_clear(void);
void cmci_reenable(void);
void cmci_rediscover(int dying);
void cmci_recheck(void);
#else
static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
static inline void cmci_clear(void) {}
static inline void cmci_reenable(void) {}
static inline void cmci_rediscover(int dying) {}
static inline void cmci_recheck(void) {}
#endif

#ifdef CONFIG_X86_MCE_AMD
void mce_amd_feature_init(struct cpuinfo_x86 *c);
#else
static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
#endif

extern int mce_available(struct cpuinfo_x86 *c);

void mce_log_therm_throt_event(__u64 status);

extern atomic_t mce_entry;

extern void do_machine_check(struct pt_regs *, long);

typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);

enum mcp_flags {
	MCP_TIMESTAMP = (1 << 0),	/* log time stamp */
	MCP_UC = (1 << 1),		/* log uncorrected errors */
};
extern void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);

extern int mce_notify_user(void);

#endif /* !CONFIG_X86_32 */

#ifdef CONFIG_X86_MCE
extern void mcheck_init(struct cpuinfo_x86 *c);
#else
#define mcheck_init(c) do { } while (0)
#endif

extern void (*mce_threshold_vector)(void);

#endif /* __KERNEL__ */
#endif /* _ASM_X86_MCE_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_MCE_H
1965aae3 PA	2	#define _ASM_X86_MCE_H
e2f43029 TG	3
	4	#ifdef __x86_64__
	5
999b697b	6	#include <linux/types.h>
e2f43029	7	#include <asm/ioctls.h>
e2f43029 TG	8
	9	/*
	10	* Machine Check support for x86
	11	*/
	12
	13	#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */
03195c6b AK	14	#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
03195c6b AK	15	#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
e2f43029 TG	16
e2f43029 TG	17	#define MCG_STATUS_RIPV (1UL<<0) /* restart ip valid */
65ea5b03	18	#define MCG_STATUS_EIPV (1UL<<1) /* ip points to correct instruction */
e2f43029 TG	19	#define MCG_STATUS_MCIP (1UL<<2) /* machine check in progress */
	20
	21	#define MCI_STATUS_VAL (1UL<<63) /* valid error */
	22	#define MCI_STATUS_OVER (1UL<<62) /* previous errors lost */
	23	#define MCI_STATUS_UC (1UL<<61) /* uncorrected error */
	24	#define MCI_STATUS_EN (1UL<<60) /* error enabled */
	25	#define MCI_STATUS_MISCV (1UL<<59) /* misc error reg. valid */
	26	#define MCI_STATUS_ADDRV (1UL<<58) /* addr reg. valid */
	27	#define MCI_STATUS_PCC (1UL<<57) /* processor context corrupt */
	28
	29	/* Fields are zero when not available */
	30	struct mce {
	31	__u64 status;
	32	__u64 misc;
	33	__u64 addr;
	34	__u64 mcgstatus;
65ea5b03	35	__u64 ip;
e2f43029 TG	36	__u64 tsc; /* cpu time stamp counter */
	37	__u64 res1; /* for future extension */
	38	__u64 res2; /* dito. */
	39	__u8 cs; /* code segment */
	40	__u8 bank; /* machine check bank */
	41	__u8 cpu; /* cpu that raised the error */
	42	__u8 finished; /* entry is valid */
	43	__u32 pad;
	44	};
	45
	46	/*
	47	* This structure contains all data related to the MCE log. Also
	48	* carries a signature to make it easier to find from external
	49	* debugging tools. Each entry is only valid when its finished flag
	50	* is set.
	51	*/
	52
	53	#define MCE_LOG_LEN 32
	54
	55	struct mce_log {
	56	char signature[12]; /* "MACHINECHECK" */
	57	unsigned len; /* = MCE_LOG_LEN */
	58	unsigned next;
	59	unsigned flags;
	60	unsigned pad0;
	61	struct mce entry[MCE_LOG_LEN];
	62	};
	63
	64	#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
	65
	66	#define MCE_LOG_SIGNATURE "MACHINECHECK"
	67
	68	#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
	69	#define MCE_GET_LOG_LEN _IOR('M', 2, int)
	70	#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
	71
	72	/* Software defined banks */
	73	#define MCE_EXTENDED_BANK 128
	74	#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
	75
	76	#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
	77	#define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
	78	#define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
	79	#define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
	80	#define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
	81	#define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
	82	#define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
	83	#define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
	84
	85	#endif /* __x86_64__ */
	86
	87	#ifdef __KERNEL__
	88
96a388de	89	#ifdef CONFIG_X86_32
e2f43029	90	extern int mce_disabled;
e2f43029 TG	91	#else /* CONFIG_X86_32 */
	92
	93	#include <asm/atomic.h>
	94
b5f2fa4e	95	void mce_setup(struct mce *m);
e2f43029 TG	96	void mce_log(struct mce *m);
e2f43029 TG	97	DECLARE_PER_CPU(struct sys_device, device_mce);
8735728e	98	extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
e2f43029	99
41fdff32 AK	100	/*
	101	* To support more than 128 would need to escape the predefined
	102	* Linux defined extended banks first.
	103	*/
	104	#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)
	105
e2f43029 TG	106	#ifdef CONFIG_X86_MCE_INTEL
e2f43029 TG	107	void mce_intel_feature_init(struct cpuinfo_x86 *c);
88ccbedd AK	108	void cmci_clear(void);
	109	void cmci_reenable(void);
	110	void cmci_rediscover(int dying);
	111	void cmci_recheck(void);
e2f43029 TG	112	#else
e2f43029 TG	113	static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
88ccbedd AK	114	static inline void cmci_clear(void) {}
	115	static inline void cmci_reenable(void) {}
	116	static inline void cmci_rediscover(int dying) {}
	117	static inline void cmci_recheck(void) {}
e2f43029 TG	118	#endif
	119
	120	#ifdef CONFIG_X86_MCE_AMD
	121	void mce_amd_feature_init(struct cpuinfo_x86 *c);
	122	#else
	123	static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
	124	#endif
	125
88ccbedd AK	126	extern int mce_available(struct cpuinfo_x86 *c);
88ccbedd AK	127
b5f2fa4e	128	void mce_log_therm_throt_event(__u64 status);
e2f43029 TG	129
	130	extern atomic_t mce_entry;
	131
	132	extern void do_machine_check(struct pt_regs *, long);
b79109c3	133
ee031c31 AK	134	typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
	135	DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
	136
b79109c3 AK	137	enum mcp_flags {
	138	MCP_TIMESTAMP = (1 << 0), /* log time stamp */
	139	MCP_UC = (1 << 1), /* log uncorrected errors */
	140	};
ee031c31	141	extern void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
b79109c3	142
e2f43029 TG	143	extern int mce_notify_user(void);
	144
	145	#endif /* !CONFIG_X86_32 */
	146
af7a78e9 TG	147	#ifdef CONFIG_X86_MCE
	148	extern void mcheck_init(struct cpuinfo_x86 *c);
	149	#else
	150	#define mcheck_init(c) do { } while (0)
	151	#endif
e2f43029	152
b2762686 AK	153	extern void (*mce_threshold_vector)(void);
b2762686 AK	154
e2f43029	155	#endif /* __KERNEL__ */
1965aae3	156	#endif /* _ASM_X86_MCE_H */