Commit | Line | Data |
---|---|---|
05e4d316 PA |
1 | #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H |
2 | #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H | |
1da177e4 | 3 | |
dd46e3ca GC |
4 | #ifdef CONFIG_X86_LOCAL_APIC |
5 | ||
1da177e4 LT |
6 | #include <mach_apicdef.h> |
7 | #include <asm/smp.h> | |
8 | ||
9 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
10 | ||
e7986739 | 11 | static inline const cpumask_t *target_cpus(void) |
1da177e4 LT |
12 | { |
13 | #ifdef CONFIG_SMP | |
e7986739 | 14 | return &cpu_online_map; |
1da177e4 | 15 | #else |
e7986739 | 16 | return &cpumask_of_cpu(0); |
1da177e4 LT |
17 | #endif |
18 | } | |
1da177e4 LT |
19 | |
20 | #define NO_BALANCE_IRQ (0) | |
21 | #define esr_disable (0) | |
22 | ||
dd46e3ca GC |
23 | #ifdef CONFIG_X86_64 |
24 | #include <asm/genapic.h> | |
25 | #define INT_DELIVERY_MODE (genapic->int_delivery_mode) | |
26 | #define INT_DEST_MODE (genapic->int_dest_mode) | |
27 | #define TARGET_CPUS (genapic->target_cpus()) | |
28 | #define apic_id_registered (genapic->apic_id_registered) | |
29 | #define init_apic_ldr (genapic->init_apic_ldr) | |
30 | #define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid) | |
31 | #define phys_pkg_id (genapic->phys_pkg_id) | |
32 | #define vector_allocation_domain (genapic->vector_allocation_domain) | |
f910a9dc | 33 | #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID))) |
cff73a6f | 34 | #define send_IPI_self (genapic->send_IPI_self) |
54ac14a8 | 35 | #define wakeup_secondary_cpu (genapic->wakeup_cpu) |
dd46e3ca GC |
36 | extern void setup_apic_routing(void); |
37 | #else | |
1da177e4 LT |
38 | #define INT_DELIVERY_MODE dest_LowestPrio |
39 | #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ | |
dd46e3ca | 40 | #define TARGET_CPUS (target_cpus()) |
54ac14a8 | 41 | #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init |
1da177e4 LT |
42 | /* |
43 | * Set up the logical destination ID. | |
44 | * | |
45 | * Intel recommends to set DFR, LDR and TPR before enabling | |
46 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
47 | * document number 292116). So here it goes... | |
48 | */ | |
49 | static inline void init_apic_ldr(void) | |
50 | { | |
51 | unsigned long val; | |
52 | ||
593f4a78 | 53 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
1da177e4 LT |
54 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
55 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
593f4a78 | 56 | apic_write(APIC_LDR, val); |
1da177e4 LT |
57 | } |
58 | ||
dd46e3ca | 59 | static inline int apic_id_registered(void) |
1da177e4 | 60 | { |
4c9961d5 | 61 | return physid_isset(read_apic_id(), phys_cpu_present_map); |
dd46e3ca GC |
62 | } |
63 | ||
e7986739 | 64 | static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask) |
dd46e3ca | 65 | { |
e7986739 | 66 | return cpus_addr(*cpumask)[0]; |
dd46e3ca GC |
67 | } |
68 | ||
69 | static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) | |
70 | { | |
71 | return cpuid_apic >> index_msb; | |
1da177e4 LT |
72 | } |
73 | ||
3c43f039 | 74 | static inline void setup_apic_routing(void) |
1da177e4 | 75 | { |
61048c63 | 76 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
77 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", |
78 | "Flat", nr_ioapics); | |
61048c63 | 79 | #endif |
1da177e4 LT |
80 | } |
81 | ||
dd46e3ca | 82 | static inline int apicid_to_node(int logical_apicid) |
1da177e4 | 83 | { |
f47f9d53 YL |
84 | #ifdef CONFIG_SMP |
85 | return apicid_2_node[hard_smp_processor_id()]; | |
86 | #else | |
1da177e4 | 87 | return 0; |
f47f9d53 | 88 | #endif |
1da177e4 | 89 | } |
497c9a19 | 90 | |
e7986739 | 91 | static inline void vector_allocation_domain(int cpu, cpumask_t *retmask) |
497c9a19 YL |
92 | { |
93 | /* Careful. Some cpus do not strictly honor the set of cpus | |
94 | * specified in the interrupt destination when using lowest | |
95 | * priority interrupt delivery mode. | |
96 | * | |
97 | * In particular there was a hyperthreading cpu observed to | |
98 | * deliver interrupts to the wrong hyperthread when only one | |
99 | * hyperthread was specified in the interrupt desitination. | |
100 | */ | |
e7986739 | 101 | *retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } }; |
497c9a19 | 102 | } |
dd46e3ca | 103 | #endif |
1da177e4 | 104 | |
dd46e3ca GC |
105 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) |
106 | { | |
107 | return physid_isset(apicid, bitmap); | |
108 | } | |
109 | ||
110 | static inline unsigned long check_apicid_present(int bit) | |
111 | { | |
112 | return physid_isset(bit, phys_cpu_present_map); | |
113 | } | |
114 | ||
115 | static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map) | |
116 | { | |
117 | return phys_map; | |
118 | } | |
119 | ||
120 | static inline int multi_timer_check(int apic, int irq) | |
1da177e4 LT |
121 | { |
122 | return 0; | |
123 | } | |
124 | ||
125 | /* Mapping from cpu number to logical apicid */ | |
126 | static inline int cpu_to_logical_apicid(int cpu) | |
127 | { | |
128 | return 1 << cpu; | |
129 | } | |
130 | ||
131 | static inline int cpu_present_to_apicid(int mps_cpu) | |
132 | { | |
e7986739 | 133 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) |
f6bc4029 | 134 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); |
1da177e4 LT |
135 | else |
136 | return BAD_APICID; | |
137 | } | |
138 | ||
139 | static inline physid_mask_t apicid_to_cpu_present(int phys_apicid) | |
140 | { | |
141 | return physid_mask_of_physid(phys_apicid); | |
142 | } | |
143 | ||
1da177e4 LT |
144 | static inline void setup_portio_remap(void) |
145 | { | |
146 | } | |
147 | ||
148 | static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) | |
149 | { | |
150 | return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); | |
151 | } | |
152 | ||
1da177e4 LT |
153 | static inline void enable_apic_mode(void) |
154 | { | |
155 | } | |
dd46e3ca | 156 | #endif /* CONFIG_X86_LOCAL_APIC */ |
05e4d316 | 157 | #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */ |