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05e4d316 PA |
1 | #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H |
2 | #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H | |
1da177e4 | 3 | |
dd46e3ca GC |
4 | #ifdef CONFIG_X86_LOCAL_APIC |
5 | ||
1da177e4 LT |
6 | #include <mach_apicdef.h> |
7 | #include <asm/smp.h> | |
8 | ||
9 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
10 | ||
0a9cc20b | 11 | static inline const struct cpumask *default_target_cpus(void) |
1da177e4 LT |
12 | { |
13 | #ifdef CONFIG_SMP | |
bcda016e | 14 | return cpu_online_mask; |
1da177e4 | 15 | #else |
bcda016e | 16 | return cpumask_of(0); |
1da177e4 LT |
17 | #endif |
18 | } | |
1da177e4 | 19 | |
dd46e3ca GC |
20 | #ifdef CONFIG_X86_64 |
21 | #include <asm/genapic.h> | |
ca6c8ed4 | 22 | #define read_apic_id() (apic->get_apic_id(apic_read(APIC_ID))) |
c8d46cf0 IM |
23 | #define send_IPI_self (apic->send_IPI_self) |
24 | #define wakeup_secondary_cpu (apic->wakeup_cpu) | |
72ce0165 | 25 | extern void default_setup_apic_routing(void); |
dd46e3ca | 26 | #else |
54ac14a8 | 27 | #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init |
1da177e4 LT |
28 | /* |
29 | * Set up the logical destination ID. | |
30 | * | |
31 | * Intel recommends to set DFR, LDR and TPR before enabling | |
32 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
33 | * document number 292116). So here it goes... | |
34 | */ | |
a5c43296 | 35 | static inline void default_init_apic_ldr(void) |
1da177e4 LT |
36 | { |
37 | unsigned long val; | |
38 | ||
593f4a78 | 39 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
1da177e4 LT |
40 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
41 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
593f4a78 | 42 | apic_write(APIC_LDR, val); |
1da177e4 LT |
43 | } |
44 | ||
7ed248da | 45 | static inline int default_apic_id_registered(void) |
1da177e4 | 46 | { |
4c9961d5 | 47 | return physid_isset(read_apic_id(), phys_cpu_present_map); |
dd46e3ca GC |
48 | } |
49 | ||
debccb3e IM |
50 | static inline unsigned int |
51 | default_cpu_mask_to_apicid(const struct cpumask *cpumask) | |
dd46e3ca | 52 | { |
bcda016e | 53 | return cpumask_bits(cpumask)[0]; |
dd46e3ca GC |
54 | } |
55 | ||
debccb3e IM |
56 | static inline unsigned int |
57 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
58 | const struct cpumask *andmask) | |
95d313cf | 59 | { |
6eeb7c5a MT |
60 | unsigned long mask1 = cpumask_bits(cpumask)[0]; |
61 | unsigned long mask2 = cpumask_bits(andmask)[0]; | |
a775a38b | 62 | unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; |
95d313cf | 63 | |
a775a38b | 64 | return (unsigned int)(mask1 & mask2 & mask3); |
95d313cf MT |
65 | } |
66 | ||
cb8cc442 | 67 | static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) |
dd46e3ca GC |
68 | { |
69 | return cpuid_apic >> index_msb; | |
1da177e4 LT |
70 | } |
71 | ||
72ce0165 | 72 | static inline void default_setup_apic_routing(void) |
1da177e4 | 73 | { |
61048c63 | 74 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
75 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", |
76 | "Flat", nr_ioapics); | |
61048c63 | 77 | #endif |
1da177e4 LT |
78 | } |
79 | ||
3f57a318 | 80 | static inline int default_apicid_to_node(int logical_apicid) |
1da177e4 | 81 | { |
f47f9d53 YL |
82 | #ifdef CONFIG_SMP |
83 | return apicid_2_node[hard_smp_processor_id()]; | |
84 | #else | |
1da177e4 | 85 | return 0; |
f47f9d53 | 86 | #endif |
1da177e4 | 87 | } |
497c9a19 | 88 | |
dd46e3ca | 89 | #endif |
1da177e4 | 90 | |
d1d7cae8 | 91 | static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) |
dd46e3ca GC |
92 | { |
93 | return physid_isset(apicid, bitmap); | |
94 | } | |
95 | ||
d1d7cae8 | 96 | static inline unsigned long default_check_apicid_present(int bit) |
dd46e3ca GC |
97 | { |
98 | return physid_isset(bit, phys_cpu_present_map); | |
99 | } | |
100 | ||
d190cb87 | 101 | static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) |
dd46e3ca GC |
102 | { |
103 | return phys_map; | |
104 | } | |
105 | ||
1da177e4 | 106 | /* Mapping from cpu number to logical apicid */ |
5257c511 | 107 | static inline int default_cpu_to_logical_apicid(int cpu) |
1da177e4 LT |
108 | { |
109 | return 1 << cpu; | |
110 | } | |
111 | ||
a21769a4 | 112 | static inline int __default_cpu_present_to_apicid(int mps_cpu) |
1da177e4 | 113 | { |
e7986739 | 114 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) |
f6bc4029 | 115 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); |
1da177e4 LT |
116 | else |
117 | return BAD_APICID; | |
118 | } | |
119 | ||
a27a6210 IM |
120 | static inline int |
121 | __default_check_phys_apicid_present(int boot_cpu_physical_apicid) | |
122 | { | |
123 | return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); | |
124 | } | |
125 | ||
a21769a4 IM |
126 | #ifdef CONFIG_X86_32 |
127 | static inline int default_cpu_present_to_apicid(int mps_cpu) | |
128 | { | |
129 | return __default_cpu_present_to_apicid(mps_cpu); | |
130 | } | |
a27a6210 IM |
131 | |
132 | static inline int | |
133 | default_check_phys_apicid_present(int boot_cpu_physical_apicid) | |
134 | { | |
135 | return __default_check_phys_apicid_present(boot_cpu_physical_apicid); | |
136 | } | |
a21769a4 IM |
137 | #else |
138 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
a27a6210 | 139 | extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); |
a21769a4 IM |
140 | #endif |
141 | ||
8058714a | 142 | static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) |
1da177e4 LT |
143 | { |
144 | return physid_mask_of_physid(phys_apicid); | |
145 | } | |
146 | ||
dd46e3ca | 147 | #endif /* CONFIG_X86_LOCAL_APIC */ |
05e4d316 | 148 | #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */ |