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05e4d316 PA |
1 | #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H |
2 | #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H | |
1da177e4 | 3 | |
dd46e3ca GC |
4 | #ifdef CONFIG_X86_LOCAL_APIC |
5 | ||
1da177e4 LT |
6 | #include <mach_apicdef.h> |
7 | #include <asm/smp.h> | |
8 | ||
9 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
10 | ||
0a9cc20b | 11 | static inline const struct cpumask *default_target_cpus(void) |
1da177e4 LT |
12 | { |
13 | #ifdef CONFIG_SMP | |
bcda016e | 14 | return cpu_online_mask; |
1da177e4 | 15 | #else |
bcda016e | 16 | return cpumask_of(0); |
1da177e4 LT |
17 | #endif |
18 | } | |
1da177e4 | 19 | |
dd46e3ca GC |
20 | #ifdef CONFIG_X86_64 |
21 | #include <asm/genapic.h> | |
ca6c8ed4 | 22 | #define read_apic_id() (apic->get_apic_id(apic_read(APIC_ID))) |
c8d46cf0 | 23 | #define wakeup_secondary_cpu (apic->wakeup_cpu) |
72ce0165 | 24 | extern void default_setup_apic_routing(void); |
dd46e3ca | 25 | #else |
54ac14a8 | 26 | #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init |
1da177e4 LT |
27 | /* |
28 | * Set up the logical destination ID. | |
29 | * | |
30 | * Intel recommends to set DFR, LDR and TPR before enabling | |
31 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
32 | * document number 292116). So here it goes... | |
33 | */ | |
a5c43296 | 34 | static inline void default_init_apic_ldr(void) |
1da177e4 LT |
35 | { |
36 | unsigned long val; | |
37 | ||
593f4a78 | 38 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
1da177e4 LT |
39 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
40 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
593f4a78 | 41 | apic_write(APIC_LDR, val); |
1da177e4 LT |
42 | } |
43 | ||
7ed248da | 44 | static inline int default_apic_id_registered(void) |
1da177e4 | 45 | { |
4c9961d5 | 46 | return physid_isset(read_apic_id(), phys_cpu_present_map); |
dd46e3ca GC |
47 | } |
48 | ||
debccb3e IM |
49 | static inline unsigned int |
50 | default_cpu_mask_to_apicid(const struct cpumask *cpumask) | |
dd46e3ca | 51 | { |
bcda016e | 52 | return cpumask_bits(cpumask)[0]; |
dd46e3ca GC |
53 | } |
54 | ||
debccb3e IM |
55 | static inline unsigned int |
56 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
57 | const struct cpumask *andmask) | |
95d313cf | 58 | { |
6eeb7c5a MT |
59 | unsigned long mask1 = cpumask_bits(cpumask)[0]; |
60 | unsigned long mask2 = cpumask_bits(andmask)[0]; | |
a775a38b | 61 | unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; |
95d313cf | 62 | |
a775a38b | 63 | return (unsigned int)(mask1 & mask2 & mask3); |
95d313cf MT |
64 | } |
65 | ||
cb8cc442 | 66 | static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) |
dd46e3ca GC |
67 | { |
68 | return cpuid_apic >> index_msb; | |
1da177e4 LT |
69 | } |
70 | ||
72ce0165 | 71 | static inline void default_setup_apic_routing(void) |
1da177e4 | 72 | { |
61048c63 | 73 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
74 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", |
75 | "Flat", nr_ioapics); | |
61048c63 | 76 | #endif |
1da177e4 LT |
77 | } |
78 | ||
3f57a318 | 79 | static inline int default_apicid_to_node(int logical_apicid) |
1da177e4 | 80 | { |
f47f9d53 YL |
81 | #ifdef CONFIG_SMP |
82 | return apicid_2_node[hard_smp_processor_id()]; | |
83 | #else | |
1da177e4 | 84 | return 0; |
f47f9d53 | 85 | #endif |
1da177e4 | 86 | } |
497c9a19 | 87 | |
dd46e3ca | 88 | #endif |
1da177e4 | 89 | |
d1d7cae8 | 90 | static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) |
dd46e3ca GC |
91 | { |
92 | return physid_isset(apicid, bitmap); | |
93 | } | |
94 | ||
d1d7cae8 | 95 | static inline unsigned long default_check_apicid_present(int bit) |
dd46e3ca GC |
96 | { |
97 | return physid_isset(bit, phys_cpu_present_map); | |
98 | } | |
99 | ||
d190cb87 | 100 | static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) |
dd46e3ca GC |
101 | { |
102 | return phys_map; | |
103 | } | |
104 | ||
1da177e4 | 105 | /* Mapping from cpu number to logical apicid */ |
5257c511 | 106 | static inline int default_cpu_to_logical_apicid(int cpu) |
1da177e4 LT |
107 | { |
108 | return 1 << cpu; | |
109 | } | |
110 | ||
a21769a4 | 111 | static inline int __default_cpu_present_to_apicid(int mps_cpu) |
1da177e4 | 112 | { |
e7986739 | 113 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) |
f6bc4029 | 114 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); |
1da177e4 LT |
115 | else |
116 | return BAD_APICID; | |
117 | } | |
118 | ||
a27a6210 IM |
119 | static inline int |
120 | __default_check_phys_apicid_present(int boot_cpu_physical_apicid) | |
121 | { | |
122 | return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); | |
123 | } | |
124 | ||
a21769a4 IM |
125 | #ifdef CONFIG_X86_32 |
126 | static inline int default_cpu_present_to_apicid(int mps_cpu) | |
127 | { | |
128 | return __default_cpu_present_to_apicid(mps_cpu); | |
129 | } | |
a27a6210 IM |
130 | |
131 | static inline int | |
132 | default_check_phys_apicid_present(int boot_cpu_physical_apicid) | |
133 | { | |
134 | return __default_check_phys_apicid_present(boot_cpu_physical_apicid); | |
135 | } | |
a21769a4 IM |
136 | #else |
137 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
a27a6210 | 138 | extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); |
a21769a4 IM |
139 | #endif |
140 | ||
8058714a | 141 | static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) |
1da177e4 LT |
142 | { |
143 | return physid_mask_of_physid(phys_apicid); | |
144 | } | |
145 | ||
dd46e3ca | 146 | #endif /* CONFIG_X86_LOCAL_APIC */ |
05e4d316 | 147 | #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */ |