Commit | Line | Data |
---|---|---|
a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
447ae316 | 20 | #include <linux/irq.h> |
34c16eec ZX |
21 | |
22 | #include <linux/kvm.h> | |
23 | #include <linux/kvm_para.h> | |
edf88417 | 24 | #include <linux/kvm_types.h> |
f5132b01 | 25 | #include <linux/perf_event.h> |
d828199e MT |
26 | #include <linux/pvclock_gtod.h> |
27 | #include <linux/clocksource.h> | |
87276880 | 28 | #include <linux/irqbypass.h> |
5c919412 | 29 | #include <linux/hyperv.h> |
34c16eec | 30 | |
7d669f50 | 31 | #include <asm/apic.h> |
50d0a0f9 | 32 | #include <asm/pvclock-abi.h> |
e01a1b57 | 33 | #include <asm/desc.h> |
0bed3b56 | 34 | #include <asm/mtrr.h> |
9962d032 | 35 | #include <asm/msr-index.h> |
3ee89722 | 36 | #include <asm/asm.h> |
21ebbeda | 37 | #include <asm/kvm_page_track.h> |
95c7b77d | 38 | #include <asm/kvm_vcpu_regs.h> |
5a485803 | 39 | #include <asm/hyperv-tlfs.h> |
e01a1b57 | 40 | |
682f732e | 41 | #define KVM_MAX_VCPUS 288 |
757883de | 42 | #define KVM_SOFT_MAX_VCPUS 240 |
af1bae54 | 43 | #define KVM_MAX_VCPU_ID 1023 |
1d4e7e3c | 44 | #define KVM_USER_MEM_SLOTS 509 |
0743247f AW |
45 | /* memory slots that are not exposed to userspace */ |
46 | #define KVM_PRIVATE_MEM_SLOTS 3 | |
bbacc0c1 | 47 | #define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
93a5cef0 | 48 | |
b401ee0b | 49 | #define KVM_HALT_POLL_NS_DEFAULT 200000 |
69a9f69b | 50 | |
8175e5b7 AG |
51 | #define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS |
52 | ||
2860c4b1 | 53 | /* x86-specific vcpu->requests bit members */ |
2387149e AJ |
54 | #define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0) |
55 | #define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1) | |
56 | #define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2) | |
57 | #define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3) | |
58 | #define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4) | |
6e42782f | 59 | #define KVM_REQ_LOAD_CR3 KVM_ARCH_REQ(5) |
2387149e AJ |
60 | #define KVM_REQ_EVENT KVM_ARCH_REQ(6) |
61 | #define KVM_REQ_APF_HALT KVM_ARCH_REQ(7) | |
62 | #define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8) | |
63 | #define KVM_REQ_NMI KVM_ARCH_REQ(9) | |
64 | #define KVM_REQ_PMU KVM_ARCH_REQ(10) | |
65 | #define KVM_REQ_PMI KVM_ARCH_REQ(11) | |
66 | #define KVM_REQ_SMI KVM_ARCH_REQ(12) | |
67 | #define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13) | |
68 | #define KVM_REQ_MCLOCK_INPROGRESS \ | |
69 | KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
70 | #define KVM_REQ_SCAN_IOAPIC \ | |
71 | KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
72 | #define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16) | |
73 | #define KVM_REQ_APIC_PAGE_RELOAD \ | |
74 | KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) | |
75 | #define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18) | |
76 | #define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19) | |
77 | #define KVM_REQ_HV_RESET KVM_ARCH_REQ(20) | |
78 | #define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21) | |
79 | #define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22) | |
e40ff1d6 | 80 | #define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23) |
7f7f1ba3 | 81 | #define KVM_REQ_GET_VMCS12_PAGES KVM_ARCH_REQ(24) |
2860c4b1 | 82 | |
cfec82cb JR |
83 | #define CR0_RESERVED_BITS \ |
84 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
85 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
86 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
87 | ||
cfec82cb JR |
88 | #define CR4_RESERVED_BITS \ |
89 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
90 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
ad756a16 | 91 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ |
afcbf13f | 92 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ |
fd8cb433 | 93 | | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ |
ae3e61e1 | 94 | | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) |
cfec82cb JR |
95 | |
96 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
97 | ||
98 | ||
cd6e8f87 | 99 | |
cd6e8f87 | 100 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
101 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
102 | ||
cd6e8f87 ZX |
103 | #define UNMAPPED_GVA (~(gpa_t)0) |
104 | ||
ec04b260 | 105 | /* KVM Hugepage definitions for x86 */ |
4fef0f49 WY |
106 | enum { |
107 | PT_PAGE_TABLE_LEVEL = 1, | |
108 | PT_DIRECTORY_LEVEL = 2, | |
109 | PT_PDPE_LEVEL = 3, | |
110 | /* set max level to the biggest one */ | |
111 | PT_MAX_HUGEPAGE_LEVEL = PT_PDPE_LEVEL, | |
112 | }; | |
113 | #define KVM_NR_PAGE_SIZES (PT_MAX_HUGEPAGE_LEVEL - \ | |
114 | PT_PAGE_TABLE_LEVEL + 1) | |
82855413 JR |
115 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
116 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
117 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
118 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
119 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 120 | |
6d9d41e5 CD |
121 | static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level) |
122 | { | |
123 | /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */ | |
124 | return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) - | |
125 | (base_gfn >> KVM_HPAGE_GFN_SHIFT(level)); | |
126 | } | |
127 | ||
d657a98e | 128 | #define KVM_PERMILLE_MMU_PAGES 20 |
bc8a3d89 | 129 | #define KVM_MIN_ALLOC_MMU_PAGES 64UL |
114df303 | 130 | #define KVM_MMU_HASH_SHIFT 12 |
1ae0a13d | 131 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) |
d657a98e ZX |
132 | #define KVM_MIN_FREE_MMU_PAGES 5 |
133 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 134 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 135 | #define KVM_NR_FIXED_MTRR_REGION 88 |
0d234daf | 136 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 137 | |
af585b92 GN |
138 | #define ASYNC_PF_PER_VCPU 64 |
139 | ||
5fdbf976 | 140 | enum kvm_reg { |
95c7b77d SC |
141 | VCPU_REGS_RAX = __VCPU_REGS_RAX, |
142 | VCPU_REGS_RCX = __VCPU_REGS_RCX, | |
143 | VCPU_REGS_RDX = __VCPU_REGS_RDX, | |
144 | VCPU_REGS_RBX = __VCPU_REGS_RBX, | |
145 | VCPU_REGS_RSP = __VCPU_REGS_RSP, | |
146 | VCPU_REGS_RBP = __VCPU_REGS_RBP, | |
147 | VCPU_REGS_RSI = __VCPU_REGS_RSI, | |
148 | VCPU_REGS_RDI = __VCPU_REGS_RDI, | |
2b3ccfa0 | 149 | #ifdef CONFIG_X86_64 |
95c7b77d SC |
150 | VCPU_REGS_R8 = __VCPU_REGS_R8, |
151 | VCPU_REGS_R9 = __VCPU_REGS_R9, | |
152 | VCPU_REGS_R10 = __VCPU_REGS_R10, | |
153 | VCPU_REGS_R11 = __VCPU_REGS_R11, | |
154 | VCPU_REGS_R12 = __VCPU_REGS_R12, | |
155 | VCPU_REGS_R13 = __VCPU_REGS_R13, | |
156 | VCPU_REGS_R14 = __VCPU_REGS_R14, | |
157 | VCPU_REGS_R15 = __VCPU_REGS_R15, | |
2b3ccfa0 | 158 | #endif |
5fdbf976 | 159 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
160 | NR_VCPU_REGS |
161 | }; | |
162 | ||
6de4f3ad AK |
163 | enum kvm_reg_ex { |
164 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 165 | VCPU_EXREG_CR3, |
6de12732 | 166 | VCPU_EXREG_RFLAGS, |
2fb92db1 | 167 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
168 | }; |
169 | ||
2b3ccfa0 | 170 | enum { |
81609e3e | 171 | VCPU_SREG_ES, |
2b3ccfa0 | 172 | VCPU_SREG_CS, |
81609e3e | 173 | VCPU_SREG_SS, |
2b3ccfa0 | 174 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
175 | VCPU_SREG_FS, |
176 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
177 | VCPU_SREG_TR, |
178 | VCPU_SREG_LDTR, | |
179 | }; | |
180 | ||
56e82318 | 181 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 182 | |
d657a98e ZX |
183 | #define KVM_NR_MEM_OBJS 40 |
184 | ||
42dbaa5a JK |
185 | #define KVM_NR_DB_REGS 4 |
186 | ||
187 | #define DR6_BD (1 << 13) | |
188 | #define DR6_BS (1 << 14) | |
cfb634fe | 189 | #define DR6_BT (1 << 15) |
6f43ed01 NA |
190 | #define DR6_RTM (1 << 16) |
191 | #define DR6_FIXED_1 0xfffe0ff0 | |
192 | #define DR6_INIT 0xffff0ff0 | |
193 | #define DR6_VOLATILE 0x0001e00f | |
42dbaa5a JK |
194 | |
195 | #define DR7_BP_EN_MASK 0x000000ff | |
196 | #define DR7_GE (1 << 9) | |
197 | #define DR7_GD (1 << 13) | |
198 | #define DR7_FIXED_1 0x00000400 | |
6f43ed01 | 199 | #define DR7_VOLATILE 0xffff2bff |
42dbaa5a | 200 | |
c205fb7d NA |
201 | #define PFERR_PRESENT_BIT 0 |
202 | #define PFERR_WRITE_BIT 1 | |
203 | #define PFERR_USER_BIT 2 | |
204 | #define PFERR_RSVD_BIT 3 | |
205 | #define PFERR_FETCH_BIT 4 | |
be94f6b7 | 206 | #define PFERR_PK_BIT 5 |
14727754 TL |
207 | #define PFERR_GUEST_FINAL_BIT 32 |
208 | #define PFERR_GUEST_PAGE_BIT 33 | |
c205fb7d NA |
209 | |
210 | #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) | |
211 | #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) | |
212 | #define PFERR_USER_MASK (1U << PFERR_USER_BIT) | |
213 | #define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT) | |
214 | #define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT) | |
be94f6b7 | 215 | #define PFERR_PK_MASK (1U << PFERR_PK_BIT) |
14727754 TL |
216 | #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) |
217 | #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) | |
218 | ||
219 | #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ | |
14727754 TL |
220 | PFERR_WRITE_MASK | \ |
221 | PFERR_PRESENT_MASK) | |
c205fb7d | 222 | |
37f0e8fe JS |
223 | /* |
224 | * The mask used to denote special SPTEs, which can be either MMIO SPTEs or | |
225 | * Access Tracking SPTEs. We use bit 62 instead of bit 63 to avoid conflicting | |
226 | * with the SVE bit in EPT PTEs. | |
227 | */ | |
228 | #define SPTE_SPECIAL_MASK (1ULL << 62) | |
229 | ||
41383771 GN |
230 | /* apic attention bits */ |
231 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
232 | /* |
233 | * The following bit is set with PV-EOI, unset on EOI. | |
234 | * We detect PV-EOI changes by guest by comparing | |
235 | * this bit with PV-EOI in guest memory. | |
236 | * See the implementation in apic_update_pv_eoi. | |
237 | */ | |
238 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 239 | |
d84f1e07 FW |
240 | struct kvm_kernel_irq_routing_entry; |
241 | ||
d657a98e ZX |
242 | /* |
243 | * We don't want allocation failures within the mmu code, so we preallocate | |
244 | * enough memory for a single page fault in a cache. | |
245 | */ | |
246 | struct kvm_mmu_memory_cache { | |
247 | int nobjs; | |
248 | void *objects[KVM_NR_MEM_OBJS]; | |
249 | }; | |
250 | ||
21ebbeda XG |
251 | /* |
252 | * the pages used as guest page table on soft mmu are tracked by | |
253 | * kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used | |
254 | * by indirect shadow page can not be more than 15 bits. | |
255 | * | |
47c42e6b | 256 | * Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access, |
21ebbeda XG |
257 | * @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp. |
258 | */ | |
d657a98e | 259 | union kvm_mmu_page_role { |
36d9594d | 260 | u32 word; |
d657a98e | 261 | struct { |
7d76b4d3 | 262 | unsigned level:4; |
47c42e6b | 263 | unsigned gpte_is_8_bytes:1; |
7d76b4d3 | 264 | unsigned quadrant:2; |
f6e2c02b | 265 | unsigned direct:1; |
7d76b4d3 | 266 | unsigned access:3; |
2e53d63a | 267 | unsigned invalid:1; |
9645bb56 | 268 | unsigned nxe:1; |
3dbe1415 | 269 | unsigned cr0_wp:1; |
411c588d | 270 | unsigned smep_andnot_wp:1; |
0be0226f | 271 | unsigned smap_andnot_wp:1; |
ac8d57e5 | 272 | unsigned ad_disabled:1; |
1313cc2b JM |
273 | unsigned guest_mode:1; |
274 | unsigned :6; | |
699023e2 PB |
275 | |
276 | /* | |
277 | * This is left at the top of the word so that | |
278 | * kvm_memslots_for_spte_role can extract it with a | |
279 | * simple shift. While there is room, give it a whole | |
280 | * byte so it is also faster to load it from memory. | |
281 | */ | |
282 | unsigned smm:8; | |
d657a98e ZX |
283 | }; |
284 | }; | |
285 | ||
36d9594d | 286 | union kvm_mmu_extended_role { |
a336282d VK |
287 | /* |
288 | * This structure complements kvm_mmu_page_role caching everything needed for | |
289 | * MMU configuration. If nothing in both these structures changed, MMU | |
290 | * re-configuration can be skipped. @valid bit is set on first usage so we don't | |
291 | * treat all-zero structure as valid data. | |
292 | */ | |
36d9594d | 293 | u32 word; |
a336282d VK |
294 | struct { |
295 | unsigned int valid:1; | |
296 | unsigned int execonly:1; | |
7dcd5755 | 297 | unsigned int cr0_pg:1; |
a336282d VK |
298 | unsigned int cr4_pse:1; |
299 | unsigned int cr4_pke:1; | |
300 | unsigned int cr4_smap:1; | |
301 | unsigned int cr4_smep:1; | |
7dcd5755 | 302 | unsigned int cr4_la57:1; |
de3ccd26 | 303 | unsigned int maxphyaddr:6; |
a336282d | 304 | }; |
36d9594d VK |
305 | }; |
306 | ||
307 | union kvm_mmu_role { | |
308 | u64 as_u64; | |
309 | struct { | |
310 | union kvm_mmu_page_role base; | |
311 | union kvm_mmu_extended_role ext; | |
312 | }; | |
313 | }; | |
314 | ||
018aabb5 TY |
315 | struct kvm_rmap_head { |
316 | unsigned long val; | |
317 | }; | |
318 | ||
d657a98e ZX |
319 | struct kvm_mmu_page { |
320 | struct list_head link; | |
321 | struct hlist_node hash_link; | |
3ff519f2 | 322 | bool unsync; |
4771450c | 323 | bool mmio_cached; |
d657a98e ZX |
324 | |
325 | /* | |
326 | * The following two entries are used to key the shadow page in the | |
327 | * hash table. | |
328 | */ | |
d657a98e | 329 | union kvm_mmu_page_role role; |
3ff519f2 | 330 | gfn_t gfn; |
d657a98e ZX |
331 | |
332 | u64 *spt; | |
333 | /* hold the gfn of each spte inside spt */ | |
334 | gfn_t *gfns; | |
0571d366 | 335 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 336 | unsigned int unsync_children; |
018aabb5 | 337 | struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */ |
0074ff63 | 338 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
339 | |
340 | #ifdef CONFIG_X86_32 | |
accaefe0 XG |
341 | /* |
342 | * Used out of the mmu-lock to avoid reading spte values while an | |
343 | * update is in progress; see the comments in __get_spte_lockless(). | |
344 | */ | |
c2a2ac2b XG |
345 | int clear_spte_count; |
346 | #endif | |
347 | ||
0cbf8e43 | 348 | /* Number of writes since the last time traversal visited this page. */ |
e5691a81 | 349 | atomic_t write_flooding_count; |
d657a98e ZX |
350 | }; |
351 | ||
1c08364c | 352 | struct kvm_pio_request { |
45def77e | 353 | unsigned long linear_rip; |
1c08364c | 354 | unsigned long count; |
1c08364c AK |
355 | int in; |
356 | int port; | |
357 | int size; | |
1c08364c AK |
358 | }; |
359 | ||
855feb67 | 360 | #define PT64_ROOT_MAX_LEVEL 5 |
2a7266a8 | 361 | |
a0a64f50 | 362 | struct rsvd_bits_validate { |
2a7266a8 | 363 | u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL]; |
a0a64f50 XG |
364 | u64 bad_mt_xwr; |
365 | }; | |
366 | ||
7c390d35 JS |
367 | struct kvm_mmu_root_info { |
368 | gpa_t cr3; | |
369 | hpa_t hpa; | |
370 | }; | |
371 | ||
372 | #define KVM_MMU_ROOT_INFO_INVALID \ | |
373 | ((struct kvm_mmu_root_info) { .cr3 = INVALID_PAGE, .hpa = INVALID_PAGE }) | |
374 | ||
b94742c9 JS |
375 | #define KVM_MMU_NUM_PREV_ROOTS 3 |
376 | ||
d657a98e | 377 | /* |
855feb67 YZ |
378 | * x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit, |
379 | * and 2-level 32-bit). The kvm_mmu structure abstracts the details of the | |
380 | * current mmu mode. | |
d657a98e ZX |
381 | */ |
382 | struct kvm_mmu { | |
f43addd4 | 383 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 384 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 385 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
386 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
387 | bool prefault); | |
6389ee94 AK |
388 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
389 | struct x86_exception *fault); | |
1871c602 | 390 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 391 | struct x86_exception *exception); |
54987b7a PB |
392 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
393 | struct x86_exception *exception); | |
e8bc217a | 394 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 395 | struct kvm_mmu_page *sp); |
7eb77e9f | 396 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa); |
0f53b5b1 | 397 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 398 | u64 *spte, const void *pte); |
d657a98e | 399 | hpa_t root_hpa; |
ad7dc69a | 400 | gpa_t root_cr3; |
36d9594d | 401 | union kvm_mmu_role mmu_role; |
ae1e2d10 PB |
402 | u8 root_level; |
403 | u8 shadow_root_level; | |
404 | u8 ept_ad; | |
c5a78f2b | 405 | bool direct_map; |
b94742c9 | 406 | struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS]; |
d657a98e | 407 | |
97d64b78 AK |
408 | /* |
409 | * Bitmap; bit set = permission fault | |
410 | * Byte index: page fault error code [4:1] | |
411 | * Bit index: pte permissions in ACC_* format | |
412 | */ | |
413 | u8 permissions[16]; | |
414 | ||
2d344105 HH |
415 | /* |
416 | * The pkru_mask indicates if protection key checks are needed. It | |
417 | * consists of 16 domains indexed by page fault error code bits [4:1], | |
418 | * with PFEC.RSVD replaced by ACC_USER_MASK from the page tables. | |
419 | * Each domain has 2 bits which are ANDed with AD and WD from PKRU. | |
420 | */ | |
421 | u32 pkru_mask; | |
422 | ||
d657a98e | 423 | u64 *pae_root; |
81407ca5 | 424 | u64 *lm_root; |
c258b62b XG |
425 | |
426 | /* | |
427 | * check zero bits on shadow page table entries, these | |
428 | * bits include not only hardware reserved bits but also | |
429 | * the bits spte never used. | |
430 | */ | |
431 | struct rsvd_bits_validate shadow_zero_check; | |
432 | ||
a0a64f50 | 433 | struct rsvd_bits_validate guest_rsvd_check; |
ff03a073 | 434 | |
6bb69c9b PB |
435 | /* Can have large pages at levels 2..last_nonleaf_level-1. */ |
436 | u8 last_nonleaf_level; | |
6fd01b71 | 437 | |
2d48a985 JR |
438 | bool nx; |
439 | ||
ff03a073 | 440 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
441 | }; |
442 | ||
a49b9635 LT |
443 | struct kvm_tlb_range { |
444 | u64 start_gfn; | |
445 | u64 pages; | |
446 | }; | |
447 | ||
f5132b01 GN |
448 | enum pmc_type { |
449 | KVM_PMC_GP = 0, | |
450 | KVM_PMC_FIXED, | |
451 | }; | |
452 | ||
453 | struct kvm_pmc { | |
454 | enum pmc_type type; | |
455 | u8 idx; | |
456 | u64 counter; | |
457 | u64 eventsel; | |
458 | struct perf_event *perf_event; | |
459 | struct kvm_vcpu *vcpu; | |
460 | }; | |
461 | ||
462 | struct kvm_pmu { | |
463 | unsigned nr_arch_gp_counters; | |
464 | unsigned nr_arch_fixed_counters; | |
465 | unsigned available_event_types; | |
466 | u64 fixed_ctr_ctrl; | |
467 | u64 global_ctrl; | |
468 | u64 global_status; | |
469 | u64 global_ovf_ctrl; | |
470 | u64 counter_bitmask[2]; | |
471 | u64 global_ctrl_mask; | |
c715eb9f | 472 | u64 global_ovf_ctrl_mask; |
103af0a9 | 473 | u64 reserved_bits; |
f5132b01 | 474 | u8 version; |
15c7ad51 RR |
475 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
476 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; | |
f5132b01 GN |
477 | struct irq_work irq_work; |
478 | u64 reprogram_pmi; | |
479 | }; | |
480 | ||
25462f7f WH |
481 | struct kvm_pmu_ops; |
482 | ||
360b948d PB |
483 | enum { |
484 | KVM_DEBUGREG_BP_ENABLED = 1, | |
c77fb5fe | 485 | KVM_DEBUGREG_WONT_EXIT = 2, |
ae561ede | 486 | KVM_DEBUGREG_RELOAD = 4, |
360b948d PB |
487 | }; |
488 | ||
86fd5270 XG |
489 | struct kvm_mtrr_range { |
490 | u64 base; | |
491 | u64 mask; | |
19efffa2 | 492 | struct list_head node; |
86fd5270 XG |
493 | }; |
494 | ||
70109e7d | 495 | struct kvm_mtrr { |
86fd5270 | 496 | struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR]; |
70109e7d | 497 | mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION]; |
10fac2dc | 498 | u64 deftype; |
19efffa2 XG |
499 | |
500 | struct list_head head; | |
70109e7d XG |
501 | }; |
502 | ||
1f4b34f8 AS |
503 | /* Hyper-V SynIC timer */ |
504 | struct kvm_vcpu_hv_stimer { | |
505 | struct hrtimer timer; | |
506 | int index; | |
6a058a1e | 507 | union hv_stimer_config config; |
1f4b34f8 AS |
508 | u64 count; |
509 | u64 exp_time; | |
510 | struct hv_message msg; | |
511 | bool msg_pending; | |
512 | }; | |
513 | ||
5c919412 AS |
514 | /* Hyper-V synthetic interrupt controller (SynIC)*/ |
515 | struct kvm_vcpu_hv_synic { | |
516 | u64 version; | |
517 | u64 control; | |
518 | u64 msg_page; | |
519 | u64 evt_page; | |
520 | atomic64_t sint[HV_SYNIC_SINT_COUNT]; | |
521 | atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT]; | |
522 | DECLARE_BITMAP(auto_eoi_bitmap, 256); | |
523 | DECLARE_BITMAP(vec_bitmap, 256); | |
524 | bool active; | |
efc479e6 | 525 | bool dont_zero_synic_pages; |
5c919412 AS |
526 | }; |
527 | ||
e83d5887 AS |
528 | /* Hyper-V per vcpu emulation context */ |
529 | struct kvm_vcpu_hv { | |
d3457c87 | 530 | u32 vp_index; |
e83d5887 | 531 | u64 hv_vapic; |
9eec50b8 | 532 | s64 runtime_offset; |
5c919412 | 533 | struct kvm_vcpu_hv_synic synic; |
db397571 | 534 | struct kvm_hyperv_exit exit; |
1f4b34f8 AS |
535 | struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT]; |
536 | DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT); | |
e6b6c483 | 537 | cpumask_t tlb_flush; |
e83d5887 AS |
538 | }; |
539 | ||
ad312c7c | 540 | struct kvm_vcpu_arch { |
5fdbf976 MT |
541 | /* |
542 | * rip and regs accesses must go through | |
543 | * kvm_{register,rip}_{read,write} functions. | |
544 | */ | |
545 | unsigned long regs[NR_VCPU_REGS]; | |
546 | u32 regs_avail; | |
547 | u32 regs_dirty; | |
34c16eec ZX |
548 | |
549 | unsigned long cr0; | |
e8467fda | 550 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
551 | unsigned long cr2; |
552 | unsigned long cr3; | |
553 | unsigned long cr4; | |
fc78f519 | 554 | unsigned long cr4_guest_owned_bits; |
34c16eec | 555 | unsigned long cr8; |
b9dd21e1 | 556 | u32 pkru; |
1371d904 | 557 | u32 hflags; |
f6801dff | 558 | u64 efer; |
34c16eec ZX |
559 | u64 apic_base; |
560 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
d62caabb | 561 | bool apicv_active; |
e40ff1d6 | 562 | bool load_eoi_exitmap_pending; |
6308630b | 563 | DECLARE_BITMAP(ioapic_handled_vectors, 256); |
41383771 | 564 | unsigned long apic_attention; |
e1035715 | 565 | int32_t apic_arb_prio; |
34c16eec | 566 | int mp_state; |
34c16eec | 567 | u64 ia32_misc_enable_msr; |
64d60670 | 568 | u64 smbase; |
52797bf9 | 569 | u64 smi_count; |
b209749f | 570 | bool tpr_access_reporting; |
20300099 | 571 | u64 ia32_xss; |
518e7b94 | 572 | u64 microcode_version; |
0cf9135b | 573 | u64 arch_capabilities; |
34c16eec | 574 | |
14dfe855 JR |
575 | /* |
576 | * Paging state of the vcpu | |
577 | * | |
578 | * If the vcpu runs in guest mode with two level paging this still saves | |
579 | * the paging mode of the l1 guest. This context is always used to | |
580 | * handle faults. | |
581 | */ | |
44dd3ffa VK |
582 | struct kvm_mmu *mmu; |
583 | ||
584 | /* Non-nested MMU for L1 */ | |
585 | struct kvm_mmu root_mmu; | |
8df25a32 | 586 | |
14c07ad8 VK |
587 | /* L1 MMU when running nested */ |
588 | struct kvm_mmu guest_mmu; | |
589 | ||
6539e738 JR |
590 | /* |
591 | * Paging state of an L2 guest (used for nested npt) | |
592 | * | |
593 | * This context will save all necessary information to walk page tables | |
594 | * of the an L2 guest. This context is only initialized for page table | |
595 | * walking and not for faulting since we never handle l2 page faults on | |
596 | * the host. | |
597 | */ | |
598 | struct kvm_mmu nested_mmu; | |
599 | ||
14dfe855 JR |
600 | /* |
601 | * Pointer to the mmu context currently used for | |
602 | * gva_to_gpa translations. | |
603 | */ | |
604 | struct kvm_mmu *walk_mmu; | |
605 | ||
53c07b18 | 606 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
607 | struct kvm_mmu_memory_cache mmu_page_cache; |
608 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
609 | ||
f775b13e RR |
610 | /* |
611 | * QEMU userspace and the guest each have their own FPU state. | |
240c35a3 MO |
612 | * In vcpu_run, we switch between the user, maintained in the |
613 | * task_struct struct, and guest FPU contexts. While running a VCPU, | |
614 | * the VCPU thread will have the guest FPU context. | |
f775b13e RR |
615 | * |
616 | * Note that while the PKRU state lives inside the fpu registers, | |
617 | * it is switched out separately at VMENTER and VMEXIT time. The | |
618 | * "guest_fpu" state here contains the guest FPU context, with the | |
619 | * host PRKU bits. | |
620 | */ | |
b666a4b6 | 621 | struct fpu *guest_fpu; |
f775b13e | 622 | |
2acf923e | 623 | u64 xcr0; |
d7876f1b | 624 | u64 guest_supported_xcr0; |
4344ee98 | 625 | u32 guest_xstate_size; |
34c16eec | 626 | |
34c16eec ZX |
627 | struct kvm_pio_request pio; |
628 | void *pio_data; | |
629 | ||
66fd3f7f GN |
630 | u8 event_exit_inst_len; |
631 | ||
298101da AK |
632 | struct kvm_queued_exception { |
633 | bool pending; | |
664f8e26 | 634 | bool injected; |
298101da AK |
635 | bool has_error_code; |
636 | u8 nr; | |
637 | u32 error_code; | |
c851436a JM |
638 | unsigned long payload; |
639 | bool has_payload; | |
adfe20fb | 640 | u8 nested_apf; |
298101da AK |
641 | } exception; |
642 | ||
937a7eae | 643 | struct kvm_queued_interrupt { |
04140b41 | 644 | bool injected; |
66fd3f7f | 645 | bool soft; |
937a7eae AK |
646 | u8 nr; |
647 | } interrupt; | |
648 | ||
34c16eec ZX |
649 | int halt_request; /* real mode on Intel only */ |
650 | ||
651 | int cpuid_nent; | |
07716717 | 652 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
5a4f55cd EK |
653 | |
654 | int maxphyaddr; | |
655 | ||
34c16eec ZX |
656 | /* emulate context */ |
657 | ||
658 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
659 | bool emulate_regs_need_sync_to_vcpu; |
660 | bool emulate_regs_need_sync_from_vcpu; | |
716d51ab | 661 | int (*complete_userspace_io)(struct kvm_vcpu *vcpu); |
18068523 GOC |
662 | |
663 | gpa_t time; | |
50d0a0f9 | 664 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 665 | unsigned int hw_tsc_khz; |
0b79459b AH |
666 | struct gfn_to_hva_cache pv_time; |
667 | bool pv_time_enabled; | |
51d59c6b MT |
668 | /* set guest stopped flag in pvclock flags field */ |
669 | bool pvclock_set_guest_stopped_request; | |
c9aaa895 GC |
670 | |
671 | struct { | |
672 | u64 msr_val; | |
673 | u64 last_steal; | |
c9aaa895 GC |
674 | struct gfn_to_hva_cache stime; |
675 | struct kvm_steal_time steal; | |
676 | } st; | |
677 | ||
a545ab6a | 678 | u64 tsc_offset; |
1d5f066e | 679 | u64 last_guest_tsc; |
6f526ec5 | 680 | u64 last_host_tsc; |
0dd6a6ed | 681 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
682 | u64 this_tsc_nsec; |
683 | u64 this_tsc_write; | |
0d3da0d2 | 684 | u64 this_tsc_generation; |
c285545f | 685 | bool tsc_catchup; |
cc578287 ZA |
686 | bool tsc_always_catchup; |
687 | s8 virtual_tsc_shift; | |
688 | u32 virtual_tsc_mult; | |
689 | u32 virtual_tsc_khz; | |
ba904635 | 690 | s64 ia32_tsc_adjust_msr; |
ad721883 | 691 | u64 tsc_scaling_ratio; |
3419ffc8 | 692 | |
7460fb4a AK |
693 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
694 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
695 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
f077825a | 696 | bool smi_pending; /* SMI queued after currently running handler */ |
9ba075a6 | 697 | |
70109e7d | 698 | struct kvm_mtrr mtrr_state; |
7cb060a9 | 699 | u64 pat; |
42dbaa5a | 700 | |
360b948d | 701 | unsigned switch_db_regs; |
42dbaa5a JK |
702 | unsigned long db[KVM_NR_DB_REGS]; |
703 | unsigned long dr6; | |
704 | unsigned long dr7; | |
705 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
c8639010 | 706 | unsigned long guest_debug_dr7; |
db2336a8 KH |
707 | u64 msr_platform_info; |
708 | u64 msr_misc_features_enables; | |
890ca9ae HY |
709 | |
710 | u64 mcg_cap; | |
711 | u64 mcg_status; | |
712 | u64 mcg_ctl; | |
c45dcc71 | 713 | u64 mcg_ext_ctl; |
890ca9ae | 714 | u64 *mce_banks; |
94fe45da | 715 | |
bebb106a XG |
716 | /* Cache MMIO info */ |
717 | u64 mmio_gva; | |
718 | unsigned access; | |
719 | gfn_t mmio_gfn; | |
56f17dd3 | 720 | u64 mmio_gen; |
bebb106a | 721 | |
f5132b01 GN |
722 | struct kvm_pmu pmu; |
723 | ||
94fe45da | 724 | /* used for guest single stepping over the given code position */ |
94fe45da | 725 | unsigned long singlestep_rip; |
f92653ee | 726 | |
e83d5887 | 727 | struct kvm_vcpu_hv hyperv; |
f5f48ee1 SY |
728 | |
729 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 730 | |
1cb3f3ae XG |
731 | unsigned long last_retry_eip; |
732 | unsigned long last_retry_addr; | |
733 | ||
af585b92 GN |
734 | struct { |
735 | bool halted; | |
736 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
737 | struct gfn_to_hva_cache data; |
738 | u64 msr_val; | |
7c90705b | 739 | u32 id; |
6adba527 | 740 | bool send_user_only; |
1261bfa3 | 741 | u32 host_apf_reason; |
adfe20fb | 742 | unsigned long nested_apf_token; |
52a5c155 | 743 | bool delivery_as_pf_vmexit; |
af585b92 | 744 | } apf; |
2b036c6b BO |
745 | |
746 | /* OSVW MSRs (AMD only) */ | |
747 | struct { | |
748 | u64 length; | |
749 | u64 status; | |
750 | } osvw; | |
ae7a2a3f MT |
751 | |
752 | struct { | |
753 | u64 msr_val; | |
754 | struct gfn_to_hva_cache data; | |
755 | } pv_eoi; | |
93c05d3e XG |
756 | |
757 | /* | |
758 | * Indicate whether the access faults on its page table in guest | |
759 | * which is set when fix page fault and used to detect unhandeable | |
760 | * instruction. | |
761 | */ | |
762 | bool write_fault_to_shadow_pgtable; | |
25d92081 YZ |
763 | |
764 | /* set at EPT violation at this point */ | |
765 | unsigned long exit_qualification; | |
6aef266c SV |
766 | |
767 | /* pv related host specific info */ | |
768 | struct { | |
769 | bool pv_unhalted; | |
770 | } pv; | |
7543a635 SR |
771 | |
772 | int pending_ioapic_eoi; | |
1c1a9ce9 | 773 | int pending_external_vector; |
0f89b207 | 774 | |
618232e2 | 775 | /* GPA available */ |
0f89b207 | 776 | bool gpa_available; |
618232e2 | 777 | gpa_t gpa_val; |
de63ad4c LM |
778 | |
779 | /* be preempted when it's in kernel-mode(cpl=0) */ | |
780 | bool preempted_in_kernel; | |
c595ceee PB |
781 | |
782 | /* Flush the L1 Data cache for L1TF mitigation on VMENTER */ | |
783 | bool l1tf_flush_l1d; | |
34c16eec ZX |
784 | }; |
785 | ||
db3fe4eb | 786 | struct kvm_lpage_info { |
92f94f1e | 787 | int disallow_lpage; |
db3fe4eb TY |
788 | }; |
789 | ||
790 | struct kvm_arch_memory_slot { | |
018aabb5 | 791 | struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES]; |
db3fe4eb | 792 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; |
21ebbeda | 793 | unsigned short *gfn_track[KVM_PAGE_TRACK_MAX]; |
db3fe4eb TY |
794 | }; |
795 | ||
3548a259 RK |
796 | /* |
797 | * We use as the mode the number of bits allocated in the LDR for the | |
798 | * logical processor ID. It happens that these are all powers of two. | |
799 | * This makes it is very easy to detect cases where the APICs are | |
800 | * configured for multiple modes; in that case, we cannot use the map and | |
801 | * hence cannot use kvm_irq_delivery_to_apic_fast either. | |
802 | */ | |
803 | #define KVM_APIC_MODE_XAPIC_CLUSTER 4 | |
804 | #define KVM_APIC_MODE_XAPIC_FLAT 8 | |
805 | #define KVM_APIC_MODE_X2APIC 16 | |
806 | ||
1e08ec4a GN |
807 | struct kvm_apic_map { |
808 | struct rcu_head rcu; | |
3548a259 | 809 | u8 mode; |
0ca52e7b | 810 | u32 max_apic_id; |
e45115b6 RK |
811 | union { |
812 | struct kvm_lapic *xapic_flat_map[8]; | |
813 | struct kvm_lapic *xapic_cluster_map[16][4]; | |
814 | }; | |
0ca52e7b | 815 | struct kvm_lapic *phys_map[]; |
1e08ec4a GN |
816 | }; |
817 | ||
e83d5887 AS |
818 | /* Hyper-V emulation context */ |
819 | struct kvm_hv { | |
3f5ad8be | 820 | struct mutex hv_lock; |
e83d5887 AS |
821 | u64 hv_guest_os_id; |
822 | u64 hv_hypercall; | |
823 | u64 hv_tsc_page; | |
e7d9513b AS |
824 | |
825 | /* Hyper-v based guest crash (NT kernel bugcheck) parameters */ | |
826 | u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS]; | |
827 | u64 hv_crash_ctl; | |
095cf55d PB |
828 | |
829 | HV_REFERENCE_TSC_PAGE tsc_ref; | |
faeb7833 RK |
830 | |
831 | struct idr conn_to_evt; | |
a2e164e7 VK |
832 | |
833 | u64 hv_reenlightenment_control; | |
834 | u64 hv_tsc_emulation_control; | |
835 | u64 hv_tsc_emulation_status; | |
87ee613d VK |
836 | |
837 | /* How many vCPUs have VP index != vCPU index */ | |
838 | atomic_t num_mismatched_vp_indexes; | |
e83d5887 AS |
839 | }; |
840 | ||
49776faf RK |
841 | enum kvm_irqchip_mode { |
842 | KVM_IRQCHIP_NONE, | |
843 | KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */ | |
844 | KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */ | |
845 | }; | |
846 | ||
fef9cce0 | 847 | struct kvm_arch { |
bc8a3d89 BG |
848 | unsigned long n_used_mmu_pages; |
849 | unsigned long n_requested_mmu_pages; | |
850 | unsigned long n_max_mmu_pages; | |
332b207d | 851 | unsigned int indirect_shadow_pages; |
f05e70ac ZX |
852 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
853 | /* | |
854 | * Hash table of struct kvm_mmu_page. | |
855 | */ | |
856 | struct list_head active_mmu_pages; | |
13d268ca | 857 | struct kvm_page_track_notifier_node mmu_sp_tracker; |
0eb05bf2 | 858 | struct kvm_page_track_notifier_head track_notifier_head; |
365c8868 | 859 | |
4d5c5d0f | 860 | struct list_head assigned_dev_head; |
19de40a8 | 861 | struct iommu_domain *iommu_domain; |
d96eb2c6 | 862 | bool iommu_noncoherent; |
e0f0bbc5 AW |
863 | #define __KVM_HAVE_ARCH_NONCOHERENT_DMA |
864 | atomic_t noncoherent_dma_count; | |
5544eb9b PB |
865 | #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE |
866 | atomic_t assigned_device_count; | |
d7deeeb0 ZX |
867 | struct kvm_pic *vpic; |
868 | struct kvm_ioapic *vioapic; | |
7837699f | 869 | struct kvm_pit *vpit; |
42720138 | 870 | atomic_t vapics_in_nmi_mode; |
1e08ec4a GN |
871 | struct mutex apic_map_lock; |
872 | struct kvm_apic_map *apic_map; | |
bfc6d222 | 873 | |
c24ae0dc | 874 | bool apic_access_page_done; |
18068523 GOC |
875 | |
876 | gpa_t wall_clock; | |
b7ebfb05 | 877 | |
4d5422ce | 878 | bool mwait_in_guest; |
caa057a2 | 879 | bool hlt_in_guest; |
b31c114b | 880 | bool pause_in_guest; |
4d5422ce | 881 | |
5550af4d | 882 | unsigned long irq_sources_bitmap; |
afbcf7ab | 883 | s64 kvmclock_offset; |
038f8c11 | 884 | raw_spinlock_t tsc_write_lock; |
f38e098f | 885 | u64 last_tsc_nsec; |
f38e098f | 886 | u64 last_tsc_write; |
5d3cb0f6 | 887 | u32 last_tsc_khz; |
e26101b1 ZA |
888 | u64 cur_tsc_nsec; |
889 | u64 cur_tsc_write; | |
890 | u64 cur_tsc_offset; | |
0d3da0d2 | 891 | u64 cur_tsc_generation; |
b48aa97e | 892 | int nr_vcpus_matched_tsc; |
ffde22ac | 893 | |
d828199e MT |
894 | spinlock_t pvclock_gtod_sync_lock; |
895 | bool use_master_clock; | |
896 | u64 master_kernel_ns; | |
a5a1d1c2 | 897 | u64 master_cycle_now; |
7e44e449 | 898 | struct delayed_work kvmclock_update_work; |
332967a3 | 899 | struct delayed_work kvmclock_sync_work; |
d828199e | 900 | |
ffde22ac | 901 | struct kvm_xen_hvm_config xen_hvm_config; |
55cd8e5a | 902 | |
6ef768fa PB |
903 | /* reads protected by irq_srcu, writes by irq_lock */ |
904 | struct hlist_head mask_notifier_list; | |
905 | ||
e83d5887 | 906 | struct kvm_hv hyperv; |
b034cf01 XG |
907 | |
908 | #ifdef CONFIG_KVM_MMU_AUDIT | |
909 | int audit_point; | |
910 | #endif | |
54750f2c | 911 | |
a826faf1 | 912 | bool backwards_tsc_observed; |
54750f2c | 913 | bool boot_vcpu_runs_old_kvmclock; |
d71ba788 | 914 | u32 bsp_vcpu_id; |
90de4a18 NA |
915 | |
916 | u64 disabled_quirks; | |
49df6397 | 917 | |
49776faf | 918 | enum kvm_irqchip_mode irqchip_mode; |
b053b2ae | 919 | u8 nr_reserved_ioapic_pins; |
52004014 FW |
920 | |
921 | bool disabled_lapic_found; | |
44a95dae | 922 | |
37131313 | 923 | bool x2apic_format; |
c519265f | 924 | bool x2apic_broadcast_quirk_disabled; |
6fbbde9a DS |
925 | |
926 | bool guest_can_read_msr_platform_info; | |
59073aaf | 927 | bool exception_payload_enabled; |
d69fb81f ZX |
928 | }; |
929 | ||
0711456c | 930 | struct kvm_vm_stat { |
8a7e75d4 SJS |
931 | ulong mmu_shadow_zapped; |
932 | ulong mmu_pte_write; | |
933 | ulong mmu_pte_updated; | |
934 | ulong mmu_pde_zapped; | |
935 | ulong mmu_flooded; | |
936 | ulong mmu_recycled; | |
937 | ulong mmu_cache_miss; | |
938 | ulong mmu_unsync; | |
939 | ulong remote_tlb_flush; | |
940 | ulong lpages; | |
f3414bc7 | 941 | ulong max_mmu_page_hash_collisions; |
0711456c ZX |
942 | }; |
943 | ||
77b4c255 | 944 | struct kvm_vcpu_stat { |
8a7e75d4 SJS |
945 | u64 pf_fixed; |
946 | u64 pf_guest; | |
947 | u64 tlb_flush; | |
948 | u64 invlpg; | |
949 | ||
950 | u64 exits; | |
951 | u64 io_exits; | |
952 | u64 mmio_exits; | |
953 | u64 signal_exits; | |
954 | u64 irq_window_exits; | |
955 | u64 nmi_window_exits; | |
c595ceee | 956 | u64 l1d_flush; |
8a7e75d4 SJS |
957 | u64 halt_exits; |
958 | u64 halt_successful_poll; | |
959 | u64 halt_attempted_poll; | |
960 | u64 halt_poll_invalid; | |
961 | u64 halt_wakeup; | |
962 | u64 request_irq_exits; | |
963 | u64 irq_exits; | |
964 | u64 host_state_reload; | |
8a7e75d4 SJS |
965 | u64 fpu_reload; |
966 | u64 insn_emulation; | |
967 | u64 insn_emulation_fail; | |
968 | u64 hypercalls; | |
969 | u64 irq_injections; | |
970 | u64 nmi_injections; | |
0f1e261e | 971 | u64 req_event; |
77b4c255 | 972 | }; |
ad312c7c | 973 | |
8a76d7f2 JR |
974 | struct x86_instruction_info; |
975 | ||
8fe8ab46 WA |
976 | struct msr_data { |
977 | bool host_initiated; | |
978 | u32 index; | |
979 | u64 data; | |
980 | }; | |
981 | ||
cb5281a5 PB |
982 | struct kvm_lapic_irq { |
983 | u32 vector; | |
b7cb2231 PB |
984 | u16 delivery_mode; |
985 | u16 dest_mode; | |
986 | bool level; | |
987 | u16 trig_mode; | |
cb5281a5 PB |
988 | u32 shorthand; |
989 | u32 dest_id; | |
93bbf0b8 | 990 | bool msi_redir_hint; |
cb5281a5 PB |
991 | }; |
992 | ||
ea4a5ff8 ZX |
993 | struct kvm_x86_ops { |
994 | int (*cpu_has_kvm_support)(void); /* __init */ | |
995 | int (*disabled_by_bios)(void); /* __init */ | |
13a34e06 RK |
996 | int (*hardware_enable)(void); |
997 | void (*hardware_disable)(void); | |
ea4a5ff8 ZX |
998 | void (*check_processor_compatibility)(void *rtn); |
999 | int (*hardware_setup)(void); /* __init */ | |
1000 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 1001 | bool (*cpu_has_accelerated_tpr)(void); |
bc226f07 | 1002 | bool (*has_emulated_msr)(int index); |
0e851880 | 1003 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 1004 | |
434a1e94 SC |
1005 | struct kvm *(*vm_alloc)(void); |
1006 | void (*vm_free)(struct kvm *); | |
03543133 SS |
1007 | int (*vm_init)(struct kvm *kvm); |
1008 | void (*vm_destroy)(struct kvm *kvm); | |
1009 | ||
ea4a5ff8 ZX |
1010 | /* Create, but do not attach this VCPU */ |
1011 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
1012 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
d28bc9dd | 1013 | void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event); |
ea4a5ff8 ZX |
1014 | |
1015 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
1016 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
1017 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 1018 | |
a96036b8 | 1019 | void (*update_bp_intercept)(struct kvm_vcpu *vcpu); |
609e36d3 | 1020 | int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1021 | int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr); |
ea4a5ff8 ZX |
1022 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); |
1023 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
1024 | struct kvm_segment *var, int seg); | |
2e4d2653 | 1025 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
1026 | void (*set_segment)(struct kvm_vcpu *vcpu, |
1027 | struct kvm_segment *var, int seg); | |
1028 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 1029 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 1030 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
1031 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
1032 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
1033 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 1034 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 1035 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
1036 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
1037 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
1038 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
1039 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
73aaf249 JK |
1040 | u64 (*get_dr6)(struct kvm_vcpu *vcpu); |
1041 | void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value); | |
c77fb5fe | 1042 | void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu); |
020df079 | 1043 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 1044 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
1045 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
1046 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
1047 | ||
c2ba05cc | 1048 | void (*tlb_flush)(struct kvm_vcpu *vcpu, bool invalidate_gpa); |
b08660e5 | 1049 | int (*tlb_remote_flush)(struct kvm *kvm); |
a49b9635 LT |
1050 | int (*tlb_remote_flush_with_range)(struct kvm *kvm, |
1051 | struct kvm_tlb_range *range); | |
ea4a5ff8 | 1052 | |
faff8758 JS |
1053 | /* |
1054 | * Flush any TLB entries associated with the given GVA. | |
1055 | * Does not need to flush GPA->HPA mappings. | |
1056 | * Can potentially get non-canonical addresses through INVLPGs, which | |
1057 | * the implementation may choose to ignore if appropriate. | |
1058 | */ | |
1059 | void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr); | |
ea4a5ff8 | 1060 | |
851ba692 AK |
1061 | void (*run)(struct kvm_vcpu *vcpu); |
1062 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 1063 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 | 1064 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
37ccdcbe | 1065 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
1066 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
1067 | unsigned char *hypercall_addr); | |
66fd3f7f | 1068 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 1069 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
cfcd20e5 | 1070 | void (*queue_exception)(struct kvm_vcpu *vcpu); |
b463a6f7 | 1071 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 1072 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 1073 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
1074 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
1075 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
c9a7953f JK |
1076 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
1077 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
95ba8273 | 1078 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); |
b2a05fef | 1079 | bool (*get_enable_apicv)(struct kvm_vcpu *vcpu); |
d62caabb | 1080 | void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu); |
c7c9c56c | 1081 | void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr); |
67c9dddc | 1082 | void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr); |
e6c67d8c | 1083 | bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu); |
6308630b | 1084 | void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); |
8d860bbe | 1085 | void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu); |
4256f43f | 1086 | void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa); |
a20ed54d | 1087 | void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector); |
76dfafd5 | 1088 | int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu); |
ea4a5ff8 | 1089 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
2ac52ab8 | 1090 | int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr); |
855feb67 | 1091 | int (*get_tdp_level)(struct kvm_vcpu *vcpu); |
4b12f0de | 1092 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 1093 | int (*get_lpage_level)(void); |
4e47c7a6 | 1094 | bool (*rdtscp_supported)(void); |
ad756a16 | 1095 | bool (*invpcid_supported)(void); |
344f414f | 1096 | |
1c97f0a0 JR |
1097 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
1098 | ||
d4330ef2 JR |
1099 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
1100 | ||
f5f48ee1 SY |
1101 | bool (*has_wbinvd_exit)(void); |
1102 | ||
e79f245d | 1103 | u64 (*read_l1_tsc_offset)(struct kvm_vcpu *vcpu); |
326e7425 LS |
1104 | /* Returns actual tsc_offset set in active VMCS */ |
1105 | u64 (*write_l1_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); | |
99e3e30a | 1106 | |
586f9607 | 1107 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
1108 | |
1109 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
1110 | struct x86_instruction_info *info, | |
1111 | enum x86_intercept_stage stage); | |
a547c6db | 1112 | void (*handle_external_intr)(struct kvm_vcpu *vcpu); |
da8999d3 | 1113 | bool (*mpx_supported)(void); |
55412b2e | 1114 | bool (*xsaves_supported)(void); |
66336cab | 1115 | bool (*umip_emulated)(void); |
86f5201d | 1116 | bool (*pt_supported)(void); |
b6b8a145 JK |
1117 | |
1118 | int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr); | |
d264ee0c | 1119 | void (*request_immediate_exit)(struct kvm_vcpu *vcpu); |
ae97a3b8 RK |
1120 | |
1121 | void (*sched_in)(struct kvm_vcpu *kvm, int cpu); | |
88178fd4 KH |
1122 | |
1123 | /* | |
1124 | * Arch-specific dirty logging hooks. These hooks are only supposed to | |
1125 | * be valid if the specific arch has hardware-accelerated dirty logging | |
1126 | * mechanism. Currently only for PML on VMX. | |
1127 | * | |
1128 | * - slot_enable_log_dirty: | |
1129 | * called when enabling log dirty mode for the slot. | |
1130 | * - slot_disable_log_dirty: | |
1131 | * called when disabling log dirty mode for the slot. | |
1132 | * also called when slot is created with log dirty disabled. | |
1133 | * - flush_log_dirty: | |
1134 | * called before reporting dirty_bitmap to userspace. | |
1135 | * - enable_log_dirty_pt_masked: | |
1136 | * called when reenabling log dirty for the GFNs in the mask after | |
1137 | * corresponding bits are cleared in slot->dirty_bitmap. | |
1138 | */ | |
1139 | void (*slot_enable_log_dirty)(struct kvm *kvm, | |
1140 | struct kvm_memory_slot *slot); | |
1141 | void (*slot_disable_log_dirty)(struct kvm *kvm, | |
1142 | struct kvm_memory_slot *slot); | |
1143 | void (*flush_log_dirty)(struct kvm *kvm); | |
1144 | void (*enable_log_dirty_pt_masked)(struct kvm *kvm, | |
1145 | struct kvm_memory_slot *slot, | |
1146 | gfn_t offset, unsigned long mask); | |
bab4165e BD |
1147 | int (*write_log_dirty)(struct kvm_vcpu *vcpu); |
1148 | ||
25462f7f WH |
1149 | /* pmu operations of sub-arch */ |
1150 | const struct kvm_pmu_ops *pmu_ops; | |
efc64404 | 1151 | |
bf9f6ac8 FW |
1152 | /* |
1153 | * Architecture specific hooks for vCPU blocking due to | |
1154 | * HLT instruction. | |
1155 | * Returns for .pre_block(): | |
1156 | * - 0 means continue to block the vCPU. | |
1157 | * - 1 means we cannot block the vCPU since some event | |
1158 | * happens during this period, such as, 'ON' bit in | |
1159 | * posted-interrupts descriptor is set. | |
1160 | */ | |
1161 | int (*pre_block)(struct kvm_vcpu *vcpu); | |
1162 | void (*post_block)(struct kvm_vcpu *vcpu); | |
d1ed092f SS |
1163 | |
1164 | void (*vcpu_blocking)(struct kvm_vcpu *vcpu); | |
1165 | void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); | |
1166 | ||
efc64404 FW |
1167 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, |
1168 | uint32_t guest_irq, bool set); | |
be8ca170 | 1169 | void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); |
ce7a058a | 1170 | |
f9927982 SC |
1171 | int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, |
1172 | bool *expired); | |
ce7a058a | 1173 | void (*cancel_hv_timer)(struct kvm_vcpu *vcpu); |
c45dcc71 AR |
1174 | |
1175 | void (*setup_mce)(struct kvm_vcpu *vcpu); | |
0234bf88 | 1176 | |
8fcc4b59 JM |
1177 | int (*get_nested_state)(struct kvm_vcpu *vcpu, |
1178 | struct kvm_nested_state __user *user_kvm_nested_state, | |
1179 | unsigned user_data_size); | |
1180 | int (*set_nested_state)(struct kvm_vcpu *vcpu, | |
1181 | struct kvm_nested_state __user *user_kvm_nested_state, | |
1182 | struct kvm_nested_state *kvm_state); | |
7f7f1ba3 PB |
1183 | void (*get_vmcs12_pages)(struct kvm_vcpu *vcpu); |
1184 | ||
72d7b374 | 1185 | int (*smi_allowed)(struct kvm_vcpu *vcpu); |
0234bf88 | 1186 | int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate); |
ed19321f | 1187 | int (*pre_leave_smm)(struct kvm_vcpu *vcpu, const char *smstate); |
cc3d967f | 1188 | int (*enable_smi_window)(struct kvm_vcpu *vcpu); |
5acc5c06 BS |
1189 | |
1190 | int (*mem_enc_op)(struct kvm *kvm, void __user *argp); | |
69eaedee BS |
1191 | int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp); |
1192 | int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp); | |
801e459a TL |
1193 | |
1194 | int (*get_msr_feature)(struct kvm_msr_entry *entry); | |
57b119da VK |
1195 | |
1196 | int (*nested_enable_evmcs)(struct kvm_vcpu *vcpu, | |
1197 | uint16_t *vmcs_version); | |
e2e871ab | 1198 | uint16_t (*nested_get_evmcs_version)(struct kvm_vcpu *vcpu); |
05d5a486 SB |
1199 | |
1200 | bool (*need_emulation_on_page_fault)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 ZX |
1201 | }; |
1202 | ||
af585b92 | 1203 | struct kvm_arch_async_pf { |
7c90705b | 1204 | u32 token; |
af585b92 | 1205 | gfn_t gfn; |
fb67e14f | 1206 | unsigned long cr3; |
c4806acd | 1207 | bool direct_map; |
af585b92 GN |
1208 | }; |
1209 | ||
97896d04 | 1210 | extern struct kvm_x86_ops *kvm_x86_ops; |
b666a4b6 | 1211 | extern struct kmem_cache *x86_fpu_cache; |
97896d04 | 1212 | |
434a1e94 SC |
1213 | #define __KVM_HAVE_ARCH_VM_ALLOC |
1214 | static inline struct kvm *kvm_arch_alloc_vm(void) | |
1215 | { | |
1216 | return kvm_x86_ops->vm_alloc(); | |
1217 | } | |
1218 | ||
1219 | static inline void kvm_arch_free_vm(struct kvm *kvm) | |
1220 | { | |
1221 | return kvm_x86_ops->vm_free(kvm); | |
1222 | } | |
1223 | ||
b08660e5 TL |
1224 | #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB |
1225 | static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm) | |
1226 | { | |
1227 | if (kvm_x86_ops->tlb_remote_flush && | |
1228 | !kvm_x86_ops->tlb_remote_flush(kvm)) | |
1229 | return 0; | |
1230 | else | |
1231 | return -ENOTSUPP; | |
1232 | } | |
1233 | ||
54f1585a ZX |
1234 | int kvm_mmu_module_init(void); |
1235 | void kvm_mmu_module_exit(void); | |
1236 | ||
1237 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
1238 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
13d268ca XG |
1239 | void kvm_mmu_init_vm(struct kvm *kvm); |
1240 | void kvm_mmu_uninit_vm(struct kvm *kvm); | |
7b52345e | 1241 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 | 1242 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
d0ec49d4 | 1243 | u64 acc_track_mask, u64 me_mask); |
54f1585a | 1244 | |
8a3c1a33 | 1245 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu); |
1c91cad4 KH |
1246 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
1247 | struct kvm_memory_slot *memslot); | |
3ea3b7fa | 1248 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, |
f36f3f28 | 1249 | const struct kvm_memory_slot *memslot); |
f4b4b180 KH |
1250 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
1251 | struct kvm_memory_slot *memslot); | |
1252 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
1253 | struct kvm_memory_slot *memslot); | |
1254 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
1255 | struct kvm_memory_slot *memslot); | |
1256 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1257 | struct kvm_memory_slot *slot, | |
1258 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 1259 | void kvm_mmu_zap_all(struct kvm *kvm); |
15248258 | 1260 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); |
bc8a3d89 BG |
1261 | unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm); |
1262 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); | |
54f1585a | 1263 | |
ff03a073 | 1264 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
9ed38ffa | 1265 | bool pdptrs_changed(struct kvm_vcpu *vcpu); |
cc4b6871 | 1266 | |
3200f405 | 1267 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 1268 | const void *val, int bytes); |
2f333bcb | 1269 | |
6ef768fa PB |
1270 | struct kvm_irq_mask_notifier { |
1271 | void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked); | |
1272 | int irq; | |
1273 | struct hlist_node link; | |
1274 | }; | |
1275 | ||
1276 | void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq, | |
1277 | struct kvm_irq_mask_notifier *kimn); | |
1278 | void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq, | |
1279 | struct kvm_irq_mask_notifier *kimn); | |
1280 | void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin, | |
1281 | bool mask); | |
1282 | ||
2f333bcb | 1283 | extern bool tdp_enabled; |
9f811285 | 1284 | |
a3e06bbe LJ |
1285 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
1286 | ||
92a1f12d JR |
1287 | /* control of guest tsc rate supported? */ |
1288 | extern bool kvm_has_tsc_control; | |
92a1f12d JR |
1289 | /* maximum supported tsc_khz for guests */ |
1290 | extern u32 kvm_max_guest_tsc_khz; | |
bc9b961b HZ |
1291 | /* number of bits of the fractional part of the TSC scaling ratio */ |
1292 | extern u8 kvm_tsc_scaling_ratio_frac_bits; | |
1293 | /* maximum allowed value of TSC scaling ratio */ | |
1294 | extern u64 kvm_max_tsc_scaling_ratio; | |
64672c95 YJ |
1295 | /* 1ull << kvm_tsc_scaling_ratio_frac_bits */ |
1296 | extern u64 kvm_default_tsc_scaling_ratio; | |
92a1f12d | 1297 | |
c45dcc71 | 1298 | extern u64 kvm_mce_cap_supported; |
92a1f12d | 1299 | |
54f1585a | 1300 | enum emulation_result { |
ac0a48c3 PB |
1301 | EMULATE_DONE, /* no further processing */ |
1302 | EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */ | |
54f1585a ZX |
1303 | EMULATE_FAIL, /* can't emulate this instruction */ |
1304 | }; | |
1305 | ||
571008da SY |
1306 | #define EMULTYPE_NO_DECODE (1 << 0) |
1307 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 1308 | #define EMULTYPE_SKIP (1 << 2) |
384bf221 SC |
1309 | #define EMULTYPE_ALLOW_RETRY (1 << 3) |
1310 | #define EMULTYPE_NO_UD_ON_FAIL (1 << 4) | |
1311 | #define EMULTYPE_VMWARE (1 << 5) | |
c60658d1 SC |
1312 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type); |
1313 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
1314 | void *insn, int insn_len); | |
35be0ade | 1315 | |
f2b4b7dd | 1316 | void kvm_enable_efer_bits(u64); |
384bb783 | 1317 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer); |
609e36d3 | 1318 | int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1319 | int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a ZX |
1320 | |
1321 | struct x86_emulate_ctxt; | |
1322 | ||
dca7f128 | 1323 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); |
6a908b62 | 1324 | int kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
54f1585a | 1325 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); |
5cb56059 | 1326 | int kvm_vcpu_halt(struct kvm_vcpu *vcpu); |
f5f48ee1 | 1327 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 1328 | |
3e6e0aab | 1329 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 1330 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
2b4a273b | 1331 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); |
3e6e0aab | 1332 | |
7f3d35fd KW |
1333 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
1334 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 1335 | |
49a9b07e | 1336 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 1337 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 1338 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 1339 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
1340 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
1341 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
1342 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
1343 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 1344 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 1345 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a | 1346 | |
609e36d3 | 1347 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
8fe8ab46 | 1348 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr); |
54f1585a | 1349 | |
91586a3b JK |
1350 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
1351 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 1352 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 1353 | |
298101da AK |
1354 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1355 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
1356 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
1357 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 1358 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
1359 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1360 | gfn_t gfn, void *data, int offset, int len, | |
1361 | u32 access); | |
0a79b009 | 1362 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
16f8a6f9 | 1363 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr); |
298101da | 1364 | |
1a577b72 MT |
1365 | static inline int __kvm_irq_line_state(unsigned long *irq_state, |
1366 | int irq_source_id, int level) | |
1367 | { | |
1368 | /* Logical OR for level trig interrupt */ | |
1369 | if (level) | |
1370 | __set_bit(irq_source_id, irq_state); | |
1371 | else | |
1372 | __clear_bit(irq_source_id, irq_state); | |
1373 | ||
1374 | return !!(*irq_state); | |
1375 | } | |
1376 | ||
b94742c9 JS |
1377 | #define KVM_MMU_ROOT_CURRENT BIT(0) |
1378 | #define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i) | |
1379 | #define KVM_MMU_ROOTS_ALL (~0UL) | |
08fb59d8 | 1380 | |
1a577b72 MT |
1381 | int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level); |
1382 | void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id); | |
3de42dc0 | 1383 | |
3419ffc8 SY |
1384 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
1385 | ||
1cb3f3ae | 1386 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
1387 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
1388 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
1389 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
1390 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 1391 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
6a82cd1c VK |
1392 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
1393 | ulong roots_to_free); | |
54987b7a PB |
1394 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1395 | struct x86_exception *exception); | |
ab9ae313 AK |
1396 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
1397 | struct x86_exception *exception); | |
1398 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
1399 | struct x86_exception *exception); | |
1400 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
1401 | struct x86_exception *exception); | |
1402 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
1403 | struct x86_exception *exception); | |
54f1585a | 1404 | |
d62caabb AS |
1405 | void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu); |
1406 | ||
54f1585a ZX |
1407 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); |
1408 | ||
14727754 | 1409 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code, |
dc25e89e | 1410 | void *insn, int insn_len); |
a7052897 | 1411 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
eb4b248e | 1412 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid); |
ade61e28 | 1413 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush); |
34c16eec | 1414 | |
18552672 | 1415 | void kvm_enable_tdp(void); |
5f4cb662 | 1416 | void kvm_disable_tdp(void); |
18552672 | 1417 | |
54987b7a PB |
1418 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access, |
1419 | struct x86_exception *exception) | |
e459e322 XG |
1420 | { |
1421 | return gpa; | |
1422 | } | |
1423 | ||
ec6d273d ZX |
1424 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
1425 | { | |
1426 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
1427 | ||
1428 | return (struct kvm_mmu_page *)page_private(page); | |
1429 | } | |
1430 | ||
d6e88aec | 1431 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
1432 | { |
1433 | u16 ldt; | |
1434 | asm("sldt %0" : "=g"(ldt)); | |
1435 | return ldt; | |
1436 | } | |
1437 | ||
d6e88aec | 1438 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
1439 | { |
1440 | asm("lldt %0" : : "rm"(sel)); | |
1441 | } | |
ec6d273d | 1442 | |
ec6d273d ZX |
1443 | #ifdef CONFIG_X86_64 |
1444 | static inline unsigned long read_msr(unsigned long msr) | |
1445 | { | |
1446 | u64 value; | |
1447 | ||
1448 | rdmsrl(msr, value); | |
1449 | return value; | |
1450 | } | |
1451 | #endif | |
1452 | ||
ec6d273d ZX |
1453 | static inline u32 get_rdx_init_val(void) |
1454 | { | |
1455 | return 0x600; /* P6 family */ | |
1456 | } | |
1457 | ||
c1a5d4f9 AK |
1458 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
1459 | { | |
1460 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
1461 | } | |
1462 | ||
ec6d273d ZX |
1463 | #define TSS_IOPB_BASE_OFFSET 0x66 |
1464 | #define TSS_BASE_SIZE 0x68 | |
1465 | #define TSS_IOPB_SIZE (65536 / 8) | |
1466 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
1467 | #define RMODE_TSS_SIZE \ |
1468 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 1469 | |
37817f29 IE |
1470 | enum { |
1471 | TASK_SWITCH_CALL = 0, | |
1472 | TASK_SWITCH_IRET = 1, | |
1473 | TASK_SWITCH_JMP = 2, | |
1474 | TASK_SWITCH_GATE = 3, | |
1475 | }; | |
1476 | ||
1371d904 | 1477 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
1478 | #define HF_HIF_MASK (1 << 1) |
1479 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 1480 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 1481 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 1482 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
f077825a PB |
1483 | #define HF_SMM_MASK (1 << 6) |
1484 | #define HF_SMM_INSIDE_NMI_MASK (1 << 7) | |
1371d904 | 1485 | |
699023e2 PB |
1486 | #define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE |
1487 | #define KVM_ADDRESS_SPACE_NUM 2 | |
1488 | ||
1489 | #define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0) | |
1490 | #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) | |
1371d904 | 1491 | |
4ecac3fd AK |
1492 | /* |
1493 | * Hardware virtualization extension instructions may fault if a | |
1494 | * reboot turns off virtualization while processes are running. | |
1495 | * Trap the fault and ignore the instruction if that happens. | |
1496 | */ | |
b7c4145b | 1497 | asmlinkage void kvm_spurious_fault(void); |
4ecac3fd | 1498 | |
5e520e62 | 1499 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 1500 | "666: " insn "\n\t" \ |
b7c4145b | 1501 | "668: \n\t" \ |
18b13e54 | 1502 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 1503 | "667: \n\t" \ |
5e520e62 | 1504 | cleanup_insn "\n\t" \ |
b7c4145b AK |
1505 | "cmpb $0, kvm_rebooting \n\t" \ |
1506 | "jne 668b \n\t" \ | |
8ceed347 | 1507 | __ASM_SIZE(push) " $666b \n\t" \ |
e8143499 | 1508 | "jmp kvm_spurious_fault \n\t" \ |
4ecac3fd | 1509 | ".popsection \n\t" \ |
3ee89722 | 1510 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 1511 | |
5e520e62 AK |
1512 | #define __kvm_handle_fault_on_reboot(insn) \ |
1513 | ____kvm_handle_fault_on_reboot(insn, "") | |
1514 | ||
e930bffe | 1515 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
b3ae2096 | 1516 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end); |
57128468 | 1517 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
8ee53820 | 1518 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
748c0e31 | 1519 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
c7c9c56c | 1520 | int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v); |
a1b37100 GN |
1521 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
1522 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 1523 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
d28bc9dd | 1524 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event); |
4256f43f | 1525 | void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu); |
e930bffe | 1526 | |
4180bf1b | 1527 | int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low, |
bdf7ffc8 | 1528 | unsigned long ipi_bitmap_high, u32 min, |
4180bf1b WL |
1529 | unsigned long icr, int op_64_bit); |
1530 | ||
5b76a3cf | 1531 | u64 kvm_get_arch_capabilities(void); |
18863bdd | 1532 | void kvm_define_shared_msr(unsigned index, u32 msr); |
8b3c3104 | 1533 | int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 1534 | |
35181e86 | 1535 | u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc); |
4ba76538 | 1536 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); |
35181e86 | 1537 | |
82b32774 | 1538 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu); |
f92653ee JK |
1539 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
1540 | ||
2860c4b1 PB |
1541 | void kvm_make_mclock_inprogress_request(struct kvm *kvm); |
1542 | void kvm_make_scan_ioapic_request(struct kvm *kvm); | |
1543 | ||
af585b92 GN |
1544 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
1545 | struct kvm_async_pf *work); | |
1546 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
1547 | struct kvm_async_pf *work); | |
56028d08 GN |
1548 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
1549 | struct kvm_async_pf *work); | |
7c90705b | 1550 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
1551 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
1552 | ||
6affcbed KH |
1553 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu); |
1554 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); | |
d264ee0c | 1555 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu); |
db8fcefa | 1556 | |
f5132b01 GN |
1557 | int kvm_is_in_guest(void); |
1558 | ||
1d8007bd PB |
1559 | int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); |
1560 | int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size); | |
d71ba788 PB |
1561 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu); |
1562 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu); | |
f5132b01 | 1563 | |
8feb4a04 FW |
1564 | bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq, |
1565 | struct kvm_vcpu **dest_vcpu); | |
1566 | ||
37131313 | 1567 | void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, |
d84f1e07 | 1568 | struct kvm_lapic_irq *irq); |
197a4f4b | 1569 | |
d1ed092f SS |
1570 | static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) |
1571 | { | |
1572 | if (kvm_x86_ops->vcpu_blocking) | |
1573 | kvm_x86_ops->vcpu_blocking(vcpu); | |
1574 | } | |
1575 | ||
1576 | static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) | |
1577 | { | |
1578 | if (kvm_x86_ops->vcpu_unblocking) | |
1579 | kvm_x86_ops->vcpu_unblocking(vcpu); | |
1580 | } | |
1581 | ||
3491caf2 | 1582 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
3217f7c2 | 1583 | |
7d669f50 SS |
1584 | static inline int kvm_cpu_get_apicid(int mps_cpu) |
1585 | { | |
1586 | #ifdef CONFIG_X86_LOCAL_APIC | |
64063505 | 1587 | return default_cpu_present_to_apicid(mps_cpu); |
7d669f50 SS |
1588 | #else |
1589 | WARN_ON_ONCE(1); | |
1590 | return BAD_APICID; | |
1591 | #endif | |
1592 | } | |
1593 | ||
05cade71 LP |
1594 | #define put_smstate(type, buf, offset, val) \ |
1595 | *(type *)((buf) + (offset) - 0x7e00) = val | |
1596 | ||
ed19321f SC |
1597 | #define GET_SMSTATE(type, buf, offset) \ |
1598 | (*(type *)((buf) + (offset) - 0x7e00)) | |
1599 | ||
1965aae3 | 1600 | #endif /* _ASM_X86_KVM_HOST_H */ |