[linux-2.6-block.git] / arch / x86 / include / asm / kvm.h

#ifndef _ASM_X86_KVM_H
#define _ASM_X86_KVM_H

/*
 * KVM x86 specific structures and definitions
 *
 */

#include <linux/types.h>
#include <linux/ioctl.h>

/* Select x86 specific features in <linux/kvm.h> */
#define __KVM_HAVE_PIT
#define __KVM_HAVE_IOAPIC
#define __KVM_HAVE_DEVICE_ASSIGNMENT
#define __KVM_HAVE_MSI
#define __KVM_HAVE_USER_NMI
#define __KVM_HAVE_GUEST_DEBUG
#define __KVM_HAVE_MSIX
#define __KVM_HAVE_MCE
#define __KVM_HAVE_PIT_STATE2
#define __KVM_HAVE_XEN_HVM
#define __KVM_HAVE_VCPU_EVENTS
#define __KVM_HAVE_DEBUGREGS

/* Architectural interrupt line count. */
#define KVM_NR_INTERRUPTS 256

struct kvm_memory_alias {
	__u32 slot;  /* this has a different namespace than memory slots */
	__u32 flags;
	__u64 guest_phys_addr;
	__u64 memory_size;
	__u64 target_phys_addr;
};

/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
struct kvm_pic_state {
	__u8 last_irr;	/* edge detection */
	__u8 irr;		/* interrupt request register */
	__u8 imr;		/* interrupt mask register */
	__u8 isr;		/* interrupt service register */
	__u8 priority_add;	/* highest irq priority */
	__u8 irq_base;
	__u8 read_reg_select;
	__u8 poll;
	__u8 special_mask;
	__u8 init_state;
	__u8 auto_eoi;
	__u8 rotate_on_auto_eoi;
	__u8 special_fully_nested_mode;
	__u8 init4;		/* true if 4 byte init */
	__u8 elcr;		/* PIIX edge/trigger selection */
	__u8 elcr_mask;
};

#define KVM_IOAPIC_NUM_PINS  24
struct kvm_ioapic_state {
	__u64 base_address;
	__u32 ioregsel;
	__u32 id;
	__u32 irr;
	__u32 pad;
	union {
		__u64 bits;
		struct {
			__u8 vector;
			__u8 delivery_mode:3;
			__u8 dest_mode:1;
			__u8 delivery_status:1;
			__u8 polarity:1;
			__u8 remote_irr:1;
			__u8 trig_mode:1;
			__u8 mask:1;
			__u8 reserve:7;
			__u8 reserved[4];
			__u8 dest_id;
		} fields;
	} redirtbl[KVM_IOAPIC_NUM_PINS];
};

#define KVM_IRQCHIP_PIC_MASTER   0
#define KVM_IRQCHIP_PIC_SLAVE    1
#define KVM_IRQCHIP_IOAPIC       2
#define KVM_NR_IRQCHIPS          3

/* for KVM_GET_REGS and KVM_SET_REGS */
struct kvm_regs {
	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
	__u64 rax, rbx, rcx, rdx;
	__u64 rsi, rdi, rsp, rbp;
	__u64 r8,  r9,  r10, r11;
	__u64 r12, r13, r14, r15;
	__u64 rip, rflags;
};

/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
#define KVM_APIC_REG_SIZE 0x400
struct kvm_lapic_state {
	char regs[KVM_APIC_REG_SIZE];
};

struct kvm_segment {
	__u64 base;
	__u32 limit;
	__u16 selector;
	__u8  type;
	__u8  present, dpl, db, s, l, g, avl;
	__u8  unusable;
	__u8  padding;
};

struct kvm_dtable {
	__u64 base;
	__u16 limit;
	__u16 padding[3];
};


/* for KVM_GET_SREGS and KVM_SET_SREGS */
struct kvm_sregs {
	/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
	struct kvm_segment cs, ds, es, fs, gs, ss;
	struct kvm_segment tr, ldt;
	struct kvm_dtable gdt, idt;
	__u64 cr0, cr2, cr3, cr4, cr8;
	__u64 efer;
	__u64 apic_base;
	__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
};

/* for KVM_GET_FPU and KVM_SET_FPU */
struct kvm_fpu {
	__u8  fpr[8][16];
	__u16 fcw;
	__u16 fsw;
	__u8  ftwx;  /* in fxsave format */
	__u8  pad1;
	__u16 last_opcode;
	__u64 last_ip;
	__u64 last_dp;
	__u8  xmm[16][16];
	__u32 mxcsr;
	__u32 pad2;
};

struct kvm_msr_entry {
	__u32 index;
	__u32 reserved;
	__u64 data;
};

/* for KVM_GET_MSRS and KVM_SET_MSRS */
struct kvm_msrs {
	__u32 nmsrs; /* number of msrs in entries */
	__u32 pad;

	struct kvm_msr_entry entries[0];
};

/* for KVM_GET_MSR_INDEX_LIST */
struct kvm_msr_list {
	__u32 nmsrs; /* number of msrs in entries */
	__u32 indices[0];
};


struct kvm_cpuid_entry {
	__u32 function;
	__u32 eax;
	__u32 ebx;
	__u32 ecx;
	__u32 edx;
	__u32 padding;
};

/* for KVM_SET_CPUID */
struct kvm_cpuid {
	__u32 nent;
	__u32 padding;
	struct kvm_cpuid_entry entries[0];
};

struct kvm_cpuid_entry2 {
	__u32 function;
	__u32 index;
	__u32 flags;
	__u32 eax;
	__u32 ebx;
	__u32 ecx;
	__u32 edx;
	__u32 padding[3];
};

#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
#define KVM_CPUID_FLAG_STATEFUL_FUNC    2
#define KVM_CPUID_FLAG_STATE_READ_NEXT  4

/* for KVM_SET_CPUID2 */
struct kvm_cpuid2 {
	__u32 nent;
	__u32 padding;
	struct kvm_cpuid_entry2 entries[0];
};

/* for KVM_GET_PIT and KVM_SET_PIT */
struct kvm_pit_channel_state {
	__u32 count; /* can be 65536 */
	__u16 latched_count;
	__u8 count_latched;
	__u8 status_latched;
	__u8 status;
	__u8 read_state;
	__u8 write_state;
	__u8 write_latch;
	__u8 rw_mode;
	__u8 mode;
	__u8 bcd;
	__u8 gate;
	__s64 count_load_time;
};

struct kvm_debug_exit_arch {
	__u32 exception;
	__u32 pad;
	__u64 pc;
	__u64 dr6;
	__u64 dr7;
};

#define KVM_GUESTDBG_USE_SW_BP		0x00010000
#define KVM_GUESTDBG_USE_HW_BP		0x00020000
#define KVM_GUESTDBG_INJECT_DB		0x00040000
#define KVM_GUESTDBG_INJECT_BP		0x00080000

/* for KVM_SET_GUEST_DEBUG */
struct kvm_guest_debug_arch {
	__u64 debugreg[8];
};

struct kvm_pit_state {
	struct kvm_pit_channel_state channels[3];
};

#define KVM_PIT_FLAGS_HPET_LEGACY  0x00000001

struct kvm_pit_state2 {
	struct kvm_pit_channel_state channels[3];
	__u32 flags;
	__u32 reserved[9];
};

struct kvm_reinject_control {
	__u8 pit_reinject;
	__u8 reserved[31];
};

/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
#define KVM_VCPUEVENT_VALID_NMI_PENDING	0x00000001
#define KVM_VCPUEVENT_VALID_SIPI_VECTOR	0x00000002
#define KVM_VCPUEVENT_VALID_SHADOW	0x00000004

/* Interrupt shadow states */
#define KVM_X86_SHADOW_INT_MOV_SS	0x01
#define KVM_X86_SHADOW_INT_STI		0x02

/* for KVM_GET/SET_VCPU_EVENTS */
struct kvm_vcpu_events {
	struct {
		__u8 injected;
		__u8 nr;
		__u8 has_error_code;
		__u8 pad;
		__u32 error_code;
	} exception;
	struct {
		__u8 injected;
		__u8 nr;
		__u8 soft;
		__u8 shadow;
	} interrupt;
	struct {
		__u8 injected;
		__u8 pending;
		__u8 masked;
		__u8 pad;
	} nmi;
	__u32 sipi_vector;
	__u32 flags;
	__u32 reserved[10];
};

/* for KVM_GET/SET_DEBUGREGS */
struct kvm_debugregs {
	__u64 db[4];
	__u64 dr6;
	__u64 dr7;
	__u64 flags;
	__u64 reserved[9];
};

#endif /* _ASM_X86_KVM_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_KVM_H
1965aae3 PA	2	#define _ASM_X86_KVM_H
f6a40e3b JY	3
	4	/*
	5	* KVM x86 specific structures and definitions
	6	*
	7	*/
	8
cef37678	9	#include <linux/types.h>
f6a40e3b JY	10	#include <linux/ioctl.h>
f6a40e3b JY	11
7a0eb196 AK	12	/* Select x86 specific features in <linux/kvm.h> */
	13	#define __KVM_HAVE_PIT
	14	#define __KVM_HAVE_IOAPIC
	15	#define __KVM_HAVE_DEVICE_ASSIGNMENT
	16	#define __KVM_HAVE_MSI
	17	#define __KVM_HAVE_USER_NMI
91b2ae77	18	#define __KVM_HAVE_GUEST_DEBUG
d510d6cc	19	#define __KVM_HAVE_MSIX
890ca9ae	20	#define __KVM_HAVE_MCE
e9f42757	21	#define __KVM_HAVE_PIT_STATE2
ffde22ac	22	#define __KVM_HAVE_XEN_HVM
3cfc3092	23	#define __KVM_HAVE_VCPU_EVENTS
a1efbe77	24	#define __KVM_HAVE_DEBUGREGS
7a0eb196	25
244d57ec JY	26	/* Architectural interrupt line count. */
	27	#define KVM_NR_INTERRUPTS 256
	28
f6a40e3b JY	29	struct kvm_memory_alias {
	30	__u32 slot; /* this has a different namespace than memory slots */
	31	__u32 flags;
	32	__u64 guest_phys_addr;
	33	__u64 memory_size;
	34	__u64 target_phys_addr;
	35	};
	36
da1386a5 JY	37	/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
	38	struct kvm_pic_state {
	39	__u8 last_irr; /* edge detection */
	40	__u8 irr; /* interrupt request register */
	41	__u8 imr; /* interrupt mask register */
	42	__u8 isr; /* interrupt service register */
	43	__u8 priority_add; /* highest irq priority */
	44	__u8 irq_base;
	45	__u8 read_reg_select;
	46	__u8 poll;
	47	__u8 special_mask;
	48	__u8 init_state;
	49	__u8 auto_eoi;
	50	__u8 rotate_on_auto_eoi;
	51	__u8 special_fully_nested_mode;
	52	__u8 init4; /* true if 4 byte init */
	53	__u8 elcr; /* PIIX edge/trigger selection */
	54	__u8 elcr_mask;
	55	};
	56
	57	#define KVM_IOAPIC_NUM_PINS 24
	58	struct kvm_ioapic_state {
	59	__u64 base_address;
	60	__u32 ioregsel;
	61	__u32 id;
	62	__u32 irr;
	63	__u32 pad;
	64	union {
	65	__u64 bits;
	66	struct {
	67	__u8 vector;
	68	__u8 delivery_mode:3;
	69	__u8 dest_mode:1;
	70	__u8 delivery_status:1;
	71	__u8 polarity:1;
	72	__u8 remote_irr:1;
	73	__u8 trig_mode:1;
	74	__u8 mask:1;
	75	__u8 reserve:7;
	76	__u8 reserved[4];
	77	__u8 dest_id;
	78	} fields;
	79	} redirtbl[KVM_IOAPIC_NUM_PINS];
	80	};
	81
	82	#define KVM_IRQCHIP_PIC_MASTER 0
	83	#define KVM_IRQCHIP_PIC_SLAVE 1
	84	#define KVM_IRQCHIP_IOAPIC 2
3e71f88b	85	#define KVM_NR_IRQCHIPS 3
da1386a5	86
19d30b16 JY	87	/* for KVM_GET_REGS and KVM_SET_REGS */
	88	struct kvm_regs {
	89	/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
	90	__u64 rax, rbx, rcx, rdx;
	91	__u64 rsi, rdi, rsp, rbp;
	92	__u64 r8, r9, r10, r11;
	93	__u64 r12, r13, r14, r15;
	94	__u64 rip, rflags;
	95	};
	96
d9ecf928 JY	97	/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
	98	#define KVM_APIC_REG_SIZE 0x400
	99	struct kvm_lapic_state {
	100	char regs[KVM_APIC_REG_SIZE];
	101	};
	102
3a56b201 JY	103	struct kvm_segment {
	104	__u64 base;
	105	__u32 limit;
	106	__u16 selector;
	107	__u8 type;
	108	__u8 present, dpl, db, s, l, g, avl;
	109	__u8 unusable;
	110	__u8 padding;
	111	};
	112
	113	struct kvm_dtable {
	114	__u64 base;
	115	__u16 limit;
	116	__u16 padding[3];
	117	};
	118
	119
244d57ec JY	120	/* for KVM_GET_SREGS and KVM_SET_SREGS */
	121	struct kvm_sregs {
	122	/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
	123	struct kvm_segment cs, ds, es, fs, gs, ss;
	124	struct kvm_segment tr, ldt;
	125	struct kvm_dtable gdt, idt;
	126	__u64 cr0, cr2, cr3, cr4, cr8;
	127	__u64 efer;
	128	__u64 apic_base;
	129	__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
	130	};
	131
6f723c79 CE	132	/* for KVM_GET_FPU and KVM_SET_FPU */
	133	struct kvm_fpu {
	134	__u8 fpr[8][16];
	135	__u16 fcw;
	136	__u16 fsw;
	137	__u8 ftwx; /* in fxsave format */
	138	__u8 pad1;
	139	__u16 last_opcode;
	140	__u64 last_ip;
	141	__u64 last_dp;
	142	__u8 xmm[16][16];
	143	__u32 mxcsr;
	144	__u32 pad2;
	145	};
	146
244d57ec JY	147	struct kvm_msr_entry {
	148	__u32 index;
	149	__u32 reserved;
	150	__u64 data;
	151	};
	152
	153	/* for KVM_GET_MSRS and KVM_SET_MSRS */
	154	struct kvm_msrs {
	155	__u32 nmsrs; /* number of msrs in entries */
	156	__u32 pad;
	157
	158	struct kvm_msr_entry entries[0];
	159	};
	160
	161	/* for KVM_GET_MSR_INDEX_LIST */
	162	struct kvm_msr_list {
	163	__u32 nmsrs; /* number of msrs in entries */
	164	__u32 indices[0];
	165	};
	166
	167
a162dd58 JY	168	struct kvm_cpuid_entry {
	169	__u32 function;
	170	__u32 eax;
	171	__u32 ebx;
	172	__u32 ecx;
	173	__u32 edx;
	174	__u32 padding;
	175	};
	176
	177	/* for KVM_SET_CPUID */
	178	struct kvm_cpuid {
	179	__u32 nent;
	180	__u32 padding;
	181	struct kvm_cpuid_entry entries[0];
	182	};
	183
07716717 DK	184	struct kvm_cpuid_entry2 {
	185	__u32 function;
	186	__u32 index;
	187	__u32 flags;
	188	__u32 eax;
	189	__u32 ebx;
	190	__u32 ecx;
	191	__u32 edx;
	192	__u32 padding[3];
	193	};
	194
	195	#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
	196	#define KVM_CPUID_FLAG_STATEFUL_FUNC 2
	197	#define KVM_CPUID_FLAG_STATE_READ_NEXT 4
	198
	199	/* for KVM_SET_CPUID2 */
	200	struct kvm_cpuid2 {
	201	__u32 nent;
	202	__u32 padding;
	203	struct kvm_cpuid_entry2 entries[0];
	204	};
a162dd58	205
e0f63cb9 SY	206	/* for KVM_GET_PIT and KVM_SET_PIT */
	207	struct kvm_pit_channel_state {
	208	__u32 count; /* can be 65536 */
	209	__u16 latched_count;
	210	__u8 count_latched;
	211	__u8 status_latched;
	212	__u8 status;
	213	__u8 read_state;
	214	__u8 write_state;
	215	__u8 write_latch;
	216	__u8 rw_mode;
	217	__u8 mode;
	218	__u8 bcd;
	219	__u8 gate;
	220	__s64 count_load_time;
	221	};
	222
d0bfb940 JK	223	struct kvm_debug_exit_arch {
	224	__u32 exception;
	225	__u32 pad;
	226	__u64 pc;
	227	__u64 dr6;
	228	__u64 dr7;
	229	};
	230
	231	#define KVM_GUESTDBG_USE_SW_BP 0x00010000
	232	#define KVM_GUESTDBG_USE_HW_BP 0x00020000
	233	#define KVM_GUESTDBG_INJECT_DB 0x00040000
	234	#define KVM_GUESTDBG_INJECT_BP 0x00080000
	235
	236	/* for KVM_SET_GUEST_DEBUG */
	237	struct kvm_guest_debug_arch {
	238	__u64 debugreg[8];
	239	};
	240
e0f63cb9 SY	241	struct kvm_pit_state {
	242	struct kvm_pit_channel_state channels[3];
	243	};
52d939a0	244
e9f42757 BK	245	#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
	246
	247	struct kvm_pit_state2 {
	248	struct kvm_pit_channel_state channels[3];
	249	__u32 flags;
	250	__u32 reserved[9];
	251	};
	252
52d939a0 MT	253	struct kvm_reinject_control {
	254	__u8 pit_reinject;
	255	__u8 reserved[31];
	256	};
3cfc3092	257
dab4b911 JK	258	/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
	259	#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
	260	#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
48005f64 JK	261	#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
	262
	263	/* Interrupt shadow states */
	264	#define KVM_X86_SHADOW_INT_MOV_SS 0x01
	265	#define KVM_X86_SHADOW_INT_STI 0x02
dab4b911	266
3cfc3092 JK	267	/* for KVM_GET/SET_VCPU_EVENTS */
	268	struct kvm_vcpu_events {
	269	struct {
	270	__u8 injected;
	271	__u8 nr;
	272	__u8 has_error_code;
	273	__u8 pad;
	274	__u32 error_code;
	275	} exception;
	276	struct {
	277	__u8 injected;
	278	__u8 nr;
	279	__u8 soft;
48005f64	280	__u8 shadow;
3cfc3092 JK	281	} interrupt;
	282	struct {
	283	__u8 injected;
	284	__u8 pending;
	285	__u8 masked;
	286	__u8 pad;
	287	} nmi;
	288	__u32 sipi_vector;
	289	__u32 flags;
	290	__u32 reserved[10];
	291	};
	292
a1efbe77 JK	293	/* for KVM_GET/SET_DEBUGREGS */
	294	struct kvm_debugregs {
	295	__u64 db[4];
	296	__u64 dr6;
	297	__u64 dr7;
	298	__u64 flags;
	299	__u64 reserved[9];
	300	};
	301
1965aae3	302	#endif /* _ASM_X86_KVM_H */