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1965aae3 PA |
1 | #ifndef _ASM_X86_KVM_H |
2 | #define _ASM_X86_KVM_H | |
f6a40e3b JY |
3 | |
4 | /* | |
5 | * KVM x86 specific structures and definitions | |
6 | * | |
7 | */ | |
8 | ||
cef37678 | 9 | #include <linux/types.h> |
f6a40e3b JY |
10 | #include <linux/ioctl.h> |
11 | ||
7a0eb196 AK |
12 | /* Select x86 specific features in <linux/kvm.h> */ |
13 | #define __KVM_HAVE_PIT | |
14 | #define __KVM_HAVE_IOAPIC | |
15 | #define __KVM_HAVE_DEVICE_ASSIGNMENT | |
16 | #define __KVM_HAVE_MSI | |
17 | #define __KVM_HAVE_USER_NMI | |
18 | ||
244d57ec JY |
19 | /* Architectural interrupt line count. */ |
20 | #define KVM_NR_INTERRUPTS 256 | |
21 | ||
f6a40e3b JY |
22 | struct kvm_memory_alias { |
23 | __u32 slot; /* this has a different namespace than memory slots */ | |
24 | __u32 flags; | |
25 | __u64 guest_phys_addr; | |
26 | __u64 memory_size; | |
27 | __u64 target_phys_addr; | |
28 | }; | |
29 | ||
da1386a5 JY |
30 | /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */ |
31 | struct kvm_pic_state { | |
32 | __u8 last_irr; /* edge detection */ | |
33 | __u8 irr; /* interrupt request register */ | |
34 | __u8 imr; /* interrupt mask register */ | |
35 | __u8 isr; /* interrupt service register */ | |
36 | __u8 priority_add; /* highest irq priority */ | |
37 | __u8 irq_base; | |
38 | __u8 read_reg_select; | |
39 | __u8 poll; | |
40 | __u8 special_mask; | |
41 | __u8 init_state; | |
42 | __u8 auto_eoi; | |
43 | __u8 rotate_on_auto_eoi; | |
44 | __u8 special_fully_nested_mode; | |
45 | __u8 init4; /* true if 4 byte init */ | |
46 | __u8 elcr; /* PIIX edge/trigger selection */ | |
47 | __u8 elcr_mask; | |
48 | }; | |
49 | ||
50 | #define KVM_IOAPIC_NUM_PINS 24 | |
51 | struct kvm_ioapic_state { | |
52 | __u64 base_address; | |
53 | __u32 ioregsel; | |
54 | __u32 id; | |
55 | __u32 irr; | |
56 | __u32 pad; | |
57 | union { | |
58 | __u64 bits; | |
59 | struct { | |
60 | __u8 vector; | |
61 | __u8 delivery_mode:3; | |
62 | __u8 dest_mode:1; | |
63 | __u8 delivery_status:1; | |
64 | __u8 polarity:1; | |
65 | __u8 remote_irr:1; | |
66 | __u8 trig_mode:1; | |
67 | __u8 mask:1; | |
68 | __u8 reserve:7; | |
69 | __u8 reserved[4]; | |
70 | __u8 dest_id; | |
71 | } fields; | |
72 | } redirtbl[KVM_IOAPIC_NUM_PINS]; | |
73 | }; | |
74 | ||
75 | #define KVM_IRQCHIP_PIC_MASTER 0 | |
76 | #define KVM_IRQCHIP_PIC_SLAVE 1 | |
77 | #define KVM_IRQCHIP_IOAPIC 2 | |
78 | ||
19d30b16 JY |
79 | /* for KVM_GET_REGS and KVM_SET_REGS */ |
80 | struct kvm_regs { | |
81 | /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ | |
82 | __u64 rax, rbx, rcx, rdx; | |
83 | __u64 rsi, rdi, rsp, rbp; | |
84 | __u64 r8, r9, r10, r11; | |
85 | __u64 r12, r13, r14, r15; | |
86 | __u64 rip, rflags; | |
87 | }; | |
88 | ||
d9ecf928 JY |
89 | /* for KVM_GET_LAPIC and KVM_SET_LAPIC */ |
90 | #define KVM_APIC_REG_SIZE 0x400 | |
91 | struct kvm_lapic_state { | |
92 | char regs[KVM_APIC_REG_SIZE]; | |
93 | }; | |
94 | ||
3a56b201 JY |
95 | struct kvm_segment { |
96 | __u64 base; | |
97 | __u32 limit; | |
98 | __u16 selector; | |
99 | __u8 type; | |
100 | __u8 present, dpl, db, s, l, g, avl; | |
101 | __u8 unusable; | |
102 | __u8 padding; | |
103 | }; | |
104 | ||
105 | struct kvm_dtable { | |
106 | __u64 base; | |
107 | __u16 limit; | |
108 | __u16 padding[3]; | |
109 | }; | |
110 | ||
111 | ||
244d57ec JY |
112 | /* for KVM_GET_SREGS and KVM_SET_SREGS */ |
113 | struct kvm_sregs { | |
114 | /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */ | |
115 | struct kvm_segment cs, ds, es, fs, gs, ss; | |
116 | struct kvm_segment tr, ldt; | |
117 | struct kvm_dtable gdt, idt; | |
118 | __u64 cr0, cr2, cr3, cr4, cr8; | |
119 | __u64 efer; | |
120 | __u64 apic_base; | |
121 | __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; | |
122 | }; | |
123 | ||
6f723c79 CE |
124 | /* for KVM_GET_FPU and KVM_SET_FPU */ |
125 | struct kvm_fpu { | |
126 | __u8 fpr[8][16]; | |
127 | __u16 fcw; | |
128 | __u16 fsw; | |
129 | __u8 ftwx; /* in fxsave format */ | |
130 | __u8 pad1; | |
131 | __u16 last_opcode; | |
132 | __u64 last_ip; | |
133 | __u64 last_dp; | |
134 | __u8 xmm[16][16]; | |
135 | __u32 mxcsr; | |
136 | __u32 pad2; | |
137 | }; | |
138 | ||
244d57ec JY |
139 | struct kvm_msr_entry { |
140 | __u32 index; | |
141 | __u32 reserved; | |
142 | __u64 data; | |
143 | }; | |
144 | ||
145 | /* for KVM_GET_MSRS and KVM_SET_MSRS */ | |
146 | struct kvm_msrs { | |
147 | __u32 nmsrs; /* number of msrs in entries */ | |
148 | __u32 pad; | |
149 | ||
150 | struct kvm_msr_entry entries[0]; | |
151 | }; | |
152 | ||
153 | /* for KVM_GET_MSR_INDEX_LIST */ | |
154 | struct kvm_msr_list { | |
155 | __u32 nmsrs; /* number of msrs in entries */ | |
156 | __u32 indices[0]; | |
157 | }; | |
158 | ||
159 | ||
a162dd58 JY |
160 | struct kvm_cpuid_entry { |
161 | __u32 function; | |
162 | __u32 eax; | |
163 | __u32 ebx; | |
164 | __u32 ecx; | |
165 | __u32 edx; | |
166 | __u32 padding; | |
167 | }; | |
168 | ||
169 | /* for KVM_SET_CPUID */ | |
170 | struct kvm_cpuid { | |
171 | __u32 nent; | |
172 | __u32 padding; | |
173 | struct kvm_cpuid_entry entries[0]; | |
174 | }; | |
175 | ||
07716717 DK |
176 | struct kvm_cpuid_entry2 { |
177 | __u32 function; | |
178 | __u32 index; | |
179 | __u32 flags; | |
180 | __u32 eax; | |
181 | __u32 ebx; | |
182 | __u32 ecx; | |
183 | __u32 edx; | |
184 | __u32 padding[3]; | |
185 | }; | |
186 | ||
187 | #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1 | |
188 | #define KVM_CPUID_FLAG_STATEFUL_FUNC 2 | |
189 | #define KVM_CPUID_FLAG_STATE_READ_NEXT 4 | |
190 | ||
191 | /* for KVM_SET_CPUID2 */ | |
192 | struct kvm_cpuid2 { | |
193 | __u32 nent; | |
194 | __u32 padding; | |
195 | struct kvm_cpuid_entry2 entries[0]; | |
196 | }; | |
a162dd58 | 197 | |
e0f63cb9 SY |
198 | /* for KVM_GET_PIT and KVM_SET_PIT */ |
199 | struct kvm_pit_channel_state { | |
200 | __u32 count; /* can be 65536 */ | |
201 | __u16 latched_count; | |
202 | __u8 count_latched; | |
203 | __u8 status_latched; | |
204 | __u8 status; | |
205 | __u8 read_state; | |
206 | __u8 write_state; | |
207 | __u8 write_latch; | |
208 | __u8 rw_mode; | |
209 | __u8 mode; | |
210 | __u8 bcd; | |
211 | __u8 gate; | |
212 | __s64 count_load_time; | |
213 | }; | |
214 | ||
d0bfb940 JK |
215 | struct kvm_debug_exit_arch { |
216 | __u32 exception; | |
217 | __u32 pad; | |
218 | __u64 pc; | |
219 | __u64 dr6; | |
220 | __u64 dr7; | |
221 | }; | |
222 | ||
223 | #define KVM_GUESTDBG_USE_SW_BP 0x00010000 | |
224 | #define KVM_GUESTDBG_USE_HW_BP 0x00020000 | |
225 | #define KVM_GUESTDBG_INJECT_DB 0x00040000 | |
226 | #define KVM_GUESTDBG_INJECT_BP 0x00080000 | |
227 | ||
228 | /* for KVM_SET_GUEST_DEBUG */ | |
229 | struct kvm_guest_debug_arch { | |
230 | __u64 debugreg[8]; | |
231 | }; | |
232 | ||
e0f63cb9 SY |
233 | struct kvm_pit_state { |
234 | struct kvm_pit_channel_state channels[3]; | |
235 | }; | |
52d939a0 MT |
236 | |
237 | struct kvm_reinject_control { | |
238 | __u8 pit_reinject; | |
239 | __u8 reserved[31]; | |
240 | }; | |
1965aae3 | 241 | #endif /* _ASM_X86_KVM_H */ |