[linux-2.6-block.git] / arch / x86 / include / asm / io_apic.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_IO_APIC_H
#define _ASM_X86_IO_APIC_H

#include <linux/types.h>
#include <asm/mpspec.h>
#include <asm/apicdef.h>
#include <asm/irq_vectors.h>
#include <asm/x86_init.h>
/*
 * Intel IO-APIC support for SMP and UP systems.
 *
 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
 */

/*
 * The structure of the IO-APIC:
 */
union IO_APIC_reg_00 {
	u32	raw;
	struct {
		u32	__reserved_2	: 14,
			LTS		:  1,
			delivery_type	:  1,
			__reserved_1	:  8,
			ID		:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_01 {
	u32	raw;
	struct {
		u32	version		:  8,
			__reserved_2	:  7,
			PRQ		:  1,
			entries		:  8,
			__reserved_1	:  8;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_02 {
	u32	raw;
	struct {
		u32	__reserved_2	: 24,
			arbitration	:  4,
			__reserved_1	:  4;
	} __attribute__ ((packed)) bits;
};

union IO_APIC_reg_03 {
	u32	raw;
	struct {
		u32	boot_DT		:  1,
			__reserved_1	: 31;
	} __attribute__ ((packed)) bits;
};

struct IO_APIC_route_entry {
	union {
		struct {
			u64	vector			:  8,
				delivery_mode		:  3,
				dest_mode_logical	:  1,
				delivery_status		:  1,
				active_low		:  1,
				irr			:  1,
				is_level		:  1,
				masked			:  1,
				reserved_0		: 15,
				reserved_1		: 17,
				virt_destid_8_14	:  7,
				destid_0_7		:  8;
		};
		struct {
			u64	ir_shared_0		:  8,
				ir_zero			:  3,
				ir_index_15		:  1,
				ir_shared_1		:  5,
				ir_reserved_0		: 31,
				ir_format		:  1,
				ir_index_0_14		: 15;
		};
		struct {
			u64	w1			: 32,
				w2			: 32;
		};
	};
} __attribute__ ((packed));

struct irq_alloc_info;
struct ioapic_domain_cfg;

#define	IOAPIC_MAP_ALLOC		0x1
#define	IOAPIC_MAP_CHECK		0x2

#ifdef CONFIG_X86_IO_APIC

/*
 * # of IO-APICs and # of IRQ routing registers
 */
extern int nr_ioapics;

extern int mpc_ioapic_id(int ioapic);
extern unsigned int mpc_ioapic_addr(int ioapic);

/* # of MP IRQ source entries */
extern int mp_irq_entries;

/* MP IRQ source entries */
extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];

/* True if "noapic" boot option passed */
extern bool ioapic_is_disabled;

/* 1 if "noapic" boot option passed */
extern int noioapicquirk;

/* -1 if "noapic" boot option passed */
extern int noioapicreroute;

extern u32 gsi_top;

extern unsigned long io_apic_irqs;

#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))

/*
 * If we use the IO-APIC for IRQ routing, disable automatic
 * assignment of PCI IRQ's.
 */
#define io_apic_assign_pci_irqs \
	(mp_irq_entries && !ioapic_is_disabled && io_apic_irqs)

struct irq_cfg;
extern void ioapic_insert_resources(void);
extern int arch_early_ioapic_init(void);

extern int save_ioapic_entries(void);
extern void mask_ioapic_entries(void);
extern int restore_ioapic_entries(void);

extern void setup_ioapic_ids_from_mpc(void);
extern void setup_ioapic_ids_from_mpc_nocheck(void);

extern int mp_find_ioapic(u32 gsi);
extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
			     struct irq_alloc_info *info);
extern void mp_unmap_irq(int irq);
extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
			      struct ioapic_domain_cfg *cfg);
extern int mp_unregister_ioapic(u32 gsi_base);
extern int mp_ioapic_registered(u32 gsi_base);

extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
				  int node, int trigger, int polarity);

extern void mp_save_irq(struct mpc_intsrc *m);

extern void disable_ioapic_support(void);

extern void __init io_apic_init_mappings(void);
extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
extern void native_restore_boot_irq_mode(void);

static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
{
	return x86_apic_ops.io_apic_read(apic, reg);
}

extern void setup_IO_APIC(void);
extern void enable_IO_APIC(void);
extern void clear_IO_APIC(void);
extern void restore_boot_irq_mode(void);
extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
extern void print_IO_APICs(void);
#else  /* !CONFIG_X86_IO_APIC */

#define IO_APIC_IRQ(x)		0
#define io_apic_assign_pci_irqs 0
#define setup_ioapic_ids_from_mpc x86_init_noop
#define nr_ioapics		(0)
static inline void ioapic_insert_resources(void) { }
static inline int arch_early_ioapic_init(void) { return 0; }
static inline void print_IO_APICs(void) {}
#define gsi_top (NR_IRQS_LEGACY)
static inline int mp_find_ioapic(u32 gsi) { return 0; }
static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
				    struct irq_alloc_info *info)
{
	return gsi;
}

static inline void mp_unmap_irq(int irq) { }

static inline int save_ioapic_entries(void)
{
	return -ENOMEM;
}

static inline void mask_ioapic_entries(void) { }
static inline int restore_ioapic_entries(void)
{
	return -ENOMEM;
}

static inline void mp_save_irq(struct mpc_intsrc *m) { }
static inline void disable_ioapic_support(void) { }
static inline void io_apic_init_mappings(void) { }
#define native_io_apic_read		NULL
#define native_restore_boot_irq_mode	NULL

static inline void setup_IO_APIC(void) { }
static inline void enable_IO_APIC(void) { }
static inline void restore_boot_irq_mode(void) { }

#endif

#endif /* _ASM_X86_IO_APIC_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1965aae3 PA	2	#ifndef _ASM_X86_IO_APIC_H
1965aae3 PA	3	#define _ASM_X86_IO_APIC_H
e1d91978	4
a1a33fa3	5	#include <linux/types.h>
e1d91978 TG	6	#include <asm/mpspec.h>
e1d91978 TG	7	#include <asm/apicdef.h>
9d6a4d08	8	#include <asm/irq_vectors.h>
4a8e2a31	9	#include <asm/x86_init.h>
e1d91978 TG	10	/*
	11	* Intel IO-APIC support for SMP and UP systems.
	12	*
	13	* Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
	14	*/
	15
	16	/*
	17	* The structure of the IO-APIC:
	18	*/
	19	union IO_APIC_reg_00 {
	20	u32 raw;
	21	struct {
	22	u32 __reserved_2 : 14,
	23	LTS : 1,
	24	delivery_type : 1,
	25	__reserved_1 : 8,
	26	ID : 8;
	27	} __attribute__ ((packed)) bits;
	28	};
	29
	30	union IO_APIC_reg_01 {
	31	u32 raw;
	32	struct {
	33	u32 version : 8,
	34	__reserved_2 : 7,
	35	PRQ : 1,
	36	entries : 8,
	37	__reserved_1 : 8;
	38	} __attribute__ ((packed)) bits;
	39	};
	40
	41	union IO_APIC_reg_02 {
	42	u32 raw;
	43	struct {
	44	u32 __reserved_2 : 24,
	45	arbitration : 4,
	46	__reserved_1 : 4;
	47	} __attribute__ ((packed)) bits;
	48	};
	49
	50	union IO_APIC_reg_03 {
	51	u32 raw;
	52	struct {
	53	u32 boot_DT : 1,
	54	__reserved_1 : 31;
	55	} __attribute__ ((packed)) bits;
	56	};
	57
e1d91978	58	struct IO_APIC_route_entry {
341b4a72 TG	59	union {
	60	struct {
	61	u64 vector : 8,
	62	delivery_mode : 3,
	63	dest_mode_logical : 1,
	64	delivery_status : 1,
	65	active_low : 1,
	66	irr : 1,
	67	is_level : 1,
	68	masked : 1,
	69	reserved_0 : 15,
51130d21 DW	70	reserved_1 : 17,
51130d21 DW	71	virt_destid_8_14 : 7,
341b4a72 TG	72	destid_0_7 : 8;
	73	};
	74	struct {
	75	u64 ir_shared_0 : 8,
	76	ir_zero : 3,
	77	ir_index_15 : 1,
	78	ir_shared_1 : 5,
	79	ir_reserved_0 : 31,
	80	ir_format : 1,
	81	ir_index_0_14 : 15;
	82	};
	83	struct {
	84	u64 w1 : 32,
	85	w2 : 32;
	86	};
	87	};
e1d91978 TG	88	} __attribute__ ((packed));
e1d91978 TG	89
c4d05a2c	90	struct irq_alloc_info;
f7a0c786	91	struct ioapic_domain_cfg;
c4d05a2c	92
d7f3d478 JL	93	#define IOAPIC_MAP_ALLOC 0x1
d7f3d478 JL	94	#define IOAPIC_MAP_CHECK 0x2
abb00522	95
e1d91978 TG	96	#ifdef CONFIG_X86_IO_APIC
	97
	98	/*
	99	* # of IO-APICs and # of IRQ routing registers
	100	*/
	101	extern int nr_ioapics;
e1d91978	102
d5371430 SS	103	extern int mpc_ioapic_id(int ioapic);
d5371430 SS	104	extern unsigned int mpc_ioapic_addr(int ioapic);
e1d91978 TG	105
	106	/* # of MP IRQ source entries */
	107	extern int mp_irq_entries;
	108
	109	/* MP IRQ source entries */
c2c21745	110	extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
e1d91978	111
ecf600f8 TG	112	/* True if "noapic" boot option passed */
ecf600f8 TG	113	extern bool ioapic_is_disabled;
e1d91978	114
a9322f64 SA	115	/* 1 if "noapic" boot option passed */
	116	extern int noioapicquirk;
	117
9197979b SA	118	/* -1 if "noapic" boot option passed */
	119	extern int noioapicreroute;
	120
154d9e50 JL	121	extern u32 gsi_top;
154d9e50 JL	122
8643e28d JL	123	extern unsigned long io_apic_irqs;
	124
	125	#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) \|\| ((1 << (x)) & io_apic_irqs))
	126
e1d91978 TG	127	/*
	128	* If we use the IO-APIC for IRQ routing, disable automatic
	129	* assignment of PCI IRQ's.
	130	*/
	131	#define io_apic_assign_pci_irqs \
ecf600f8	132	(mp_irq_entries && !ioapic_is_disabled && io_apic_irqs)
e1d91978	133
9b1b0e42	134	struct irq_cfg;
857fdc53	135	extern void ioapic_insert_resources(void);
11d686e9	136	extern int arch_early_ioapic_init(void);
e1d91978	137
31dce14a SS	138	extern int save_ioapic_entries(void);
	139	extern void mask_ioapic_entries(void);
	140	extern int restore_ioapic_entries(void);
4dc2f96c	141
de934103	142	extern void setup_ioapic_ids_from_mpc(void);
a38c5380	143	extern void setup_ioapic_ids_from_mpc_nocheck(void);
2a4ab640	144
3eb2be5f JL	145	extern int mp_find_ioapic(u32 gsi);
3eb2be5f JL	146	extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
c4d05a2c JL	147	extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
c4d05a2c JL	148	struct irq_alloc_info *info);
df334bea	149	extern void mp_unmap_irq(int irq);
35ef9c94 JL	150	extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
35ef9c94 JL	151	struct ioapic_domain_cfg *cfg);
15516a3b	152	extern int mp_unregister_ioapic(u32 gsi_base);
e89900c9	153	extern int mp_ioapic_registered(u32 gsi_base);
f7a0c786	154
c4d05a2c JL	155	extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
c4d05a2c JL	156	int node, int trigger, int polarity);
2a4ab640	157
2d8009ba FT	158	extern void mp_save_irq(struct mpc_intsrc *m);
2d8009ba FT	159
7167d08e HK	160	extern void disable_ioapic_support(void);
7167d08e HK	161
ca1b8862	162	extern void __init io_apic_init_mappings(void);
4a8e2a31	163	extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
51b146c5	164	extern void native_restore_boot_irq_mode(void);
4a8e2a31 KRW	165
	166	static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
	167	{
51b146c5	168	return x86_apic_ops.io_apic_read(apic, reg);
4a8e2a31 KRW	169	}
4a8e2a31 KRW	170
8643e28d JL	171	extern void setup_IO_APIC(void);
8643e28d JL	172	extern void enable_IO_APIC(void);
3c9e76db	173	extern void clear_IO_APIC(void);
ce279cdc	174	extern void restore_boot_irq_mode(void);
8643e28d JL	175	extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
8643e28d JL	176	extern void print_IO_APICs(void);
e1d91978	177	#else /* !CONFIG_X86_IO_APIC */
78f28b7c	178
8643e28d	179	#define IO_APIC_IRQ(x) 0
e1d91978	180	#define io_apic_assign_pci_irqs 0
de934103	181	#define setup_ioapic_ids_from_mpc x86_init_noop
ecf600f8	182	#define nr_ioapics (0)
857fdc53	183	static inline void ioapic_insert_resources(void) { }
11d686e9	184	static inline int arch_early_ioapic_init(void) { return 0; }
8643e28d	185	static inline void print_IO_APICs(void) {}
a4384df3	186	#define gsi_top (NR_IRQS_LEGACY)
eddb0c55	187	static inline int mp_find_ioapic(u32 gsi) { return 0; }
c4d05a2c JL	188	static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
	189	struct irq_alloc_info *info)
	190	{
	191	return gsi;
	192	}
	193
df334bea	194	static inline void mp_unmap_irq(int irq) { }
78f28b7c	195
31dce14a	196	static inline int save_ioapic_entries(void)
7d0f1926 HK	197	{
	198	return -ENOMEM;
	199	}
	200
31dce14a SS	201	static inline void mask_ioapic_entries(void) { }
31dce14a SS	202	static inline int restore_ioapic_entries(void)
7d0f1926 HK	203	{
	204	return -ENOMEM;
	205	}
	206
ca1b8862	207	static inline void mp_save_irq(struct mpc_intsrc *m) { }
7167d08e	208	static inline void disable_ioapic_support(void) { }
ca1b8862	209	static inline void io_apic_init_mappings(void) { }
4a8e2a31	210	#define native_io_apic_read NULL
51b146c5	211	#define native_restore_boot_irq_mode NULL
86866083 TG	212
	213	static inline void setup_IO_APIC(void) { }
	214	static inline void enable_IO_APIC(void) { }
ce279cdc	215	static inline void restore_boot_irq_mode(void) { }
86866083	216
96a388de	217	#endif
e1d91978	218
1965aae3	219	#endif /* _ASM_X86_IO_APIC_H */