[linux-block.git] / arch / x86 / include / asm / intel-family.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_INTEL_FAMILY_H
#define _ASM_X86_INTEL_FAMILY_H

/*
 * "Big Core" Processors (Branded as Core, Xeon, etc...)
 *
 * While adding a new CPUID for a new microarchitecture, add a new
 * group to keep logically sorted out in chronological order. Within
 * that group keep the CPUID for the variants sorted by model number.
 *
 * The defined symbol names have the following form:
 *	INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
 * where:
 * OPTFAMILY	Describes the family of CPUs that this belongs to. Default
 *		is assumed to be "_CORE" (and should be omitted). Other values
 *		currently in use are _ATOM and _XEON_PHI
 * MICROARCH	Is the code name for the micro-architecture for this core.
 *		N.B. Not the platform name.
 * OPTDIFF	If needed, a short string to differentiate by market segment.
 *
 *		Common OPTDIFFs:
 *
 *			- regular client parts
 *		_L	- regular mobile parts
 *		_G	- parts with extra graphics on
 *		_X	- regular server parts
 *		_D	- micro server parts
 *		_N,_P	- other mobile parts
 *		_H	- premium mobile parts
 *		_S	- other client parts
 *
 *		Historical OPTDIFFs:
 *
 *		_EP	- 2 socket server parts
 *		_EX	- 4+ socket server parts
 *
 * The #define line may optionally include a comment including platform or core
 * names. An exception is made for skylake/kabylake where steppings seem to have gotten
 * their own names :-(
 */

/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
#define INTEL_FAM6_ANY			X86_MODEL_ANY

#define INTEL_FAM6_CORE_YONAH		0x0E

#define INTEL_FAM6_CORE2_MEROM		0x0F
#define INTEL_FAM6_CORE2_MEROM_L	0x16
#define INTEL_FAM6_CORE2_PENRYN		0x17
#define INTEL_FAM6_CORE2_DUNNINGTON	0x1D

#define INTEL_FAM6_NEHALEM		0x1E
#define INTEL_FAM6_NEHALEM_G		0x1F /* Auburndale / Havendale */
#define INTEL_FAM6_NEHALEM_EP		0x1A
#define INTEL_FAM6_NEHALEM_EX		0x2E

#define INTEL_FAM6_WESTMERE		0x25
#define INTEL_FAM6_WESTMERE_EP		0x2C
#define INTEL_FAM6_WESTMERE_EX		0x2F

#define INTEL_FAM6_SANDYBRIDGE		0x2A
#define INTEL_FAM6_SANDYBRIDGE_X	0x2D
#define INTEL_FAM6_IVYBRIDGE		0x3A
#define INTEL_FAM6_IVYBRIDGE_X		0x3E

#define INTEL_FAM6_HASWELL		0x3C
#define INTEL_FAM6_HASWELL_X		0x3F
#define INTEL_FAM6_HASWELL_L		0x45
#define INTEL_FAM6_HASWELL_G		0x46

#define INTEL_FAM6_BROADWELL		0x3D
#define INTEL_FAM6_BROADWELL_G		0x47
#define INTEL_FAM6_BROADWELL_X		0x4F
#define INTEL_FAM6_BROADWELL_D		0x56

#define INTEL_FAM6_SKYLAKE_L		0x4E	/* Sky Lake             */
#define INTEL_FAM6_SKYLAKE		0x5E	/* Sky Lake             */
#define INTEL_FAM6_SKYLAKE_X		0x55	/* Sky Lake             */
/*                 CASCADELAKE_X	0x55	   Sky Lake -- s: 7     */
/*                 COOPERLAKE_X		0x55	   Sky Lake -- s: 11    */

#define INTEL_FAM6_KABYLAKE_L		0x8E	/* Sky Lake             */
/*                 AMBERLAKE_L		0x8E	   Sky Lake -- s: 9     */
/*                 COFFEELAKE_L		0x8E	   Sky Lake -- s: 10    */
/*                 WHISKEYLAKE_L	0x8E       Sky Lake -- s: 11,12 */

#define INTEL_FAM6_KABYLAKE		0x9E	/* Sky Lake             */
/*                 COFFEELAKE		0x9E	   Sky Lake -- s: 10-13 */

#define INTEL_FAM6_COMETLAKE		0xA5	/* Sky Lake             */
#define INTEL_FAM6_COMETLAKE_L		0xA6	/* Sky Lake             */

#define INTEL_FAM6_CANNONLAKE_L		0x66	/* Palm Cove */

#define INTEL_FAM6_ICELAKE_X		0x6A	/* Sunny Cove */
#define INTEL_FAM6_ICELAKE_D		0x6C	/* Sunny Cove */
#define INTEL_FAM6_ICELAKE		0x7D	/* Sunny Cove */
#define INTEL_FAM6_ICELAKE_L		0x7E	/* Sunny Cove */
#define INTEL_FAM6_ICELAKE_NNPI		0x9D	/* Sunny Cove */

#define INTEL_FAM6_ROCKETLAKE		0xA7	/* Cypress Cove */

#define INTEL_FAM6_TIGERLAKE_L		0x8C	/* Willow Cove */
#define INTEL_FAM6_TIGERLAKE		0x8D	/* Willow Cove */

#define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Golden Cove */

#define INTEL_FAM6_EMERALDRAPIDS_X	0xCF

#define INTEL_FAM6_GRANITERAPIDS_X	0xAD
#define INTEL_FAM6_GRANITERAPIDS_D	0xAE

/* "Hybrid" Processors (P-Core/E-Core) */

#define INTEL_FAM6_LAKEFIELD		0x8A	/* Sunny Cove / Tremont */

#define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */
#define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */

#define INTEL_FAM6_RAPTORLAKE		0xB7	/* Raptor Cove / Enhanced Gracemont */
#define INTEL_FAM6_RAPTORLAKE_P		0xBA
#define INTEL_FAM6_RAPTORLAKE_S		0xBF

#define INTEL_FAM6_METEORLAKE		0xAC
#define INTEL_FAM6_METEORLAKE_L		0xAA

#define INTEL_FAM6_ARROWLAKE_H		0xC5
#define INTEL_FAM6_ARROWLAKE		0xC6

#define INTEL_FAM6_LUNARLAKE_M		0xBD

/* "Small Core" Processors (Atom/E-Core) */

#define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */
#define INTEL_FAM6_ATOM_BONNELL_MID	0x26 /* Silverthorne, Lincroft */

#define INTEL_FAM6_ATOM_SALTWELL	0x36 /* Cedarview */
#define INTEL_FAM6_ATOM_SALTWELL_MID	0x27 /* Penwell */
#define INTEL_FAM6_ATOM_SALTWELL_TABLET	0x35 /* Cloverview */

#define INTEL_FAM6_ATOM_SILVERMONT	0x37 /* Bay Trail, Valleyview */
#define INTEL_FAM6_ATOM_SILVERMONT_D	0x4D /* Avaton, Rangely */
#define INTEL_FAM6_ATOM_SILVERMONT_MID	0x4A /* Merriefield */

#define INTEL_FAM6_ATOM_AIRMONT		0x4C /* Cherry Trail, Braswell */
#define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Moorefield */
#define INTEL_FAM6_ATOM_AIRMONT_NP	0x75 /* Lightning Mountain */

#define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
#define INTEL_FAM6_ATOM_GOLDMONT_D	0x5F /* Denverton */

/* Note: the micro-architecture is "Goldmont Plus" */
#define INTEL_FAM6_ATOM_GOLDMONT_PLUS	0x7A /* Gemini Lake */

#define INTEL_FAM6_ATOM_TREMONT_D	0x86 /* Jacobsville */
#define INTEL_FAM6_ATOM_TREMONT		0x96 /* Elkhart Lake */
#define INTEL_FAM6_ATOM_TREMONT_L	0x9C /* Jasper Lake */

#define INTEL_FAM6_ATOM_GRACEMONT	0xBE /* Alderlake N */

#define INTEL_FAM6_ATOM_CRESTMONT_X	0xAF /* Sierra Forest */
#define INTEL_FAM6_ATOM_CRESTMONT	0xB6 /* Grand Ridge */

/* Xeon Phi */

#define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */
#define INTEL_FAM6_XEON_PHI_KNM		0x85 /* Knights Mill */

/* Family 5 */
#define INTEL_FAM5_QUARK_X1000		0x09 /* Quark X1000 SoC */

#endif /* _ASM_X86_INTEL_FAMILY_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
970442c5 DH	2	#ifndef _ASM_X86_INTEL_FAMILY_H
	3	#define _ASM_X86_INTEL_FAMILY_H
	4
	5	/*
	6	* "Big Core" Processors (Branded as Core, Xeon, etc...)
	7	*
850eb9fb RB	8	* While adding a new CPUID for a new microarchitecture, add a new
	9	* group to keep logically sorted out in chronological order. Within
	10	* that group keep the CPUID for the variants sorted by model number.
12ece2d5 TL	11	*
	12	* The defined symbol names have the following form:
	13	* INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
	14	* where:
	15	* OPTFAMILY Describes the family of CPUs that this belongs to. Default
	16	* is assumed to be "_CORE" (and should be omitted). Other values
	17	* currently in use are _ATOM and _XEON_PHI
	18	* MICROARCH Is the code name for the micro-architecture for this core.
	19	* N.B. Not the platform name.
	20	* OPTDIFF If needed, a short string to differentiate by market segment.
a3d8c0d1 PZ	21	*
	22	* Common OPTDIFFs:
	23	*
	24	* - regular client parts
	25	* _L - regular mobile parts
	26	* _G - parts with extra graphics on
	27	* _X - regular server parts
	28	* _D - micro server parts
3ccce934	29	* _N,_P - other mobile parts
b99d70c0	30	* _H - premium mobile parts
ea902bcc	31	* _S - other client parts
a3d8c0d1 PZ	32	*
	33	* Historical OPTDIFFs:
	34	*
	35	* _EP - 2 socket server parts
	36	* _EX - 4+ socket server parts
12ece2d5	37	*
53375a5a	38	* The #define line may optionally include a comment including platform or core
99cb64de	39	* names. An exception is made for skylake/kabylake where steppings seem to have gotten
53375a5a	40	* their own names :-(
970442c5 DH	41	*/
970442c5 DH	42
20d43744 TG	43	/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
	44	#define INTEL_FAM6_ANY X86_MODEL_ANY
	45
970442c5	46	#define INTEL_FAM6_CORE_YONAH 0x0E
c238f234	47
970442c5 DH	48	#define INTEL_FAM6_CORE2_MEROM 0x0F
	49	#define INTEL_FAM6_CORE2_MEROM_L 0x16
	50	#define INTEL_FAM6_CORE2_PENRYN 0x17
	51	#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
	52
	53	#define INTEL_FAM6_NEHALEM 0x1E
4b3b234f	54	#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
970442c5 DH	55	#define INTEL_FAM6_NEHALEM_EP 0x1A
970442c5 DH	56	#define INTEL_FAM6_NEHALEM_EX 0x2E
c238f234	57
970442c5	58	#define INTEL_FAM6_WESTMERE 0x25
970442c5 DH	59	#define INTEL_FAM6_WESTMERE_EP 0x2C
	60	#define INTEL_FAM6_WESTMERE_EX 0x2F
	61
	62	#define INTEL_FAM6_SANDYBRIDGE 0x2A
	63	#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
	64	#define INTEL_FAM6_IVYBRIDGE 0x3A
	65	#define INTEL_FAM6_IVYBRIDGE_X 0x3E
	66
c66f78a6	67	#define INTEL_FAM6_HASWELL 0x3C
970442c5	68	#define INTEL_FAM6_HASWELL_X 0x3F
af239c44	69	#define INTEL_FAM6_HASWELL_L 0x45
5e741407	70	#define INTEL_FAM6_HASWELL_G 0x46
970442c5	71
c66f78a6	72	#define INTEL_FAM6_BROADWELL 0x3D
5e741407	73	#define INTEL_FAM6_BROADWELL_G 0x47
970442c5	74	#define INTEL_FAM6_BROADWELL_X 0x4F
5ebb34ed	75	#define INTEL_FAM6_BROADWELL_D 0x56
970442c5	76
53375a5a PZ	77	#define INTEL_FAM6_SKYLAKE_L 0x4E /* Sky Lake */
	78	#define INTEL_FAM6_SKYLAKE 0x5E /* Sky Lake */
	79	#define INTEL_FAM6_SKYLAKE_X 0x55 /* Sky Lake */
99cb64de AC	80	/* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */
99cb64de AC	81	/* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */
970442c5	82
53375a5a PZ	83	#define INTEL_FAM6_KABYLAKE_L 0x8E /* Sky Lake */
	84	/* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */
	85	/* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */
	86	/* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */
850eb9fb	87
53375a5a PZ	88	#define INTEL_FAM6_KABYLAKE 0x9E /* Sky Lake */
53375a5a PZ	89	/* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */
8cd8f0ce	90
53375a5a PZ	91	#define INTEL_FAM6_COMETLAKE 0xA5 /* Sky Lake */
53375a5a PZ	92	#define INTEL_FAM6_COMETLAKE_L 0xA6 /* Sky Lake */
6e1c32c5	93
53375a5a	94	#define INTEL_FAM6_CANNONLAKE_L 0x66 /* Palm Cove */
8d7c6ac3	95
53375a5a PZ	96	#define INTEL_FAM6_ICELAKE_X 0x6A /* Sunny Cove */
	97	#define INTEL_FAM6_ICELAKE_D 0x6C /* Sunny Cove */
	98	#define INTEL_FAM6_ICELAKE 0x7D /* Sunny Cove */
	99	#define INTEL_FAM6_ICELAKE_L 0x7E /* Sunny Cove */
	100	#define INTEL_FAM6_ICELAKE_NNPI 0x9D /* Sunny Cove */
e00b62f0	101
53375a5a	102	#define INTEL_FAM6_ROCKETLAKE 0xA7 /* Cypress Cove */
e00b62f0	103
53375a5a PZ	104	#define INTEL_FAM6_TIGERLAKE_L 0x8C /* Willow Cove */
53375a5a PZ	105	#define INTEL_FAM6_TIGERLAKE 0x8D /* Willow Cove */
28188cc4 AK	106
28188cc4 AK	107	#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */
53375a5a	108
7beade0d TL	109	#define INTEL_FAM6_EMERALDRAPIDS_X 0xCF
	110
	111	#define INTEL_FAM6_GRANITERAPIDS_X 0xAD
	112	#define INTEL_FAM6_GRANITERAPIDS_D 0xAE
	113
53544562 PZ	114	/* "Hybrid" Processors (P-Core/E-Core) */
	115
	116	#define INTEL_FAM6_LAKEFIELD 0x8A /* Sunny Cove / Tremont */
	117
53375a5a PZ	118	#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */
53375a5a PZ	119	#define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */
e00b62f0	120
53544562	121	#define INTEL_FAM6_RAPTORLAKE 0xB7 /* Raptor Cove / Enhanced Gracemont */
3ccce934	122	#define INTEL_FAM6_RAPTORLAKE_P 0xBA
ea902bcc	123	#define INTEL_FAM6_RAPTORLAKE_S 0xBF
fbdb5e8f	124
5515d21c TL	125	#define INTEL_FAM6_METEORLAKE 0xAC
	126	#define INTEL_FAM6_METEORLAKE_L 0xAA
	127
b99d70c0	128	#define INTEL_FAM6_ARROWLAKE_H 0xC5
81515ecf TL	129	#define INTEL_FAM6_ARROWLAKE 0xC6
81515ecf TL	130
53544562 PZ	131	#define INTEL_FAM6_LUNARLAKE_M 0xBD
53544562 PZ	132
7beade0d	133	/* "Small Core" Processors (Atom/E-Core) */
970442c5	134
f2c4db1b PZ	135	#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
	136	#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
	137
	138	#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
	139	#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
	140	#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
	141
	142	#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
5ebb34ed	143	#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */
f2c4db1b PZ	144	#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
	145
	146	#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
	147	#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
855fa1f3	148	#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
f2c4db1b PZ	149
f2c4db1b PZ	150	#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
5ebb34ed	151	#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */
a3d8c0d1 PZ	152
a3d8c0d1 PZ	153	/* Note: the micro-architecture is "Goldmont Plus" */
f2c4db1b	154	#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
0a05fa67	155
5ebb34ed	156	#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */
0f65605a	157	#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
b2d32af0	158	#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */
970442c5	159
882cdb06 PZ	160	#define INTEL_FAM6_ATOM_GRACEMONT 0xBE /* Alderlake N */
882cdb06 PZ	161
0cfd8fba PZ	162	#define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */
0cfd8fba PZ	163	#define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */
7beade0d	164
970442c5 DH	165	/* Xeon Phi */
	166
	167	#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
0047f598	168	#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
970442c5	169
20d43744 TG	170	/* Family 5 */
	171	#define INTEL_FAM5_QUARK_X1000 0x09 /* Quark X1000 SoC */
	172
970442c5	173	#endif /* _ASM_X86_INTEL_FAMILY_H */