[linux-2.6-block.git] / arch / x86 / include / asm / gart.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_GART_H
#define _ASM_X86_GART_H

#include <asm/e820/api.h>

extern void set_up_gart_resume(u32, u32);

extern int fallback_aper_order;
extern int fallback_aper_force;
extern int fix_aperture;

/* PTE bits. */
#define GPTE_VALID	1
#define GPTE_COHERENT	2

/* Aperture control register bits. */
#define GARTEN		(1<<0)
#define DISGARTCPU	(1<<4)
#define DISGARTIO	(1<<5)
#define DISTLBWALKPRB	(1<<6)

/* GART cache control register bits. */
#define INVGART		(1<<0)
#define GARTPTEERR	(1<<1)

/* K8 On-cpu GART registers */
#define AMD64_GARTAPERTURECTL	0x90
#define AMD64_GARTAPERTUREBASE	0x94
#define AMD64_GARTTABLEBASE	0x98
#define AMD64_GARTCACHECTL	0x9c

#ifdef CONFIG_GART_IOMMU
extern int gart_iommu_aperture;
extern int gart_iommu_aperture_allowed;
extern int gart_iommu_aperture_disabled;

extern void early_gart_iommu_check(void);
extern int gart_iommu_init(void);
extern void __init gart_parse_options(char *);
void gart_iommu_hole_init(void);

#else
#define gart_iommu_aperture            0
#define gart_iommu_aperture_allowed    0
#define gart_iommu_aperture_disabled   1

static inline void early_gart_iommu_check(void)
{
}
static inline void gart_parse_options(char *options)
{
}
static inline void gart_iommu_hole_init(void)
{
}
#endif

extern int agp_amd64_init(void);

static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
{
	u32 ctl;

	/*
	 * Don't enable translation but enable GART IO and CPU accesses.
	 * Also, set DISTLBWALKPRB since GART tables memory is UC.
	 */
	ctl = order << 1;

	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
}

static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
{
	u32 tmp, ctl;

	/* address of the mappings table */
	addr >>= 12;
	tmp = (u32) addr<<4;
	tmp &= ~0xf;
	pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);

	/* Enable GART translation for this hammer. */
	pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
	ctl |= GARTEN | DISTLBWALKPRB;
	ctl &= ~(DISGARTCPU | DISGARTIO);
	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
}

static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
{
	if (!aper_base)
		return 0;

	if (aper_base + aper_size > 0x100000000ULL) {
		printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
		return 0;
	}
	if (e820__mapped_any(aper_base, aper_base + aper_size, E820_TYPE_RAM)) {
		printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
		return 0;
	}
	if (aper_size < min_size) {
		printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
				 aper_size>>20, min_size>>20);
		return 0;
	}

	return 1;
}

#endif /* _ASM_X86_GART_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1965aae3 PA	2	#ifndef _ASM_X86_GART_H
1965aae3 PA	3	#define _ASM_X86_GART_H
395624fc	4
66441bd3	5	#include <asm/e820/api.h>
0abbc78a	6
6703f6d1	7	extern void set_up_gart_resume(u32, u32);
e93be88d	8
395624fc JR	9	extern int fallback_aper_order;
395624fc JR	10	extern int fallback_aper_force;
395624fc	11	extern int fix_aperture;
395624fc	12
aa134f1b PM	13	/* PTE bits. */
	14	#define GPTE_VALID 1
	15	#define GPTE_COHERENT 2
	16
	17	/* Aperture control register bits. */
	18	#define GARTEN (1<<0)
	19	#define DISGARTCPU (1<<4)
	20	#define DISGARTIO (1<<5)
260133ab	21	#define DISTLBWALKPRB (1<<6)
aa134f1b PM	22
	23	/* GART cache control register bits. */
	24	#define INVGART (1<<0)
	25	#define GARTPTEERR (1<<1)
	26
	27	/* K8 On-cpu GART registers */
	28	#define AMD64_GARTAPERTURECTL 0x90
	29	#define AMD64_GARTAPERTUREBASE 0x94
	30	#define AMD64_GARTTABLEBASE 0x98
	31	#define AMD64_GARTCACHECTL 0x9c
aa134f1b	32
1d9b16d1 JR	33	#ifdef CONFIG_GART_IOMMU
	34	extern int gart_iommu_aperture;
	35	extern int gart_iommu_aperture_allowed;
	36	extern int gart_iommu_aperture_disabled;
	37
	38	extern void early_gart_iommu_check(void);
de957628	39	extern int gart_iommu_init(void);
1d9b16d1	40	extern void __init gart_parse_options(char *);
78013eaa	41	void gart_iommu_hole_init(void);
1d9b16d1 JR	42
	43	#else
	44	#define gart_iommu_aperture 0
	45	#define gart_iommu_aperture_allowed 0
	46	#define gart_iommu_aperture_disabled 1
	47
	48	static inline void early_gart_iommu_check(void)
	49	{
	50	}
1d9b16d1 JR	51	static inline void gart_parse_options(char *options)
	52	{
	53	}
78013eaa	54	static inline void gart_iommu_hole_init(void)
1d9b16d1 JR	55	{
	56	}
	57	#endif
	58
237a6224 JR	59	extern int agp_amd64_init(void);
237a6224 JR	60
260133ab BP	61	static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
	62	{
	63	u32 ctl;
	64
	65	/*
	66	* Don't enable translation but enable GART IO and CPU accesses.
	67	* Also, set DISTLBWALKPRB since GART tables memory is UC.
	68	*/
c34151a7	69	ctl = order << 1;
260133ab BP	70
	71	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
	72	}
	73
3bb6fbf9 PM	74	static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
	75	{
	76	u32 tmp, ctl;
	77
af289bfe JR	78	/* address of the mappings table */
	79	addr >>= 12;
	80	tmp = (u32) addr<<4;
	81	tmp &= ~0xf;
	82	pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
	83
	84	/* Enable GART translation for this hammer. */
	85	pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
c34151a7	86	ctl \|= GARTEN \| DISTLBWALKPRB;
af289bfe JR	87	ctl &= ~(DISGARTCPU \| DISGARTIO);
af289bfe JR	88	pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
3bb6fbf9 PM	89	}
3bb6fbf9 PM	90
0abbc78a PM	91	static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
	92	{
	93	if (!aper_base)
	94	return 0;
	95
	96	if (aper_base + aper_size > 0x100000000ULL) {
9b156845	97	printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
0abbc78a PM	98	return 0;
0abbc78a PM	99	}
09821ff1	100	if (e820__mapped_any(aper_base, aper_base + aper_size, E820_TYPE_RAM)) {
9b156845	101	printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
0abbc78a PM	102	return 0;
	103	}
	104	if (aper_size < min_size) {
9b156845	105	printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
0abbc78a PM	106	aper_size>>20, min_size>>20);
	107	return 0;
	108	}
	109
	110	return 1;
	111	}
	112
1965aae3	113	#endif /* _ASM_X86_GART_H */