Commit | Line | Data |
---|---|---|
1361b83a LT |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
10 | #ifndef _FPU_INTERNAL_H | |
11 | #define _FPU_INTERNAL_H | |
12 | ||
1361b83a | 13 | #include <linux/regset.h> |
050902c0 | 14 | #include <linux/compat.h> |
1361b83a | 15 | #include <linux/slab.h> |
f89e32e0 | 16 | |
1361b83a | 17 | #include <asm/user.h> |
f89e32e0 | 18 | #include <asm/i387.h> |
1361b83a LT |
19 | #include <asm/xsave.h> |
20 | ||
72a671ce SS |
21 | #ifdef CONFIG_X86_64 |
22 | # include <asm/sigcontext32.h> | |
23 | # include <asm/user32.h> | |
235b8022 AV |
24 | struct ksignal; |
25 | int ia32_setup_rt_frame(int sig, struct ksignal *ksig, | |
72a671ce | 26 | compat_sigset_t *set, struct pt_regs *regs); |
235b8022 | 27 | int ia32_setup_frame(int sig, struct ksignal *ksig, |
72a671ce SS |
28 | compat_sigset_t *set, struct pt_regs *regs); |
29 | #else | |
30 | # define user_i387_ia32_struct user_i387_struct | |
31 | # define user32_fxsr_struct user_fxsr_struct | |
32 | # define ia32_setup_frame __setup_frame | |
33 | # define ia32_setup_rt_frame __setup_rt_frame | |
34 | #endif | |
35 | ||
36 | extern unsigned int mxcsr_feature_mask; | |
3a9c4b0d | 37 | extern void fpu__cpu_init(void); |
5d2bd700 | 38 | extern void eager_fpu_init(void); |
1361b83a | 39 | |
36b544dc | 40 | DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); |
1361b83a | 41 | |
72a671ce SS |
42 | extern void convert_from_fxsr(struct user_i387_ia32_struct *env, |
43 | struct task_struct *tsk); | |
44 | extern void convert_to_fxsr(struct task_struct *tsk, | |
45 | const struct user_i387_ia32_struct *env); | |
46 | ||
1361b83a LT |
47 | extern user_regset_active_fn fpregs_active, xfpregs_active; |
48 | extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get, | |
49 | xstateregs_get; | |
50 | extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set, | |
51 | xstateregs_set; | |
52 | ||
1361b83a LT |
53 | /* |
54 | * xstateregs_active == fpregs_active. Please refer to the comment | |
55 | * at the definition of fpregs_active. | |
56 | */ | |
57 | #define xstateregs_active fpregs_active | |
58 | ||
1361b83a LT |
59 | #ifdef CONFIG_MATH_EMULATION |
60 | extern void finit_soft_fpu(struct i387_soft_struct *soft); | |
61 | #else | |
62 | static inline void finit_soft_fpu(struct i387_soft_struct *soft) {} | |
63 | #endif | |
64 | ||
1c927eea | 65 | /* |
36b544dc | 66 | * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx, |
1c927eea RR |
67 | * on this CPU. |
68 | * | |
69 | * This will disable any lazy FPU state restore of the current FPU state, | |
70 | * but if the current thread owns the FPU, it will still be saved by. | |
71 | */ | |
72 | static inline void __cpu_disable_lazy_restore(unsigned int cpu) | |
73 | { | |
36b544dc | 74 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
1c927eea RR |
75 | } |
76 | ||
66ddc2cb | 77 | static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu) |
1c927eea | 78 | { |
66ddc2cb | 79 | return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu; |
1c927eea RR |
80 | } |
81 | ||
050902c0 SS |
82 | static inline int is_ia32_compat_frame(void) |
83 | { | |
84 | return config_enabled(CONFIG_IA32_EMULATION) && | |
85 | test_thread_flag(TIF_IA32); | |
86 | } | |
87 | ||
88 | static inline int is_ia32_frame(void) | |
89 | { | |
90 | return config_enabled(CONFIG_X86_32) || is_ia32_compat_frame(); | |
91 | } | |
92 | ||
93 | static inline int is_x32_frame(void) | |
94 | { | |
95 | return config_enabled(CONFIG_X86_X32_ABI) && test_thread_flag(TIF_X32); | |
96 | } | |
97 | ||
1361b83a LT |
98 | #define X87_FSW_ES (1 << 7) /* Exception Summary */ |
99 | ||
5d2bd700 SS |
100 | static __always_inline __pure bool use_eager_fpu(void) |
101 | { | |
c6b40691 | 102 | return static_cpu_has_safe(X86_FEATURE_EAGER_FPU); |
5d2bd700 SS |
103 | } |
104 | ||
1361b83a LT |
105 | static __always_inline __pure bool use_xsaveopt(void) |
106 | { | |
c6b40691 | 107 | return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); |
1361b83a LT |
108 | } |
109 | ||
110 | static __always_inline __pure bool use_xsave(void) | |
111 | { | |
c6b40691 | 112 | return static_cpu_has_safe(X86_FEATURE_XSAVE); |
1361b83a LT |
113 | } |
114 | ||
115 | static __always_inline __pure bool use_fxsr(void) | |
116 | { | |
c6b40691 | 117 | return static_cpu_has_safe(X86_FEATURE_FXSR); |
1361b83a LT |
118 | } |
119 | ||
5d2bd700 SS |
120 | static inline void fx_finit(struct i387_fxsave_struct *fx) |
121 | { | |
5d2bd700 | 122 | fx->cwd = 0x37f; |
a8615af4 | 123 | fx->mxcsr = MXCSR_DEFAULT; |
5d2bd700 SS |
124 | } |
125 | ||
1361b83a LT |
126 | extern void __sanitize_i387_state(struct task_struct *); |
127 | ||
128 | static inline void sanitize_i387_state(struct task_struct *tsk) | |
129 | { | |
130 | if (!use_xsaveopt()) | |
131 | return; | |
132 | __sanitize_i387_state(tsk); | |
133 | } | |
134 | ||
49b8c695 PA |
135 | #define user_insn(insn, output, input...) \ |
136 | ({ \ | |
137 | int err; \ | |
138 | asm volatile(ASM_STAC "\n" \ | |
139 | "1:" #insn "\n\t" \ | |
140 | "2: " ASM_CLAC "\n" \ | |
141 | ".section .fixup,\"ax\"\n" \ | |
142 | "3: movl $-1,%[err]\n" \ | |
143 | " jmp 2b\n" \ | |
144 | ".previous\n" \ | |
145 | _ASM_EXTABLE(1b, 3b) \ | |
146 | : [err] "=r" (err), output \ | |
147 | : "0"(0), input); \ | |
148 | err; \ | |
149 | }) | |
150 | ||
0ca5bd0d SS |
151 | #define check_insn(insn, output, input...) \ |
152 | ({ \ | |
153 | int err; \ | |
154 | asm volatile("1:" #insn "\n\t" \ | |
155 | "2:\n" \ | |
156 | ".section .fixup,\"ax\"\n" \ | |
157 | "3: movl $-1,%[err]\n" \ | |
158 | " jmp 2b\n" \ | |
159 | ".previous\n" \ | |
160 | _ASM_EXTABLE(1b, 3b) \ | |
161 | : [err] "=r" (err), output \ | |
162 | : "0"(0), input); \ | |
163 | err; \ | |
164 | }) | |
165 | ||
166 | static inline int fsave_user(struct i387_fsave_struct __user *fx) | |
1361b83a | 167 | { |
49b8c695 | 168 | return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx)); |
1361b83a LT |
169 | } |
170 | ||
171 | static inline int fxsave_user(struct i387_fxsave_struct __user *fx) | |
172 | { | |
0ca5bd0d | 173 | if (config_enabled(CONFIG_X86_32)) |
49b8c695 | 174 | return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx)); |
0ca5bd0d | 175 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
49b8c695 | 176 | return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx)); |
1361b83a | 177 | |
0ca5bd0d | 178 | /* See comment in fpu_fxsave() below. */ |
49b8c695 | 179 | return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx)); |
1361b83a LT |
180 | } |
181 | ||
0ca5bd0d | 182 | static inline int fxrstor_checking(struct i387_fxsave_struct *fx) |
1361b83a | 183 | { |
0ca5bd0d SS |
184 | if (config_enabled(CONFIG_X86_32)) |
185 | return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
186 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
187 | return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a | 188 | |
0ca5bd0d SS |
189 | /* See comment in fpu_fxsave() below. */ |
190 | return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), | |
191 | "m" (*fx)); | |
1361b83a LT |
192 | } |
193 | ||
e139e955 PA |
194 | static inline int fxrstor_user(struct i387_fxsave_struct __user *fx) |
195 | { | |
196 | if (config_enabled(CONFIG_X86_32)) | |
197 | return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
198 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
199 | return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
200 | ||
201 | /* See comment in fpu_fxsave() below. */ | |
202 | return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), | |
203 | "m" (*fx)); | |
204 | } | |
205 | ||
0ca5bd0d | 206 | static inline int frstor_checking(struct i387_fsave_struct *fx) |
1361b83a | 207 | { |
0ca5bd0d | 208 | return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
e139e955 PA |
209 | } |
210 | ||
211 | static inline int frstor_user(struct i387_fsave_struct __user *fx) | |
212 | { | |
213 | return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a LT |
214 | } |
215 | ||
216 | static inline void fpu_fxsave(struct fpu *fpu) | |
217 | { | |
0ca5bd0d SS |
218 | if (config_enabled(CONFIG_X86_32)) |
219 | asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state->fxsave)); | |
220 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
6ca7a8a1 | 221 | asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state->fxsave)); |
0ca5bd0d SS |
222 | else { |
223 | /* Using "rex64; fxsave %0" is broken because, if the memory | |
224 | * operand uses any extended registers for addressing, a second | |
225 | * REX prefix will be generated (to the assembler, rex64 | |
226 | * followed by semicolon is a separate instruction), and hence | |
227 | * the 64-bitness is lost. | |
228 | * | |
229 | * Using "fxsaveq %0" would be the ideal choice, but is only | |
230 | * supported starting with gas 2.16. | |
231 | * | |
232 | * Using, as a workaround, the properly prefixed form below | |
233 | * isn't accepted by any binutils version so far released, | |
234 | * complaining that the same type of prefix is used twice if | |
235 | * an extended register is needed for addressing (fix submitted | |
236 | * to mainline 2005-11-21). | |
237 | * | |
238 | * asm volatile("rex64/fxsave %0" : "=m" (fpu->state->fxsave)); | |
239 | * | |
240 | * This, however, we can work around by forcing the compiler to | |
241 | * select an addressing mode that doesn't require extended | |
242 | * registers. | |
243 | */ | |
244 | asm volatile( "rex64/fxsave (%[fx])" | |
245 | : "=m" (fpu->state->fxsave) | |
246 | : [fx] "R" (&fpu->state->fxsave)); | |
247 | } | |
1361b83a LT |
248 | } |
249 | ||
1361b83a LT |
250 | /* |
251 | * These must be called with preempt disabled. Returns | |
252 | * 'true' if the FPU state is still intact. | |
253 | */ | |
254 | static inline int fpu_save_init(struct fpu *fpu) | |
255 | { | |
256 | if (use_xsave()) { | |
0afc4a94 | 257 | xsave_state(&fpu->state->xsave); |
1361b83a LT |
258 | |
259 | /* | |
260 | * xsave header may indicate the init state of the FP. | |
261 | */ | |
262 | if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP)) | |
263 | return 1; | |
264 | } else if (use_fxsr()) { | |
265 | fpu_fxsave(fpu); | |
266 | } else { | |
267 | asm volatile("fnsave %[fx]; fwait" | |
268 | : [fx] "=m" (fpu->state->fsave)); | |
269 | return 0; | |
270 | } | |
271 | ||
272 | /* | |
273 | * If exceptions are pending, we need to clear them so | |
274 | * that we don't randomly get exceptions later. | |
275 | * | |
276 | * FIXME! Is this perhaps only true for the old-style | |
277 | * irq13 case? Maybe we could leave the x87 state | |
278 | * intact otherwise? | |
279 | */ | |
280 | if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) { | |
281 | asm volatile("fnclex"); | |
282 | return 0; | |
283 | } | |
284 | return 1; | |
285 | } | |
286 | ||
1361b83a LT |
287 | static inline int fpu_restore_checking(struct fpu *fpu) |
288 | { | |
289 | if (use_xsave()) | |
0ca5bd0d SS |
290 | return fpu_xrstor_checking(&fpu->state->xsave); |
291 | else if (use_fxsr()) | |
292 | return fxrstor_checking(&fpu->state->fxsave); | |
1361b83a | 293 | else |
0ca5bd0d | 294 | return frstor_checking(&fpu->state->fsave); |
1361b83a LT |
295 | } |
296 | ||
11f2d50b | 297 | static inline int restore_fpu_checking(struct fpu *fpu) |
1361b83a | 298 | { |
6ca7a8a1 BP |
299 | /* |
300 | * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is | |
301 | * pending. Clear the x87 state here by setting it to fixed values. | |
302 | * "m" is a random variable that should be in L1. | |
303 | */ | |
9b13a93d | 304 | if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { |
26bef131 LT |
305 | asm volatile( |
306 | "fnclex\n\t" | |
307 | "emms\n\t" | |
308 | "fildl %P[addr]" /* set F?P to defined value */ | |
11f2d50b | 309 | : : [addr] "m" (fpu->has_fpu)); |
26bef131 | 310 | } |
1361b83a | 311 | |
11f2d50b | 312 | return fpu_restore_checking(fpu); |
1361b83a LT |
313 | } |
314 | ||
1361b83a | 315 | /* Must be paired with an 'stts' after! */ |
36fe6175 | 316 | static inline void __thread_clear_has_fpu(struct fpu *fpu) |
1361b83a | 317 | { |
36fe6175 | 318 | fpu->has_fpu = 0; |
36b544dc | 319 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
1361b83a LT |
320 | } |
321 | ||
322 | /* Must be paired with a 'clts' before! */ | |
c0311f63 | 323 | static inline void __thread_set_has_fpu(struct fpu *fpu) |
1361b83a | 324 | { |
c0311f63 IM |
325 | fpu->has_fpu = 1; |
326 | this_cpu_write(fpu_fpregs_owner_ctx, fpu); | |
1361b83a LT |
327 | } |
328 | ||
329 | /* | |
330 | * Encapsulate the CR0.TS handling together with the | |
331 | * software flag. | |
332 | * | |
333 | * These generally need preemption protection to work, | |
334 | * do try to avoid using these on their own. | |
335 | */ | |
35191e3f | 336 | static inline void __thread_fpu_end(struct fpu *fpu) |
1361b83a | 337 | { |
35191e3f | 338 | __thread_clear_has_fpu(fpu); |
5d2bd700 | 339 | if (!use_eager_fpu()) |
304bceda | 340 | stts(); |
1361b83a LT |
341 | } |
342 | ||
4540d3fa | 343 | static inline void __thread_fpu_begin(struct fpu *fpu) |
1361b83a | 344 | { |
31d96338 | 345 | if (!use_eager_fpu()) |
304bceda | 346 | clts(); |
4540d3fa | 347 | __thread_set_has_fpu(fpu); |
1361b83a LT |
348 | } |
349 | ||
ca6787ba | 350 | static inline void drop_fpu(struct fpu *fpu) |
304bceda | 351 | { |
d2d0ac9a BP |
352 | /* |
353 | * Forget coprocessor state.. | |
354 | */ | |
355 | preempt_disable(); | |
ca6787ba | 356 | fpu->counter = 0; |
d2d0ac9a | 357 | |
276983f8 | 358 | if (fpu->has_fpu) { |
304bceda SS |
359 | /* Ignore delayed exceptions from user space */ |
360 | asm volatile("1: fwait\n" | |
361 | "2:\n" | |
362 | _ASM_EXTABLE(1b, 2b)); | |
35191e3f | 363 | __thread_fpu_end(fpu); |
304bceda | 364 | } |
304bceda | 365 | |
c5bedc68 | 366 | fpu->fpstate_active = 0; |
4c138410 | 367 | |
304bceda SS |
368 | preempt_enable(); |
369 | } | |
370 | ||
8f4d8186 ON |
371 | static inline void restore_init_xstate(void) |
372 | { | |
373 | if (use_xsave()) | |
374 | xrstor_state(init_xstate_buf, -1); | |
375 | else | |
376 | fxrstor_checking(&init_xstate_buf->i387); | |
377 | } | |
378 | ||
b85e67d1 BP |
379 | /* |
380 | * Reset the FPU state in the eager case and drop it in the lazy case (later use | |
381 | * will reinit it). | |
382 | */ | |
af2d94fd | 383 | static inline void fpu_reset_state(struct fpu *fpu) |
304bceda | 384 | { |
5d2bd700 | 385 | if (!use_eager_fpu()) |
ca6787ba | 386 | drop_fpu(fpu); |
8f4d8186 ON |
387 | else |
388 | restore_init_xstate(); | |
304bceda SS |
389 | } |
390 | ||
1361b83a LT |
391 | /* |
392 | * FPU state switching for scheduling. | |
393 | * | |
394 | * This is a two-stage process: | |
395 | * | |
396 | * - switch_fpu_prepare() saves the old state and | |
397 | * sets the new state of the CR0.TS bit. This is | |
398 | * done within the context of the old process. | |
399 | * | |
400 | * - switch_fpu_finish() restores the new state as | |
401 | * necessary. | |
402 | */ | |
403 | typedef struct { int preload; } fpu_switch_t; | |
404 | ||
cb8818b6 IM |
405 | static inline fpu_switch_t |
406 | switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu) | |
1361b83a LT |
407 | { |
408 | fpu_switch_t fpu; | |
409 | ||
304bceda SS |
410 | /* |
411 | * If the task has used the math, pre-load the FPU on xsave processors | |
412 | * or if the past 5 consecutive context-switches used math. | |
413 | */ | |
c5bedc68 | 414 | fpu.preload = new_fpu->fpstate_active && |
cb8818b6 | 415 | (use_eager_fpu() || new_fpu->counter > 5); |
1361ef29 | 416 | |
276983f8 | 417 | if (old_fpu->has_fpu) { |
cb8818b6 IM |
418 | if (!fpu_save_init(old_fpu)) |
419 | old_fpu->last_cpu = -1; | |
1361ef29 | 420 | else |
cb8818b6 | 421 | old_fpu->last_cpu = cpu; |
1361ef29 | 422 | |
36b544dc | 423 | /* But leave fpu_fpregs_owner_ctx! */ |
cb8818b6 | 424 | old_fpu->has_fpu = 0; |
1361b83a LT |
425 | |
426 | /* Don't change CR0.TS if we just switch! */ | |
427 | if (fpu.preload) { | |
cb8818b6 | 428 | new_fpu->counter++; |
c0311f63 | 429 | __thread_set_has_fpu(new_fpu); |
cb8818b6 | 430 | prefetch(new_fpu->state); |
5d2bd700 | 431 | } else if (!use_eager_fpu()) |
1361b83a LT |
432 | stts(); |
433 | } else { | |
cb8818b6 IM |
434 | old_fpu->counter = 0; |
435 | old_fpu->last_cpu = -1; | |
1361b83a | 436 | if (fpu.preload) { |
cb8818b6 | 437 | new_fpu->counter++; |
66ddc2cb | 438 | if (fpu_want_lazy_restore(new_fpu, cpu)) |
1361b83a LT |
439 | fpu.preload = 0; |
440 | else | |
cb8818b6 | 441 | prefetch(new_fpu->state); |
4540d3fa | 442 | __thread_fpu_begin(new_fpu); |
1361b83a LT |
443 | } |
444 | } | |
445 | return fpu; | |
446 | } | |
447 | ||
448 | /* | |
449 | * By the time this gets called, we've already cleared CR0.TS and | |
450 | * given the process the FPU if we are going to preload the FPU | |
451 | * state - all we need to do is to conditionally restore the register | |
452 | * state itself. | |
453 | */ | |
384a23f9 | 454 | static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switch) |
1361b83a | 455 | { |
384a23f9 | 456 | if (fpu_switch.preload) { |
11f2d50b | 457 | if (unlikely(restore_fpu_checking(new_fpu))) |
af2d94fd | 458 | fpu_reset_state(new_fpu); |
1361b83a LT |
459 | } |
460 | } | |
461 | ||
462 | /* | |
463 | * Signal frame handlers... | |
464 | */ | |
72a671ce SS |
465 | extern int save_xstate_sig(void __user *buf, void __user *fx, int size); |
466 | extern int __restore_xstate_sig(void __user *buf, void __user *fx, int size); | |
1361b83a | 467 | |
72a671ce | 468 | static inline int xstate_sigframe_size(void) |
1361b83a | 469 | { |
72a671ce SS |
470 | return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size; |
471 | } | |
472 | ||
473 | static inline int restore_xstate_sig(void __user *buf, int ia32_frame) | |
474 | { | |
475 | void __user *buf_fx = buf; | |
476 | int size = xstate_sigframe_size(); | |
477 | ||
478 | if (ia32_frame && use_fxsr()) { | |
479 | buf_fx = buf + sizeof(struct i387_fsave_struct); | |
480 | size += sizeof(struct i387_fsave_struct); | |
1361b83a | 481 | } |
72a671ce SS |
482 | |
483 | return __restore_xstate_sig(buf, buf_fx, size); | |
1361b83a LT |
484 | } |
485 | ||
486 | /* | |
fb14b4ea | 487 | * Needs to be preemption-safe. |
1361b83a | 488 | * |
377ffbcc | 489 | * NOTE! user_fpu_begin() must be used only immediately before restoring |
fb14b4ea ON |
490 | * the save state. It does not do any saving/restoring on its own. In |
491 | * lazy FPU mode, it is just an optimization to avoid a #NM exception, | |
492 | * the task can lose the FPU right after preempt_enable(). | |
1361b83a | 493 | */ |
1361b83a LT |
494 | static inline void user_fpu_begin(void) |
495 | { | |
4540d3fa IM |
496 | struct fpu *fpu = ¤t->thread.fpu; |
497 | ||
1361b83a LT |
498 | preempt_disable(); |
499 | if (!user_has_fpu()) | |
4540d3fa | 500 | __thread_fpu_begin(fpu); |
1361b83a LT |
501 | preempt_enable(); |
502 | } | |
503 | ||
1361b83a LT |
504 | /* |
505 | * i387 state interaction | |
506 | */ | |
507 | static inline unsigned short get_fpu_cwd(struct task_struct *tsk) | |
508 | { | |
509 | if (cpu_has_fxsr) { | |
510 | return tsk->thread.fpu.state->fxsave.cwd; | |
511 | } else { | |
512 | return (unsigned short)tsk->thread.fpu.state->fsave.cwd; | |
513 | } | |
514 | } | |
515 | ||
516 | static inline unsigned short get_fpu_swd(struct task_struct *tsk) | |
517 | { | |
518 | if (cpu_has_fxsr) { | |
519 | return tsk->thread.fpu.state->fxsave.swd; | |
520 | } else { | |
521 | return (unsigned short)tsk->thread.fpu.state->fsave.swd; | |
522 | } | |
523 | } | |
524 | ||
525 | static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk) | |
526 | { | |
527 | if (cpu_has_xmm) { | |
528 | return tsk->thread.fpu.state->fxsave.mxcsr; | |
529 | } else { | |
530 | return MXCSR_DEFAULT; | |
531 | } | |
532 | } | |
533 | ||
8ffb53ab IM |
534 | extern void fpstate_cache_init(void); |
535 | ||
ed97b085 | 536 | extern int fpstate_alloc(struct fpu *fpu); |
5a12bf63 | 537 | extern void fpstate_free(struct fpu *fpu); |
c69e098b | 538 | extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu); |
1361b83a | 539 | |
72a671ce SS |
540 | static inline unsigned long |
541 | alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx, | |
542 | unsigned long *size) | |
543 | { | |
544 | unsigned long frame_size = xstate_sigframe_size(); | |
545 | ||
546 | *buf_fx = sp = round_down(sp - frame_size, 64); | |
547 | if (ia32_frame && use_fxsr()) { | |
548 | frame_size += sizeof(struct i387_fsave_struct); | |
549 | sp -= sizeof(struct i387_fsave_struct); | |
550 | } | |
551 | ||
552 | *size = frame_size; | |
553 | return sp; | |
554 | } | |
1361b83a LT |
555 | |
556 | #endif |